Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'
This commit is contained in:
+24
@@ -0,0 +1,24 @@
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#!/usr/bin/env python3
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import test_lite
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import test_iter
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import test_skipdata
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import test_customized_mnem
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import test_compatibility_layer
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import test_riscv_sysreg
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import test_riscv_reg_access
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errors = []
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errors.extend(test_lite.test_class())
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errors.extend(test_iter.test_class())
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errors.extend(test_skipdata.test_class())
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errors.extend(test_customized_mnem.test())
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errors.extend(test_compatibility_layer.test_compatibility())
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errors.extend(test_riscv_sysreg.test())
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errors.extend(test_riscv_reg_access.test())
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if errors:
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print("Some errors happened. Please check the output")
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for error in errors:
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print(error)
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exit(1)
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@@ -0,0 +1,72 @@
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#!/usr/bin/env python3
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# Copyright © 2024 Peace-Maker <peacemakerctf@gmail.com>
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# SPDX-License-Identifier: BSD-3
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import capstone.arm64
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import capstone.sysz_const
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from capstone import *
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import capstone.aarch64
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import capstone.arm
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import capstone.systemz
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AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
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SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
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all_tests = (
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(CS_ARCH_ARM64, CS_MODE_ARM, AARCH64_CODE, "ARM64"),
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(CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, SYSZ_CODE, "SysZ"),
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)
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# Test arm64 and sysz compatibility layer
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def test_compatibility():
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errors = []
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for arch, mode, code, comment in all_tests:
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print("*" * 16)
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print("Platform: %s" % comment)
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print("Code: %s" % code.hex(' '))
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print("Disasm:")
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try:
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md = Cs(arch, mode)
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md.detail = True
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for insn in md.disasm(code, 0x1000):
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print("0x%x:\t%s\t%s\t(cc: %s)" % (insn.address, insn.mnemonic, insn.op_str, insn.cc))
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print("0x%x:" % (insn.address + insn.size))
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print()
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except CsError as e:
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print("ERROR: %s" % e)
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errors.append(str(e))
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# Test ARM64_ constants
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print("arm64.ARM64_CC_AL = %d" % capstone.arm64.ARM64_CC_AL)
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print("aarch64.AArch64CC_AL = %d" % capstone.aarch64.AArch64CC_AL)
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assert capstone.arm64.ARM64_CC_AL == capstone.aarch64.AArch64CC_AL
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print("arm64.ARM64_INS_FDIV = %d" % capstone.arm64.ARM64_INS_FDIV)
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print("aarch64.AARCH64_INS_FDIV = %d" % capstone.aarch64.AARCH64_INS_FDIV)
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assert capstone.arm64.ARM64_INS_FDIV == capstone.aarch64.AARCH64_INS_FDIV
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# Test SYSZ_ constants
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print("systemz.SYSZ_INS_LG = %d" % capstone.systemz.SYSZ_INS_LG)
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print("systemz.SYSTEMZ_INS_LG = %d" % capstone.systemz.SYSTEMZ_INS_LG)
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assert capstone.systemz.SYSZ_INS_LG == capstone.systemz.SYSTEMZ_INS_LG
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# Test ARM_CC_ constants
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print("arm.ARM_CC_MI = %d" % capstone.arm.ARM_CC_MI)
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print("arm.ARMCC_MI = %d" % capstone.arm.ARMCC_MI)
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assert capstone.arm.ARM_CC_MI == capstone.arm.ARMCC_MI
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print("arm.ARM_CC_INVALID = %d" % capstone.arm.ARM_CC_INVALID)
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print("arm.ARMCC_Invalid = %d" % capstone.arm.ARMCC_Invalid)
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assert capstone.arm.ARM_CC_INVALID == capstone.arm.ARMCC_Invalid
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return errors
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if __name__ == "__main__":
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if test_compatibility():
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print("Some errors happened. Please check the output")
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exit(1)
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+43
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#!/usr/bin/env python3
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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from capstone import *
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from capstone.x86 import *
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X86_CODE32 = b"\x75\x01"
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def print_insn(md, code):
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print("%s\t" % code.hex(' '), end="")
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for insn in md.disasm(code, 0x1000):
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print("\t%s\t%s" % (insn.mnemonic, insn.op_str))
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def test():
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errors = []
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try:
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md = Cs(CS_ARCH_X86, CS_MODE_32)
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print("Disassemble X86 code with default instruction mnemonic")
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print_insn(md, X86_CODE32)
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print("\nNow customize engine to change mnemonic from 'JNE' to 'JNZ'")
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md.mnemonic_setup(X86_INS_JNE, "jnz")
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print_insn(md, X86_CODE32)
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print("\nReset engine to use the default mnemonic")
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md.mnemonic_setup(X86_INS_JNE, None)
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print_insn(md, X86_CODE32)
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except CsError as e:
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print("ERROR: %s" % e)
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errors.append(str(e))
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return errors
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if __name__ == '__main__':
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if test():
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print("Some errors happened. Please check the output")
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exit(1)
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+100
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#!/usr/bin/env python3
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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from capstone import *
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X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
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X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
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X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
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ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
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ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
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THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
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THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
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THUMB_MCLASS = b"\xef\xf3\x02\x80"
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ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
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MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
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MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
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MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
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MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
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AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
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PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
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PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
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SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
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SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
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SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
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XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
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M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
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M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
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ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
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ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00'
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HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad'
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HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14'
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HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1'
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HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c'
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ARC_CODE = b"\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
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all_tests = (
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(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
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(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
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(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
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(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM),
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(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
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(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
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(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
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(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
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(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
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(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
|
||||
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),
|
||||
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
|
||||
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
|
||||
(CS_ARCH_SYSTEMZ, CS_MODE_BIG_ENDIAN, SYSZ_CODE, "SystemZ", None),
|
||||
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
|
||||
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
|
||||
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
|
||||
(CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None),
|
||||
(CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None),
|
||||
(CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None),
|
||||
(CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None),
|
||||
(CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None),
|
||||
(CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None),
|
||||
(CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, ARC_CODE, "ARC", None),
|
||||
)
|
||||
|
||||
# ## Test class Cs
|
||||
def test_class():
|
||||
errors = []
|
||||
for (arch, mode, code, comment, syntax) in all_tests:
|
||||
print('*' * 16)
|
||||
print("Platform: %s" % comment)
|
||||
print("Code: %s" % code.hex(' '))
|
||||
print("Disasm:")
|
||||
|
||||
try:
|
||||
md = Cs(arch, mode)
|
||||
|
||||
if syntax is not None:
|
||||
md.syntax = syntax
|
||||
|
||||
for (addr, size, mnemonic, op_str) in md.disasm_iter(code, 0x1000):
|
||||
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
|
||||
|
||||
print("0x%x:" % (addr + size))
|
||||
print()
|
||||
except CsError as e:
|
||||
print("ERROR: %s" % e)
|
||||
errors.append(str(e))
|
||||
return errors
|
||||
|
||||
if __name__ == '__main__':
|
||||
if test_class():
|
||||
print("Some errors happened. Please check the output")
|
||||
exit(1)
|
||||
+105
@@ -0,0 +1,105 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
|
||||
from capstone import *
|
||||
|
||||
|
||||
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
|
||||
X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
|
||||
X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
|
||||
ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
|
||||
ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
|
||||
THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
|
||||
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
|
||||
THUMB_MCLASS = b"\xef\xf3\x02\x80"
|
||||
ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
|
||||
MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
|
||||
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
|
||||
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
|
||||
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
|
||||
AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
|
||||
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
|
||||
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
|
||||
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
|
||||
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
|
||||
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
|
||||
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
|
||||
M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
|
||||
M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
|
||||
ARC_CODE = b"\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
|
||||
|
||||
|
||||
all_tests = (
|
||||
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
|
||||
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
|
||||
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
|
||||
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM),
|
||||
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
|
||||
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
|
||||
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
|
||||
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
|
||||
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
|
||||
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
|
||||
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
|
||||
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
|
||||
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
|
||||
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
|
||||
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
|
||||
(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
|
||||
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
|
||||
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
|
||||
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),
|
||||
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
|
||||
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
|
||||
(CS_ARCH_SYSTEMZ, CS_MODE_BIG_ENDIAN, SYSZ_CODE, "SystemZ", None),
|
||||
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
|
||||
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
|
||||
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
|
||||
(CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, ARC_CODE, "ARC", None),
|
||||
)
|
||||
|
||||
|
||||
# ## Test cs_disasm_quick()
|
||||
def test_cs_disasm_quick():
|
||||
for (arch, mode, code, comment, syntax) in all_tests:
|
||||
print('*' * 40)
|
||||
print("Platform: %s" % comment)
|
||||
print("Disasm:"),
|
||||
print(code.hex(' '))
|
||||
for (addr, size, mnemonic, op_str) in cs_disasm_lite(arch, mode, code, 0x1000):
|
||||
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
|
||||
print()
|
||||
|
||||
|
||||
# ## Test class Cs
|
||||
def test_class():
|
||||
errors = []
|
||||
for (arch, mode, code, comment, syntax) in all_tests:
|
||||
print('*' * 16)
|
||||
print("Platform: %s" % comment)
|
||||
print("Code: %s" % code.hex(' '))
|
||||
print("Disasm:")
|
||||
|
||||
try:
|
||||
md = Cs(arch, mode)
|
||||
|
||||
if syntax is not None:
|
||||
md.syntax = syntax
|
||||
|
||||
for (addr, size, mnemonic, op_str) in md.disasm_lite(code, 0x1000):
|
||||
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
|
||||
|
||||
print("0x%x:" % (addr + size))
|
||||
print()
|
||||
except CsError as e:
|
||||
print("ERROR: %s" % e)
|
||||
errors.append(str(e))
|
||||
return errors
|
||||
|
||||
|
||||
# test_cs_disasm_quick()
|
||||
# print "*" * 40
|
||||
if __name__ == '__main__':
|
||||
if test_class():
|
||||
print("Some errors happened. Please check the output")
|
||||
exit(1)
|
||||
@@ -0,0 +1,102 @@
|
||||
import unittest
|
||||
from capstone import *
|
||||
from capstone.riscv import *
|
||||
import unittest
|
||||
|
||||
class TestRiscvRegAccess(unittest.TestCase):
|
||||
def setUp(self):
|
||||
self.cs = Cs(CS_ARCH_RISCV, CS_MODE_RISCV64)
|
||||
self.cs.option(CS_OPT_DETAIL, CS_OPT_DETAIL_REAL | CS_OPT_ON)
|
||||
|
||||
def test_addi(self):
|
||||
# addi a0, a1, 10
|
||||
code = b"\x13\x85\xa5\x00"
|
||||
insns = list(self.cs.disasm(code, 0))
|
||||
self.assertEqual(len(insns), 1)
|
||||
insn = insns[0]
|
||||
|
||||
read, write = insn.regs_access()
|
||||
# a1 = RISCV_REG_X11, a0 = RISCV_REG_X10
|
||||
self.assertIn(RISCV_REG_X11, read)
|
||||
self.assertIn(RISCV_REG_X10, write)
|
||||
self.assertEqual(len(read), 1)
|
||||
self.assertEqual(len(write), 1)
|
||||
|
||||
def test_jalr(self):
|
||||
# jalr ra, a1, 0 -> 0x000580e7 (rd=x1=ra, rs1=x11=a1, imm=0)
|
||||
code = b"\xe7\x80\x05\x00"
|
||||
insns = list(self.cs.disasm(code, 0))
|
||||
self.assertEqual(len(insns), 1)
|
||||
insn = insns[0]
|
||||
|
||||
read, write = insn.regs_access()
|
||||
# ra = RISCV_REG_X1
|
||||
self.assertIn(RISCV_REG_X11, read)
|
||||
self.assertIn(RISCV_REG_X1, write)
|
||||
self.assertEqual(len(read), 1)
|
||||
self.assertEqual(len(write), 1)
|
||||
|
||||
def test_lb(self):
|
||||
# lb a0, 0(sp)
|
||||
code = b"\x03\x05\x01\x00"
|
||||
insns = list(self.cs.disasm(code, 0))
|
||||
self.assertEqual(len(insns), 1)
|
||||
insn = insns[0]
|
||||
|
||||
read, write = insn.regs_access()
|
||||
# sp = RISCV_REG_X2
|
||||
self.assertIn(RISCV_REG_X2, read)
|
||||
self.assertIn(RISCV_REG_X10, write)
|
||||
self.assertEqual(len(read), 1)
|
||||
self.assertEqual(len(write), 1)
|
||||
|
||||
def test_caddi(self):
|
||||
# c.addi a0, 10 (0x0529)
|
||||
code = b"\x29\x05"
|
||||
insns = list(self.cs.disasm(code, 0))
|
||||
self.assertEqual(len(insns), 1)
|
||||
insn = insns[0]
|
||||
|
||||
read, write = insn.regs_access()
|
||||
# x10 is both read and written
|
||||
self.assertIn(RISCV_REG_X10, read)
|
||||
self.assertIn(RISCV_REG_X10, write)
|
||||
self.assertEqual(len(read), 1)
|
||||
self.assertEqual(len(write), 1)
|
||||
|
||||
def test_ecall(self):
|
||||
# ecall
|
||||
code = b"\x73\x00\x00\x00"
|
||||
insns = list(self.cs.disasm(code, 0))
|
||||
self.assertEqual(len(insns), 1)
|
||||
insn = insns[0]
|
||||
|
||||
read, write = insn.regs_access()
|
||||
self.assertEqual(len(read), 0)
|
||||
self.assertEqual(len(write), 0)
|
||||
|
||||
def test_csrrw(self):
|
||||
# csrrw a0, sstatus, a1
|
||||
code = b"\x73\x95\x05\x10"
|
||||
insns = list(self.cs.disasm(code, 0))
|
||||
self.assertEqual(len(insns), 1)
|
||||
insn = insns[0]
|
||||
|
||||
read, write = insn.regs_access()
|
||||
# CSRs should NOT be in the reg_access list
|
||||
self.assertIn(RISCV_REG_X11, read)
|
||||
self.assertIn(RISCV_REG_X10, write)
|
||||
self.assertEqual(len(read), 1)
|
||||
self.assertEqual(len(write), 1)
|
||||
|
||||
def test():
|
||||
loader = unittest.TestLoader()
|
||||
suite = loader.loadTestsFromTestCase(TestRiscvRegAccess)
|
||||
runner = unittest.TextTestRunner(verbosity=2)
|
||||
return runner.run(suite).failures
|
||||
|
||||
def main():
|
||||
unittest.main()
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
@@ -0,0 +1,66 @@
|
||||
from capstone import *
|
||||
from capstone.riscv import *
|
||||
from capstone.riscv_const import *
|
||||
import sys
|
||||
|
||||
def test():
|
||||
print("Test test_riscv_sysreg (Python)")
|
||||
errors = []
|
||||
# csrr a0, sstatus (0x10002573)
|
||||
# csrr a0, mtvec (0x30502573)
|
||||
# csrr a0, mcause (0x34202573)
|
||||
CODE = b"\x73\x25\x00\x10\x73\x25\x50\x30\x73\x25\x20\x34"
|
||||
|
||||
expected_sysregs = [
|
||||
RISCV_SYSREG_SSTATUS,
|
||||
RISCV_SYSREG_MTVEC,
|
||||
RISCV_SYSREG_MCAUSE,
|
||||
]
|
||||
|
||||
try:
|
||||
md = Cs(CS_ARCH_RISCV, CS_MODE_RISCV64)
|
||||
md.detail = True
|
||||
|
||||
count = 0
|
||||
for insn in md.disasm(CODE, 0):
|
||||
found_sysreg = False
|
||||
for op in insn.operands:
|
||||
if op.type == RISCV_OP_CSR:
|
||||
if count >= len(expected_sysregs):
|
||||
errors.append(f"FAIL: Found CSR operand in instruction {count}, but only {len(expected_sysregs)} expected.")
|
||||
break
|
||||
|
||||
if op.csr != expected_sysregs[count]:
|
||||
errors.append(f"FAIL: Expected sysreg {expected_sysregs[count]}, got {op.csr}")
|
||||
|
||||
if op.csr == RISCV_SYSREG_SSTATUS:
|
||||
print(" Recognized SSTATUS")
|
||||
elif op.csr == RISCV_SYSREG_MTVEC:
|
||||
print(" Recognized MTVEC")
|
||||
elif op.csr == RISCV_SYSREG_MCAUSE:
|
||||
print(" Recognized MCAUSE")
|
||||
|
||||
found_sysreg = True
|
||||
|
||||
if not found_sysreg:
|
||||
errors.append(f"FAIL: No CSR operand found in instruction {count}")
|
||||
|
||||
count += 1
|
||||
|
||||
if count != 3:
|
||||
errors.append(f"FAIL: Expected 3 instructions, got {count}")
|
||||
except CsError as e:
|
||||
errors.append(str(e))
|
||||
|
||||
return errors
|
||||
|
||||
if __name__ == '__main__':
|
||||
errs = test()
|
||||
if not errs:
|
||||
print("Python sysreg test PASSED")
|
||||
sys.exit(0)
|
||||
else:
|
||||
print("Python sysreg test FAILED")
|
||||
for e in errs:
|
||||
print(f" {e}")
|
||||
sys.exit(1)
|
||||
+75
@@ -0,0 +1,75 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
|
||||
|
||||
from capstone import *
|
||||
|
||||
|
||||
X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x00\x91\x92"
|
||||
RANDOM_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
|
||||
|
||||
all_tests = (
|
||||
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
|
||||
(CS_ARCH_ARM, CS_MODE_ARM, RANDOM_CODE, "Arm", None),
|
||||
)
|
||||
|
||||
|
||||
# Sample callback for SKIPDATA option
|
||||
def testcb(buffer, size, offset, userdata):
|
||||
# always skip 2 bytes of data
|
||||
return 2
|
||||
|
||||
|
||||
# ## Test class Cs
|
||||
def test_class():
|
||||
errors = []
|
||||
for (arch, mode, code, comment, syntax) in all_tests:
|
||||
print('*' * 16)
|
||||
print("Platform: %s" %comment)
|
||||
print("Code: %s" % code.hex(' '))
|
||||
print("Disasm:")
|
||||
|
||||
try:
|
||||
md = Cs(arch, mode)
|
||||
|
||||
if syntax is not None:
|
||||
md.syntax = syntax
|
||||
|
||||
md.skipdata = True
|
||||
|
||||
# Default "data" instruction's name is ".byte". To rename it to "db", just use
|
||||
# the code below.
|
||||
md.skipdata_setup = ("db", None, None)
|
||||
|
||||
# NOTE: This example ignores SKIPDATA's callback (first None) & user_data (second None)
|
||||
# Can also use dedicated setter
|
||||
#md.skipdata_mnem = 'db'
|
||||
|
||||
# To customize the SKIPDATA callback, use the line below.
|
||||
#md.skipdata_setup = (".db", testcb, None)
|
||||
|
||||
# Or use dedicated setter with custom parameter
|
||||
#md.skipdata_callback = (testcb, 42)
|
||||
|
||||
# Or provide just a function
|
||||
#md.skipdata_callback = testcb
|
||||
# Note that reading this property will always return a tuple
|
||||
#assert md.skipdata_callback == (testcb, None)
|
||||
|
||||
for insn in md.disasm(code, 0x1000):
|
||||
#bytes = binascii.hexlify(insn.bytes)
|
||||
#print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes))
|
||||
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
|
||||
|
||||
print("0x%x:" % (insn.address + insn.size))
|
||||
print
|
||||
except CsError as e:
|
||||
print("ERROR: %s" % e)
|
||||
errors.append(str(e))
|
||||
return errors
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
if test_class():
|
||||
print("Some errors happened. Please check the output")
|
||||
exit(1)
|
||||
Reference in New Issue
Block a user