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Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'

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iris
2026-05-11 11:55:07 +02:00
parent ef8e742694 802798ce3c
commit c0de07465b
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external/capstone/suite/MC/RISCV/XCVbitmanip_riscv32_riscv_xcvbitmanip.txt.cs
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# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVBITMANIP", None
0xdb,0x02,0x13,0x00 == cv.extract t0, t1, 0, 1
0x5b,0x85,0x25,0x23 == cv.extract a0, a1, 17, 18
0x5b,0x84,0xf4,0x3d == cv.extract s0, s1, 30, 31
0xdb,0x02,0x13,0x40 == cv.extractu t0, t1, 0, 1
0x5b,0x85,0x25,0x63 == cv.extractu a0, a1, 17, 18
0x5b,0x84,0xf4,0x7d == cv.extractu s0, s1, 30, 31
0xdb,0x02,0x13,0x80 == cv.insert t0, t1, 0, 1
0x5b,0x85,0x25,0xa3 == cv.insert a0, a1, 17, 18
0x5b,0x84,0xf4,0xbd == cv.insert s0, s1, 30, 31
0xdb,0x12,0x13,0x00 == cv.bclr t0, t1, 0, 1
0x5b,0x95,0x25,0x23 == cv.bclr a0, a1, 17, 18
0x5b,0x94,0xf4,0x3d == cv.bclr s0, s1, 30, 31
0xdb,0x12,0x13,0x40 == cv.bset t0, t1, 0, 1
0x5b,0x95,0x25,0x63 == cv.bset a0, a1, 17, 18
0x5b,0x94,0xf4,0x7d == cv.bset s0, s1, 30, 31
0xdb,0x12,0x13,0xc0 == cv.bitrev t0, t1, 0, 1
0x5b,0x95,0x25,0xc3 == cv.bitrev a0, a1, 1, 18
0x5b,0x94,0xf4,0xc5 == cv.bitrev s0, s1, 2, 31
0xab,0x32,0x73,0x30 == cv.extractr t0, t1, t2
0x2b,0xb5,0xc5,0x30 == cv.extractr a0, a1, a2
0x2b,0xb4,0x24,0x31 == cv.extractr s0, s1, s2
0xab,0x32,0x73,0x32 == cv.extractur t0, t1, t2
0x2b,0xb5,0xc5,0x32 == cv.extractur a0, a1, a2
0x2b,0xb4,0x24,0x33 == cv.extractur s0, s1, s2
0xab,0x32,0x73,0x34 == cv.insertr t0, t1, t2
0x2b,0xb5,0xc5,0x34 == cv.insertr a0, a1, a2
0x2b,0xb4,0x24,0x35 == cv.insertr s0, s1, s2
0xab,0x32,0x73,0x38 == cv.bclrr t0, t1, t2
0x2b,0xb5,0xc5,0x38 == cv.bclrr a0, a1, a2
0x2b,0xb4,0x24,0x39 == cv.bclrr s0, s1, s2
0xab,0x32,0x73,0x3a == cv.bsetr t0, t1, t2
0x2b,0xb5,0xc5,0x3a == cv.bsetr a0, a1, a2
0x2b,0xb4,0x24,0x3b == cv.bsetr s0, s1, s2
0xab,0x32,0x73,0x40 == cv.ror t0, t1, t2
0x2b,0xb5,0xc5,0x40 == cv.ror a0, a1, a2
0x2b,0xb4,0x24,0x41 == cv.ror s0, s1, s2
0xab,0x32,0x03,0x42 == cv.ff1 t0, t1
0x2b,0xb5,0x05,0x42 == cv.ff1 a0, a1
0x2b,0xb4,0x04,0x42 == cv.ff1 s0, s1
0xab,0x32,0x03,0x44 == cv.fl1 t0, t1
0x2b,0xb5,0x05,0x44 == cv.fl1 a0, a1
0x2b,0xb4,0x04,0x44 == cv.fl1 s0, s1
0xab,0x32,0x03,0x46 == cv.clb t0, t1
0x2b,0xb5,0x05,0x46 == cv.clb a0, a1
0x2b,0xb4,0x04,0x46 == cv.clb s0, s1
0xab,0x32,0x03,0x48 == cv.cnt t0, t1
0x2b,0xb5,0x05,0x48 == cv.cnt a0, a1
0x2b,0xb4,0x04,0x48 == cv.cnt s0, s1