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Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'

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iris
2026-05-11 11:55:07 +02:00
parent ef8e742694 802798ce3c
commit c0de07465b
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external/capstone/suite/MC/RISCV/mul_riscv64_riscv_v.txt.cs
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# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x94 == vmul.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x96 == vmul.vv v8, v4, v20
0x57,0x64,0x45,0x94 == vmul.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x96 == vmul.vx v8, v4, a0
0x57,0x24,0x4a,0x9c == vmulh.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x9e == vmulh.vv v8, v4, v20
0x57,0x64,0x45,0x9c == vmulh.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x9e == vmulh.vx v8, v4, a0
0x57,0x24,0x4a,0x90 == vmulhu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x92 == vmulhu.vv v8, v4, v20
0x57,0x64,0x45,0x90 == vmulhu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x92 == vmulhu.vx v8, v4, a0
0x57,0x24,0x4a,0x98 == vmulhsu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x9a == vmulhsu.vv v8, v4, v20
0x57,0x64,0x45,0x98 == vmulhsu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x9a == vmulhsu.vx v8, v4, a0
0x57,0x24,0x4a,0xec == vwmul.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xee == vwmul.vv v8, v4, v20
0x57,0x64,0x45,0xec == vwmul.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xee == vwmul.vx v8, v4, a0
0x57,0x24,0x4a,0xe0 == vwmulu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xe2 == vwmulu.vv v8, v4, v20
0x57,0x64,0x45,0xe0 == vwmulu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xe2 == vwmulu.vx v8, v4, a0
0x57,0x24,0x4a,0xe8 == vwmulsu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xea == vwmulsu.vv v8, v4, v20
0x57,0x64,0x45,0xe8 == vwmulsu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xea == vwmulsu.vx v8, v4, a0
0x57,0x04,0x4a,0x9c == vsmul.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x9e == vsmul.vv v8, v4, v20
0x57,0x44,0x45,0x9c == vsmul.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x9e == vsmul.vx v8, v4, a0