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Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'

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iris
2026-05-11 11:55:07 +02:00
parent ef8e742694 802798ce3c
commit c0de07465b
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external/capstone/tests/MC/RISCV/shift_riscv64_riscv_v.txt.yaml
Vendored
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test_cases:
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x94 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsll.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x96 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsll.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x94 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsll.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x96 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsll.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0x94 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsll.vi v8, v4, 31, v0.t"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0x96 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsll.vi v8, v4, 31"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xa0 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsrl.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xa2 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsrl.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xa0 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsrl.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xa2 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsrl.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xa0 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsrl.vi v8, v4, 31, v0.t"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xa2 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsrl.vi v8, v4, 31"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xa4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsra.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xa6 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsra.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xa4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsra.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xa6 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsra.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xa4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsra.vi v8, v4, 31, v0.t"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xa6 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vsra.vi v8, v4, 31"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xb0 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsrl.wv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x02, 0x4a, 0xb0 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsrl.wv v4, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xb2 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsrl.wv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xb0 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsrl.wx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xb2 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsrl.wx v8, v4, a0"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xb0 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsrl.wi v8, v4, 31, v0.t"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xb2 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsrl.wi v8, v4, 31"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xb4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsra.wv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xb6 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsra.wv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xb4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsra.wx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xb6 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsra.wx v8, v4, a0"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xb4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsra.wi v8, v4, 31, v0.t"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xb6 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vnsra.wi v8, v4, 31"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xa8 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssrl.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xaa ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssrl.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xa8 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssrl.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xaa ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssrl.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xa8 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssrl.vi v8, v4, 31, v0.t"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xaa ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssrl.vi v8, v4, 31"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xac ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssra.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0xae ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssra.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xac ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssra.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0xae ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssra.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xac ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssra.vi v8, v4, 31, v0.t"
-
input:
bytes: [ 0x57, 0xb4, 0x4f, 0xae ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vssra.vi v8, v4, 31"