# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADCMO", None
0x0b,0x00,0x18,0x02 == th.dcache.csw a6
0x0b,0x80,0x22,0x02 == th.dcache.isw t0
0x0b,0x80,0x38,0x02 == th.dcache.cisw a7
0x0b,0x80,0x43,0x02 == th.dcache.cval1 t2
0x0b,0x80,0x56,0x02 == th.dcache.cva a3
0x0b,0x80,0x67,0x02 == th.dcache.iva a5
0x0b,0x00,0x77,0x02 == th.dcache.civa a4
0x0b,0x00,0x83,0x02 == th.dcache.cpal1 t1
0x0b,0x00,0x95,0x02 == th.dcache.cpa a0
0x0b,0x00,0xa6,0x02 == th.dcache.ipa a2
0x0b,0x80,0xb5,0x02 == th.dcache.cipa a1
0x0b,0x80,0x0e,0x03 == th.icache.iva t4
0x0b,0x00,0x8e,0x03 == th.icache.ipa t3
0x0b,0x00,0x10,0x00 == th.dcache.call
0x0b,0x00,0x20,0x00 == th.dcache.iall
0x0b,0x00,0x30,0x00 == th.dcache.ciall
0x0b,0x00,0x00,0x01 == th.icache.iall
0x0b,0x00,0x10,0x01 == th.icache.ialls
0x0b,0x00,0x50,0x01 == th.l2cache.call
0x0b,0x00,0x60,0x01 == th.l2cache.iall
0x0b,0x00,0x70,0x01 == th.l2cache.ciall