test_cases: - input: bytes: [ 0x37, 0x34, 0x00, 0x00, 0x97, 0x82, 0x00, 0x00, 0xef, 0x00, 0x80, 0x00, 0xef, 0xf0, 0x1f, 0xff, 0xe7, 0x00, 0x45, 0x00, 0xe7, 0x00, 0xc0, 0xff, 0x63, 0x05, 0x41, 0x00, 0xe3, 0x9d, 0x61, 0xfe, 0x63, 0xca, 0x93, 0x00, 0x63, 0x53, 0xb5, 0x00, 0x63, 0x65, 0xd6, 0x00, 0x63, 0x76, 0xf7, 0x00, 0x03, 0x88, 0x18, 0x00, 0x03, 0x99, 0x49, 0x00, 0x03, 0xaa, 0x6a, 0x00, 0x03, 0xcb, 0x2b, 0x01, 0x03, 0xdc, 0x8c, 0x01, 0x23, 0x86, 0xad, 0x03, 0x23, 0x9a, 0xce, 0x03, 0x23, 0x8f, 0xef, 0x01, 0x93, 0x00, 0xe0, 0x00, 0x13, 0xa1, 0x01, 0x01, 0x13, 0xb2, 0x02, 0x7d, 0x13, 0xc3, 0x03, 0xdd, 0x13, 0xe4, 0xc4, 0x12, 0x13, 0xf5, 0x85, 0x0c, 0x13, 0x96, 0xe6, 0x01, 0x13, 0xd7, 0x97, 0x01, 0x13, 0xd8, 0xf8, 0x40, 0x33, 0x89, 0x49, 0x01, 0xb3, 0x0a, 0x7b, 0x41, 0x33, 0xac, 0xac, 0x01, 0xb3, 0x3d, 0xde, 0x01, 0x33, 0xd2, 0x62, 0x40, 0xb3, 0x43, 0x94, 0x00, 0x33, 0xe5, 0xc5, 0x00, 0xb3, 0x76, 0xf7, 0x00, 0xb3, 0x54, 0x39, 0x01, 0xb3, 0x50, 0x31, 0x00, 0x33, 0x9f, 0x0f, 0x00, 0x73, 0x15, 0x04, 0xb0, 0xf3, 0x56, 0x00, 0x10, 0x33, 0x05, 0x7b, 0x03, 0xb3, 0x45, 0x9c, 0x03, 0x33, 0x66, 0xbd, 0x03, 0x2f, 0xa4, 0x02, 0x10, 0xaf, 0x23, 0x65, 0x18, 0x2f, 0x27, 0x2f, 0x01, 0x43, 0xf0, 0x20, 0x18, 0xd3, 0x72, 0x73, 0x00, 0x53, 0xf4, 0x04, 0x58, 0x53, 0x85, 0xc5, 0x28, 0x53, 0x2e, 0xde, 0xa1, 0xd3, 0x84, 0x05, 0xf0, 0x53, 0x06, 0x05, 0xe0, 0x53, 0x75, 0x00, 0xc0, 0xd3, 0xf0, 0x05, 0xd0, 0xd3, 0x15, 0x08, 0xe0, 0x87, 0xaa, 0x75, 0x00, 0x27, 0x27, 0x66, 0x01, 0x43, 0xf0, 0x20, 0x1a, 0xd3, 0x72, 0x73, 0x02, 0x53, 0xf4, 0x04, 0x5a, 0x53, 0x85, 0xc5, 0x2a, 0x53, 0x2e, 0xde, 0xa3, ] arch: "CS_ARCH_RISCV" options: [ CS_OPT_DETAIL, CS_MODE_RISCV32, CS_MODE_RISCV_A, CS_MODE_RISCV_D, CS_OPT_SYNTAX_NO_ALIAS_TEXT, ] address: 0x1000 expected: insns: - asm_text: "lui s0, 3" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x3 access: CS_AC_READ - asm_text: "auipc t0, 8" details: riscv: operands: - type: RISCV_OP_REG reg: t0 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x8 access: CS_AC_READ - asm_text: "jal ra, 4112" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 4112 access: CS_AC_READ groups: [RISCV_GRP_CALL, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "jal ra, 4092" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 4092 access: CS_AC_READ groups: [RISCV_GRP_CALL, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "jalr ra, 4(a0)" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x4 access: CS_AC_READ groups: [RISCV_GRP_CALL] - asm_text: "jalr ra, -4(zero)" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: -4 access: CS_AC_READ groups: [RISCV_GRP_CALL] - asm_text: "beq sp, tp, 4130" details: riscv: operands: - type: RISCV_OP_REG reg: sp access: CS_AC_READ - type: RISCV_OP_REG reg: tp access: CS_AC_READ - type: RISCV_OP_IMM imm: 4130 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "bne gp, t1, 4118" details: riscv: operands: - type: RISCV_OP_REG reg: gp access: CS_AC_READ - type: RISCV_OP_REG reg: t1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 4118 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "blt t2, s1, 4148" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_READ - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 4148 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "bge a0, a1, 4138" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 4138 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "bltu a2, a3, 4146" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_READ - type: RISCV_OP_REG reg: a3 access: CS_AC_READ - type: RISCV_OP_IMM imm: 4146 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "bgeu a4, a5, 4152" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_READ - type: RISCV_OP_REG reg: a5 access: CS_AC_READ - type: RISCV_OP_IMM imm: 4152 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - asm_text: "lb a6, 1(a7)" details: riscv: operands: - type: RISCV_OP_REG reg: a6 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a7 mem_disp: 0x1 access: CS_AC_READ - asm_text: "lh s2, 4(s3)" details: riscv: operands: - type: RISCV_OP_REG reg: s2 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s3 mem_disp: 0x4 access: CS_AC_READ - asm_text: "lw s4, 6(s5)" details: riscv: operands: - type: RISCV_OP_REG reg: s4 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s5 mem_disp: 0x6 access: CS_AC_READ - asm_text: "lbu s6, 0x12(s7)" details: riscv: operands: - type: RISCV_OP_REG reg: s6 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s7 mem_disp: 0x12 access: CS_AC_READ - asm_text: "lhu s8, 0x18(s9)" details: riscv: operands: - type: RISCV_OP_REG reg: s8 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s9 mem_disp: 0x18 access: CS_AC_READ - asm_text: "sb s10, 0x2c(s11)" details: riscv: operands: - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: s11 mem_disp: 0x2c access: CS_AC_WRITE - asm_text: "sh t3, 0x34(t4)" details: riscv: operands: - type: RISCV_OP_REG reg: t3 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: t4 mem_disp: 0x34 access: CS_AC_WRITE - asm_text: "sb t5, 0x1e(t6)" details: riscv: operands: - type: RISCV_OP_REG reg: t5 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: t6 mem_disp: 0x1e access: CS_AC_WRITE - asm_text: "addi ra, zero, 0xe" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xe access: CS_AC_READ - asm_text: "slti sp, gp, 0x10" details: riscv: operands: - type: RISCV_OP_REG reg: sp access: CS_AC_WRITE - type: RISCV_OP_REG reg: gp access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x10 access: CS_AC_READ - asm_text: "sltiu tp, t0, 0x7d0" details: riscv: operands: - type: RISCV_OP_REG reg: tp access: CS_AC_WRITE - type: RISCV_OP_REG reg: t0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x7d0 access: CS_AC_READ - asm_text: "xori t1, t2, -0x230" details: riscv: operands: - type: RISCV_OP_REG reg: t1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t2 access: CS_AC_READ - type: RISCV_OP_IMM imm: -0x230 access: CS_AC_READ - asm_text: "ori s0, s1, 0x12c" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x12c access: CS_AC_READ - asm_text: "andi a0, a1, 0xc8" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xc8 access: CS_AC_READ - asm_text: "slli a2, a3, 0x1e" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a3 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1e access: CS_AC_READ - asm_text: "srli a4, a5, 0x19" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a5 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x19 access: CS_AC_READ - asm_text: "srai a6, a7, 0xf" details: riscv: operands: - type: RISCV_OP_REG reg: a6 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a7 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xf access: CS_AC_READ - asm_text: "add s2, s3, s4" details: riscv: operands: - type: RISCV_OP_REG reg: s2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s3 access: CS_AC_READ - type: RISCV_OP_REG reg: s4 access: CS_AC_READ - asm_text: "sub s5, s6, s7" details: riscv: operands: - type: RISCV_OP_REG reg: s5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s6 access: CS_AC_READ - type: RISCV_OP_REG reg: s7 access: CS_AC_READ - asm_text: "slt s8, s9, s10" details: riscv: operands: - type: RISCV_OP_REG reg: s8 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s9 access: CS_AC_READ - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - asm_text: "sltu s11, t3, t4" details: riscv: operands: - type: RISCV_OP_REG reg: s11 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t3 access: CS_AC_READ - type: RISCV_OP_REG reg: t4 access: CS_AC_READ - asm_text: "sra tp, t0, t1" details: riscv: operands: - type: RISCV_OP_REG reg: tp access: CS_AC_WRITE - type: RISCV_OP_REG reg: t0 access: CS_AC_READ - type: RISCV_OP_REG reg: t1 access: CS_AC_READ - asm_text: "xor t2, s0, s1" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s0 access: CS_AC_READ - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - asm_text: "or a0, a1, a2" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_REG reg: a2 access: CS_AC_READ - asm_text: "and a3, a4, a5" details: riscv: operands: - type: RISCV_OP_REG reg: a3 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a4 access: CS_AC_READ - type: RISCV_OP_REG reg: a5 access: CS_AC_READ - asm_text: "srl s1, s2, s3" details: riscv: operands: - type: RISCV_OP_REG reg: s1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s2 access: CS_AC_READ - type: RISCV_OP_REG reg: s3 access: CS_AC_READ - asm_text: "srl ra, sp, gp" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: sp access: CS_AC_READ - type: RISCV_OP_REG reg: gp access: CS_AC_READ - asm_text: "sll t5, t6, zero" details: riscv: operands: - type: RISCV_OP_REG reg: t5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t6 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - asm_text: "csrrw a0, mcycle, s0" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_CSR csr: mcycle access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: s0 access: CS_AC_READ - asm_text: "csrrwi a3, sstatus, 0" details: riscv: operands: - type: RISCV_OP_REG reg: a3 access: CS_AC_WRITE - type: RISCV_OP_CSR csr: sstatus access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - asm_text: "mul a0, s6, s7" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s6 access: CS_AC_READ - type: RISCV_OP_REG reg: s7 access: CS_AC_READ groups: [HasStdExtMOrZmmul] - asm_text: "div a1, s8, s9" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s8 access: CS_AC_READ - type: RISCV_OP_REG reg: s9 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM] - asm_text: "rem a2, s10, s11" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - type: RISCV_OP_REG reg: s11 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM] - asm_text: "lr.w s0, (t0)" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA] - asm_text: "sc.w t2, t1, (a0)" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a0 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: t1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA] - asm_text: "amoadd.w a4, s2, (t5)" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t5 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: s2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA] - asm_text: "fmadd.s ft0, ft1, ft2, ft3, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: ft0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft1 access: CS_AC_READ - type: RISCV_OP_REG reg: ft2 access: CS_AC_READ - type: RISCV_OP_REG reg: ft3 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fadd.s ft5, ft6, ft7, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: ft5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft6 access: CS_AC_READ - type: RISCV_OP_REG reg: ft7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fsqrt.s fs0, fs1, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fs1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fmin.s fa0, fa1, fa2" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "feq.s t3, ft8, ft9" details: riscv: operands: - type: RISCV_OP_REG reg: t3 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft8 access: CS_AC_READ - type: RISCV_OP_REG reg: ft9 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fmv.w.x fs1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: fs1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fmv.x.w a2, fa0" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fcvt.w.s a0, ft0, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fcvt.s.w ft1, a1, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fclass.s a1, fa6" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa6 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "flw fs5, 7(a1)" details: riscv: operands: - type: RISCV_OP_REG reg: fs5 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a1 mem_disp: 0x7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fsw fs6, 0xe(a2)" details: riscv: operands: - type: RISCV_OP_REG reg: fs6 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a2 mem_disp: 0xe access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtF] - asm_text: "fmadd.d ft0, ft1, ft2, ft3, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: ft0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft1 access: CS_AC_READ - type: RISCV_OP_REG reg: ft2 access: CS_AC_READ - type: RISCV_OP_REG reg: ft3 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "fadd.d ft5, ft6, ft7, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: ft5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft6 access: CS_AC_READ - type: RISCV_OP_REG reg: ft7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "fsqrt.d fs0, fs1, dyn" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fs1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "fmin.d fa0, fa1, fa2" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "feq.d t3, ft8, ft9" details: riscv: operands: - type: RISCV_OP_REG reg: t3 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft8 access: CS_AC_READ - type: RISCV_OP_REG reg: ft9 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [ 0x13, 0x04, 0xa8, 0x7a, 0xbb, 0x07, 0x9c, 0x02, 0xbb, 0x40, 0x5d, 0x02, 0x3b, 0x63, 0xb7, 0x03, 0x2f, 0xb4, 0x02, 0x10, 0xaf, 0x33, 0x65, 0x18, 0x2f, 0x37, 0x2f, 0x01, 0x53, 0x75, 0x20, 0xc0, 0xd3, 0xf0, 0x25, 0xd0, 0xd3, 0x84, 0x05, 0xf2, 0x53, 0x06, 0x05, 0xe2, 0x53, 0x75, 0x00, 0xc2, 0xd3, 0x80, 0x05, 0xd2, 0xd3, 0x15, 0x08, 0xe2, 0x87, 0xba, 0x75, 0x00, 0x27, 0x37, 0x66, 0x01, ] arch: "CS_ARCH_RISCV" options: [CS_OPT_DETAIL, CS_MODE_RISCV64, CS_MODE_RISCV_A, CS_MODE_RISCV_D] address: 0x1000 expected: insns: - asm_text: "addi s0, a6, 0x7aa" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a6 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x7aa access: CS_AC_READ - asm_text: "mulw a5, s8, s1" details: riscv: operands: - type: RISCV_OP_REG reg: a5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s8 access: CS_AC_READ - type: RISCV_OP_REG reg: s1 access: CS_AC_READ groups: [HasStdExtMOrZmmul, RISCV_FEATURE_IsRV64] - asm_text: "divw ra, s10, t0" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - type: RISCV_OP_REG reg: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM, RISCV_FEATURE_IsRV64] - asm_text: "remw t1, a4, s11" details: riscv: operands: - type: RISCV_OP_REG reg: t1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a4 access: CS_AC_READ - type: RISCV_OP_REG reg: s11 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM, RISCV_FEATURE_IsRV64] - asm_text: "lr.d s0, (t0)" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA, RISCV_FEATURE_IsRV64] - asm_text: "sc.d t2, t1, (a0)" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a0 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: t1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA, RISCV_FEATURE_IsRV64] - asm_text: "amoadd.d a4, s2, (t5)" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t5 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: s2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA, RISCV_FEATURE_IsRV64] - asm_text: "fcvt.l.s a0, ft0" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV64] - asm_text: "fcvt.s.l ft1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV64] - asm_text: "fmv.d.x fs1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: fs1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD, RISCV_FEATURE_IsRV64] - asm_text: "fmv.x.d a2, fa0" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD, RISCV_FEATURE_IsRV64] - asm_text: "fcvt.w.d a0, ft0" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "fcvt.d.w ft1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "fclass.d a1, fa6" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa6 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "fld fs5, 7(a1)" details: riscv: operands: - type: RISCV_OP_REG reg: fs5 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a1 mem_disp: 0x7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - asm_text: "fsd fs6, 0xe(a2)" details: riscv: operands: - type: RISCV_OP_REG reg: fs6 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a2 mem_disp: 0xe access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [ 0xe8, 0x1f, 0x7d, 0x61, 0x80, 0x25, 0x00, 0x46, 0x88, 0xa2, 0x04, 0xcb, 0x55, 0x13, 0xf2, 0x93, 0x5d, 0x45, 0x19, 0x80, 0x15, 0x68, 0x2a, 0xa4, 0x62, 0x24, 0xa6, 0xff, 0x2a, 0x65, 0x76, 0x86, 0x65, 0xdd, 0x01, 0x00, 0xfd, 0xaf, 0x82, 0x82, 0x11, 0x20, 0x82, 0x94, ] arch: "CS_ARCH_RISCV" options: [CS_OPT_DETAIL, CS_MODE_RISCV_C, CS_MODE_RISCV_F, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.addi4spn a0, sp, 0x3fc" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: sp access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x3fc access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.addi16sp sp, 0x1f0" details: riscv: operands: - type: RISCV_OP_REG reg: sp access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x1f0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.fld fs0, 8(a1)" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a1 mem_disp: 0x8 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - asm_text: "c.lw s0, 8(a2)" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a2 mem_disp: 0x8 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.fsd fa0, 0(a3)" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a3 access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - asm_text: "c.sw s1, 0x10(a4)" details: riscv: operands: - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a4 mem_disp: 0x10 access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.addi t1, -0xb" details: riscv: operands: - type: RISCV_OP_REG reg: t1 access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: -0xb access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.add t2, t3" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: t3 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.li a0, 0x17" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x17 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.srli s0, 6" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x6 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.lui a6, 5" details: riscv: operands: - type: RISCV_OP_REG reg: a6 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x5 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.fsdsp fa0, 8(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: sp mem_disp: 0x8 access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - asm_text: "c.fldsp fs0, 0x18(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: sp mem_disp: 0x18 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - asm_text: "c.fswsp fs1, 0xfc(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fs1 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: sp mem_disp: 0xfc access: CS_AC_WRITE groups: [ RISCV_FEATURE_HasStdExtCOrZcfOrZce, RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV32, ] - asm_text: "c.flwsp fa0, 0x88(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: sp mem_disp: 0x88 access: CS_AC_READ groups: [ RISCV_FEATURE_HasStdExtCOrZcfOrZce, RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV32, ] - asm_text: "c.mv a2, t4" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t4 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.beqz a0, 4120" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 4120 access: CS_AC_READ groups: [ RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca, ] - asm_text: "c.nop" details: groups: [RISCV_FEATURE_HasStdExtCOrZca] - asm_text: "c.j 6178" details: riscv: operands: - type: RISCV_OP_IMM imm: 6178 access: CS_AC_READ groups: [ RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca, ] - asm_text: "c.jr t0" details: riscv: operands: - type: RISCV_OP_REG reg: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_JUMP] - asm_text: "c.jal 4140" details: riscv: operands: - type: RISCV_OP_IMM imm: 4140 access: CS_AC_READ groups: [ RISCV_GRP_CALL, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca, RISCV_FEATURE_IsRV32, ] - asm_text: "c.jalr s1" details: riscv: operands: - type: RISCV_OP_REG reg: s1 access: CS_AC_READ groups: [RISCV_GRP_CALL, RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x37, 0x34, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "lui s0, 3" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x3 access: CS_AC_READ - input: bytes: [0x97, 0x82, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "auipc t0, 8" details: riscv: operands: - type: RISCV_OP_REG reg: t0 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x8 access: CS_AC_READ - input: bytes: [0xef, 0x00, 0x80, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "jal 8" details: riscv: operands: - type: RISCV_OP_IMM imm: 0x8 access: CS_AC_READ groups: [RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0xef, 0xf0, 0x1f, 0xff] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "jal -0x10" details: riscv: operands: - type: RISCV_OP_IMM imm: -0x10 access: CS_AC_READ groups: [RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0xe7, 0x00, 0x45, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "jalr ra, 4(a0)" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x4 access: CS_AC_READ groups: [RISCV_GRP_CALL] - input: bytes: [0xe7, 0x00, 0xc0, 0xff] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "jalr ra, -4(zero)" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: -4 access: CS_AC_READ groups: [RISCV_GRP_CALL] - input: bytes: [0x63, 0x05, 0x41, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "beq sp, tp, 0xa" details: riscv: operands: - type: RISCV_OP_REG reg: sp access: CS_AC_READ - type: RISCV_OP_REG reg: tp access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xa access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0xe3, 0x9d, 0x61, 0xfe] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "bne gp, t1, -6" details: riscv: operands: - type: RISCV_OP_REG reg: gp access: CS_AC_READ - type: RISCV_OP_REG reg: t1 access: CS_AC_READ - type: RISCV_OP_IMM imm: -6 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0x63, 0xca, 0x93, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "blt t2, s1, 0x14" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_READ - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x14 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0x63, 0x53, 0xb5, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "bge a0, a1, 6" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x6 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0x63, 0x65, 0xd6, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "bltu a2, a3, 0xa" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_READ - type: RISCV_OP_REG reg: a3 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xa access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0x63, 0x76, 0xf7, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "bgeu a4, a5, 0xc" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_READ - type: RISCV_OP_REG reg: a5 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xc access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] - input: bytes: [0x03, 0x88, 0x18, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "lb a6, 1(a7)" details: riscv: operands: - type: RISCV_OP_REG reg: a6 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a7 mem_disp: 0x1 access: CS_AC_READ - input: bytes: [0x03, 0x99, 0x49, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "lh s2, 4(s3)" details: riscv: operands: - type: RISCV_OP_REG reg: s2 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s3 mem_disp: 0x4 access: CS_AC_READ - input: bytes: [0x03, 0xaa, 0x6a, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "lw s4, 6(s5)" details: riscv: operands: - type: RISCV_OP_REG reg: s4 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s5 mem_disp: 0x6 access: CS_AC_READ - input: bytes: [0x03, 0xcb, 0x2b, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "lbu s6, 0x12(s7)" details: riscv: operands: - type: RISCV_OP_REG reg: s6 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s7 mem_disp: 0x12 access: CS_AC_READ - input: bytes: [0x03, 0xdc, 0x8c, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "lhu s8, 0x18(s9)" details: riscv: operands: - type: RISCV_OP_REG reg: s8 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: s9 mem_disp: 0x18 access: CS_AC_READ - input: bytes: [0x23, 0x86, 0xad, 0x03] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sb s10, 0x2c(s11)" details: riscv: operands: - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: s11 mem_disp: 0x2c access: CS_AC_WRITE - input: bytes: [0x23, 0x9a, 0xce, 0x03] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sh t3, 0x34(t4)" details: riscv: operands: - type: RISCV_OP_REG reg: t3 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: t4 mem_disp: 0x34 access: CS_AC_WRITE - input: bytes: [0x23, 0x8f, 0xef, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sb t5, 0x1e(t6)" details: riscv: operands: - type: RISCV_OP_REG reg: t5 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: t6 mem_disp: 0x1e access: CS_AC_WRITE - input: bytes: [0x93, 0x00, 0xe0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "addi ra, zero, 0xe" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xe access: CS_AC_READ - input: bytes: [0x13, 0xa1, 0x01, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "slti sp, gp, 0x10" details: riscv: operands: - type: RISCV_OP_REG reg: sp access: CS_AC_WRITE - type: RISCV_OP_REG reg: gp access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x10 access: CS_AC_READ - input: bytes: [0x13, 0xb2, 0x02, 0x7d] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sltiu tp, t0, 0x7d0" details: riscv: operands: - type: RISCV_OP_REG reg: tp access: CS_AC_WRITE - type: RISCV_OP_REG reg: t0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x7d0 access: CS_AC_READ - input: bytes: [0x13, 0xc3, 0x03, 0xdd] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "xori t1, t2, -0x230" details: riscv: operands: - type: RISCV_OP_REG reg: t1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t2 access: CS_AC_READ - type: RISCV_OP_IMM imm: -0x230 access: CS_AC_READ - input: bytes: [0x13, 0xe4, 0xc4, 0x12] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "ori s0, s1, 0x12c" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x12c access: CS_AC_READ - input: bytes: [0x13, 0xf5, 0x85, 0x0c] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "andi a0, a1, 0xc8" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xc8 access: CS_AC_READ - input: bytes: [0x13, 0x96, 0xe6, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "slli a2, a3, 0x1e" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a3 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1e access: CS_AC_READ - input: bytes: [0x13, 0xd7, 0x97, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "srli a4, a5, 0x19" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a5 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x19 access: CS_AC_READ - input: bytes: [0x13, 0xd8, 0xf8, 0x40] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "srai a6, a7, 0xf" details: riscv: operands: - type: RISCV_OP_REG reg: a6 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a7 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0xf access: CS_AC_READ - input: bytes: [0x33, 0x89, 0x49, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "add s2, s3, s4" details: riscv: operands: - type: RISCV_OP_REG reg: s2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s3 access: CS_AC_READ - type: RISCV_OP_REG reg: s4 access: CS_AC_READ - input: bytes: [0xb3, 0x0a, 0x7b, 0x41] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sub s5, s6, s7" details: riscv: operands: - type: RISCV_OP_REG reg: s5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s6 access: CS_AC_READ - type: RISCV_OP_REG reg: s7 access: CS_AC_READ - input: bytes: [0x33, 0xac, 0xac, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "slt s8, s9, s10" details: riscv: operands: - type: RISCV_OP_REG reg: s8 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s9 access: CS_AC_READ - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - input: bytes: [0xb3, 0x3d, 0xde, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sltu s11, t3, t4" details: riscv: operands: - type: RISCV_OP_REG reg: s11 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t3 access: CS_AC_READ - type: RISCV_OP_REG reg: t4 access: CS_AC_READ - input: bytes: [0x33, 0xd2, 0x62, 0x40] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sra tp, t0, t1" details: riscv: operands: - type: RISCV_OP_REG reg: tp access: CS_AC_WRITE - type: RISCV_OP_REG reg: t0 access: CS_AC_READ - type: RISCV_OP_REG reg: t1 access: CS_AC_READ - input: bytes: [0xb3, 0x43, 0x94, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "xor t2, s0, s1" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s0 access: CS_AC_READ - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - input: bytes: [0x33, 0xe5, 0xc5, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "or a0, a1, a2" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_REG reg: a2 access: CS_AC_READ - input: bytes: [0xb3, 0x76, 0xf7, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "and a3, a4, a5" details: riscv: operands: - type: RISCV_OP_REG reg: a3 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a4 access: CS_AC_READ - type: RISCV_OP_REG reg: a5 access: CS_AC_READ - input: bytes: [0xb3, 0x54, 0x39, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "srl s1, s2, s3" details: riscv: operands: - type: RISCV_OP_REG reg: s1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s2 access: CS_AC_READ - type: RISCV_OP_REG reg: s3 access: CS_AC_READ - input: bytes: [0xb3, 0x50, 0x31, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "srl ra, sp, gp" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: sp access: CS_AC_READ - type: RISCV_OP_REG reg: gp access: CS_AC_READ - input: bytes: [0x33, 0x9f, 0x0f, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "sll t5, t6, zero" details: riscv: operands: - type: RISCV_OP_REG reg: t5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t6 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - input: bytes: [0x73, 0x15, 0x04, 0xb0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "csrrw a0, mcycle, s0" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_CSR csr: mcycle access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: s0 access: CS_AC_READ - input: bytes: [0xf3, 0x56, 0x00, 0x10] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "csrrwi a3, sstatus, 0" details: riscv: operands: - type: RISCV_OP_REG reg: a3 access: CS_AC_WRITE - type: RISCV_OP_CSR csr: sstatus access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x33, 0x05, 0x7b, 0x03] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "mul a0, s6, s7" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s6 access: CS_AC_READ - type: RISCV_OP_REG reg: s7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtMOrZmmul] - input: bytes: [0xb3, 0x45, 0x9c, 0x03] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "div a1, s8, s9" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s8 access: CS_AC_READ - type: RISCV_OP_REG reg: s9 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM] - input: bytes: [0x33, 0x66, 0xbd, 0x03] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "rem a2, s10, s11" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - type: RISCV_OP_REG reg: s11 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM] - input: bytes: [0x2f, 0xa4, 0x02, 0x10] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, "CS_MODE_RISCV_A"] address: 0x0 expected: insns: - asm_text: "lr.w s0, (t0)" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA] - input: bytes: [0xaf, 0x23, 0x65, 0x18] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_A] address: 0x0 expected: insns: - asm_text: "sc.w t2, t1, (a0)" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a0 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: t1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA] - input: bytes: [0x2f, 0x27, 0x2f, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_A] address: 0x0 expected: insns: - asm_text: "amoadd.w a4, s2, (t5)" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t5 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: s2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA] - input: bytes: [0x43, 0xf0, 0x20, 0x18] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fmadd.s ft0, ft1, ft2, ft3" details: riscv: operands: - type: RISCV_OP_REG reg: ft0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft1 access: CS_AC_READ - type: RISCV_OP_REG reg: ft2 access: CS_AC_READ - type: RISCV_OP_REG reg: ft3 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0xd3, 0x72, 0x73, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fadd.s ft5, ft6, ft7" details: riscv: operands: - type: RISCV_OP_REG reg: ft5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft6 access: CS_AC_READ - type: RISCV_OP_REG reg: ft7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x53, 0xf4, 0x04, 0x58] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fsqrt.s fs0, fs1" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fs1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x53, 0x85, 0xc5, 0x28] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fmin.s fa0, fa1, fa2" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x53, 0x2e, 0xde, 0xa1] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "feq.s t3, ft8, ft9" details: riscv: operands: - type: RISCV_OP_REG reg: t3 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft8 access: CS_AC_READ - type: RISCV_OP_REG reg: ft9 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0xd3, 0x84, 0x05, 0xf0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fmv.w.x fs1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: fs1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x53, 0x06, 0x05, 0xe0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fmv.x.w a2, fa0" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x53, 0x75, 0x00, 0xc0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fcvt.w.s a0, ft0" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0xd3, 0xf0, 0x05, 0xd0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fcvt.s.w ft1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0xd3, 0x15, 0x08, 0xe0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fclass.s a1, fa6" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa6 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x87, 0xaa, 0x75, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "flw fs5, 7(a1)" details: riscv: operands: - type: RISCV_OP_REG reg: fs5 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a1 mem_disp: 0x7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x27, 0x27, 0x66, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fsw fs6, 0xe(a2)" details: riscv: operands: - type: RISCV_OP_REG reg: fs6 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a2 mem_disp: 0xe access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x43, 0xf0, 0x20, 0x1a] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fmadd.d ft0, ft1, ft2, ft3" details: riscv: operands: - type: RISCV_OP_REG reg: ft0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft1 access: CS_AC_READ - type: RISCV_OP_REG reg: ft2 access: CS_AC_READ - type: RISCV_OP_REG reg: ft3 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0xd3, 0x72, 0x73, 0x02] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fadd.d ft5, ft6, ft7" details: riscv: operands: - type: RISCV_OP_REG reg: ft5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft6 access: CS_AC_READ - type: RISCV_OP_REG reg: ft7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x53, 0xf4, 0x04, 0x5a] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fsqrt.d fs0, fs1" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fs1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x53, 0x85, 0xc5, 0x2a] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fmin.d fa0, fa1, fa2" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x53, 0x2e, 0xde, 0xa3] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "feq.d t3, ft8, ft9" details: riscv: operands: - type: RISCV_OP_REG reg: t3 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft8 access: CS_AC_READ - type: RISCV_OP_REG reg: ft9 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x13, 0x04, 0xa8, 0x7a] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "addi s0, a6, 0x7aa" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a6 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x7aa access: CS_AC_READ - input: bytes: [0xbb, 0x07, 0x9c, 0x02] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "mulw a5, s8, s1" details: riscv: operands: - type: RISCV_OP_REG reg: a5 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s8 access: CS_AC_READ - type: RISCV_OP_REG reg: s1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtMOrZmmul, RISCV_FEATURE_IsRV64] - input: bytes: [0xbb, 0x40, 0x5d, 0x02] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "divw ra, s10, t0" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: s10 access: CS_AC_READ - type: RISCV_OP_REG reg: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM, RISCV_FEATURE_IsRV64] - input: bytes: [0x3b, 0x63, 0xb7, 0x03] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL] address: 0x0 expected: insns: - asm_text: "remw t1, a4, s11" details: riscv: operands: - type: RISCV_OP_REG reg: t1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a4 access: CS_AC_READ - type: RISCV_OP_REG reg: s11 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtM, RISCV_FEATURE_IsRV64] - input: bytes: [0x2f, 0xb4, 0x02, 0x10] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_A] address: 0x0 expected: insns: - asm_text: "lr.d s0, (t0)" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA, RISCV_FEATURE_IsRV64] - input: bytes: [0xaf, 0x33, 0x65, 0x18] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_A] address: 0x0 expected: insns: - asm_text: "sc.d t2, t1, (a0)" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a0 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: t1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA, RISCV_FEATURE_IsRV64] - input: bytes: [0x2f, 0x37, 0x2f, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_A] address: 0x0 expected: insns: - asm_text: "amoadd.d a4, s2, (t5)" details: riscv: operands: - type: RISCV_OP_REG reg: a4 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: t5 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: s2 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtA, RISCV_FEATURE_IsRV64] - input: bytes: [0x53, 0x75, 0x20, 0xc0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fcvt.l.s a0, ft0" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV64] - input: bytes: [0xd3, 0xf0, 0x25, 0xd0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "fcvt.s.l ft1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV64] - input: bytes: [0xd3, 0x84, 0x05, 0xf2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fmv.d.x fs1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: fs1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD, RISCV_FEATURE_IsRV64] - input: bytes: [0x53, 0x06, 0x05, 0xe2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fmv.x.d a2, fa0" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD, RISCV_FEATURE_IsRV64] - input: bytes: [0x53, 0x75, 0x00, 0xc2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fcvt.w.d a0, ft0" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ft0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0xd3, 0x80, 0x05, 0xd2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fcvt.d.w ft1, a1" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0xd3, 0x15, 0x08, 0xe2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fclass.d a1, fa6" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa6 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x87, 0xba, 0x75, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fld fs5, 7(a1)" details: riscv: operands: - type: RISCV_OP_REG reg: fs5 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a1 mem_disp: 0x7 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x27, 0x37, 0x66, 0x01] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "fsd fs6, 0xe(a2)" details: riscv: operands: - type: RISCV_OP_REG reg: fs6 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a2 mem_disp: 0xe access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0xe8, 0x1f] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.addi4spn a0, sp, 0x3fc" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: sp access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x3fc access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x7d, 0x61] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.addi16sp sp, 0x1f0" details: riscv: operands: - type: RISCV_OP_REG reg: sp access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x1f0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x80, 0x25] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "c.fld fs0, 8(a1)" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a1 mem_disp: 0x8 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - input: bytes: [0x00, 0x46] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.lw s0, 8(a2)" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: a2 mem_disp: 0x8 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x88, 0xa2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "c.fsd fa0, 0(a3)" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a3 access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - input: bytes: [0x04, 0xcb] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.sw s1, 0x10(a4)" details: riscv: operands: - type: RISCV_OP_REG reg: s1 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: a4 mem_disp: 0x10 access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x55, 0x13] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.addi t1, -0xb" details: riscv: operands: - type: RISCV_OP_REG reg: t1 access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: -0xb access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0xf2, 0x93] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.add t2, t3" details: riscv: operands: - type: RISCV_OP_REG reg: t2 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: t3 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x5d, 0x45] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.li a0, 0x17" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x17 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x19, 0x80] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.srli s0, 6" details: riscv: operands: - type: RISCV_OP_REG reg: s0 access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x6 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x15, 0x68] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.lui a6, 5" details: riscv: operands: - type: RISCV_OP_REG reg: a6 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x5 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x2a, 0xa4] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "c.fsdsp fa0, 8(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: sp mem_disp: 0x8 access: CS_AC_WRITE groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - input: bytes: [0x62, 0x24] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_MODE_RISCV_D] address: 0x0 expected: insns: - asm_text: "c.fldsp fs0, 0x18(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fs0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: sp mem_disp: 0x18 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZcd, RISCV_FEATURE_HasStdExtD] - input: bytes: [0xa6, 0xff] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "c.fswsp fs1, 0xfc(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fs1 access: CS_AC_READ - type: RISCV_OP_MEM mem_base: sp mem_disp: 0xfc access: CS_AC_WRITE groups: [ RISCV_FEATURE_HasStdExtCOrZcfOrZce, RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV32, ] - input: bytes: [0x2a, 0x65] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_MODE_RISCV_F] address: 0x0 expected: insns: - asm_text: "c.flwsp fa0, 0x88(sp)" details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_MEM mem_base: sp mem_disp: 0x88 access: CS_AC_READ groups: [ RISCV_FEATURE_HasStdExtCOrZcfOrZce, RISCV_FEATURE_HasStdExtF, RISCV_FEATURE_IsRV32, ] - input: bytes: [0x76, 0x86] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.mv a2, t4" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: t4 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x65, 0xdd] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.beqz a0, -8" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: -0x8 access: CS_AC_READ groups: [ RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca, ] - input: bytes: [0x01, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.nop" details: groups: [RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0xfd, 0xaf] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.j 0x7fe" details: riscv: operands: - type: RISCV_OP_IMM imm: 0x7fe access: CS_AC_READ groups: [ RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca, ] - input: bytes: [0x82, 0x82] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.jr t0" details: riscv: operands: - type: RISCV_OP_REG reg: t0 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_JUMP] - input: bytes: [0x11, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.jal 4" details: riscv: operands: - type: RISCV_OP_IMM imm: 0x4 access: CS_AC_READ groups: [ RISCV_GRP_CALL, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca, RISCV_FEATURE_IsRV32, ] - input: bytes: [0x82, 0x94] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x0 expected: insns: - asm_text: "c.jalr s1" details: riscv: operands: - type: RISCV_OP_REG reg: s1 access: CS_AC_READ groups: [RISCV_GRP_CALL, RISCV_FEATURE_HasStdExtCOrZca] - input: bytes: [0x13, 0x85, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "mv a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x13, 0x00, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "nop" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "ret" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x67, 0x80, 0x02, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "jr t0" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: t0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x6f, 0x00, 0x80, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "j 8" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x8 access: CS_AC_READ - input: bytes: [0x63, 0x04, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "beqz a0, 8" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x8 access: CS_AC_READ - input: bytes: [0x63, 0x14, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "bnez a0, 8" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x8 access: CS_AC_READ - input: bytes: [0x13, 0xc5, 0xf5, 0xff] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "not a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: -0x1 access: CS_AC_READ - input: bytes: [0x33, 0x05, 0xb0, 0x40] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "neg a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - input: bytes: [0x13, 0xb5, 0x15, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "seqz a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1 access: CS_AC_READ - input: bytes: [0x33, 0x35, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "snez a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - input: bytes: [0x33, 0xa5, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "sltz a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - input: bytes: [0x33, 0x25, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "sgtz a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x10, 0xf0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.s ft1, -1.0" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: -1.0 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x10, 0xf2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.d ft1, -1.0" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: -1.0 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x10, 0xf4] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.h ft1, -1.0" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: -1.0 access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x10, 0xf0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.s ft1, min" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 1.1754943508222875e-38 access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x13, 0xf0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.s ft1, 0.125" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 0.125 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x18, 0xf0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.s ft1, 1.0" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 1.0 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x1f, 0xf0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.s ft1, inf" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: inf access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x1f, 0xf0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.s ft1, nan" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: nan access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x10, 0xf2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.d ft1, min" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 2.2250738585072014e-308 access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x13, 0xf2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.d ft1, 0.125" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 0.125 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x18, 0xf2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.d ft1, 1.0" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 1.0 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x1f, 0xf2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.d ft1, inf" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: inf access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x1f, 0xf2] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.d ft1, nan" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: nan access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x10, 0xf4] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.h ft1, min" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 6.103515625e-05 access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x13, 0xf4] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.h ft1, 0.125" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 0.125 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x18, 0xf4] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.h ft1, 1.0" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: 1.0 access: CS_AC_READ - input: bytes: [0xd3, 0x00, 0x1f, 0xf4] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.h ft1, inf" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: inf access: CS_AC_READ - input: bytes: [0xd3, 0x80, 0x1f, 0xf4] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fli.h ft1, nan" details: riscv: operands: - type: RISCV_OP_REG reg: ft1 access: CS_AC_WRITE - type: RISCV_OP_FP dimm: nan access: CS_AC_READ - input: bytes: [0x13, 0x85, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "mv a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x13, 0xc5, 0xf5, 0xff] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "not a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: -0x1 access: CS_AC_READ - input: bytes: [0x33, 0x05, 0xb0, 0x40] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "neg a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "ret" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x6f, 0x10, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "j 0x1000" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x1000 access: CS_AC_READ - input: bytes: [0x13, 0x05, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "li a0, 0" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x13, 0x05, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "mv a0, a0" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x67, 0x00, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "jr a0" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x63, 0x08, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x1000 expected: insns: - asm_text: "beqz a0, 0x1010" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ - input: bytes: [0x63, 0x18, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x1000 expected: insns: - asm_text: "bnez a0, 0x1010" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ - input: bytes: [0x53, 0x85, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fmv.s fa0, fa1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x53, 0xa5, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fabs.s fa0, fa1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x53, 0x95, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fneg.s fa0, fa1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtF] - input: bytes: [0x73, 0x25, 0x00, 0x30] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "csrr a0, mstatus" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_CSR csr: mstatus access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - input: bytes: [0x73, 0x10, 0x05, 0x30] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "csrw mstatus, a0" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_CSR csr: mstatus access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - input: bytes: [0x13, 0x05, 0x10, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "li a0, 1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1 access: CS_AC_READ - input: bytes: [0x1b, 0x85, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "sext.w a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ - input: bytes: [0x3b, 0x05, 0xb0, 0x40] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "negw a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - input: bytes: [0x13, 0xb5, 0x15, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "seqz a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1 access: CS_AC_READ - input: bytes: [0x33, 0x35, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "snez a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - input: bytes: [0x33, 0xa5, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "sltz a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - input: bytes: [0x33, 0x25, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "sgtz a0, a1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - input: bytes: [0x63, 0x58, 0xa0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x1000 expected: insns: - asm_text: "blez a0, 0x1010" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ - input: bytes: [0x53, 0x85, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fmv.d fa0, fa1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x73, 0xd0, 0x00, 0x30] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "csrwi mstatus, 1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_CSR csr: mstatus access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x1 access: CS_AC_READ - input: bytes: [0x73, 0xe0, 0x00, 0x30] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "csrsi mstatus, 1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_CSR csr: mstatus access: CS_AC_READ_WRITE - type: RISCV_OP_IMM imm: 0x1 access: CS_AC_READ - input: bytes: [0x63, 0x58, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x1000 expected: insns: - asm_text: "bgez a0, 0x1010" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ - input: bytes: [0x63, 0x48, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x1000 expected: insns: - asm_text: "bltz a0, 0x1010" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ - input: bytes: [0x63, 0x48, 0xa0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x1000 expected: insns: - asm_text: "bgtz a0, 0x1010" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ - input: bytes: [0x53, 0xa5, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fabs.d fa0, fa1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x53, 0x95, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "fneg.d fa0, fa1" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: fa0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ - type: RISCV_OP_REG reg: fa1 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtD] - input: bytes: [0x13, 0x00, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL_REAL] address: 0x0 expected: insns: - asm_text: "nop" is_alias: 1 details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ # ================================== Test cases for RISC-V return instruction idioms ================================== # Standard return: JALR x0, 0(ra) - the canonical return instruction - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr zero, 0(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ groups: [RISCV_GRP_RET] # Compressed return: C.JR ra - compressed form of return - input: bytes: [0x82, 0x80] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_MODE_RISCV_C, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.jr ra" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_RET] # Edge case: JALR x2, 5(ra) - NOT A RETURN # A return MUST have an x0 destination link register and zero offset - input: bytes: [0x67, 0x81, 0x50, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr sp, 5(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: sp access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x5 access: CS_AC_READ groups: [RISCV_GRP_CALL] # Edge case: JALR x0, 5(ra) - NOT A RETURN # A return MUST have a zero offset - input: bytes: [0x67, 0x80, 0x50, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr zero, 5(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x5 access: CS_AC_READ groups: [RISCV_GRP_JUMP] # Edge case: JALR x1, 0(ra) - NOT A RETURN # A return MUST have an x0 destination link register - input: bytes: [0xe7, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr ra, 0(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ groups: [RISCV_GRP_CALL] # Edge case: JALR x0, -4(ra) - NOT A RETURN # A return MUST have a zero offset - input: bytes: [0x67, 0x80, 0xc0, 0xff] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr zero, -4(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: -4 access: CS_AC_READ groups: [RISCV_GRP_JUMP] # Edge case: JALR x5, 0(ra) - NOT A RETURN # A return MUST have an x0 destination link register - input: bytes: [0xe7, 0x82, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr t0, 0(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: t0 access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ groups: [RISCV_GRP_CALL] # RV64 specific: Same tests should work in RV64 mode # Standard return in RV64: JALR x0, 0(ra) - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr zero, 0(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ groups: [RISCV_GRP_RET] # RV64 with compressed: C.JR ra - input: bytes: [0x82, 0x80] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV64, CS_OPT_DETAIL, CS_MODE_RISCV_C, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.jr ra" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_RET] # ================================================================================================== # Tests for +noalias / +noaliascompressed interaction matrix # # Interaction matrix: # (1-) +noalias=false, +noaliascompressed=false (neither option given): # All instruction aliases will be printed (default behavior). # (2-) +noalias=true, +noaliascompressed=false (CS_OPT_SYNTAX_NO_ALIAS_TEXT only): # All instruction aliases will NOT be printed; exact text only. # (3-) +noalias=false, +noaliascompressed=true (CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED only): # Non-compressed instructions show aliases normally; compressed instructions # are printed exactly with no aliases. # (4-) +noalias=true, +noaliascompressed=true # (both CS_OPT_SYNTAX_NO_ALIAS_TEXT & CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED: # All instruction aliases will NOT be printed. (redundant/equivalent to 2) # ================================================================================================== # -------------------------------------------------------------------------------------------------- # CASE 1: +noalias=false, +noaliascompressed=false # => All instruction aliases will be printed # -------------------------------------------------------------------------------------------------- # CASE1-TC1: nop alias (addi zero, zero, 0) - input: bytes: [0x13, 0x00, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "nop" is_alias: 1 # CASE1-TC2: ret alias (jalr zero, 0(ra)) - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "ret" is_alias: 1 # CASE1-TC3: mv alias (addi a0, a1, 0) - input: bytes: [0x13, 0x85, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "mv a0, a1" is_alias: 1 # CASE1-TC4: li alias (addi a0, zero, 5) - input: bytes: [0x13, 0x05, 0x50, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "li a0, 5" is_alias: 1 # CASE1-TC5: beqz alias (beq a0, zero, offset) - input: bytes: [0x63, 0x08, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "beqz a0, 0x1010" is_alias: 1 # CASE1-TC6: bnez alias (bne a0, zero, offset) - input: bytes: [0x63, 0x18, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "bnez a0, 0x1010" is_alias: 1 # CASE1-TC7: bgez alias (bge a0, zero, offset) - input: bytes: [0x63, 0x58, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "bgez a0, 0x1010" is_alias: 1 # CASE1-TC8: bltz alias (blt a0, zero, offset) - input: bytes: [0x63, 0x48, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "bltz a0, 0x1010" is_alias: 1 # CASE1-TC9: bgtz alias (blt zero, a0, offset) - input: bytes: [0x63, 0x48, 0xa0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "bgtz a0, 0x1010" is_alias: 1 # CASE1-TC10: seqz alias (sltiu a0, a1, 1) — set pseudo, alias expected - input: bytes: [0x13, 0xb5, 0x15, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "seqz a0, a1" is_alias: 1 # CASE1-TC11: snez alias (sltu a0, zero, a1) — set pseudo, alias expected - input: bytes: [0x33, 0x35, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "snez a0, a1" is_alias: 1 # CASE1-TC12: csrr alias (csrrs rd, csr, zero) - input: bytes: [0x73, 0x25, 0x40, 0xb0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "csrr a0, mhpmcounter4" is_alias: 1 # CASE1-TC13: fmv.s alias (fsgnj.s fa0, fa1, fa1) - input: bytes: [0x53, 0x85, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "fmv.s fa0, fa1" is_alias: 1 # CASE1-TC14: fabs.s alias (fsgnjx.s fa0, fa1, fa1) - input: bytes: [0x53, 0xa5, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "fabs.s fa0, fa1" is_alias: 1 # CASE1-TC15: fneg.s alias (fsgnjn.s fa0, fa1, fa1) - input: bytes: [0x53, 0x95, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "fneg.s fa0, fa1" is_alias: 1 # CASE1-TC16: c.nop compressed - input: bytes: [0x01, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "nop" is_alias: 1 # CASE1-TC17: c.li compressed — alias form of addi rd, zero, imm - input: bytes: [0x55, 0x45] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "li a0, 0x15" is_alias: 1 # CASE1-TC18: c.mv compressed — alias form of add rd, zero, rs - input: bytes: [0x62, 0x86] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "mv a2, s8" is_alias: 1 # CASE1-TC19: c.beqz compressed — compressed branch alias - input: bytes: [0x89, 0xc1] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "beqz a1, 0x1002" # CASE1-TC20: c.j compressed — compressed jump - input: bytes: [0x01, 0xa0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL] address: 0x1000 expected: insns: - asm_text: "j 0x1000" # -------------------------------------------------------------------------------------------------- # CASE 2: +noalias=true, +noaliascompressed=false # => All instruction aliases will NOT be printed; exact/real text only for all instructions # -------------------------------------------------------------------------------------------------- # CASE2-TC1: nop -> must print as exact: addi zero, zero, 0 - input: bytes: [0x13, 0x00, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "addi zero, zero, 0" # CASE2-TC2: ret -> must print as exact: jalr zero, 0(ra) - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "jalr zero, 0(ra)" details: riscv: operands: - type: RISCV_OP_REG reg: zero access: CS_AC_WRITE - type: RISCV_OP_REG reg: ra access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x0 access: CS_AC_READ groups: [RISCV_GRP_RET] # CASE2-TC3: mv -> must print as exact: addi a0, a1, 0 - input: bytes: [0x13, 0x85, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "addi a0, a1, 0" # CASE2-TC4: li -> must print as exact: addi a0, zero, 5 - input: bytes: [0x13, 0x05, 0x50, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "addi a0, zero, 5" # CASE2-TC5: beqz -> must print as exact: beq a0, zero, offset - input: bytes: [0x63, 0x08, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "beq a0, zero, 0x1010" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] # CASE2-TC6: bnez -> must print as exact: bne a0, zero, offset - input: bytes: [0x63, 0x18, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "bne a0, zero, 0x1010" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_READ - type: RISCV_OP_REG reg: zero access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1010 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE] # CASE2-TC7: bgez -> must print as exact: bge a0, zero, offset - input: bytes: [0x63, 0x58, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "bge a0, zero, 0x1010" # CASE2-TC8: bltz -> must print as exact: blt a0, zero, offset - input: bytes: [0x63, 0x48, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "blt a0, zero, 0x1010" # CASE2-TC9: bgtz -> must print as exact: blt zero, a0, offset - input: bytes: [0x63, 0x48, 0xa0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "blt zero, a0, 0x1010" # CASE2-TC10: seqz -> must print as exact: sltiu a0, a0, 1 - input: bytes: [0x13, 0x35, 0x15, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "sltiu a0, a0, 1" # CASE2-TC11: snez -> must print as exact: sltu a0, zero, a1 - input: bytes: [0x33, 0x35, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "sltu a0, zero, a1" # CASE2-TC12: csrr -> must print as exact: csrrs a0, mhpmcounter4, zero - input: bytes: [0x73, 0x25, 0x40, 0xb0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "csrrs a0, mhpmcounter4, zero" # CASE2-TC13: fmv.s -> must print as exact: fsgnj.s fa0, fa1, fa1 - input: bytes: [0x53, 0x85, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "fsgnj.s fa0, fa1, fa1" # CASE2-TC14: fabs.s -> must print as exact: fsgnjx.s fa0, fa1, fa1 - input: bytes: [0x53, 0xa5, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "fsgnjx.s fa0, fa1, fa1" # CASE2-TC15: fneg.s -> must print as exact: fsgnjn.s fa0, fa1, fa1 - input: bytes: [0x53, 0x95, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "fsgnjn.s fa0, fa1, fa1" # CASE2-TC16: fmv.d -> must print as exact: fsgnj.d fa0, fa1, fa1 - input: bytes: [0x53, 0x85, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "fsgnj.d fa0, fa1, fa1" # CASE2-TC17: fabs.d -> must print as exact: fsgnjx.d fa0, fa1, fa1 - input: bytes: [0x53, 0xa5, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "fsgnjx.d fa0, fa1, fa1" # CASE2-TC18: compressed c.nop with +noalias — still printed as c.nop (no further expansion) - input: bytes: [0x01, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.nop" # CASE2-TC19: compressed c.li with +noalias — exact text, not expanded to li alias - input: bytes: [0x55, 0x45] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.li a0, 0x15" # CASE2-TC20: compressed c.mv with +noalias — exact text, not expanded to mv alias - input: bytes: [0x62, 0x86] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.mv a2, s8" # CASE2-TC21: compressed c.beqz with +noalias — exact, not expanded - input: bytes: [0x89, 0xc1] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.beqz a1, 0x1002" # CASE2-TC22: compressed c.jr with +noalias — exact text - input: bytes: [0x82, 0x80] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT] address: 0x1000 expected: insns: - asm_text: "c.jr ra" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_RET] # -------------------------------------------------------------------------------------------------- # CASE 3: +noalias=false (not given), +noaliascompressed=true (CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED) # => Non-compressed instructions show aliases normally; # compressed instructions are printed exactly with no aliases. # -------------------------------------------------------------------------------------------------- # CASE3-TC1: nop (non-compressed) — alias printed - input: bytes: [0x13, 0x00, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "nop" is_alias: 1 # CASE3-TC2: ret (non-compressed) — alias printed - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "ret" is_alias: 1 # CASE3-TC3: mv (non-compressed) — alias printed - input: bytes: [0x13, 0x85, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "mv a0, a1" is_alias: 1 # CASE3-TC4: li (non-compressed) — alias printed - input: bytes: [0x13, 0x05, 0x50, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "li a0, 5" is_alias: 1 # CASE3-TC5: beqz (non-compressed) — alias printed - input: bytes: [0x63, 0x08, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "beqz a0, 0x1010" is_alias: 1 # CASE3-TC6: bnez (non-compressed) — alias printed - input: bytes: [0x63, 0x18, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "bnez a0, 0x1010" is_alias: 1 # CASE3-TC7: bgez (non-compressed) — alias printed - input: bytes: [0x63, 0x58, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "bgez a0, 0x1010" is_alias: 1 # CASE3-TC8: bltz (non-compressed) — alias printed - input: bytes: [0x63, 0x48, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "bltz a0, 0x1010" is_alias: 1 # CASE3-TC9: seqz (non-compressed) — alias printed - input: bytes: [0x13, 0x35, 0x15, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "seqz a0, a0" is_alias: 1 # CASE3-TC10: snez (non-compressed) — alias printed - input: bytes: [0x33, 0x35, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "snez a0, a1" is_alias: 1 # CASE3-TC11: csrr (non-compressed) — alias printed - input: bytes: [0x73, 0x25, 0x40, 0xb0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "csrr a0, mhpmcounter4" is_alias: 1 # CASE3-TC12: fmv.s (non-compressed) — alias printed - input: bytes: [0x53, 0x85, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "fmv.s fa0, fa1" is_alias: 1 # CASE3-TC13: fabs.d (non-compressed) — alias printed - input: bytes: [0x53, 0xa5, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "fabs.d fa0, fa1" is_alias: 1 # CASE3-TC14: fneg.d (non-compressed) — alias printed - input: bytes: [0x53, 0x95, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "fneg.d fa0, fa1" is_alias: 1 # CASE3-TC15: c.nop (COMPRESSED) printed exactly as c.nop - input: bytes: [0x01, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.nop" is_alias: 0 details: groups: [RISCV_FEATURE_HasStdExtCOrZca] # CASE3-TC16: c.li (COMPRESSED) printed exactly as c.li, NOT as "li" - input: bytes: [0x55, 0x45] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.li a0, 0x15" details: riscv: operands: - type: RISCV_OP_REG reg: a0 access: CS_AC_WRITE - type: RISCV_OP_IMM imm: 0x15 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] # CASE3-TC17: c.mv (COMPRESSED) printed exactly as c.mv, NOT as "mv" - input: bytes: [0x62, 0x86] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.mv a2, s8" details: riscv: operands: - type: RISCV_OP_REG reg: a2 access: CS_AC_WRITE - type: RISCV_OP_REG reg: s8 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] # CASE3-TC18: c.add (COMPRESSED) printed exactly as c.add - input: bytes: [0xf2, 0x97] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.add a5, t3" details: riscv: operands: - type: RISCV_OP_REG reg: a5 access: CS_AC_READ_WRITE - type: RISCV_OP_REG reg: t3 access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca] # CASE3-TC19: c.beqz (COMPRESSED) printed exactly as c.beqz, NOT as "beqz" - input: bytes: [0x89, 0xc1] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.beqz a1, 0x1002" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1002 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca] # CASE3-TC20: c.bnez (COMPRESSED) printed exactly as c.bnez, NOT as "bnez" - input: bytes: [0x89, 0xe1] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.bnez a1, 0x1002" details: riscv: operands: - type: RISCV_OP_REG reg: a1 access: CS_AC_READ - type: RISCV_OP_IMM imm: 0x1002 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca] # CASE3-TC21: c.j (COMPRESSED) printed exactly as c.j, NOT as "j" - input: bytes: [0x01, 0xa0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.j 0x1000" details: riscv: operands: - type: RISCV_OP_IMM imm: 0x1000 access: CS_AC_READ groups: [RISCV_GRP_JUMP, RISCV_GRP_BRANCH_RELATIVE, RISCV_FEATURE_HasStdExtCOrZca] # CASE3-TC22: c.jr ra (COMPRESSED) printed exactly as c.jr, NOT as "ret" - input: bytes: [0x82, 0x80] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.jr ra" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_RET] # CASE3-TC23: Mixed in one test — non-compressed aliases print, compressed prints exactly. - input: bytes: [0x13, 0x00, 0x00, 0x00, 0x01, 0x00, 0x13, 0x85, 0x05, 0x00, 0x55, 0x45] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "nop" is_alias: 1 - asm_text: "c.nop" - asm_text: "mv a0, a1" is_alias: 1 - asm_text: "c.li a0, 0x15" # -------------------------------------------------------------------------------------------------- # CASE 4: +noalias=true, +noaliascompressed=true [redundant — equivalent to CASE 2] # => All instruction aliases will NOT be printed (same as +noalias=true alone) # -------------------------------------------------------------------------------------------------- # CASE4-TC1: nop (non-compressed) with both flags — printed as exact "addi zero, zero, 0" - input: bytes: [0x13, 0x00, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "addi zero, zero, 0" # CASE4-TC2: ret (non-compressed) with both flags — printed as exact "jalr zero, 0(ra)" - input: bytes: [0x67, 0x80, 0x00, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "jalr zero, 0(ra)" # CASE4-TC3: mv (non-compressed) with both flags — printed as exact "addi a0, a1, 0" - input: bytes: [0x13, 0x85, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "addi a0, a1, 0" # CASE4-TC4: li (non-compressed) with both flags — printed as exact "addi a0, zero, 5" - input: bytes: [0x13, 0x05, 0x50, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "addi a0, zero, 5" # CASE4-TC5: beqz (non-compressed) with both flags — exact: "beq a0, zero, 0x1010" - input: bytes: [0x63, 0x08, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "beq a0, zero, 0x1010" # CASE4-TC6: bltz (non-compressed) with both flags — exact: "blt a0, zero, 0x1010" - input: bytes: [0x63, 0x48, 0x05, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "blt a0, zero, 0x1010" # CASE4-TC7: seqz (non-compressed) with both flags — exact: "sltiu a0, a1, 1" - input: bytes: [0x13, 0x35, 0x15, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "sltiu a0, a0, 1" # CASE4-TC8: csrr (non-compressed) with both flags — exact: "csrrs a0, mstatus, zero" - input: bytes: [0x73, 0x25, 0x40, 0xb0] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "csrrs a0, mhpmcounter4, zero" # CASE4-TC9: fmv.s (non-compressed FP) with both flags — exact: "fsgnj.s fa0, fa1, fa1" - input: bytes: [0x53, 0x85, 0xb5, 0x20] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_F, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "fsgnj.s fa0, fa1, fa1" # CASE4-TC10: fabs.d (non-compressed FP) with both flags — exact: "fsgnjx.d fa0, fa1, fa1" - input: bytes: [0x53, 0xa5, 0xb5, 0x22] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_D, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "fsgnjx.d fa0, fa1, fa1" # CASE4-TC11: c.nop (COMPRESSED) with both flags — exact: c.nop (no alias either way) - input: bytes: [0x01, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.nop" # CASE4-TC12: c.li (COMPRESSED) with both flags — exact: c.li (not expanded to li or addi) - input: bytes: [0x55, 0x45] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.li a0, 0x15" # CASE4-TC13: c.mv (COMPRESSED) with both flags — exact: c.mv (not expanded to mv or add) - input: bytes: [0x62, 0x86] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.mv a2, s8" # CASE4-TC14: c.jr ra (COMPRESSED) with both flags — exact: c.jr ra (not expanded to ret) - input: bytes: [0x82, 0x80] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.jr ra" details: riscv: operands: - type: RISCV_OP_REG reg: ra access: CS_AC_READ groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_RET] # CASE4-TC15: c.beqz (COMPRESSED) with both flags — exact: c.beqz - input: bytes: [0x89, 0xc1] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "c.beqz a1, 0x1002" # CASE4-TC16: Verify redundancy — both flags give same result as +noalias alone for non-compressed. # snez (non-compressed) with both flags — exact: "sltu a0, zero, a1" - input: bytes: [0x33, 0x35, 0xb0, 0x00] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "sltu a0, zero, a1" # CASE4-TC17: Mixed — addi a0, a1, 0 (non-compressed mv) + c.li (compressed) # Both flags: addi printed as "addi a0, a1, 0" (no mv alias), c.li printed as c.li - input: bytes: [0x13, 0x85, 0x05, 0x00, 0x55, 0x45] arch: "CS_ARCH_RISCV" options: [CS_MODE_RISCV32, CS_MODE_RISCV_C, CS_OPT_DETAIL, CS_OPT_SYNTAX_NO_ALIAS_TEXT, CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED] address: 0x1000 expected: insns: - asm_text: "addi a0, a1, 0" - asm_text: "c.li a0, 0x15"