186 lines
6.0 KiB
C
186 lines
6.0 KiB
C
#include "platform.h"
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struct platform platforms[] = {
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{ // item 0
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CS_ARCH_X86, CS_MODE_32, "X86 32 (Intel syntax)", "x32" },
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{ // item 1
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CS_ARCH_X86, CS_MODE_64, "X86 64 (Intel syntax)", "x64" },
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{ // item 2
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CS_ARCH_ARM, CS_MODE_ARM, "ARM", "arm" },
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{ // item 3
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CS_ARCH_ARM, CS_MODE_THUMB, "THUMB", "thumb" },
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{ // item 4
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CS_ARCH_ARM, (cs_mode)(CS_MODE_ARM + CS_MODE_V8), "Arm-V8", "armv8" },
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{ // item 5
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CS_ARCH_ARM, (cs_mode)(CS_MODE_THUMB + CS_MODE_V8), "THUMB+V8",
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"thumbv8" },
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{ // item 6
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CS_ARCH_ARM, (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
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"Thumb-MClass", "cortexm" },
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{ // item 7
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CS_ARCH_AARCH64, (cs_mode)0, "AARCH64", "aarch64" },
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{ // item 8
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CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
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"MIPS-32 (Big-endian)", "mipsbe" },
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{ // item 9
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CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO),
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"MIPS-32 (micro)", "mipsmicro" },
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{ //item 10
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CS_ARCH_MIPS, CS_MODE_MIPS64, "MIPS-64-EL (Little-endian)",
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"mips64" },
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{ //item 11
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CS_ARCH_MIPS, CS_MODE_MIPS32, "MIPS-32-EL (Little-endian)", "mips" },
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{ //item 12
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CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN),
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"MIPS-64 (Big-endian)", "mips64be" },
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{ //item 13
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
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"MIPS-32 | Micro (Big-endian)", "mipsbemicro" },
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{ //item 14
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CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, "PPC-64", "ppc64be" },
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{ //item 15
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CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", "sparc" },
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{ //item 16
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CS_ARCH_SPARC, (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), "SparcV9",
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"sparcv9" },
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{ //item 17
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CS_ARCH_SYSTEMZ, (cs_mode)CS_MODE_BIG_ENDIAN, "SystemZ", "systemz" },
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{ //item 18
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CS_ARCH_XCORE, (cs_mode)0, "XCore", "xcore" },
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{ //item 19
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CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
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"MIPS-32R6 (Big-endian)", "mipsbe32r6" },
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{ //item 20
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
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"MIPS-32R6 (Micro+Big-endian)", "mipsbe32r6micro" },
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{ //item 21
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CS_ARCH_MIPS, CS_MODE_MIPS32R6, "MIPS-32R6 (Little-endian)",
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"mips32r6" },
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{ //item 22
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CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO),
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"MIPS-32R6 (Micro+Little-endian)", "mips32r6micro" },
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{ //item 23
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CS_ARCH_M68K, (cs_mode)0, "M68K", "m68k" },
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{ //item 24
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6809, "M680X_M6809", "m6809" },
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{ //item 25
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CS_ARCH_EVM, (cs_mode)0, "EVM", "evm" },
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{ //item 26
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CS_ARCH_MOS65XX, (cs_mode)0, "MOS65XX", "mos65xx" },
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{ //item 27
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CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN, "tms320c64x", "tms320c64x" },
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{ //item 28
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CS_ARCH_WASM, (cs_mode)0, "WASM", "wasm" },
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{ //item 29
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CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC, "cBPF",
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"bpf" },
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{ //item 30
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CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, "eBPF",
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"ebpf" },
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{ //item 31
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CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC, "cBPF",
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"bpfbe" },
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{ //item 32
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CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED, "eBPF",
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"ebpfbe" },
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{ // item 33
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CS_ARCH_X86, CS_MODE_16, "X86 16 (Intel syntax)", "x16" },
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{ // item 34
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CS_ARCH_M68K, CS_MODE_M68K_040, "M68K mode 40", "m68k40" },
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{ //item 35
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6800, "M680X_M6800", "m6800" },
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{ //item 36
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6801, "M680X_M6801", "m6801" },
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{ //item 37
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6805, "M680X_M6805", "m6805" },
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{ //item 38
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6808, "M680X_M6808", "m6808" },
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{ //item 39
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6811, "M680X_M6811", "m6811" },
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{ //item 40
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_CPU12, "M680X_cpu12", "cpu12" },
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{ //item 41
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6301, "M680X_M6808", "hd6301" },
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{ //item 42
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6309, "M680X_M6808", "hd6309" },
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{ //item 43
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CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_HCS08, "M680X_M6808", "hcs08" },
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{ CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_RS08, "M680X_RS08", "rs08" },
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{ CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_HCS12X, "M680X_HCS12X",
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"hcs12x" },
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{ //item 44
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CS_ARCH_RISCV, CS_MODE_RISCV32, "RISCV", "riscv32" },
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{ //item 45
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CS_ARCH_RISCV, CS_MODE_RISCV64, "RISCV", "riscv64" },
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{ //item 46
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CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX, "ppc+qpx",
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"ppc64beqpx" },
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{ //item 46
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CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_PS, "ppc+ps",
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"ppc32beps" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_110, "TRICORE",
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"tc110" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_120, "TRICORE",
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"tc120" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_130, "TRICORE",
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"tc130" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_131, "TRICORE",
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"tc131" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_160, "TRICORE",
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"tc160" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_161, "TRICORE",
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"tc161" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_162, "TRICORE",
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"tc162" },
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{ CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_180, "TRICORE",
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"tc180" },
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{ CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32, "XTENSA ESP32", "esp32" },
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{ CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S2, "XTENSA ESP32S2", "esp32s2" },
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{ CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP8266, "XTENSA ESP8266", "esp8266" },
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// dummy entry to mark the end of this array.
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// DO NOT DELETE THIS
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{
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0,
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0,
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NULL,
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NULL,
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},
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};
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// get length of platforms[]
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unsigned int platform_len(void)
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{
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unsigned int c;
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for (c = 0; platforms[c].cstoolname; c++)
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;
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return c;
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}
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// get platform entry encoded n (first byte for input data of OSS fuzz)
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unsigned int get_platform_entry(uint8_t n)
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{
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unsigned len = platform_len();
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if (len == 0) {
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return 0;
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}
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return n % len;
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}
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// get cstoolname from encoded n (first byte for input data of OSS fuzz)
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const char *get_platform_cstoolname(uint8_t n)
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{
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return platforms[get_platform_entry(n)].cstoolname;
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}
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