ircolib/tests/MC/RISCV/xtheadcmo_valid_riscv32_riscv_xtheadcmo.txt.yaml

test_cases:
  -
    input:
      bytes: [ 0x0b, 0x00, 0x18, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.csw a6"

  -
    input:
      bytes: [ 0x0b, 0x80, 0x22, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.isw t0"

  -
    input:
      bytes: [ 0x0b, 0x80, 0x38, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.cisw a7"

  -
    input:
      bytes: [ 0x0b, 0x80, 0x43, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.cval1 t2"

  -
    input:
      bytes: [ 0x0b, 0x80, 0x56, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.cva a3"

  -
    input:
      bytes: [ 0x0b, 0x80, 0x67, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.iva a5"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x77, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.civa a4"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x83, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.cpal1 t1"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x95, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.cpa a0"

  -
    input:
      bytes: [ 0x0b, 0x00, 0xa6, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.ipa a2"

  -
    input:
      bytes: [ 0x0b, 0x80, 0xb5, 0x02 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.cipa a1"

  -
    input:
      bytes: [ 0x0b, 0x80, 0x0e, 0x03 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.icache.iva t4"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x8e, 0x03 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.icache.ipa t3"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x10, 0x00 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.call"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.iall"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.dcache.ciall"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.icache.iall"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.icache.ialls"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.l2cache.call"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x60, 0x01 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.l2cache.iall"

  -
    input:
      bytes: [ 0x0b, 0x00, 0x70, 0x01 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XTHEADCMO" ]
    expected:
      insns:
        -
          asm_text: "th.l2cache.ciall"