2799 lines
121 KiB
C
2799 lines
121 KiB
C
#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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enum {
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RISCV_NoRegister,
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RISCV_FFLAGS = 1,
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RISCV_FRM = 2,
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RISCV_SSP = 3,
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RISCV_VL = 4,
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RISCV_VLENB = 5,
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RISCV_VTYPE = 6,
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RISCV_VXRM = 7,
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RISCV_VXSAT = 8,
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RISCV_DUMMY_REG_PAIR_WITH_X0 = 9,
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RISCV_V0 = 10,
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RISCV_V1 = 11,
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RISCV_V2 = 12,
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RISCV_V3 = 13,
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RISCV_V4 = 14,
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RISCV_V5 = 15,
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RISCV_V6 = 16,
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RISCV_V7 = 17,
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RISCV_V8 = 18,
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RISCV_V9 = 19,
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RISCV_V10 = 20,
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RISCV_V11 = 21,
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RISCV_V12 = 22,
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RISCV_V13 = 23,
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RISCV_V14 = 24,
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RISCV_V15 = 25,
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RISCV_V16 = 26,
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RISCV_V17 = 27,
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RISCV_V18 = 28,
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RISCV_V19 = 29,
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RISCV_V20 = 30,
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RISCV_V21 = 31,
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RISCV_V22 = 32,
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RISCV_V23 = 33,
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RISCV_V24 = 34,
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RISCV_V25 = 35,
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RISCV_V26 = 36,
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RISCV_V27 = 37,
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RISCV_V28 = 38,
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RISCV_V29 = 39,
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RISCV_V30 = 40,
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RISCV_V31 = 41,
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RISCV_X0 = 42,
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RISCV_X1 = 43,
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RISCV_X2 = 44,
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RISCV_X3 = 45,
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RISCV_X4 = 46,
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RISCV_X5 = 47,
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RISCV_X6 = 48,
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RISCV_X7 = 49,
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RISCV_X8 = 50,
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RISCV_X9 = 51,
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RISCV_X10 = 52,
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RISCV_X11 = 53,
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RISCV_X12 = 54,
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RISCV_X13 = 55,
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RISCV_X14 = 56,
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RISCV_X15 = 57,
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RISCV_X16 = 58,
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RISCV_X17 = 59,
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RISCV_X18 = 60,
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RISCV_X19 = 61,
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RISCV_X20 = 62,
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RISCV_X21 = 63,
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RISCV_X22 = 64,
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RISCV_X23 = 65,
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RISCV_X24 = 66,
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RISCV_X25 = 67,
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RISCV_X26 = 68,
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RISCV_X27 = 69,
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RISCV_X28 = 70,
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RISCV_X29 = 71,
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RISCV_X30 = 72,
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RISCV_X31 = 73,
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RISCV_F0_D = 74,
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RISCV_F1_D = 75,
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RISCV_F2_D = 76,
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RISCV_F3_D = 77,
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RISCV_F4_D = 78,
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RISCV_F5_D = 79,
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RISCV_F6_D = 80,
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RISCV_F7_D = 81,
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RISCV_F8_D = 82,
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RISCV_F9_D = 83,
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RISCV_F10_D = 84,
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RISCV_F11_D = 85,
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RISCV_F12_D = 86,
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RISCV_F13_D = 87,
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RISCV_F14_D = 88,
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RISCV_F15_D = 89,
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RISCV_F16_D = 90,
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RISCV_F17_D = 91,
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RISCV_F18_D = 92,
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RISCV_F19_D = 93,
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RISCV_F20_D = 94,
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RISCV_F21_D = 95,
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RISCV_F22_D = 96,
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RISCV_F23_D = 97,
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RISCV_F24_D = 98,
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RISCV_F25_D = 99,
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RISCV_F26_D = 100,
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RISCV_F27_D = 101,
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RISCV_F28_D = 102,
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RISCV_F29_D = 103,
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RISCV_F30_D = 104,
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RISCV_F31_D = 105,
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RISCV_F0_F = 106,
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RISCV_F1_F = 107,
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RISCV_F2_F = 108,
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RISCV_F3_F = 109,
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RISCV_F4_F = 110,
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RISCV_F5_F = 111,
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RISCV_F6_F = 112,
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RISCV_F7_F = 113,
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RISCV_F8_F = 114,
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RISCV_F9_F = 115,
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RISCV_F10_F = 116,
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RISCV_F11_F = 117,
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RISCV_F12_F = 118,
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RISCV_F13_F = 119,
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RISCV_F14_F = 120,
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RISCV_F15_F = 121,
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RISCV_F16_F = 122,
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RISCV_F17_F = 123,
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RISCV_F18_F = 124,
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RISCV_F19_F = 125,
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RISCV_F20_F = 126,
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RISCV_F21_F = 127,
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RISCV_F22_F = 128,
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RISCV_F23_F = 129,
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RISCV_F24_F = 130,
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RISCV_F25_F = 131,
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RISCV_F26_F = 132,
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RISCV_F27_F = 133,
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RISCV_F28_F = 134,
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RISCV_F29_F = 135,
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RISCV_F30_F = 136,
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RISCV_F31_F = 137,
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RISCV_F0_H = 138,
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RISCV_F1_H = 139,
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RISCV_F2_H = 140,
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RISCV_F3_H = 141,
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RISCV_F4_H = 142,
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RISCV_F5_H = 143,
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RISCV_F6_H = 144,
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RISCV_F7_H = 145,
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RISCV_F8_H = 146,
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RISCV_F9_H = 147,
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RISCV_F10_H = 148,
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RISCV_F11_H = 149,
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RISCV_F12_H = 150,
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RISCV_F13_H = 151,
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RISCV_F14_H = 152,
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RISCV_F15_H = 153,
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RISCV_F16_H = 154,
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RISCV_F17_H = 155,
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RISCV_F18_H = 156,
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RISCV_F19_H = 157,
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RISCV_F20_H = 158,
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RISCV_F21_H = 159,
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RISCV_F22_H = 160,
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RISCV_F23_H = 161,
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RISCV_F24_H = 162,
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RISCV_F25_H = 163,
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RISCV_F26_H = 164,
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RISCV_F27_H = 165,
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RISCV_F28_H = 166,
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RISCV_F29_H = 167,
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RISCV_F30_H = 168,
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RISCV_F31_H = 169,
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RISCV_X0_Pair = 170,
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RISCV_V0M2 = 171,
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RISCV_V0M4 = 172,
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RISCV_V0M8 = 173,
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RISCV_V2M2 = 174,
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RISCV_V4M2 = 175,
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RISCV_V4M4 = 176,
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RISCV_V6M2 = 177,
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RISCV_V8M2 = 178,
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RISCV_V8M4 = 179,
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RISCV_V8M8 = 180,
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RISCV_V10M2 = 181,
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RISCV_V12M2 = 182,
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RISCV_V12M4 = 183,
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RISCV_V14M2 = 184,
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RISCV_V16M2 = 185,
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RISCV_V16M4 = 186,
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RISCV_V16M8 = 187,
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RISCV_V18M2 = 188,
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RISCV_V20M2 = 189,
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RISCV_V20M4 = 190,
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RISCV_V22M2 = 191,
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RISCV_V24M2 = 192,
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RISCV_V24M4 = 193,
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RISCV_V24M8 = 194,
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RISCV_V26M2 = 195,
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RISCV_V28M2 = 196,
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RISCV_V28M4 = 197,
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RISCV_V30M2 = 198,
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RISCV_X2_X3 = 199,
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RISCV_X4_X5 = 200,
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RISCV_X6_X7 = 201,
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RISCV_X8_X9 = 202,
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RISCV_X10_X11 = 203,
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RISCV_X12_X13 = 204,
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RISCV_X14_X15 = 205,
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RISCV_X16_X17 = 206,
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RISCV_X18_X19 = 207,
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RISCV_X20_X21 = 208,
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RISCV_X22_X23 = 209,
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RISCV_X24_X25 = 210,
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RISCV_X26_X27 = 211,
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RISCV_X28_X29 = 212,
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RISCV_X30_X31 = 213,
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RISCV_V1_V2 = 214,
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RISCV_V2_V3 = 215,
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RISCV_V3_V4 = 216,
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RISCV_V4_V5 = 217,
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RISCV_V5_V6 = 218,
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RISCV_V6_V7 = 219,
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RISCV_V7_V8 = 220,
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RISCV_V8_V9 = 221,
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RISCV_V9_V10 = 222,
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RISCV_V10_V11 = 223,
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RISCV_V11_V12 = 224,
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RISCV_V12_V13 = 225,
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RISCV_V13_V14 = 226,
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RISCV_V14_V15 = 227,
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RISCV_V15_V16 = 228,
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RISCV_V16_V17 = 229,
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RISCV_V17_V18 = 230,
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RISCV_V18_V19 = 231,
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RISCV_V19_V20 = 232,
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RISCV_V20_V21 = 233,
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RISCV_V21_V22 = 234,
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RISCV_V22_V23 = 235,
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RISCV_V23_V24 = 236,
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RISCV_V24_V25 = 237,
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RISCV_V25_V26 = 238,
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RISCV_V26_V27 = 239,
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RISCV_V27_V28 = 240,
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RISCV_V28_V29 = 241,
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RISCV_V29_V30 = 242,
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RISCV_V30_V31 = 243,
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RISCV_V0_V1 = 244,
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RISCV_V2M2_V4M2 = 245,
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RISCV_V4M2_V6M2 = 246,
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RISCV_V6M2_V8M2 = 247,
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RISCV_V8M2_V10M2 = 248,
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RISCV_V10M2_V12M2 = 249,
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RISCV_V12M2_V14M2 = 250,
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RISCV_V14M2_V16M2 = 251,
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RISCV_V16M2_V18M2 = 252,
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RISCV_V18M2_V20M2 = 253,
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RISCV_V20M2_V22M2 = 254,
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RISCV_V22M2_V24M2 = 255,
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RISCV_V24M2_V26M2 = 256,
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RISCV_V26M2_V28M2 = 257,
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RISCV_V28M2_V30M2 = 258,
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RISCV_V0M2_V2M2 = 259,
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RISCV_V4M4_V8M4 = 260,
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RISCV_V8M4_V12M4 = 261,
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RISCV_V12M4_V16M4 = 262,
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RISCV_V16M4_V20M4 = 263,
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RISCV_V20M4_V24M4 = 264,
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RISCV_V24M4_V28M4 = 265,
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RISCV_V0M4_V4M4 = 266,
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RISCV_V1_V2_V3 = 267,
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RISCV_V2_V3_V4 = 268,
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RISCV_V3_V4_V5 = 269,
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RISCV_V4_V5_V6 = 270,
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RISCV_V5_V6_V7 = 271,
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RISCV_V6_V7_V8 = 272,
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RISCV_V7_V8_V9 = 273,
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RISCV_V8_V9_V10 = 274,
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RISCV_V9_V10_V11 = 275,
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RISCV_V10_V11_V12 = 276,
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RISCV_V11_V12_V13 = 277,
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RISCV_V12_V13_V14 = 278,
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RISCV_V13_V14_V15 = 279,
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RISCV_V14_V15_V16 = 280,
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RISCV_V15_V16_V17 = 281,
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RISCV_V16_V17_V18 = 282,
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RISCV_V17_V18_V19 = 283,
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RISCV_V18_V19_V20 = 284,
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RISCV_V19_V20_V21 = 285,
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RISCV_V20_V21_V22 = 286,
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RISCV_V21_V22_V23 = 287,
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RISCV_V22_V23_V24 = 288,
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RISCV_V23_V24_V25 = 289,
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RISCV_V24_V25_V26 = 290,
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RISCV_V25_V26_V27 = 291,
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RISCV_V26_V27_V28 = 292,
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RISCV_V27_V28_V29 = 293,
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RISCV_V28_V29_V30 = 294,
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RISCV_V29_V30_V31 = 295,
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RISCV_V0_V1_V2 = 296,
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RISCV_V2M2_V4M2_V6M2 = 297,
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RISCV_V4M2_V6M2_V8M2 = 298,
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RISCV_V6M2_V8M2_V10M2 = 299,
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RISCV_V8M2_V10M2_V12M2 = 300,
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RISCV_V10M2_V12M2_V14M2 = 301,
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RISCV_V12M2_V14M2_V16M2 = 302,
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RISCV_V14M2_V16M2_V18M2 = 303,
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RISCV_V16M2_V18M2_V20M2 = 304,
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RISCV_V18M2_V20M2_V22M2 = 305,
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RISCV_V20M2_V22M2_V24M2 = 306,
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RISCV_V22M2_V24M2_V26M2 = 307,
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RISCV_V24M2_V26M2_V28M2 = 308,
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RISCV_V26M2_V28M2_V30M2 = 309,
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RISCV_V0M2_V2M2_V4M2 = 310,
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RISCV_V1_V2_V3_V4 = 311,
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RISCV_V2_V3_V4_V5 = 312,
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RISCV_V3_V4_V5_V6 = 313,
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RISCV_V4_V5_V6_V7 = 314,
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RISCV_V5_V6_V7_V8 = 315,
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RISCV_V6_V7_V8_V9 = 316,
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RISCV_V7_V8_V9_V10 = 317,
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RISCV_V8_V9_V10_V11 = 318,
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RISCV_V9_V10_V11_V12 = 319,
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RISCV_V10_V11_V12_V13 = 320,
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RISCV_V11_V12_V13_V14 = 321,
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RISCV_V12_V13_V14_V15 = 322,
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RISCV_V13_V14_V15_V16 = 323,
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RISCV_V14_V15_V16_V17 = 324,
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RISCV_V15_V16_V17_V18 = 325,
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RISCV_V16_V17_V18_V19 = 326,
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RISCV_V17_V18_V19_V20 = 327,
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RISCV_V18_V19_V20_V21 = 328,
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RISCV_V19_V20_V21_V22 = 329,
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RISCV_V20_V21_V22_V23 = 330,
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RISCV_V21_V22_V23_V24 = 331,
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RISCV_V22_V23_V24_V25 = 332,
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RISCV_V23_V24_V25_V26 = 333,
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RISCV_V24_V25_V26_V27 = 334,
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RISCV_V25_V26_V27_V28 = 335,
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RISCV_V26_V27_V28_V29 = 336,
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RISCV_V27_V28_V29_V30 = 337,
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RISCV_V28_V29_V30_V31 = 338,
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RISCV_V0_V1_V2_V3 = 339,
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RISCV_V2M2_V4M2_V6M2_V8M2 = 340,
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RISCV_V4M2_V6M2_V8M2_V10M2 = 341,
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RISCV_V6M2_V8M2_V10M2_V12M2 = 342,
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RISCV_V8M2_V10M2_V12M2_V14M2 = 343,
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RISCV_V10M2_V12M2_V14M2_V16M2 = 344,
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RISCV_V12M2_V14M2_V16M2_V18M2 = 345,
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RISCV_V14M2_V16M2_V18M2_V20M2 = 346,
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RISCV_V16M2_V18M2_V20M2_V22M2 = 347,
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RISCV_V18M2_V20M2_V22M2_V24M2 = 348,
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RISCV_V20M2_V22M2_V24M2_V26M2 = 349,
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RISCV_V22M2_V24M2_V26M2_V28M2 = 350,
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RISCV_V24M2_V26M2_V28M2_V30M2 = 351,
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RISCV_V0M2_V2M2_V4M2_V6M2 = 352,
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RISCV_V1_V2_V3_V4_V5 = 353,
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RISCV_V2_V3_V4_V5_V6 = 354,
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RISCV_V3_V4_V5_V6_V7 = 355,
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RISCV_V4_V5_V6_V7_V8 = 356,
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RISCV_V5_V6_V7_V8_V9 = 357,
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RISCV_V6_V7_V8_V9_V10 = 358,
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RISCV_V7_V8_V9_V10_V11 = 359,
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RISCV_V8_V9_V10_V11_V12 = 360,
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RISCV_V9_V10_V11_V12_V13 = 361,
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RISCV_V10_V11_V12_V13_V14 = 362,
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RISCV_V11_V12_V13_V14_V15 = 363,
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RISCV_V12_V13_V14_V15_V16 = 364,
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RISCV_V13_V14_V15_V16_V17 = 365,
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RISCV_V14_V15_V16_V17_V18 = 366,
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RISCV_V15_V16_V17_V18_V19 = 367,
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RISCV_V16_V17_V18_V19_V20 = 368,
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RISCV_V17_V18_V19_V20_V21 = 369,
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RISCV_V18_V19_V20_V21_V22 = 370,
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RISCV_V19_V20_V21_V22_V23 = 371,
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RISCV_V20_V21_V22_V23_V24 = 372,
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RISCV_V21_V22_V23_V24_V25 = 373,
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RISCV_V22_V23_V24_V25_V26 = 374,
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RISCV_V23_V24_V25_V26_V27 = 375,
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RISCV_V24_V25_V26_V27_V28 = 376,
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RISCV_V25_V26_V27_V28_V29 = 377,
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RISCV_V26_V27_V28_V29_V30 = 378,
|
|
RISCV_V27_V28_V29_V30_V31 = 379,
|
|
RISCV_V0_V1_V2_V3_V4 = 380,
|
|
RISCV_V1_V2_V3_V4_V5_V6 = 381,
|
|
RISCV_V2_V3_V4_V5_V6_V7 = 382,
|
|
RISCV_V3_V4_V5_V6_V7_V8 = 383,
|
|
RISCV_V4_V5_V6_V7_V8_V9 = 384,
|
|
RISCV_V5_V6_V7_V8_V9_V10 = 385,
|
|
RISCV_V6_V7_V8_V9_V10_V11 = 386,
|
|
RISCV_V7_V8_V9_V10_V11_V12 = 387,
|
|
RISCV_V8_V9_V10_V11_V12_V13 = 388,
|
|
RISCV_V9_V10_V11_V12_V13_V14 = 389,
|
|
RISCV_V10_V11_V12_V13_V14_V15 = 390,
|
|
RISCV_V11_V12_V13_V14_V15_V16 = 391,
|
|
RISCV_V12_V13_V14_V15_V16_V17 = 392,
|
|
RISCV_V13_V14_V15_V16_V17_V18 = 393,
|
|
RISCV_V14_V15_V16_V17_V18_V19 = 394,
|
|
RISCV_V15_V16_V17_V18_V19_V20 = 395,
|
|
RISCV_V16_V17_V18_V19_V20_V21 = 396,
|
|
RISCV_V17_V18_V19_V20_V21_V22 = 397,
|
|
RISCV_V18_V19_V20_V21_V22_V23 = 398,
|
|
RISCV_V19_V20_V21_V22_V23_V24 = 399,
|
|
RISCV_V20_V21_V22_V23_V24_V25 = 400,
|
|
RISCV_V21_V22_V23_V24_V25_V26 = 401,
|
|
RISCV_V22_V23_V24_V25_V26_V27 = 402,
|
|
RISCV_V23_V24_V25_V26_V27_V28 = 403,
|
|
RISCV_V24_V25_V26_V27_V28_V29 = 404,
|
|
RISCV_V25_V26_V27_V28_V29_V30 = 405,
|
|
RISCV_V26_V27_V28_V29_V30_V31 = 406,
|
|
RISCV_V0_V1_V2_V3_V4_V5 = 407,
|
|
RISCV_V1_V2_V3_V4_V5_V6_V7 = 408,
|
|
RISCV_V2_V3_V4_V5_V6_V7_V8 = 409,
|
|
RISCV_V3_V4_V5_V6_V7_V8_V9 = 410,
|
|
RISCV_V4_V5_V6_V7_V8_V9_V10 = 411,
|
|
RISCV_V5_V6_V7_V8_V9_V10_V11 = 412,
|
|
RISCV_V6_V7_V8_V9_V10_V11_V12 = 413,
|
|
RISCV_V7_V8_V9_V10_V11_V12_V13 = 414,
|
|
RISCV_V8_V9_V10_V11_V12_V13_V14 = 415,
|
|
RISCV_V9_V10_V11_V12_V13_V14_V15 = 416,
|
|
RISCV_V10_V11_V12_V13_V14_V15_V16 = 417,
|
|
RISCV_V11_V12_V13_V14_V15_V16_V17 = 418,
|
|
RISCV_V12_V13_V14_V15_V16_V17_V18 = 419,
|
|
RISCV_V13_V14_V15_V16_V17_V18_V19 = 420,
|
|
RISCV_V14_V15_V16_V17_V18_V19_V20 = 421,
|
|
RISCV_V15_V16_V17_V18_V19_V20_V21 = 422,
|
|
RISCV_V16_V17_V18_V19_V20_V21_V22 = 423,
|
|
RISCV_V17_V18_V19_V20_V21_V22_V23 = 424,
|
|
RISCV_V18_V19_V20_V21_V22_V23_V24 = 425,
|
|
RISCV_V19_V20_V21_V22_V23_V24_V25 = 426,
|
|
RISCV_V20_V21_V22_V23_V24_V25_V26 = 427,
|
|
RISCV_V21_V22_V23_V24_V25_V26_V27 = 428,
|
|
RISCV_V22_V23_V24_V25_V26_V27_V28 = 429,
|
|
RISCV_V23_V24_V25_V26_V27_V28_V29 = 430,
|
|
RISCV_V24_V25_V26_V27_V28_V29_V30 = 431,
|
|
RISCV_V25_V26_V27_V28_V29_V30_V31 = 432,
|
|
RISCV_V0_V1_V2_V3_V4_V5_V6 = 433,
|
|
RISCV_V1_V2_V3_V4_V5_V6_V7_V8 = 434,
|
|
RISCV_V2_V3_V4_V5_V6_V7_V8_V9 = 435,
|
|
RISCV_V3_V4_V5_V6_V7_V8_V9_V10 = 436,
|
|
RISCV_V4_V5_V6_V7_V8_V9_V10_V11 = 437,
|
|
RISCV_V5_V6_V7_V8_V9_V10_V11_V12 = 438,
|
|
RISCV_V6_V7_V8_V9_V10_V11_V12_V13 = 439,
|
|
RISCV_V7_V8_V9_V10_V11_V12_V13_V14 = 440,
|
|
RISCV_V8_V9_V10_V11_V12_V13_V14_V15 = 441,
|
|
RISCV_V9_V10_V11_V12_V13_V14_V15_V16 = 442,
|
|
RISCV_V10_V11_V12_V13_V14_V15_V16_V17 = 443,
|
|
RISCV_V11_V12_V13_V14_V15_V16_V17_V18 = 444,
|
|
RISCV_V12_V13_V14_V15_V16_V17_V18_V19 = 445,
|
|
RISCV_V13_V14_V15_V16_V17_V18_V19_V20 = 446,
|
|
RISCV_V14_V15_V16_V17_V18_V19_V20_V21 = 447,
|
|
RISCV_V15_V16_V17_V18_V19_V20_V21_V22 = 448,
|
|
RISCV_V16_V17_V18_V19_V20_V21_V22_V23 = 449,
|
|
RISCV_V17_V18_V19_V20_V21_V22_V23_V24 = 450,
|
|
RISCV_V18_V19_V20_V21_V22_V23_V24_V25 = 451,
|
|
RISCV_V19_V20_V21_V22_V23_V24_V25_V26 = 452,
|
|
RISCV_V20_V21_V22_V23_V24_V25_V26_V27 = 453,
|
|
RISCV_V21_V22_V23_V24_V25_V26_V27_V28 = 454,
|
|
RISCV_V22_V23_V24_V25_V26_V27_V28_V29 = 455,
|
|
RISCV_V23_V24_V25_V26_V27_V28_V29_V30 = 456,
|
|
RISCV_V24_V25_V26_V27_V28_V29_V30_V31 = 457,
|
|
RISCV_V0_V1_V2_V3_V4_V5_V6_V7 = 458,
|
|
NUM_TARGET_REGS // 459
|
|
};
|
|
|
|
// Register classes
|
|
|
|
enum {
|
|
RISCV_FPR16RegClassID = 0,
|
|
RISCV_GPRAllRegClassID = 1,
|
|
RISCV_FPR32RegClassID = 2,
|
|
RISCV_GPRRegClassID = 3,
|
|
RISCV_GPRF16RegClassID = 4,
|
|
RISCV_GPRF32RegClassID = 5,
|
|
RISCV_GPRNoX0RegClassID = 6,
|
|
RISCV_GPRNoX0X2RegClassID = 7,
|
|
RISCV_GPRJALRRegClassID = 8,
|
|
RISCV_GPRTCRegClassID = 9,
|
|
RISCV_FPR32CRegClassID = 10,
|
|
RISCV_GPRCRegClassID = 11,
|
|
RISCV_SR07RegClassID = 12,
|
|
RISCV_GPRC_and_GPRTCRegClassID = 13,
|
|
RISCV_VCSRRegClassID = 14,
|
|
RISCV_GPRC_and_SR07RegClassID = 15,
|
|
RISCV_GPRX1X5RegClassID = 16,
|
|
RISCV_GPRX0RegClassID = 17,
|
|
RISCV_GPRX1RegClassID = 18,
|
|
RISCV_GPRX5RegClassID = 19,
|
|
RISCV_SPRegClassID = 20,
|
|
RISCV_FPR64RegClassID = 21,
|
|
RISCV_VMRegClassID = 22,
|
|
RISCV_VRRegClassID = 23,
|
|
RISCV_VRNoV0RegClassID = 24,
|
|
RISCV_GPRPairRegClassID = 25,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRNoX0RegClassID = 26,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID = 27,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID = 28,
|
|
RISCV_FPR64CRegClassID = 29,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRTCRegClassID = 30,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRCRegClassID = 31,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_SR07RegClassID = 32,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID = 33,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClassID = 34,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_GPRX0RegClassID = 35,
|
|
RISCV_GPRPair_with_sub_gpr_even_in_SPRegClassID = 36,
|
|
RISCV_GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID = 37,
|
|
RISCV_VMV0RegClassID = 38,
|
|
RISCV_VRN2M1RegClassID = 39,
|
|
RISCV_VRN2M1NoV0RegClassID = 40,
|
|
RISCV_VRM2RegClassID = 41,
|
|
RISCV_VRM2NoV0RegClassID = 42,
|
|
RISCV_VRM2_with_sub_vrm1_0_in_VMV0RegClassID = 43,
|
|
RISCV_VRN2M1_with_sub_vrm1_0_in_VMV0RegClassID = 44,
|
|
RISCV_VRN3M1RegClassID = 45,
|
|
RISCV_VRN3M1NoV0RegClassID = 46,
|
|
RISCV_VRN3M1_with_sub_vrm1_0_in_VMV0RegClassID = 47,
|
|
RISCV_VRN4M1RegClassID = 48,
|
|
RISCV_VRN4M1NoV0RegClassID = 49,
|
|
RISCV_VRN2M2RegClassID = 50,
|
|
RISCV_VRN2M2NoV0RegClassID = 51,
|
|
RISCV_VRM4RegClassID = 52,
|
|
RISCV_VRM4NoV0RegClassID = 53,
|
|
RISCV_VRM4_with_sub_vrm1_0_in_VMV0RegClassID = 54,
|
|
RISCV_VRN2M2_with_sub_vrm1_0_in_VMV0RegClassID = 55,
|
|
RISCV_VRN4M1_with_sub_vrm1_0_in_VMV0RegClassID = 56,
|
|
RISCV_VRN5M1RegClassID = 57,
|
|
RISCV_VRN5M1NoV0RegClassID = 58,
|
|
RISCV_VRN5M1_with_sub_vrm1_0_in_VMV0RegClassID = 59,
|
|
RISCV_VRN6M1RegClassID = 60,
|
|
RISCV_VRN6M1NoV0RegClassID = 61,
|
|
RISCV_VRN3M2RegClassID = 62,
|
|
RISCV_VRN3M2NoV0RegClassID = 63,
|
|
RISCV_VRN3M2_with_sub_vrm1_0_in_VMV0RegClassID = 64,
|
|
RISCV_VRN6M1_with_sub_vrm1_0_in_VMV0RegClassID = 65,
|
|
RISCV_VRN7M1RegClassID = 66,
|
|
RISCV_VRN7M1NoV0RegClassID = 67,
|
|
RISCV_VRN7M1_with_sub_vrm1_0_in_VMV0RegClassID = 68,
|
|
RISCV_VRN8M1RegClassID = 69,
|
|
RISCV_VRN8M1NoV0RegClassID = 70,
|
|
RISCV_VRN4M2RegClassID = 71,
|
|
RISCV_VRN4M2NoV0RegClassID = 72,
|
|
RISCV_VRN2M4RegClassID = 73,
|
|
RISCV_VRN2M4NoV0RegClassID = 74,
|
|
RISCV_VRM8RegClassID = 75,
|
|
RISCV_VRM8NoV0RegClassID = 76,
|
|
RISCV_VRM8_with_sub_vrm1_0_in_VMV0RegClassID = 77,
|
|
RISCV_VRN2M4_with_sub_vrm1_0_in_VMV0RegClassID = 78,
|
|
RISCV_VRN4M2_with_sub_vrm1_0_in_VMV0RegClassID = 79,
|
|
RISCV_VRN8M1_with_sub_vrm1_0_in_VMV0RegClassID = 80,
|
|
|
|
};
|
|
|
|
// Register alternate name indices
|
|
|
|
enum {
|
|
RISCV_ABIRegAltName, // 0
|
|
RISCV_NoRegAltName, // 1
|
|
NUM_TARGET_REG_ALT_NAMES = 2
|
|
};
|
|
|
|
// Subregister indices
|
|
|
|
enum {
|
|
RISCV_NoSubRegister,
|
|
RISCV_sub_16, // 1
|
|
RISCV_sub_32, // 2
|
|
RISCV_sub_gpr_even, // 3
|
|
RISCV_sub_gpr_odd, // 4
|
|
RISCV_sub_vrm1_0, // 5
|
|
RISCV_sub_vrm1_1, // 6
|
|
RISCV_sub_vrm1_2, // 7
|
|
RISCV_sub_vrm1_3, // 8
|
|
RISCV_sub_vrm1_4, // 9
|
|
RISCV_sub_vrm1_5, // 10
|
|
RISCV_sub_vrm1_6, // 11
|
|
RISCV_sub_vrm1_7, // 12
|
|
RISCV_sub_vrm2_0, // 13
|
|
RISCV_sub_vrm2_1, // 14
|
|
RISCV_sub_vrm2_2, // 15
|
|
RISCV_sub_vrm2_3, // 16
|
|
RISCV_sub_vrm4_0, // 17
|
|
RISCV_sub_vrm4_1, // 18
|
|
RISCV_sub_vrm1_0_sub_vrm1_1, // 19
|
|
RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2, // 20
|
|
RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, // 21
|
|
RISCV_sub_vrm1_1_sub_vrm1_2, // 22
|
|
RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, // 23
|
|
RISCV_sub_vrm1_2_sub_vrm1_3, // 24
|
|
RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 25
|
|
RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 26
|
|
RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 27
|
|
RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 28
|
|
RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 29
|
|
RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 30
|
|
RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 31
|
|
RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 32
|
|
RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 33
|
|
RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 34
|
|
RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 35
|
|
RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 36
|
|
RISCV_sub_vrm1_3_sub_vrm1_4, // 37
|
|
RISCV_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 38
|
|
RISCV_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 39
|
|
RISCV_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 40
|
|
RISCV_sub_vrm1_4_sub_vrm1_5, // 41
|
|
RISCV_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 42
|
|
RISCV_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 43
|
|
RISCV_sub_vrm1_5_sub_vrm1_6, // 44
|
|
RISCV_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 45
|
|
RISCV_sub_vrm1_6_sub_vrm1_7, // 46
|
|
RISCV_sub_vrm2_0_sub_vrm2_1, // 47
|
|
RISCV_sub_vrm2_0_sub_vrm2_1_sub_vrm2_2, // 48
|
|
RISCV_sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3, // 49
|
|
RISCV_sub_vrm2_1_sub_vrm2_2, // 50
|
|
RISCV_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3, // 51
|
|
RISCV_sub_vrm2_2_sub_vrm2_3, // 52
|
|
RISCV_NUM_TARGET_SUBREGS
|
|
};
|
|
#endif // GET_REGINFO_ENUM
|
|
|
|
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
|
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
|
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
|
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
|
|
|
/* LLVM-commit: <commit> */
|
|
/* LLVM-tag: <tag> */
|
|
|
|
/* Do not edit. */
|
|
|
|
/* Capstone's LLVM TableGen Backends: */
|
|
/* https://github.com/capstone-engine/llvm-capstone */
|
|
|
|
#ifdef GET_REGINFO_MC_DESC
|
|
#undef GET_REGINFO_MC_DESC
|
|
|
|
static const MCPhysReg RISCVRegDiffLists[] = {
|
|
/* 0 */ -105, 0,
|
|
/* 2 */ -103, 0,
|
|
/* 4 */ -101, 0,
|
|
/* 6 */ -99, 0,
|
|
/* 8 */ -97, 0,
|
|
/* 10 */ -95, 0,
|
|
/* 12 */ 25, -106, -86, 0,
|
|
/* 16 */ 157, -1, -3, 49, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0,
|
|
/* 31 */ 161, 1, 1, 71, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0,
|
|
/* 46 */ -1, -3, 64, 51, 42, -86, 0,
|
|
/* 53 */ 1, 1, 86, 51, 42, -86, 0,
|
|
/* 60 */ -104, -85, 0,
|
|
/* 63 */ -102, -84, 0,
|
|
/* 66 */ -100, -83, 0,
|
|
/* 69 */ -98, -82, 0,
|
|
/* 72 */ -96, -81, 0,
|
|
/* 75 */ -370, 1, 1, 1, 1, 230, 52, 43, -125, 53, -52, 96, -43, -52, 0,
|
|
/* 90 */ -342, 1, 1, 1, 1, 199, 53, 44, -96, 53, -52, 96, -43, -52, 0,
|
|
/* 105 */ -88, -161, 1, 163, -162, 1, 231, 52, 43, -125, 53, -52, 0,
|
|
/* 118 */ -397, 1, 1, 1, 1, 1, 229, 52, 43, -125, 53, -52, 165, -69, 42, -85, 44, -96, 53, -52, 0,
|
|
/* 139 */ -370, 1, 1, 1, 1, 1, 198, 53, 44, -96, 53, -52, 137, -41, 42, -85, 44, -96, 53, -52, 0,
|
|
/* 160 */ -423, 1, 1, 1, 1, 1, 1, 228, 52, 43, -125, 53, -52, 165, 27, -96, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0,
|
|
/* 188 */ -397, 1, 1, 1, 1, 1, 1, 197, 53, 44, -96, 53, -52, 137, 28, -69, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0,
|
|
/* 216 */ -448, 1, 1, 1, 1, 1, 1, 1, 227, 52, 43, -125, 53, -52, 165, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0,
|
|
/* 252 */ -423, 1, 1, 1, 1, 1, 1, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, -96, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0,
|
|
/* 288 */ -71, -162, 1, 162, -161, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 301 */ -71, -161, 1, 162, -161, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 314 */ -70, -160, 1, 162, -161, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 327 */ -70, -161, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 340 */ -68, -161, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 353 */ -68, -160, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 366 */ -67, -159, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 379 */ -67, -160, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 392 */ -65, -160, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 405 */ -65, -159, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 418 */ -64, -158, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 431 */ -64, -159, 1, 159, -158, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 444 */ -62, -159, 1, 159, -158, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 457 */ -62, -158, 1, 159, -158, 1, 200, 53, 44, -96, 53, -52, 0,
|
|
/* 470 */ -329, 1, 1, 1, 231, 52, -82, 53, -52, 0,
|
|
/* 480 */ -300, 1, 1, 1, 200, 53, -52, 53, -52, 0,
|
|
/* 490 */ -94, -1, -161, 1, 163, -162, 1, 163, -1, -161, 1, 162, -161, 1, 227, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, 42, -107, 52, -51, 0,
|
|
/* 539 */ -72, -1, -158, 1, 160, -159, 1, 160, -1, -158, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, 43, -94, 52, -51, 0,
|
|
/* 588 */ -74, -1, -159, 1, 160, -159, 1, 160, -1, -158, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, 43, -94, 52, -51, 0,
|
|
/* 637 */ -77, -1, -159, 1, 161, -160, 1, 161, -1, -159, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, 43, -94, 52, -51, 0,
|
|
/* 686 */ -79, -1, -160, 1, 161, -160, 1, 161, -1, -159, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, 43, -94, 52, -51, 0,
|
|
/* 735 */ -82, -1, -160, 1, 162, -161, 1, 162, -1, -160, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, 43, -94, 52, -51, 0,
|
|
/* 784 */ -84, -1, -161, 1, 162, -161, 1, 162, -1, -160, 1, 162, -161, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, 43, -94, 52, -51, 0,
|
|
/* 833 */ -181, -161, 1, 163, -162, 1, 162, -161, 1, 162, -161, 1, 227, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, -65, 52, -51, 0,
|
|
/* 879 */ -159, -158, 1, 160, -159, 1, 159, -158, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, -51, 52, -51, 0,
|
|
/* 925 */ -159, -159, 1, 159, -158, 1, 160, -159, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 14, 52, -51, 52, -51, 0,
|
|
/* 971 */ -160, -159, 1, 160, -159, 1, 159, -158, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, -51, 52, -51, 0,
|
|
/* 1017 */ -160, -160, 1, 160, -159, 1, 160, -159, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 16, 52, -51, 52, -51, 0,
|
|
/* 1063 */ -162, -159, 1, 161, -160, 1, 160, -159, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, -51, 52, -51, 0,
|
|
/* 1109 */ -162, -160, 1, 160, -159, 1, 161, -160, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 18, 52, -51, 52, -51, 0,
|
|
/* 1155 */ -163, -160, 1, 161, -160, 1, 160, -159, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, -51, 52, -51, 0,
|
|
/* 1201 */ -163, -161, 1, 161, -160, 1, 161, -160, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 20, 52, -51, 52, -51, 0,
|
|
/* 1247 */ -165, -160, 1, 162, -161, 1, 161, -160, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, -51, 52, -51, 0,
|
|
/* 1293 */ -165, -161, 1, 161, -160, 1, 162, -161, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 22, 52, -51, 52, -51, 0,
|
|
/* 1339 */ -166, -161, 1, 162, -161, 1, 161, -160, 1, 162, -161, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, -51, 52, -51, 0,
|
|
/* 1385 */ -166, -162, 1, 162, -161, 1, 162, -161, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 24, 52, -51, 52, -51, 0,
|
|
/* 1431 */ -128, -33, 0,
|
|
/* 1434 */ -32, -32, 0,
|
|
/* 1437 */ -286, 1, 1, 232, -30, 0,
|
|
/* 1443 */ -139, -161, 1, 163, -162, 1, 162, -161, 1, 229, 52, 43, -125, 53, -52, 165, 27, -96, 42, -85, 44, -96, 53, -52, 42, -14, 0,
|
|
/* 1470 */ -234, 1, 0,
|
|
/* 1473 */ -203, 1, 0,
|
|
/* 1476 */ -1, -161, 1, 163, -162, 1, 0,
|
|
/* 1483 */ -1, -1, -161, 1, 163, -162, 1, 163, -1, -161, 1, 162, -161, 1, 0,
|
|
/* 1498 */ -1, -160, 1, 162, -161, 1, 0,
|
|
/* 1505 */ -1, -1, -160, 1, 162, -161, 1, 162, -1, -160, 1, 161, -160, 1, 0,
|
|
/* 1520 */ -1, -159, 1, 161, -160, 1, 0,
|
|
/* 1527 */ -1, -1, -159, 1, 161, -160, 1, 161, -1, -159, 1, 160, -159, 1, 0,
|
|
/* 1542 */ -1, -158, 1, 160, -159, 1, 0,
|
|
/* 1549 */ -1, -1, -158, 1, 160, -159, 1, 160, -1, -158, 1, 159, -158, 1, 0,
|
|
/* 1564 */ -155, 1, 0,
|
|
/* 1567 */ -154, 1, 0,
|
|
/* 1570 */ -153, 1, 0,
|
|
/* 1573 */ -152, 1, 0,
|
|
/* 1576 */ -151, 1, 0,
|
|
/* 1579 */ -150, 1, 0,
|
|
/* 1582 */ -149, 1, 0,
|
|
/* 1585 */ -148, 1, 0,
|
|
/* 1588 */ -147, 1, 0,
|
|
/* 1591 */ -146, 1, 0,
|
|
/* 1594 */ -145, 1, 0,
|
|
/* 1597 */ -144, 1, 0,
|
|
/* 1600 */ -143, 1, 0,
|
|
/* 1603 */ -142, 1, 0,
|
|
/* 1606 */ -141, 1, 0,
|
|
/* 1609 */ 1, 1, 1, 1, 1, 1, 1, 0,
|
|
/* 1617 */ -114, -159, 1, 159, -158, 1, 159, -158, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 14, 1, 0,
|
|
/* 1644 */ -116, -158, 1, 160, -159, 1, 159, -158, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 15, 1, 0,
|
|
/* 1671 */ -116, -159, 1, 159, -158, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 16, 1, 0,
|
|
/* 1698 */ -117, -159, 1, 160, -159, 1, 159, -158, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 17, 1, 0,
|
|
/* 1725 */ -117, -160, 1, 160, -159, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 18, 1, 0,
|
|
/* 1752 */ -119, -159, 1, 161, -160, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 19, 1, 0,
|
|
/* 1779 */ -119, -160, 1, 160, -159, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 20, 1, 0,
|
|
/* 1806 */ -120, -160, 1, 161, -160, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 21, 1, 0,
|
|
/* 1833 */ -120, -161, 1, 161, -160, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 22, 1, 0,
|
|
/* 1860 */ -122, -160, 1, 162, -161, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 23, 1, 0,
|
|
/* 1887 */ -122, -161, 1, 161, -160, 1, 162, -161, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 24, 1, 0,
|
|
/* 1914 */ -123, -161, 1, 162, -161, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 25, 1, 0,
|
|
/* 1941 */ -123, -162, 1, 162, -161, 1, 162, -161, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 26, 1, 0,
|
|
/* 1968 */ 1, 70, 1, 0,
|
|
/* 1972 */ 1, 75, 1, 0,
|
|
/* 1976 */ -3, 76, 1, 0,
|
|
/* 1980 */ 1, 80, 1, 0,
|
|
/* 1984 */ -3, 81, 1, 0,
|
|
/* 1988 */ -256, 1, 1, 201, 1, 0,
|
|
/* 1994 */ 161, -2, 1, 42, 1, 51, 1, 43, -70, 28, 44, -71, 68, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 92, 2, 2, 2, 0,
|
|
/* 2044 */ 160, -1, -3, 46, 1, 51, 43, -68, 26, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0,
|
|
/* 2094 */ 160, 1, 1, 40, 1, 51, 1, 43, -69, 27, 44, -70, 67, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 122, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0,
|
|
/* 2144 */ 52, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0,
|
|
/* 2179 */ 160, -1, -3, 46, 1, 51, 1, 43, -72, 30, 44, -73, 70, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 94, 2, 2, 2, 0,
|
|
/* 2229 */ 160, 1, -3, 44, 1, 51, 1, 43, -71, 29, 44, -72, 69, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 125, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0,
|
|
/* 2279 */ 160, -2, 1, 43, 1, 51, 43, -70, 28, 1, 43, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0,
|
|
/* 2329 */ 52, 1, 43, -71, 70, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0,
|
|
/* 2364 */ 159, 1, 1, 41, 1, 51, 43, -69, 27, 1, 43, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 2, 0,
|
|
/* 2414 */ 52, 1, 43, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 2, 0,
|
|
/* 2450 */ 160, -2, 1, 43, 1, 51, 1, 43, -74, 32, 44, -75, 72, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 96, 2, 2, 2, 0,
|
|
/* 2500 */ 159, 1, 1, 41, 1, 51, 1, 43, -73, 31, 44, -74, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 128, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0,
|
|
/* 2550 */ 159, -1, -3, 47, 1, 51, 43, -72, 30, 1, 43, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0,
|
|
/* 2600 */ 52, 1, 43, -73, 72, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0,
|
|
/* 2635 */ 159, 1, -3, 45, 1, 51, 43, -71, 29, 1, 43, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 2, 0,
|
|
/* 2685 */ 52, 1, 43, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 2, 0,
|
|
/* 2721 */ 159, -1, -3, 47, 1, 51, 1, 43, -76, 34, 44, -77, 74, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 98, 2, 2, 2, 0,
|
|
/* 2771 */ 159, 1, -3, 45, 1, 51, 1, 43, -75, 33, 44, -76, 73, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 131, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0,
|
|
/* 2821 */ 159, -2, 1, 44, 1, 51, 43, -74, 32, 1, 43, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0,
|
|
/* 2871 */ 52, 1, 43, -75, 74, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0,
|
|
/* 2906 */ 158, 1, 1, 42, 1, 51, 43, -73, 31, 1, 43, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 2, 0,
|
|
/* 2956 */ 52, 1, 43, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 2, 0,
|
|
/* 2992 */ 158, 1, 1, 42, 1, 51, 1, 43, -77, 35, 44, -78, 75, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 134, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0,
|
|
/* 3042 */ 158, -1, -3, 48, 1, 51, 43, -76, 34, 1, 43, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0,
|
|
/* 3092 */ 52, 1, 43, -77, 76, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0,
|
|
/* 3127 */ 158, 1, -3, 46, 1, 51, 43, -75, 33, 1, 43, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 2, 0,
|
|
/* 3177 */ 52, 1, 43, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 2, 0,
|
|
/* 3213 */ 161, -1, -3, 45, 1, 51, 1, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0,
|
|
/* 3262 */ 52, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0,
|
|
/* 3301 */ 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0,
|
|
/* 3329 */ 52, 43, -70, 28, 44, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0,
|
|
/* 3368 */ 44, -71, 70, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0,
|
|
/* 3396 */ 52, 43, -69, 27, 44, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0,
|
|
/* 3435 */ 43, -69, 110, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 150, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0,
|
|
/* 3463 */ 44, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 0,
|
|
/* 3492 */ 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 94, 2, 2, 0,
|
|
/* 3511 */ 52, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0,
|
|
/* 3546 */ 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0,
|
|
/* 3575 */ 160, 1, -3, 44, 1, 51, 43, -67, 25, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0,
|
|
/* 3621 */ 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 2, 0,
|
|
/* 3640 */ 52, 43, -72, 30, 44, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0,
|
|
/* 3679 */ 44, -73, 72, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0,
|
|
/* 3707 */ 52, 43, -71, 29, 44, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0,
|
|
/* 3746 */ 43, -71, 112, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 153, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0,
|
|
/* 3774 */ 44, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 0,
|
|
/* 3803 */ 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 96, 2, 2, 0,
|
|
/* 3822 */ 43, -70, 111, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 2, 0,
|
|
/* 3851 */ 52, 43, -74, 32, 44, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0,
|
|
/* 3890 */ 44, -75, 74, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0,
|
|
/* 3918 */ 52, 43, -73, 31, 44, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0,
|
|
/* 3957 */ 43, -73, 114, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 156, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0,
|
|
/* 3985 */ 44, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 0,
|
|
/* 4014 */ 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 98, 2, 2, 0,
|
|
/* 4033 */ 43, -72, 113, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 2, 0,
|
|
/* 4062 */ 52, 43, -76, 34, 44, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0,
|
|
/* 4101 */ 44, -77, 76, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0,
|
|
/* 4129 */ 52, 43, -75, 33, 44, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0,
|
|
/* 4168 */ 43, -75, 116, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 159, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0,
|
|
/* 4196 */ 44, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 0,
|
|
/* 4225 */ 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 100, 2, 2, 0,
|
|
/* 4244 */ 43, -74, 115, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 2, 0,
|
|
/* 4273 */ 157, 1, 1, 43, 1, 51, 43, -77, 35, 1, 43, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0,
|
|
/* 4322 */ 52, 43, -77, 35, 44, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0,
|
|
/* 4361 */ 43, -77, 118, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 162, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0,
|
|
/* 4389 */ 159, -2, 1, 44, 1, 51, 1, 43, -78, 36, 44, -79, 76, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0,
|
|
/* 4435 */ 52, 1, 43, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0,
|
|
/* 4470 */ 44, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0,
|
|
/* 4499 */ 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 102, 2, 2, 0,
|
|
/* 4518 */ 43, -76, 117, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 2, 0,
|
|
/* 4547 */ -1, -3, 73, 1, 51, 1, 42, -81, 37, 55, -86, 74, 2, 0,
|
|
/* 4561 */ 1, 1, 67, 1, 50, 1, 42, -81, 40, 43, -82, 79, 2, 0,
|
|
/* 4575 */ 1, -3, 69, 1, 50, 1, 42, -82, 41, 43, -83, 80, 2, 0,
|
|
/* 4589 */ 51, 1, 42, -81, 80, 2, 0,
|
|
/* 4596 */ 1, 1, 64, 1, 50, 1, 42, -83, 42, 43, -84, 81, 2, 0,
|
|
/* 4610 */ -2, 1, 68, 1, 50, 42, -81, 40, 1, 42, -82, 81, 2, 0,
|
|
/* 4624 */ 51, 1, 42, -82, 81, 2, 0,
|
|
/* 4631 */ 1, -3, 66, 1, 50, 1, 42, -84, 43, 43, -85, 82, 2, 0,
|
|
/* 4645 */ -1, -3, 70, 1, 50, 42, -82, 41, 1, 42, -83, 82, 2, 0,
|
|
/* 4659 */ 51, 1, 42, -83, 82, 2, 0,
|
|
/* 4666 */ 1, 1, 61, 1, 50, 1, 42, -85, 44, 43, -86, 83, 2, 0,
|
|
/* 4680 */ -2, 1, 65, 1, 50, 42, -83, 42, 1, 42, -84, 83, 2, 0,
|
|
/* 4694 */ 51, 1, 42, -84, 83, 2, 0,
|
|
/* 4701 */ -1, -3, 67, 1, 50, 42, -84, 43, 1, 42, -85, 84, 2, 0,
|
|
/* 4715 */ 51, 1, 42, -85, 84, 2, 0,
|
|
/* 4722 */ -69, 110, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 150, 25, -95, 73, 26, -97, 94, 2, 0,
|
|
/* 4744 */ 27, 26, -25, 26, 25, -138, 42, -81, 153, 26, -97, 94, 2, 0,
|
|
/* 4758 */ 44, -68, 110, 28, 27, 26, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4786 */ -68, 110, 28, 27, 26, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4809 */ 161, 1, -3, 43, 1, 51, 1, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 51, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4852 */ 161, -2, 1, 42, 1, 52, 1, 43, -67, 22, 72, -80, 52, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4888 */ 52, 1, 43, -67, 66, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4916 */ 52, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4951 */ 43, -67, 108, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4975 */ 28, 27, 26, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 0,
|
|
/* 4989 */ -71, 112, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 153, 25, -97, 75, 26, -99, 96, 2, 0,
|
|
/* 5011 */ 27, 26, -25, 26, 25, -140, 42, -82, 156, 26, -99, 96, 2, 0,
|
|
/* 5025 */ -70, 111, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 0,
|
|
/* 5048 */ 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 96, 2, 0,
|
|
/* 5062 */ 27, 1, 26, 1, 25, -139, 43, -81, 150, 25, -95, 96, 2, 0,
|
|
/* 5076 */ -73, 114, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 156, 25, -99, 77, 26, -101, 98, 2, 0,
|
|
/* 5098 */ 27, 26, -25, 26, 25, -142, 42, -83, 159, 26, -101, 98, 2, 0,
|
|
/* 5112 */ -72, 113, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 0,
|
|
/* 5135 */ 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 98, 2, 0,
|
|
/* 5149 */ 27, 1, 26, 1, 25, -141, 43, -82, 153, 25, -97, 98, 2, 0,
|
|
/* 5163 */ -75, 116, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 159, 25, -101, 79, 26, -103, 100, 2, 0,
|
|
/* 5185 */ 27, 26, -25, 26, 25, -144, 42, -84, 162, 26, -103, 100, 2, 0,
|
|
/* 5199 */ -74, 115, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 0,
|
|
/* 5222 */ 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 100, 2, 0,
|
|
/* 5236 */ 27, 1, 26, 1, 25, -143, 43, -83, 156, 25, -99, 100, 2, 0,
|
|
/* 5250 */ -77, 118, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 162, 25, -103, 81, 26, -105, 102, 2, 0,
|
|
/* 5272 */ 27, 26, -25, 26, 25, -146, 42, -85, 165, 26, -105, 102, 2, 0,
|
|
/* 5286 */ -76, 117, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 0,
|
|
/* 5309 */ 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 102, 2, 0,
|
|
/* 5323 */ 27, 1, 26, 1, 25, -145, 43, -84, 159, 25, -101, 102, 2, 0,
|
|
/* 5337 */ 52, 43, -78, 36, 44, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5372 */ 44, -79, 78, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5396 */ 158, -2, 1, 45, 1, 51, 43, -78, 36, 1, 43, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5439 */ 158, 1, -3, 46, 1, 51, 1, 43, -79, 37, 44, -80, 77, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5475 */ 52, 1, 43, -79, 78, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5503 */ 43, -78, 119, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5531 */ -78, 119, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5554 */ 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 104, 2, 0,
|
|
/* 5568 */ 27, 1, 26, 1, 25, -147, 43, -85, 162, 25, -103, 104, 2, 0,
|
|
/* 5582 */ 26, 1, 25, -96, -81, 176, 2, 0,
|
|
/* 5590 */ 26, 1, 25, -98, -82, 179, 2, 0,
|
|
/* 5598 */ 26, 1, 25, -100, -83, 182, 2, 0,
|
|
/* 5606 */ 26, 1, 25, -102, -84, 185, 2, 0,
|
|
/* 5614 */ 26, 1, 25, -104, -85, 188, 2, 0,
|
|
/* 5622 */ -3, 87, 6, 0,
|
|
/* 5626 */ 32, 32, 0,
|
|
/* 5629 */ 33, 0,
|
|
/* 5631 */ -3, 71, 0,
|
|
/* 5634 */ 1, -3, 72, 1, 52, 43, -81, 50, -13, 55, -86, 74, 0,
|
|
/* 5647 */ -2, 1, 72, 14, 51, -13, 55, -86, 74, 0,
|
|
/* 5657 */ 65, -13, 55, -86, 74, 0,
|
|
/* 5663 */ 52, 43, -81, 37, 55, -86, 74, 0,
|
|
/* 5671 */ 43, -81, 80, 0,
|
|
/* 5675 */ 51, 42, -81, 40, 43, -82, 81, 0,
|
|
/* 5683 */ 51, 42, -82, 41, 43, -83, 82, 0,
|
|
/* 5691 */ 42, -81, 82, 0,
|
|
/* 5695 */ 51, 42, -83, 42, 43, -84, 83, 0,
|
|
/* 5703 */ 42, -82, 83, 0,
|
|
/* 5707 */ 51, 42, -84, 43, 43, -85, 84, 0,
|
|
/* 5715 */ 42, -83, 84, 0,
|
|
/* 5719 */ -2, 1, 62, 1, 50, 42, -85, 44, 1, 42, -86, 85, 0,
|
|
/* 5732 */ 1, -3, 63, 1, 50, 1, 42, -86, 85, 0,
|
|
/* 5742 */ 51, 1, 42, -86, 85, 0,
|
|
/* 5748 */ 51, 42, -85, 44, 43, -86, 85, 0,
|
|
/* 5756 */ 42, -84, 85, 0,
|
|
/* 5760 */ 42, -85, 86, 0,
|
|
/* 5764 */ 1, 93, 0,
|
|
/* 5767 */ 27, 52, -51, 26, 50, -161, 55, -86, 143, 26, -95, 94, 0,
|
|
/* 5780 */ 162, -2, 1, 41, 1, 53, 44, -67, 51, -29, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
|
|
/* 5811 */ 53, 44, -67, 22, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
|
|
/* 5836 */ 44, -67, 66, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
|
|
/* 5857 */ -67, 108, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
|
|
/* 5875 */ 26, 25, -138, 42, -81, 153, 26, -97, 96, 0,
|
|
/* 5885 */ 27, 26, -139, 43, -81, 150, 25, -95, 96, 0,
|
|
/* 5895 */ 26, 25, -140, 42, -82, 156, 26, -99, 98, 0,
|
|
/* 5905 */ 27, 26, -141, 43, -82, 153, 25, -97, 98, 0,
|
|
/* 5915 */ 26, 25, -142, 42, -83, 159, 26, -101, 100, 0,
|
|
/* 5925 */ 27, 26, -143, 43, -83, 156, 25, -99, 100, 0,
|
|
/* 5935 */ 26, 25, -144, 42, -84, 162, 26, -103, 102, 0,
|
|
/* 5945 */ 27, 26, -145, 43, -84, 159, 25, -101, 102, 0,
|
|
/* 5955 */ 26, 25, -146, 42, -85, 165, 26, -105, 104, 0,
|
|
/* 5965 */ 27, 26, -147, 43, -85, 162, 25, -103, 104, 0,
|
|
/* 5975 */ -79, 120, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
|
|
/* 5993 */ 157, 1, -3, 47, 1, 51, 43, -79, 37, 1, 43, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
|
|
/* 6024 */ 52, 43, -79, 37, 44, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
|
|
/* 6049 */ 43, -79, 120, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
|
|
/* 6070 */ 27, 1, 26, 1, 25, -149, 43, -86, 165, 25, -105, 106, 0,
|
|
/* 6083 */ 27, 26, -149, 43, -86, 165, 25, -105, 106, 0,
|
|
/* 6093 */ 128, 0,
|
|
/* 6095 */ 140, 0,
|
|
/* 6097 */ 141, 0,
|
|
/* 6099 */ 142, 0,
|
|
/* 6101 */ 143, 0,
|
|
/* 6103 */ 144, 0,
|
|
/* 6105 */ 145, 0,
|
|
/* 6107 */ 146, 0,
|
|
/* 6109 */ 147, 0,
|
|
/* 6111 */ 148, 0,
|
|
/* 6113 */ 149, 0,
|
|
/* 6115 */ 150, 0,
|
|
/* 6117 */ 151, 0,
|
|
/* 6119 */ 152, 0,
|
|
/* 6121 */ 153, 0,
|
|
/* 6123 */ 154, 0,
|
|
/* 6125 */ 155, 0,
|
|
/* 6127 */ 161, 0,
|
|
/* 6129 */ 52, -25, 50, -106, -86, 168, 0,
|
|
/* 6136 */ 160, 1, 1, 41, 30, 52, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0,
|
|
/* 6158 */ 82, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0,
|
|
/* 6175 */ 26, -96, -81, 176, 0,
|
|
/* 6180 */ 25, -96, -81, 178, 0,
|
|
/* 6185 */ 26, -98, -82, 179, 0,
|
|
/* 6190 */ 25, -98, -82, 181, 0,
|
|
/* 6195 */ 26, -100, -83, 182, 0,
|
|
/* 6200 */ 25, -100, -83, 184, 0,
|
|
/* 6205 */ 26, -102, -84, 185, 0,
|
|
/* 6210 */ 25, -102, -84, 187, 0,
|
|
/* 6215 */ 26, -104, -85, 188, 0,
|
|
/* 6220 */ 25, -104, -85, 190, 0,
|
|
/* 6225 */ 26, 1, 25, -106, -86, 191, 0,
|
|
/* 6232 */ 26, -106, -86, 191, 0,
|
|
/* 6237 */ 27, 26, -25, 26, 25, -148, 42, -86, 191, 0,
|
|
/* 6247 */ 158, -1, -3, 48, 1, 51, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0,
|
|
/* 6269 */ 52, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0,
|
|
/* 6286 */ 44, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0,
|
|
};
|
|
|
|
static const uint16_t RISCVSubRegIdxLists[] = {
|
|
/* 0 */ 2, 1, 0,
|
|
/* 3 */ 3, 4, 0,
|
|
/* 6 */ 5, 6, 0,
|
|
/* 9 */ 13, 5, 6, 14, 7, 8, 0,
|
|
/* 16 */ 17, 13, 5, 6, 14, 7, 8, 18, 15, 9, 10, 16, 11, 12, 0,
|
|
/* 31 */ 5, 6, 7, 19, 22, 0,
|
|
/* 37 */ 5, 6, 7, 8, 19, 20, 22, 23, 24, 0,
|
|
/* 47 */ 13, 5, 6, 14, 7, 8, 19, 20, 21, 22, 23, 24, 0,
|
|
/* 60 */ 5, 6, 7, 8, 9, 19, 20, 21, 22, 23, 24, 29, 33, 37, 0,
|
|
/* 75 */ 5, 6, 7, 8, 9, 10, 19, 20, 21, 22, 23, 24, 25, 29, 30, 33, 34, 37, 38, 41, 0,
|
|
/* 96 */ 5, 6, 7, 8, 9, 10, 11, 19, 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 33, 34, 35, 37, 38, 39, 41, 42, 44, 0,
|
|
/* 124 */ 5, 6, 7, 8, 9, 10, 11, 12, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 0,
|
|
/* 160 */ 13, 5, 6, 14, 7, 8, 15, 9, 10, 19, 20, 21, 22, 23, 24, 25, 26, 29, 30, 33, 34, 37, 38, 41, 47, 50, 0,
|
|
/* 187 */ 13, 5, 6, 14, 7, 8, 15, 9, 10, 16, 11, 12, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 51, 52, 0,
|
|
/* 233 */ 17, 13, 5, 6, 14, 7, 8, 18, 15, 9, 10, 16, 11, 12, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0,
|
|
};
|
|
|
|
static const MCRegisterDesc RISCVRegDesc[] = { // Descriptors
|
|
{ 24, 0, 0, 0, 0, 0 },
|
|
{ 2034, 1, 1, 2, 4096, 50 },
|
|
{ 2021, 1, 1, 2, 4097, 50 },
|
|
{ 2030, 1, 1, 2, 4098, 50 },
|
|
{ 2018, 1, 1, 2, 4099, 50 },
|
|
{ 1460, 1, 1, 2, 4100, 50 },
|
|
{ 1648, 1, 1, 2, 4101, 50 },
|
|
{ 2025, 1, 1, 2, 4102, 50 },
|
|
{ 2041, 1, 1, 2, 4103, 50 },
|
|
{ 104, 1, 6127, 2, 4104, 50 },
|
|
{ 101, 1, 31, 2, 4105, 50 },
|
|
{ 244, 1, 6136, 2, 4106, 50 },
|
|
{ 651, 1, 5780, 2, 4107, 50 },
|
|
{ 742, 1, 4852, 2, 4108, 50 },
|
|
{ 916, 1, 4809, 2, 4109, 50 },
|
|
{ 1015, 1, 3575, 2, 4110, 50 },
|
|
{ 1113, 1, 3213, 2, 4111, 50 },
|
|
{ 1220, 1, 2044, 2, 4112, 50 },
|
|
{ 1344, 1, 2094, 2, 4113, 50 },
|
|
{ 1451, 1, 2364, 2, 4114, 50 },
|
|
{ 21, 1, 1994, 2, 4115, 50 },
|
|
{ 149, 1, 2279, 2, 4116, 50 },
|
|
{ 273, 1, 2229, 2, 4117, 50 },
|
|
{ 681, 1, 2635, 2, 4118, 50 },
|
|
{ 776, 1, 2179, 2, 4119, 50 },
|
|
{ 948, 1, 2550, 2, 4120, 50 },
|
|
{ 1051, 1, 2500, 2, 4121, 50 },
|
|
{ 1147, 1, 2906, 2, 4122, 50 },
|
|
{ 1257, 1, 2450, 2, 4123, 50 },
|
|
{ 1378, 1, 2821, 2, 4124, 50 },
|
|
{ 57, 1, 2771, 2, 4125, 50 },
|
|
{ 189, 1, 3127, 2, 4126, 50 },
|
|
{ 309, 1, 2721, 2, 4127, 50 },
|
|
{ 721, 1, 3042, 2, 4128, 50 },
|
|
{ 812, 1, 2992, 2, 4129, 50 },
|
|
{ 988, 1, 4273, 2, 4130, 50 },
|
|
{ 1087, 1, 4389, 2, 4131, 50 },
|
|
{ 1187, 1, 5396, 2, 4132, 50 },
|
|
{ 1293, 1, 5439, 2, 4133, 50 },
|
|
{ 1418, 1, 5993, 2, 4134, 50 },
|
|
{ 93, 1, 6247, 2, 4135, 50 },
|
|
{ 229, 1, 16, 2, 4136, 50 },
|
|
{ 124, 1, 6093, 2, 4137, 50 },
|
|
{ 247, 1, 1, 2, 4138, 50 },
|
|
{ 654, 1, 6125, 2, 4139, 50 },
|
|
{ 748, 1, 6123, 2, 4140, 50 },
|
|
{ 919, 1, 6123, 2, 4141, 50 },
|
|
{ 1021, 1, 6121, 2, 4142, 50 },
|
|
{ 1116, 1, 6121, 2, 4143, 50 },
|
|
{ 1226, 1, 6119, 2, 4144, 50 },
|
|
{ 1347, 1, 6119, 2, 4145, 50 },
|
|
{ 1457, 1, 6117, 2, 4146, 50 },
|
|
{ 25, 1, 6117, 2, 4147, 50 },
|
|
{ 157, 1, 6115, 2, 4148, 50 },
|
|
{ 277, 1, 6115, 2, 4149, 50 },
|
|
{ 689, 1, 6113, 2, 4150, 50 },
|
|
{ 780, 1, 6113, 2, 4151, 50 },
|
|
{ 956, 1, 6111, 2, 4152, 50 },
|
|
{ 1055, 1, 6111, 2, 4153, 50 },
|
|
{ 1155, 1, 6109, 2, 4154, 50 },
|
|
{ 1261, 1, 6109, 2, 4155, 50 },
|
|
{ 1386, 1, 6107, 2, 4156, 50 },
|
|
{ 61, 1, 6107, 2, 4157, 50 },
|
|
{ 197, 1, 6105, 2, 4158, 50 },
|
|
{ 313, 1, 6105, 2, 4159, 50 },
|
|
{ 729, 1, 6103, 2, 4160, 50 },
|
|
{ 816, 1, 6103, 2, 4161, 50 },
|
|
{ 996, 1, 6101, 2, 4162, 50 },
|
|
{ 1091, 1, 6101, 2, 4163, 50 },
|
|
{ 1195, 1, 6099, 2, 4164, 50 },
|
|
{ 1297, 1, 6099, 2, 4165, 50 },
|
|
{ 1426, 1, 6097, 2, 4166, 50 },
|
|
{ 97, 1, 6097, 2, 4167, 50 },
|
|
{ 237, 1, 6095, 2, 4168, 50 },
|
|
{ 1484, 5626, 1, 0, 4169, 0 },
|
|
{ 1507, 5626, 1, 0, 4170, 0 },
|
|
{ 1524, 5626, 1, 0, 4171, 0 },
|
|
{ 1541, 5626, 1, 0, 4172, 0 },
|
|
{ 1558, 5626, 1, 0, 4173, 0 },
|
|
{ 1575, 5626, 1, 0, 4174, 0 },
|
|
{ 1592, 5626, 1, 0, 4175, 0 },
|
|
{ 1609, 5626, 1, 0, 4176, 0 },
|
|
{ 1626, 5626, 1, 0, 4177, 0 },
|
|
{ 1643, 5626, 1, 0, 4178, 0 },
|
|
{ 1466, 5626, 1, 0, 4179, 0 },
|
|
{ 1489, 5626, 1, 0, 4180, 0 },
|
|
{ 1512, 5626, 1, 0, 4181, 0 },
|
|
{ 1529, 5626, 1, 0, 4182, 0 },
|
|
{ 1546, 5626, 1, 0, 4183, 0 },
|
|
{ 1563, 5626, 1, 0, 4184, 0 },
|
|
{ 1580, 5626, 1, 0, 4185, 0 },
|
|
{ 1597, 5626, 1, 0, 4186, 0 },
|
|
{ 1614, 5626, 1, 0, 4187, 0 },
|
|
{ 1631, 5626, 1, 0, 4188, 0 },
|
|
{ 1472, 5626, 1, 0, 4189, 0 },
|
|
{ 1495, 5626, 1, 0, 4190, 0 },
|
|
{ 1518, 5626, 1, 0, 4191, 0 },
|
|
{ 1535, 5626, 1, 0, 4192, 0 },
|
|
{ 1552, 5626, 1, 0, 4193, 0 },
|
|
{ 1569, 5626, 1, 0, 4194, 0 },
|
|
{ 1586, 5626, 1, 0, 4195, 0 },
|
|
{ 1603, 5626, 1, 0, 4196, 0 },
|
|
{ 1620, 5626, 1, 0, 4197, 0 },
|
|
{ 1637, 5626, 1, 0, 4198, 0 },
|
|
{ 1478, 5626, 1, 0, 4199, 0 },
|
|
{ 1501, 5626, 1, 0, 4200, 0 },
|
|
{ 1672, 5627, 1435, 1, 4169, 0 },
|
|
{ 1695, 5627, 1435, 1, 4170, 0 },
|
|
{ 1712, 5627, 1435, 1, 4171, 0 },
|
|
{ 1729, 5627, 1435, 1, 4172, 0 },
|
|
{ 1746, 5627, 1435, 1, 4173, 0 },
|
|
{ 1763, 5627, 1435, 1, 4174, 0 },
|
|
{ 1780, 5627, 1435, 1, 4175, 0 },
|
|
{ 1797, 5627, 1435, 1, 4176, 0 },
|
|
{ 1814, 5627, 1435, 1, 4177, 0 },
|
|
{ 1831, 5627, 1435, 1, 4178, 0 },
|
|
{ 1654, 5627, 1435, 1, 4179, 0 },
|
|
{ 1677, 5627, 1435, 1, 4180, 0 },
|
|
{ 1700, 5627, 1435, 1, 4181, 0 },
|
|
{ 1717, 5627, 1435, 1, 4182, 0 },
|
|
{ 1734, 5627, 1435, 1, 4183, 0 },
|
|
{ 1751, 5627, 1435, 1, 4184, 0 },
|
|
{ 1768, 5627, 1435, 1, 4185, 0 },
|
|
{ 1785, 5627, 1435, 1, 4186, 0 },
|
|
{ 1802, 5627, 1435, 1, 4187, 0 },
|
|
{ 1819, 5627, 1435, 1, 4188, 0 },
|
|
{ 1660, 5627, 1435, 1, 4189, 0 },
|
|
{ 1683, 5627, 1435, 1, 4190, 0 },
|
|
{ 1706, 5627, 1435, 1, 4191, 0 },
|
|
{ 1723, 5627, 1435, 1, 4192, 0 },
|
|
{ 1740, 5627, 1435, 1, 4193, 0 },
|
|
{ 1757, 5627, 1435, 1, 4194, 0 },
|
|
{ 1774, 5627, 1435, 1, 4195, 0 },
|
|
{ 1791, 5627, 1435, 1, 4196, 0 },
|
|
{ 1808, 5627, 1435, 1, 4197, 0 },
|
|
{ 1825, 5627, 1435, 1, 4198, 0 },
|
|
{ 1666, 5627, 1435, 1, 4199, 0 },
|
|
{ 1689, 5627, 1435, 1, 4200, 0 },
|
|
{ 1854, 1, 1434, 2, 4169, 50 },
|
|
{ 1877, 1, 1434, 2, 4170, 50 },
|
|
{ 1894, 1, 1434, 2, 4171, 50 },
|
|
{ 1911, 1, 1434, 2, 4172, 50 },
|
|
{ 1928, 1, 1434, 2, 4173, 50 },
|
|
{ 1945, 1, 1434, 2, 4174, 50 },
|
|
{ 1962, 1, 1434, 2, 4175, 50 },
|
|
{ 1979, 1, 1434, 2, 4176, 50 },
|
|
{ 1996, 1, 1434, 2, 4177, 50 },
|
|
{ 2013, 1, 1434, 2, 4178, 50 },
|
|
{ 1836, 1, 1434, 2, 4179, 50 },
|
|
{ 1859, 1, 1434, 2, 4180, 50 },
|
|
{ 1882, 1, 1434, 2, 4181, 50 },
|
|
{ 1899, 1, 1434, 2, 4182, 50 },
|
|
{ 1916, 1, 1434, 2, 4183, 50 },
|
|
{ 1933, 1, 1434, 2, 4184, 50 },
|
|
{ 1950, 1, 1434, 2, 4185, 50 },
|
|
{ 1967, 1, 1434, 2, 4186, 50 },
|
|
{ 1984, 1, 1434, 2, 4187, 50 },
|
|
{ 2001, 1, 1434, 2, 4188, 50 },
|
|
{ 1842, 1, 1434, 2, 4189, 50 },
|
|
{ 1865, 1, 1434, 2, 4190, 50 },
|
|
{ 1888, 1, 1434, 2, 4191, 50 },
|
|
{ 1905, 1, 1434, 2, 4192, 50 },
|
|
{ 1922, 1, 1434, 2, 4193, 50 },
|
|
{ 1939, 1, 1434, 2, 4194, 50 },
|
|
{ 1956, 1, 1434, 2, 4195, 50 },
|
|
{ 1973, 1, 1434, 2, 4196, 50 },
|
|
{ 1990, 1, 1434, 2, 4197, 50 },
|
|
{ 2007, 1, 1434, 2, 4198, 50 },
|
|
{ 1848, 1, 1434, 2, 4199, 50 },
|
|
{ 1871, 1, 1434, 2, 4200, 50 },
|
|
{ 2047, 1431, 1, 3, 23056392, 2 },
|
|
{ 386, 1495, 53, 6, 6025225, 8 },
|
|
{ 832, 1476, 5764, 9, 6606857, 15 },
|
|
{ 1301, 1483, 1, 16, 6590473, 41 },
|
|
{ 442, 1480, 5647, 6, 6025227, 8 },
|
|
{ 504, 1495, 5634, 6, 6025229, 8 },
|
|
{ 865, 1491, 5622, 9, 6606861, 15 },
|
|
{ 572, 1495, 4547, 6, 6025231, 8 },
|
|
{ 640, 1517, 4561, 6, 6025233, 8 },
|
|
{ 899, 1498, 1980, 9, 6606865, 15 },
|
|
{ 1318, 1505, 1, 16, 6590481, 41 },
|
|
{ 332, 1495, 4610, 6, 6025235, 8 },
|
|
{ 407, 1517, 4575, 6, 6025237, 8 },
|
|
{ 842, 1513, 1984, 9, 6606869, 15 },
|
|
{ 464, 1517, 4645, 6, 6025239, 8 },
|
|
{ 527, 1539, 4596, 6, 6025241, 8 },
|
|
{ 876, 1520, 1972, 9, 6606873, 15 },
|
|
{ 1312, 1527, 1, 16, 6590489, 41 },
|
|
{ 595, 1517, 4680, 6, 6025243, 8 },
|
|
{ 356, 1539, 4631, 6, 6025245, 8 },
|
|
{ 826, 1535, 1976, 9, 6606877, 15 },
|
|
{ 431, 1539, 4701, 6, 6025247, 8 },
|
|
{ 488, 1561, 4666, 6, 6025249, 8 },
|
|
{ 854, 1542, 1968, 9, 6606881, 15 },
|
|
{ 1306, 1549, 1, 16, 6590497, 41 },
|
|
{ 551, 1539, 5719, 6, 6025251, 8 },
|
|
{ 619, 1561, 5732, 6, 6025253, 8 },
|
|
{ 888, 1557, 5631, 9, 6606885, 15 },
|
|
{ 380, 1561, 46, 6, 6025255, 8 },
|
|
{ 745, 1564, 1, 3, 6025259, 5 },
|
|
{ 1018, 1567, 1, 3, 6025261, 5 },
|
|
{ 1223, 1570, 1, 3, 6025263, 5 },
|
|
{ 1454, 1573, 1, 3, 6025265, 5 },
|
|
{ 153, 1576, 1, 3, 6025267, 5 },
|
|
{ 685, 1579, 1, 3, 6025269, 5 },
|
|
{ 952, 1582, 1, 3, 6025271, 5 },
|
|
{ 1151, 1585, 1, 3, 6025273, 5 },
|
|
{ 1382, 1588, 1, 3, 6025275, 5 },
|
|
{ 193, 1591, 1, 3, 6025277, 5 },
|
|
{ 725, 1594, 1, 3, 6025279, 5 },
|
|
{ 992, 1597, 1, 3, 6025281, 5 },
|
|
{ 1191, 1600, 1, 3, 6025283, 5 },
|
|
{ 1422, 1603, 1, 3, 6025285, 5 },
|
|
{ 233, 1606, 1, 3, 6025287, 5 },
|
|
{ 648, 1473, 6158, 6, 6025226, 8 },
|
|
{ 739, 1473, 5811, 6, 6025227, 8 },
|
|
{ 913, 1473, 4888, 6, 6025228, 8 },
|
|
{ 1012, 1473, 4916, 6, 6025229, 8 },
|
|
{ 1110, 1473, 3511, 6, 6025230, 8 },
|
|
{ 1217, 1473, 3262, 6, 6025231, 8 },
|
|
{ 1341, 1473, 2144, 6, 6025232, 8 },
|
|
{ 1448, 1473, 3396, 6, 6025233, 8 },
|
|
{ 18, 1473, 2414, 6, 6025234, 8 },
|
|
{ 145, 1473, 3329, 6, 6025235, 8 },
|
|
{ 269, 1473, 2329, 6, 6025236, 8 },
|
|
{ 677, 1473, 3707, 6, 6025237, 8 },
|
|
{ 772, 1473, 2685, 6, 6025238, 8 },
|
|
{ 944, 1473, 3640, 6, 6025239, 8 },
|
|
{ 1047, 1473, 2600, 6, 6025240, 8 },
|
|
{ 1143, 1473, 3918, 6, 6025241, 8 },
|
|
{ 1253, 1473, 2956, 6, 6025242, 8 },
|
|
{ 1374, 1473, 3851, 6, 6025243, 8 },
|
|
{ 53, 1473, 2871, 6, 6025244, 8 },
|
|
{ 185, 1473, 4129, 6, 6025245, 8 },
|
|
{ 305, 1473, 3177, 6, 6025246, 8 },
|
|
{ 717, 1473, 4062, 6, 6025247, 8 },
|
|
{ 808, 1473, 3092, 6, 6025248, 8 },
|
|
{ 984, 1473, 4322, 6, 6025249, 8 },
|
|
{ 1083, 1473, 4435, 6, 6025250, 8 },
|
|
{ 1183, 1473, 5337, 6, 6025251, 8 },
|
|
{ 1289, 1473, 5475, 6, 6025252, 8 },
|
|
{ 1414, 1473, 6024, 6, 6025253, 8 },
|
|
{ 89, 1473, 6269, 6, 6025254, 8 },
|
|
{ 225, 1473, 20, 6, 6025255, 8 },
|
|
{ 241, 1470, 20, 6, 6025225, 8 },
|
|
{ 499, 288, 5657, 47, 6606859, 15 },
|
|
{ 567, 301, 5663, 47, 6606861, 15 },
|
|
{ 635, 327, 4589, 47, 6606863, 15 },
|
|
{ 327, 314, 5675, 47, 6606865, 15 },
|
|
{ 401, 340, 4624, 47, 6606867, 15 },
|
|
{ 458, 353, 5683, 47, 6606869, 15 },
|
|
{ 521, 379, 4659, 47, 6606871, 15 },
|
|
{ 589, 366, 5695, 47, 6606873, 15 },
|
|
{ 350, 392, 4694, 47, 6606875, 15 },
|
|
{ 425, 405, 5707, 47, 6606877, 15 },
|
|
{ 482, 431, 4715, 47, 6606879, 15 },
|
|
{ 545, 418, 5748, 47, 6606881, 15 },
|
|
{ 613, 444, 5742, 47, 6606883, 15 },
|
|
{ 374, 457, 49, 47, 6606885, 15 },
|
|
{ 437, 105, 49, 47, 6606857, 15 },
|
|
{ 894, 784, 1, 233, 6590477, 41 },
|
|
{ 837, 735, 1, 233, 6590481, 41 },
|
|
{ 870, 686, 1, 233, 6590485, 41 },
|
|
{ 820, 637, 1, 233, 6590489, 41 },
|
|
{ 848, 588, 1, 233, 6590493, 41 },
|
|
{ 882, 539, 1, 233, 6590497, 41 },
|
|
{ 860, 490, 1, 233, 6590473, 41 },
|
|
{ 736, 1988, 6143, 31, 6610954, 11 },
|
|
{ 910, 1988, 5836, 31, 6610955, 11 },
|
|
{ 1009, 1988, 4951, 31, 6610956, 11 },
|
|
{ 1107, 1988, 4758, 31, 6610957, 11 },
|
|
{ 1214, 1988, 3546, 31, 6610958, 11 },
|
|
{ 1338, 1988, 3301, 31, 6610959, 11 },
|
|
{ 1445, 1988, 3435, 31, 6610960, 11 },
|
|
{ 15, 1988, 3463, 31, 6610961, 11 },
|
|
{ 142, 1988, 3822, 31, 6610962, 11 },
|
|
{ 265, 1988, 3368, 31, 6610963, 11 },
|
|
{ 673, 1988, 3746, 31, 6610964, 11 },
|
|
{ 768, 1988, 3774, 31, 6610965, 11 },
|
|
{ 940, 1988, 4033, 31, 6610966, 11 },
|
|
{ 1043, 1988, 3679, 31, 6610967, 11 },
|
|
{ 1139, 1988, 3957, 31, 6610968, 11 },
|
|
{ 1249, 1988, 3985, 31, 6610969, 11 },
|
|
{ 1370, 1988, 4244, 31, 6610970, 11 },
|
|
{ 49, 1988, 3890, 31, 6610971, 11 },
|
|
{ 181, 1988, 4168, 31, 6610972, 11 },
|
|
{ 301, 1988, 4196, 31, 6610973, 11 },
|
|
{ 713, 1988, 4518, 31, 6610974, 11 },
|
|
{ 804, 1988, 4101, 31, 6610975, 11 },
|
|
{ 980, 1988, 4361, 31, 6610976, 11 },
|
|
{ 1079, 1988, 4470, 31, 6610977, 11 },
|
|
{ 1179, 1988, 5503, 31, 6610978, 11 },
|
|
{ 1285, 1988, 5372, 31, 6610979, 11 },
|
|
{ 1410, 1988, 6049, 31, 6610980, 11 },
|
|
{ 85, 1988, 6286, 31, 6610981, 11 },
|
|
{ 221, 1988, 21, 31, 6610982, 11 },
|
|
{ 645, 1437, 21, 31, 6610953, 11 },
|
|
{ 562, 1941, 5643, 160, 6598667, 26 },
|
|
{ 630, 1914, 5671, 160, 6598669, 26 },
|
|
{ 322, 1887, 5691, 160, 6598671, 26 },
|
|
{ 396, 1860, 5679, 160, 6598673, 26 },
|
|
{ 452, 1833, 5703, 160, 6598675, 26 },
|
|
{ 515, 1806, 5687, 160, 6598677, 26 },
|
|
{ 583, 1779, 5715, 160, 6598679, 26 },
|
|
{ 344, 1752, 5699, 160, 6598681, 26 },
|
|
{ 419, 1725, 5756, 160, 6598683, 26 },
|
|
{ 476, 1698, 5711, 160, 6598685, 26 },
|
|
{ 539, 1671, 5760, 160, 6598687, 26 },
|
|
{ 607, 1644, 5752, 160, 6598689, 26 },
|
|
{ 368, 1617, 28, 160, 6598691, 26 },
|
|
{ 494, 1443, 28, 160, 6598665, 26 },
|
|
{ 907, 480, 6146, 37, 6606858, 15 },
|
|
{ 1006, 480, 5857, 37, 6606859, 15 },
|
|
{ 1104, 480, 4768, 37, 6606860, 15 },
|
|
{ 1211, 480, 4786, 37, 6606861, 15 },
|
|
{ 1335, 480, 3621, 37, 6606862, 15 },
|
|
{ 1442, 480, 4722, 37, 6606863, 15 },
|
|
{ 12, 480, 3492, 37, 6606864, 15 },
|
|
{ 139, 480, 5025, 37, 6606865, 15 },
|
|
{ 262, 480, 3832, 37, 6606866, 15 },
|
|
{ 669, 480, 4989, 37, 6606867, 15 },
|
|
{ 764, 480, 3803, 37, 6606868, 15 },
|
|
{ 936, 480, 5112, 37, 6606869, 15 },
|
|
{ 1039, 480, 4043, 37, 6606870, 15 },
|
|
{ 1135, 480, 5076, 37, 6606871, 15 },
|
|
{ 1245, 480, 4014, 37, 6606872, 15 },
|
|
{ 1366, 480, 5199, 37, 6606873, 15 },
|
|
{ 45, 480, 4254, 37, 6606874, 15 },
|
|
{ 177, 480, 5163, 37, 6606875, 15 },
|
|
{ 297, 480, 4225, 37, 6606876, 15 },
|
|
{ 709, 480, 5286, 37, 6606877, 15 },
|
|
{ 800, 480, 4528, 37, 6606878, 15 },
|
|
{ 976, 480, 5250, 37, 6606879, 15 },
|
|
{ 1075, 480, 4499, 37, 6606880, 15 },
|
|
{ 1175, 480, 5531, 37, 6606881, 15 },
|
|
{ 1281, 480, 5513, 37, 6606882, 15 },
|
|
{ 1406, 480, 5975, 37, 6606883, 15 },
|
|
{ 81, 480, 6257, 37, 6606884, 15 },
|
|
{ 217, 480, 22, 37, 6606885, 15 },
|
|
{ 733, 470, 22, 37, 6606857, 15 },
|
|
{ 625, 1385, 1, 187, 6590475, 41 },
|
|
{ 317, 1339, 73, 187, 6590477, 41 },
|
|
{ 391, 1293, 1, 187, 6590479, 41 },
|
|
{ 447, 1247, 70, 187, 6590481, 41 },
|
|
{ 509, 1201, 1, 187, 6590483, 41 },
|
|
{ 577, 1155, 67, 187, 6590485, 41 },
|
|
{ 338, 1109, 1, 187, 6590487, 41 },
|
|
{ 413, 1063, 64, 187, 6590489, 41 },
|
|
{ 470, 1017, 1, 187, 6590491, 41 },
|
|
{ 533, 971, 61, 187, 6590493, 41 },
|
|
{ 601, 925, 1, 187, 6590495, 41 },
|
|
{ 362, 879, 14, 187, 6590497, 41 },
|
|
{ 557, 833, 14, 187, 6590473, 41 },
|
|
{ 1003, 90, 6148, 60, 6602762, 20 },
|
|
{ 1101, 90, 5767, 60, 6602763, 20 },
|
|
{ 1208, 90, 4772, 60, 6602764, 20 },
|
|
{ 1332, 90, 4975, 60, 6602765, 20 },
|
|
{ 1439, 90, 5062, 60, 6602766, 20 },
|
|
{ 9, 90, 4744, 60, 6602767, 20 },
|
|
{ 136, 90, 5048, 60, 6602768, 20 },
|
|
{ 259, 90, 5034, 60, 6602769, 20 },
|
|
{ 666, 90, 5149, 60, 6602770, 20 },
|
|
{ 760, 90, 5011, 60, 6602771, 20 },
|
|
{ 932, 90, 5135, 60, 6602772, 20 },
|
|
{ 1035, 90, 5121, 60, 6602773, 20 },
|
|
{ 1131, 90, 5236, 60, 6602774, 20 },
|
|
{ 1241, 90, 5098, 60, 6602775, 20 },
|
|
{ 1362, 90, 5222, 60, 6602776, 20 },
|
|
{ 41, 90, 5208, 60, 6602777, 20 },
|
|
{ 173, 90, 5323, 60, 6602778, 20 },
|
|
{ 293, 90, 5185, 60, 6602779, 20 },
|
|
{ 705, 90, 5309, 60, 6602780, 20 },
|
|
{ 796, 90, 5295, 60, 6602781, 20 },
|
|
{ 972, 90, 5568, 60, 6602782, 20 },
|
|
{ 1071, 90, 5272, 60, 6602783, 20 },
|
|
{ 1171, 90, 5554, 60, 6602784, 20 },
|
|
{ 1277, 90, 5540, 60, 6602785, 20 },
|
|
{ 1402, 90, 6070, 60, 6602786, 20 },
|
|
{ 77, 90, 6237, 60, 6602787, 20 },
|
|
{ 213, 90, 24, 60, 6602788, 20 },
|
|
{ 904, 75, 24, 60, 6602761, 20 },
|
|
{ 1098, 139, 6129, 75, 6598666, 26 },
|
|
{ 1205, 139, 5770, 75, 6598667, 26 },
|
|
{ 1329, 139, 4779, 75, 6598668, 26 },
|
|
{ 1436, 139, 5885, 75, 6598669, 26 },
|
|
{ 6, 139, 5582, 75, 6598670, 26 },
|
|
{ 133, 139, 5875, 75, 6598671, 26 },
|
|
{ 256, 139, 5041, 75, 6598672, 26 },
|
|
{ 663, 139, 5905, 75, 6598673, 26 },
|
|
{ 757, 139, 5590, 75, 6598674, 26 },
|
|
{ 928, 139, 5895, 75, 6598675, 26 },
|
|
{ 1031, 139, 5128, 75, 6598676, 26 },
|
|
{ 1127, 139, 5925, 75, 6598677, 26 },
|
|
{ 1237, 139, 5598, 75, 6598678, 26 },
|
|
{ 1358, 139, 5915, 75, 6598679, 26 },
|
|
{ 37, 139, 5215, 75, 6598680, 26 },
|
|
{ 169, 139, 5945, 75, 6598681, 26 },
|
|
{ 289, 139, 5606, 75, 6598682, 26 },
|
|
{ 701, 139, 5935, 75, 6598683, 26 },
|
|
{ 792, 139, 5302, 75, 6598684, 26 },
|
|
{ 968, 139, 5965, 75, 6598685, 26 },
|
|
{ 1067, 139, 5614, 75, 6598686, 26 },
|
|
{ 1167, 139, 5955, 75, 6598687, 26 },
|
|
{ 1273, 139, 5365, 75, 6598688, 26 },
|
|
{ 1398, 139, 6083, 75, 6598689, 26 },
|
|
{ 73, 139, 6225, 75, 6598690, 26 },
|
|
{ 209, 139, 25, 75, 6598691, 26 },
|
|
{ 1000, 118, 25, 75, 6598665, 26 },
|
|
{ 1202, 188, 6131, 96, 6594570, 33 },
|
|
{ 1326, 188, 5776, 96, 6594571, 33 },
|
|
{ 1433, 188, 5891, 96, 6594572, 33 },
|
|
{ 3, 188, 6175, 96, 6594573, 33 },
|
|
{ 130, 188, 6180, 96, 6594574, 33 },
|
|
{ 253, 188, 5881, 96, 6594575, 33 },
|
|
{ 660, 188, 5911, 96, 6594576, 33 },
|
|
{ 754, 188, 6185, 96, 6594577, 33 },
|
|
{ 925, 188, 6190, 96, 6594578, 33 },
|
|
{ 1027, 188, 5901, 96, 6594579, 33 },
|
|
{ 1123, 188, 5931, 96, 6594580, 33 },
|
|
{ 1233, 188, 6195, 96, 6594581, 33 },
|
|
{ 1354, 188, 6200, 96, 6594582, 33 },
|
|
{ 33, 188, 5921, 96, 6594583, 33 },
|
|
{ 165, 188, 5951, 96, 6594584, 33 },
|
|
{ 285, 188, 6205, 96, 6594585, 33 },
|
|
{ 697, 188, 6210, 96, 6594586, 33 },
|
|
{ 788, 188, 5941, 96, 6594587, 33 },
|
|
{ 964, 188, 5971, 96, 6594588, 33 },
|
|
{ 1063, 188, 6215, 96, 6594589, 33 },
|
|
{ 1163, 188, 6220, 96, 6594590, 33 },
|
|
{ 1269, 188, 5961, 96, 6594591, 33 },
|
|
{ 1394, 188, 5989, 96, 6594592, 33 },
|
|
{ 69, 188, 6232, 96, 6594593, 33 },
|
|
{ 205, 188, 12, 96, 6594594, 33 },
|
|
{ 1095, 160, 12, 96, 6594569, 33 },
|
|
{ 1323, 252, 1, 124, 6590474, 41 },
|
|
{ 1430, 252, 10, 124, 6590475, 41 },
|
|
{ 0, 252, 1, 124, 6590476, 41 },
|
|
{ 127, 252, 72, 124, 6590477, 41 },
|
|
{ 250, 252, 1, 124, 6590478, 41 },
|
|
{ 657, 252, 8, 124, 6590479, 41 },
|
|
{ 751, 252, 1, 124, 6590480, 41 },
|
|
{ 922, 252, 69, 124, 6590481, 41 },
|
|
{ 1024, 252, 1, 124, 6590482, 41 },
|
|
{ 1119, 252, 6, 124, 6590483, 41 },
|
|
{ 1229, 252, 1, 124, 6590484, 41 },
|
|
{ 1350, 252, 66, 124, 6590485, 41 },
|
|
{ 29, 252, 1, 124, 6590486, 41 },
|
|
{ 161, 252, 4, 124, 6590487, 41 },
|
|
{ 281, 252, 1, 124, 6590488, 41 },
|
|
{ 693, 252, 63, 124, 6590489, 41 },
|
|
{ 784, 252, 1, 124, 6590490, 41 },
|
|
{ 960, 252, 2, 124, 6590491, 41 },
|
|
{ 1059, 252, 1, 124, 6590492, 41 },
|
|
{ 1159, 252, 60, 124, 6590493, 41 },
|
|
{ 1265, 252, 1, 124, 6590494, 41 },
|
|
{ 1390, 252, 0, 124, 6590495, 41 },
|
|
{ 65, 252, 1, 124, 6590496, 41 },
|
|
{ 201, 252, 13, 124, 6590497, 41 },
|
|
{ 1199, 216, 13, 124, 6590473, 41 },
|
|
};
|
|
|
|
// FPR16 Register Class...
|
|
static const MCPhysReg FPR16[] = {
|
|
RISCV_F15_H, RISCV_F14_H, RISCV_F13_H, RISCV_F12_H, RISCV_F11_H, RISCV_F10_H, RISCV_F0_H, RISCV_F1_H, RISCV_F2_H, RISCV_F3_H, RISCV_F4_H, RISCV_F5_H, RISCV_F6_H, RISCV_F7_H, RISCV_F16_H, RISCV_F17_H, RISCV_F28_H, RISCV_F29_H, RISCV_F30_H, RISCV_F31_H, RISCV_F8_H, RISCV_F9_H, RISCV_F18_H, RISCV_F19_H, RISCV_F20_H, RISCV_F21_H, RISCV_F22_H, RISCV_F23_H, RISCV_F24_H, RISCV_F25_H, RISCV_F26_H, RISCV_F27_H,
|
|
};
|
|
|
|
// FPR16 Bit set.
|
|
static const uint8_t FPR16Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRAll Register Class...
|
|
static const MCPhysReg GPRAll[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, RISCV_DUMMY_REG_PAIR_WITH_X0,
|
|
};
|
|
|
|
// GPRAll Bit set.
|
|
static const uint8_t GPRAllBits[] = {
|
|
0x00, 0x02, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// FPR32 Register Class...
|
|
static const MCPhysReg FPR32[] = {
|
|
RISCV_F15_F, RISCV_F14_F, RISCV_F13_F, RISCV_F12_F, RISCV_F11_F, RISCV_F10_F, RISCV_F0_F, RISCV_F1_F, RISCV_F2_F, RISCV_F3_F, RISCV_F4_F, RISCV_F5_F, RISCV_F6_F, RISCV_F7_F, RISCV_F16_F, RISCV_F17_F, RISCV_F28_F, RISCV_F29_F, RISCV_F30_F, RISCV_F31_F, RISCV_F8_F, RISCV_F9_F, RISCV_F18_F, RISCV_F19_F, RISCV_F20_F, RISCV_F21_F, RISCV_F22_F, RISCV_F23_F, RISCV_F24_F, RISCV_F25_F, RISCV_F26_F, RISCV_F27_F,
|
|
};
|
|
|
|
// FPR32 Bit set.
|
|
static const uint8_t FPR32Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPR Register Class...
|
|
static const MCPhysReg GPR[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
|
|
};
|
|
|
|
// GPR Bit set.
|
|
static const uint8_t GPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRF16 Register Class...
|
|
static const MCPhysReg GPRF16[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
|
|
};
|
|
|
|
// GPRF16 Bit set.
|
|
static const uint8_t GPRF16Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRF32 Register Class...
|
|
static const MCPhysReg GPRF32[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
|
|
};
|
|
|
|
// GPRF32 Bit set.
|
|
static const uint8_t GPRF32Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRNoX0 Register Class...
|
|
static const MCPhysReg GPRNoX0[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
|
|
};
|
|
|
|
// GPRNoX0 Bit set.
|
|
static const uint8_t GPRNoX0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRNoX0X2 Register Class...
|
|
static const MCPhysReg GPRNoX0X2[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4,
|
|
};
|
|
|
|
// GPRNoX0X2 Bit set.
|
|
static const uint8_t GPRNoX0X2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRJALR Register Class...
|
|
static const MCPhysReg GPRJALR[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27,
|
|
};
|
|
|
|
// GPRJALR Bit set.
|
|
static const uint8_t GPRJALRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRTC Register Class...
|
|
static const MCPhysReg GPRTC[] = {
|
|
RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31,
|
|
};
|
|
|
|
// GPRTC Bit set.
|
|
static const uint8_t GPRTCBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x0f, 0xc0, 0x03,
|
|
};
|
|
|
|
// FPR32C Register Class...
|
|
static const MCPhysReg FPR32C[] = {
|
|
RISCV_F15_F, RISCV_F14_F, RISCV_F13_F, RISCV_F12_F, RISCV_F11_F, RISCV_F10_F, RISCV_F8_F, RISCV_F9_F,
|
|
};
|
|
|
|
// FPR32C Bit set.
|
|
static const uint8_t FPR32CBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
|
};
|
|
|
|
// GPRC Register Class...
|
|
static const MCPhysReg GPRC[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9,
|
|
};
|
|
|
|
// GPRC Bit set.
|
|
static const uint8_t GPRCBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
|
};
|
|
|
|
// SR07 Register Class...
|
|
static const MCPhysReg SR07[] = {
|
|
RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23,
|
|
};
|
|
|
|
// SR07 Bit set.
|
|
static const uint8_t SR07Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0xf0, 0x03,
|
|
};
|
|
|
|
// GPRC_and_GPRTC Register Class...
|
|
static const MCPhysReg GPRC_and_GPRTC[] = {
|
|
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15,
|
|
};
|
|
|
|
// GPRC_and_GPRTC Bit set.
|
|
static const uint8_t GPRC_and_GPRTCBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
|
|
};
|
|
|
|
// VCSR Register Class...
|
|
static const MCPhysReg VCSR[] = {
|
|
RISCV_VTYPE, RISCV_VL, RISCV_VLENB,
|
|
};
|
|
|
|
// VCSR Bit set.
|
|
static const uint8_t VCSRBits[] = {
|
|
0x70,
|
|
};
|
|
|
|
// GPRC_and_SR07 Register Class...
|
|
static const MCPhysReg GPRC_and_SR07[] = {
|
|
RISCV_X8, RISCV_X9,
|
|
};
|
|
|
|
// GPRC_and_SR07 Bit set.
|
|
static const uint8_t GPRC_and_SR07Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
|
|
};
|
|
|
|
// GPRX1X5 Register Class...
|
|
static const MCPhysReg GPRX1X5[] = {
|
|
RISCV_X1, RISCV_X5,
|
|
};
|
|
|
|
// GPRX1X5 Bit set.
|
|
static const uint8_t GPRX1X5Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x88,
|
|
};
|
|
|
|
// GPRX0 Register Class...
|
|
static const MCPhysReg GPRX0[] = {
|
|
RISCV_X0,
|
|
};
|
|
|
|
// GPRX0 Bit set.
|
|
static const uint8_t GPRX0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
|
};
|
|
|
|
// GPRX1 Register Class...
|
|
static const MCPhysReg GPRX1[] = {
|
|
RISCV_X1,
|
|
};
|
|
|
|
// GPRX1 Bit set.
|
|
static const uint8_t GPRX1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
|
};
|
|
|
|
// GPRX5 Register Class...
|
|
static const MCPhysReg GPRX5[] = {
|
|
RISCV_X5,
|
|
};
|
|
|
|
// GPRX5 Bit set.
|
|
static const uint8_t GPRX5Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
|
|
};
|
|
|
|
// SP Register Class...
|
|
static const MCPhysReg SP[] = {
|
|
RISCV_X2,
|
|
};
|
|
|
|
// SP Bit set.
|
|
static const uint8_t SPBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
|
|
};
|
|
|
|
// FPR64 Register Class...
|
|
static const MCPhysReg FPR64[] = {
|
|
RISCV_F15_D, RISCV_F14_D, RISCV_F13_D, RISCV_F12_D, RISCV_F11_D, RISCV_F10_D, RISCV_F0_D, RISCV_F1_D, RISCV_F2_D, RISCV_F3_D, RISCV_F4_D, RISCV_F5_D, RISCV_F6_D, RISCV_F7_D, RISCV_F16_D, RISCV_F17_D, RISCV_F28_D, RISCV_F29_D, RISCV_F30_D, RISCV_F31_D, RISCV_F8_D, RISCV_F9_D, RISCV_F18_D, RISCV_F19_D, RISCV_F20_D, RISCV_F21_D, RISCV_F22_D, RISCV_F23_D, RISCV_F24_D, RISCV_F25_D, RISCV_F26_D, RISCV_F27_D,
|
|
};
|
|
|
|
// FPR64 Bit set.
|
|
static const uint8_t FPR64Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// VM Register Class...
|
|
static const MCPhysReg VM[] = {
|
|
RISCV_V8, RISCV_V9, RISCV_V10, RISCV_V11, RISCV_V12, RISCV_V13, RISCV_V14, RISCV_V15, RISCV_V16, RISCV_V17, RISCV_V18, RISCV_V19, RISCV_V20, RISCV_V21, RISCV_V22, RISCV_V23, RISCV_V24, RISCV_V25, RISCV_V26, RISCV_V27, RISCV_V28, RISCV_V29, RISCV_V30, RISCV_V31, RISCV_V0, RISCV_V1, RISCV_V2, RISCV_V3, RISCV_V4, RISCV_V5, RISCV_V6, RISCV_V7,
|
|
};
|
|
|
|
// VM Bit set.
|
|
static const uint8_t VMBits[] = {
|
|
0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// VR Register Class...
|
|
static const MCPhysReg VR[] = {
|
|
RISCV_V8, RISCV_V9, RISCV_V10, RISCV_V11, RISCV_V12, RISCV_V13, RISCV_V14, RISCV_V15, RISCV_V16, RISCV_V17, RISCV_V18, RISCV_V19, RISCV_V20, RISCV_V21, RISCV_V22, RISCV_V23, RISCV_V24, RISCV_V25, RISCV_V26, RISCV_V27, RISCV_V28, RISCV_V29, RISCV_V30, RISCV_V31, RISCV_V0, RISCV_V1, RISCV_V2, RISCV_V3, RISCV_V4, RISCV_V5, RISCV_V6, RISCV_V7,
|
|
};
|
|
|
|
// VR Bit set.
|
|
static const uint8_t VRBits[] = {
|
|
0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// VRNoV0 Register Class...
|
|
static const MCPhysReg VRNoV0[] = {
|
|
RISCV_V8, RISCV_V9, RISCV_V10, RISCV_V11, RISCV_V12, RISCV_V13, RISCV_V14, RISCV_V15, RISCV_V16, RISCV_V17, RISCV_V18, RISCV_V19, RISCV_V20, RISCV_V21, RISCV_V22, RISCV_V23, RISCV_V24, RISCV_V25, RISCV_V26, RISCV_V27, RISCV_V28, RISCV_V29, RISCV_V30, RISCV_V31, RISCV_V1, RISCV_V2, RISCV_V3, RISCV_V4, RISCV_V5, RISCV_V6, RISCV_V7,
|
|
};
|
|
|
|
// VRNoV0 Bit set.
|
|
static const uint8_t VRNoV0Bits[] = {
|
|
0x00, 0xf8, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// GPRPair Register Class...
|
|
static const MCPhysReg GPRPair[] = {
|
|
RISCV_X10_X11, RISCV_X12_X13, RISCV_X14_X15, RISCV_X16_X17, RISCV_X6_X7, RISCV_X28_X29, RISCV_X30_X31, RISCV_X8_X9, RISCV_X18_X19, RISCV_X20_X21, RISCV_X22_X23, RISCV_X24_X25, RISCV_X26_X27, RISCV_X0_Pair, RISCV_X2_X3, RISCV_X4_X5,
|
|
};
|
|
|
|
// GPRPair Bit set.
|
|
static const uint8_t GPRPairBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x80, 0xff, 0x3f,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRNoX0 Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRNoX0[] = {
|
|
RISCV_X10_X11, RISCV_X12_X13, RISCV_X14_X15, RISCV_X16_X17, RISCV_X6_X7, RISCV_X28_X29, RISCV_X30_X31, RISCV_X8_X9, RISCV_X18_X19, RISCV_X20_X21, RISCV_X22_X23, RISCV_X24_X25, RISCV_X26_X27, RISCV_X2_X3, RISCV_X4_X5,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRNoX0 Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRNoX0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRNoX0X2 Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRNoX0X2[] = {
|
|
RISCV_X10_X11, RISCV_X12_X13, RISCV_X14_X15, RISCV_X16_X17, RISCV_X6_X7, RISCV_X28_X29, RISCV_X30_X31, RISCV_X8_X9, RISCV_X18_X19, RISCV_X20_X21, RISCV_X22_X23, RISCV_X24_X25, RISCV_X26_X27, RISCV_X4_X5,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRNoX0X2 Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRJALR Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRJALR[] = {
|
|
RISCV_X10_X11, RISCV_X12_X13, RISCV_X14_X15, RISCV_X16_X17, RISCV_X6_X7, RISCV_X28_X29, RISCV_X30_X31, RISCV_X8_X9, RISCV_X18_X19, RISCV_X20_X21, RISCV_X22_X23, RISCV_X24_X25, RISCV_X26_X27,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRJALR Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRJALRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// FPR64C Register Class...
|
|
static const MCPhysReg FPR64C[] = {
|
|
RISCV_F15_D, RISCV_F14_D, RISCV_F13_D, RISCV_F12_D, RISCV_F11_D, RISCV_F10_D, RISCV_F8_D, RISCV_F9_D,
|
|
};
|
|
|
|
// FPR64C Bit set.
|
|
static const uint8_t FPR64CBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRTC Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRTC[] = {
|
|
RISCV_X10_X11, RISCV_X12_X13, RISCV_X14_X15, RISCV_X16_X17, RISCV_X6_X7, RISCV_X28_X29, RISCV_X30_X31,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRTC Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRTCBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x30,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRC Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC[] = {
|
|
RISCV_X10_X11, RISCV_X12_X13, RISCV_X14_X15, RISCV_X8_X9,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRC Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRCBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_SR07 Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_SR07[] = {
|
|
RISCV_X8_X9, RISCV_X18_X19, RISCV_X20_X21, RISCV_X22_X23,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_SR07 Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_SR07Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x03,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC[] = {
|
|
RISCV_X10_X11, RISCV_X12_X13, RISCV_X14_X15,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRC_and_SR07 Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC_and_SR07[] = {
|
|
RISCV_X8_X9,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRC_and_SR07 Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRX0 Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRX0[] = {
|
|
RISCV_X0_Pair,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_GPRX0 Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_GPRX0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_SP Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_even_in_SP[] = {
|
|
RISCV_X2_X3,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_even_in_SP Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_even_in_SPBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_odd_in_GPRX1X5 Register Class...
|
|
static const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRX1X5[] = {
|
|
RISCV_X4_X5,
|
|
};
|
|
|
|
// GPRPair_with_sub_gpr_odd_in_GPRX1X5 Bit set.
|
|
static const uint8_t GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
|
};
|
|
|
|
// VMV0 Register Class...
|
|
static const MCPhysReg VMV0[] = {
|
|
RISCV_V0,
|
|
};
|
|
|
|
// VMV0 Bit set.
|
|
static const uint8_t VMV0Bits[] = {
|
|
0x00, 0x04,
|
|
};
|
|
|
|
// VRN2M1 Register Class...
|
|
static const MCPhysReg VRN2M1[] = {
|
|
RISCV_V8_V9, RISCV_V9_V10, RISCV_V10_V11, RISCV_V11_V12, RISCV_V12_V13, RISCV_V13_V14, RISCV_V14_V15, RISCV_V15_V16, RISCV_V16_V17, RISCV_V17_V18, RISCV_V18_V19, RISCV_V19_V20, RISCV_V20_V21, RISCV_V21_V22, RISCV_V22_V23, RISCV_V23_V24, RISCV_V24_V25, RISCV_V25_V26, RISCV_V26_V27, RISCV_V27_V28, RISCV_V28_V29, RISCV_V29_V30, RISCV_V30_V31, RISCV_V1_V2, RISCV_V2_V3, RISCV_V3_V4, RISCV_V4_V5, RISCV_V5_V6, RISCV_V6_V7, RISCV_V7_V8, RISCV_V0_V1,
|
|
};
|
|
|
|
// VRN2M1 Bit set.
|
|
static const uint8_t VRN2M1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f,
|
|
};
|
|
|
|
// VRN2M1NoV0 Register Class...
|
|
static const MCPhysReg VRN2M1NoV0[] = {
|
|
RISCV_V8_V9, RISCV_V9_V10, RISCV_V10_V11, RISCV_V11_V12, RISCV_V12_V13, RISCV_V13_V14, RISCV_V14_V15, RISCV_V15_V16, RISCV_V16_V17, RISCV_V17_V18, RISCV_V18_V19, RISCV_V19_V20, RISCV_V20_V21, RISCV_V21_V22, RISCV_V22_V23, RISCV_V23_V24, RISCV_V24_V25, RISCV_V25_V26, RISCV_V26_V27, RISCV_V27_V28, RISCV_V28_V29, RISCV_V29_V30, RISCV_V30_V31, RISCV_V1_V2, RISCV_V2_V3, RISCV_V3_V4, RISCV_V4_V5, RISCV_V5_V6, RISCV_V6_V7, RISCV_V7_V8,
|
|
};
|
|
|
|
// VRN2M1NoV0 Bit set.
|
|
static const uint8_t VRN2M1NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f,
|
|
};
|
|
|
|
// VRM2 Register Class...
|
|
static const MCPhysReg VRM2[] = {
|
|
RISCV_V8M2, RISCV_V10M2, RISCV_V12M2, RISCV_V14M2, RISCV_V16M2, RISCV_V18M2, RISCV_V20M2, RISCV_V22M2, RISCV_V24M2, RISCV_V26M2, RISCV_V28M2, RISCV_V30M2, RISCV_V0M2, RISCV_V2M2, RISCV_V4M2, RISCV_V6M2,
|
|
};
|
|
|
|
// VRM2 Bit set.
|
|
static const uint8_t VRM2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x66, 0xb3, 0x59,
|
|
};
|
|
|
|
// VRM2NoV0 Register Class...
|
|
static const MCPhysReg VRM2NoV0[] = {
|
|
RISCV_V8M2, RISCV_V10M2, RISCV_V12M2, RISCV_V14M2, RISCV_V16M2, RISCV_V18M2, RISCV_V20M2, RISCV_V22M2, RISCV_V24M2, RISCV_V26M2, RISCV_V28M2, RISCV_V30M2, RISCV_V2M2, RISCV_V4M2, RISCV_V6M2,
|
|
};
|
|
|
|
// VRM2NoV0 Bit set.
|
|
static const uint8_t VRM2NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x66, 0xb3, 0x59,
|
|
};
|
|
|
|
// VRM2_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRM2_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0M2,
|
|
};
|
|
|
|
// VRM2_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRM2_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
|
};
|
|
|
|
// VRN2M1_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN2M1_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0_V1,
|
|
};
|
|
|
|
// VRN2M1_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN2M1_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
|
|
};
|
|
|
|
// VRN3M1 Register Class...
|
|
static const MCPhysReg VRN3M1[] = {
|
|
RISCV_V8_V9_V10, RISCV_V9_V10_V11, RISCV_V10_V11_V12, RISCV_V11_V12_V13, RISCV_V12_V13_V14, RISCV_V13_V14_V15, RISCV_V14_V15_V16, RISCV_V15_V16_V17, RISCV_V16_V17_V18, RISCV_V17_V18_V19, RISCV_V18_V19_V20, RISCV_V19_V20_V21, RISCV_V20_V21_V22, RISCV_V21_V22_V23, RISCV_V22_V23_V24, RISCV_V23_V24_V25, RISCV_V24_V25_V26, RISCV_V25_V26_V27, RISCV_V26_V27_V28, RISCV_V27_V28_V29, RISCV_V28_V29_V30, RISCV_V29_V30_V31, RISCV_V1_V2_V3, RISCV_V2_V3_V4, RISCV_V3_V4_V5, RISCV_V4_V5_V6, RISCV_V5_V6_V7, RISCV_V6_V7_V8, RISCV_V7_V8_V9, RISCV_V0_V1_V2,
|
|
};
|
|
|
|
// VRN3M1 Bit set.
|
|
static const uint8_t VRN3M1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x01,
|
|
};
|
|
|
|
// VRN3M1NoV0 Register Class...
|
|
static const MCPhysReg VRN3M1NoV0[] = {
|
|
RISCV_V8_V9_V10, RISCV_V9_V10_V11, RISCV_V10_V11_V12, RISCV_V11_V12_V13, RISCV_V12_V13_V14, RISCV_V13_V14_V15, RISCV_V14_V15_V16, RISCV_V15_V16_V17, RISCV_V16_V17_V18, RISCV_V17_V18_V19, RISCV_V18_V19_V20, RISCV_V19_V20_V21, RISCV_V20_V21_V22, RISCV_V21_V22_V23, RISCV_V22_V23_V24, RISCV_V23_V24_V25, RISCV_V24_V25_V26, RISCV_V25_V26_V27, RISCV_V26_V27_V28, RISCV_V27_V28_V29, RISCV_V28_V29_V30, RISCV_V29_V30_V31, RISCV_V1_V2_V3, RISCV_V2_V3_V4, RISCV_V3_V4_V5, RISCV_V4_V5_V6, RISCV_V5_V6_V7, RISCV_V6_V7_V8, RISCV_V7_V8_V9,
|
|
};
|
|
|
|
// VRN3M1NoV0 Bit set.
|
|
static const uint8_t VRN3M1NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff,
|
|
};
|
|
|
|
// VRN3M1_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN3M1_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0_V1_V2,
|
|
};
|
|
|
|
// VRN3M1_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN3M1_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
|
};
|
|
|
|
// VRN4M1 Register Class...
|
|
static const MCPhysReg VRN4M1[] = {
|
|
RISCV_V8_V9_V10_V11, RISCV_V9_V10_V11_V12, RISCV_V10_V11_V12_V13, RISCV_V11_V12_V13_V14, RISCV_V12_V13_V14_V15, RISCV_V13_V14_V15_V16, RISCV_V14_V15_V16_V17, RISCV_V15_V16_V17_V18, RISCV_V16_V17_V18_V19, RISCV_V17_V18_V19_V20, RISCV_V18_V19_V20_V21, RISCV_V19_V20_V21_V22, RISCV_V20_V21_V22_V23, RISCV_V21_V22_V23_V24, RISCV_V22_V23_V24_V25, RISCV_V23_V24_V25_V26, RISCV_V24_V25_V26_V27, RISCV_V25_V26_V27_V28, RISCV_V26_V27_V28_V29, RISCV_V27_V28_V29_V30, RISCV_V28_V29_V30_V31, RISCV_V1_V2_V3_V4, RISCV_V2_V3_V4_V5, RISCV_V3_V4_V5_V6, RISCV_V4_V5_V6_V7, RISCV_V5_V6_V7_V8, RISCV_V6_V7_V8_V9, RISCV_V7_V8_V9_V10, RISCV_V0_V1_V2_V3,
|
|
};
|
|
|
|
// VRN4M1 Bit set.
|
|
static const uint8_t VRN4M1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
|
|
};
|
|
|
|
// VRN4M1NoV0 Register Class...
|
|
static const MCPhysReg VRN4M1NoV0[] = {
|
|
RISCV_V8_V9_V10_V11, RISCV_V9_V10_V11_V12, RISCV_V10_V11_V12_V13, RISCV_V11_V12_V13_V14, RISCV_V12_V13_V14_V15, RISCV_V13_V14_V15_V16, RISCV_V14_V15_V16_V17, RISCV_V15_V16_V17_V18, RISCV_V16_V17_V18_V19, RISCV_V17_V18_V19_V20, RISCV_V18_V19_V20_V21, RISCV_V19_V20_V21_V22, RISCV_V20_V21_V22_V23, RISCV_V21_V22_V23_V24, RISCV_V22_V23_V24_V25, RISCV_V23_V24_V25_V26, RISCV_V24_V25_V26_V27, RISCV_V25_V26_V27_V28, RISCV_V26_V27_V28_V29, RISCV_V27_V28_V29_V30, RISCV_V28_V29_V30_V31, RISCV_V1_V2_V3_V4, RISCV_V2_V3_V4_V5, RISCV_V3_V4_V5_V6, RISCV_V4_V5_V6_V7, RISCV_V5_V6_V7_V8, RISCV_V6_V7_V8_V9, RISCV_V7_V8_V9_V10,
|
|
};
|
|
|
|
// VRN4M1NoV0 Bit set.
|
|
static const uint8_t VRN4M1NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x07,
|
|
};
|
|
|
|
// VRN2M2 Register Class...
|
|
static const MCPhysReg VRN2M2[] = {
|
|
RISCV_V8M2_V10M2, RISCV_V10M2_V12M2, RISCV_V12M2_V14M2, RISCV_V14M2_V16M2, RISCV_V16M2_V18M2, RISCV_V18M2_V20M2, RISCV_V20M2_V22M2, RISCV_V22M2_V24M2, RISCV_V24M2_V26M2, RISCV_V26M2_V28M2, RISCV_V28M2_V30M2, RISCV_V2M2_V4M2, RISCV_V4M2_V6M2, RISCV_V6M2_V8M2, RISCV_V0M2_V2M2,
|
|
};
|
|
|
|
// VRN2M2 Bit set.
|
|
static const uint8_t VRN2M2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
|
|
};
|
|
|
|
// VRN2M2NoV0 Register Class...
|
|
static const MCPhysReg VRN2M2NoV0[] = {
|
|
RISCV_V8M2_V10M2, RISCV_V10M2_V12M2, RISCV_V12M2_V14M2, RISCV_V14M2_V16M2, RISCV_V16M2_V18M2, RISCV_V18M2_V20M2, RISCV_V20M2_V22M2, RISCV_V22M2_V24M2, RISCV_V24M2_V26M2, RISCV_V26M2_V28M2, RISCV_V28M2_V30M2, RISCV_V2M2_V4M2, RISCV_V4M2_V6M2, RISCV_V6M2_V8M2,
|
|
};
|
|
|
|
// VRN2M2NoV0 Bit set.
|
|
static const uint8_t VRN2M2NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
|
|
};
|
|
|
|
// VRM4 Register Class...
|
|
static const MCPhysReg VRM4[] = {
|
|
RISCV_V8M4, RISCV_V12M4, RISCV_V16M4, RISCV_V20M4, RISCV_V24M4, RISCV_V28M4, RISCV_V0M4, RISCV_V4M4,
|
|
};
|
|
|
|
// VRM4 Bit set.
|
|
static const uint8_t VRM4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x89, 0x44, 0x22,
|
|
};
|
|
|
|
// VRM4NoV0 Register Class...
|
|
static const MCPhysReg VRM4NoV0[] = {
|
|
RISCV_V8M4, RISCV_V12M4, RISCV_V16M4, RISCV_V20M4, RISCV_V24M4, RISCV_V28M4, RISCV_V4M4,
|
|
};
|
|
|
|
// VRM4NoV0 Bit set.
|
|
static const uint8_t VRM4NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x44, 0x22,
|
|
};
|
|
|
|
// VRM4_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRM4_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0M4,
|
|
};
|
|
|
|
// VRM4_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRM4_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
|
|
};
|
|
|
|
// VRN2M2_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN2M2_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0M2_V2M2,
|
|
};
|
|
|
|
// VRN2M2_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN2M2_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
|
};
|
|
|
|
// VRN4M1_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN4M1_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0_V1_V2_V3,
|
|
};
|
|
|
|
// VRN4M1_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN4M1_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
|
};
|
|
|
|
// VRN5M1 Register Class...
|
|
static const MCPhysReg VRN5M1[] = {
|
|
RISCV_V8_V9_V10_V11_V12, RISCV_V9_V10_V11_V12_V13, RISCV_V10_V11_V12_V13_V14, RISCV_V11_V12_V13_V14_V15, RISCV_V12_V13_V14_V15_V16, RISCV_V13_V14_V15_V16_V17, RISCV_V14_V15_V16_V17_V18, RISCV_V15_V16_V17_V18_V19, RISCV_V16_V17_V18_V19_V20, RISCV_V17_V18_V19_V20_V21, RISCV_V18_V19_V20_V21_V22, RISCV_V19_V20_V21_V22_V23, RISCV_V20_V21_V22_V23_V24, RISCV_V21_V22_V23_V24_V25, RISCV_V22_V23_V24_V25_V26, RISCV_V23_V24_V25_V26_V27, RISCV_V24_V25_V26_V27_V28, RISCV_V25_V26_V27_V28_V29, RISCV_V26_V27_V28_V29_V30, RISCV_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5, RISCV_V2_V3_V4_V5_V6, RISCV_V3_V4_V5_V6_V7, RISCV_V4_V5_V6_V7_V8, RISCV_V5_V6_V7_V8_V9, RISCV_V6_V7_V8_V9_V10, RISCV_V7_V8_V9_V10_V11, RISCV_V0_V1_V2_V3_V4,
|
|
};
|
|
|
|
// VRN5M1 Bit set.
|
|
static const uint8_t VRN5M1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x1f,
|
|
};
|
|
|
|
// VRN5M1NoV0 Register Class...
|
|
static const MCPhysReg VRN5M1NoV0[] = {
|
|
RISCV_V8_V9_V10_V11_V12, RISCV_V9_V10_V11_V12_V13, RISCV_V10_V11_V12_V13_V14, RISCV_V11_V12_V13_V14_V15, RISCV_V12_V13_V14_V15_V16, RISCV_V13_V14_V15_V16_V17, RISCV_V14_V15_V16_V17_V18, RISCV_V15_V16_V17_V18_V19, RISCV_V16_V17_V18_V19_V20, RISCV_V17_V18_V19_V20_V21, RISCV_V18_V19_V20_V21_V22, RISCV_V19_V20_V21_V22_V23, RISCV_V20_V21_V22_V23_V24, RISCV_V21_V22_V23_V24_V25, RISCV_V22_V23_V24_V25_V26, RISCV_V23_V24_V25_V26_V27, RISCV_V24_V25_V26_V27_V28, RISCV_V25_V26_V27_V28_V29, RISCV_V26_V27_V28_V29_V30, RISCV_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5, RISCV_V2_V3_V4_V5_V6, RISCV_V3_V4_V5_V6_V7, RISCV_V4_V5_V6_V7_V8, RISCV_V5_V6_V7_V8_V9, RISCV_V6_V7_V8_V9_V10, RISCV_V7_V8_V9_V10_V11,
|
|
};
|
|
|
|
// VRN5M1NoV0 Bit set.
|
|
static const uint8_t VRN5M1NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x0f,
|
|
};
|
|
|
|
// VRN5M1_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN5M1_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0_V1_V2_V3_V4,
|
|
};
|
|
|
|
// VRN5M1_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN5M1_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
|
|
};
|
|
|
|
// VRN6M1 Register Class...
|
|
static const MCPhysReg VRN6M1[] = {
|
|
RISCV_V8_V9_V10_V11_V12_V13, RISCV_V9_V10_V11_V12_V13_V14, RISCV_V10_V11_V12_V13_V14_V15, RISCV_V11_V12_V13_V14_V15_V16, RISCV_V12_V13_V14_V15_V16_V17, RISCV_V13_V14_V15_V16_V17_V18, RISCV_V14_V15_V16_V17_V18_V19, RISCV_V15_V16_V17_V18_V19_V20, RISCV_V16_V17_V18_V19_V20_V21, RISCV_V17_V18_V19_V20_V21_V22, RISCV_V18_V19_V20_V21_V22_V23, RISCV_V19_V20_V21_V22_V23_V24, RISCV_V20_V21_V22_V23_V24_V25, RISCV_V21_V22_V23_V24_V25_V26, RISCV_V22_V23_V24_V25_V26_V27, RISCV_V23_V24_V25_V26_V27_V28, RISCV_V24_V25_V26_V27_V28_V29, RISCV_V25_V26_V27_V28_V29_V30, RISCV_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6, RISCV_V2_V3_V4_V5_V6_V7, RISCV_V3_V4_V5_V6_V7_V8, RISCV_V4_V5_V6_V7_V8_V9, RISCV_V5_V6_V7_V8_V9_V10, RISCV_V6_V7_V8_V9_V10_V11, RISCV_V7_V8_V9_V10_V11_V12, RISCV_V0_V1_V2_V3_V4_V5,
|
|
};
|
|
|
|
// VRN6M1 Bit set.
|
|
static const uint8_t VRN6M1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff,
|
|
};
|
|
|
|
// VRN6M1NoV0 Register Class...
|
|
static const MCPhysReg VRN6M1NoV0[] = {
|
|
RISCV_V8_V9_V10_V11_V12_V13, RISCV_V9_V10_V11_V12_V13_V14, RISCV_V10_V11_V12_V13_V14_V15, RISCV_V11_V12_V13_V14_V15_V16, RISCV_V12_V13_V14_V15_V16_V17, RISCV_V13_V14_V15_V16_V17_V18, RISCV_V14_V15_V16_V17_V18_V19, RISCV_V15_V16_V17_V18_V19_V20, RISCV_V16_V17_V18_V19_V20_V21, RISCV_V17_V18_V19_V20_V21_V22, RISCV_V18_V19_V20_V21_V22_V23, RISCV_V19_V20_V21_V22_V23_V24, RISCV_V20_V21_V22_V23_V24_V25, RISCV_V21_V22_V23_V24_V25_V26, RISCV_V22_V23_V24_V25_V26_V27, RISCV_V23_V24_V25_V26_V27_V28, RISCV_V24_V25_V26_V27_V28_V29, RISCV_V25_V26_V27_V28_V29_V30, RISCV_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6, RISCV_V2_V3_V4_V5_V6_V7, RISCV_V3_V4_V5_V6_V7_V8, RISCV_V4_V5_V6_V7_V8_V9, RISCV_V5_V6_V7_V8_V9_V10, RISCV_V6_V7_V8_V9_V10_V11, RISCV_V7_V8_V9_V10_V11_V12,
|
|
};
|
|
|
|
// VRN6M1NoV0 Bit set.
|
|
static const uint8_t VRN6M1NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x7f,
|
|
};
|
|
|
|
// VRN3M2 Register Class...
|
|
static const MCPhysReg VRN3M2[] = {
|
|
RISCV_V8M2_V10M2_V12M2, RISCV_V10M2_V12M2_V14M2, RISCV_V12M2_V14M2_V16M2, RISCV_V14M2_V16M2_V18M2, RISCV_V16M2_V18M2_V20M2, RISCV_V18M2_V20M2_V22M2, RISCV_V20M2_V22M2_V24M2, RISCV_V22M2_V24M2_V26M2, RISCV_V24M2_V26M2_V28M2, RISCV_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2, RISCV_V4M2_V6M2_V8M2, RISCV_V6M2_V8M2_V10M2, RISCV_V0M2_V2M2_V4M2,
|
|
};
|
|
|
|
// VRN3M2 Bit set.
|
|
static const uint8_t VRN3M2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f,
|
|
};
|
|
|
|
// VRN3M2NoV0 Register Class...
|
|
static const MCPhysReg VRN3M2NoV0[] = {
|
|
RISCV_V8M2_V10M2_V12M2, RISCV_V10M2_V12M2_V14M2, RISCV_V12M2_V14M2_V16M2, RISCV_V14M2_V16M2_V18M2, RISCV_V16M2_V18M2_V20M2, RISCV_V18M2_V20M2_V22M2, RISCV_V20M2_V22M2_V24M2, RISCV_V22M2_V24M2_V26M2, RISCV_V24M2_V26M2_V28M2, RISCV_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2, RISCV_V4M2_V6M2_V8M2, RISCV_V6M2_V8M2_V10M2,
|
|
};
|
|
|
|
// VRN3M2NoV0 Bit set.
|
|
static const uint8_t VRN3M2NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// VRN3M2_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN3M2_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0M2_V2M2_V4M2,
|
|
};
|
|
|
|
// VRN3M2_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN3M2_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
};
|
|
|
|
// VRN6M1_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN6M1_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0_V1_V2_V3_V4_V5,
|
|
};
|
|
|
|
// VRN6M1_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN6M1_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
|
|
};
|
|
|
|
// VRN7M1 Register Class...
|
|
static const MCPhysReg VRN7M1[] = {
|
|
RISCV_V8_V9_V10_V11_V12_V13_V14, RISCV_V9_V10_V11_V12_V13_V14_V15, RISCV_V10_V11_V12_V13_V14_V15_V16, RISCV_V11_V12_V13_V14_V15_V16_V17, RISCV_V12_V13_V14_V15_V16_V17_V18, RISCV_V13_V14_V15_V16_V17_V18_V19, RISCV_V14_V15_V16_V17_V18_V19_V20, RISCV_V15_V16_V17_V18_V19_V20_V21, RISCV_V16_V17_V18_V19_V20_V21_V22, RISCV_V17_V18_V19_V20_V21_V22_V23, RISCV_V18_V19_V20_V21_V22_V23_V24, RISCV_V19_V20_V21_V22_V23_V24_V25, RISCV_V20_V21_V22_V23_V24_V25_V26, RISCV_V21_V22_V23_V24_V25_V26_V27, RISCV_V22_V23_V24_V25_V26_V27_V28, RISCV_V23_V24_V25_V26_V27_V28_V29, RISCV_V24_V25_V26_V27_V28_V29_V30, RISCV_V25_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6_V7, RISCV_V2_V3_V4_V5_V6_V7_V8, RISCV_V3_V4_V5_V6_V7_V8_V9, RISCV_V4_V5_V6_V7_V8_V9_V10, RISCV_V5_V6_V7_V8_V9_V10_V11, RISCV_V6_V7_V8_V9_V10_V11_V12, RISCV_V7_V8_V9_V10_V11_V12_V13, RISCV_V0_V1_V2_V3_V4_V5_V6,
|
|
};
|
|
|
|
// VRN7M1 Bit set.
|
|
static const uint8_t VRN7M1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// VRN7M1NoV0 Register Class...
|
|
static const MCPhysReg VRN7M1NoV0[] = {
|
|
RISCV_V8_V9_V10_V11_V12_V13_V14, RISCV_V9_V10_V11_V12_V13_V14_V15, RISCV_V10_V11_V12_V13_V14_V15_V16, RISCV_V11_V12_V13_V14_V15_V16_V17, RISCV_V12_V13_V14_V15_V16_V17_V18, RISCV_V13_V14_V15_V16_V17_V18_V19, RISCV_V14_V15_V16_V17_V18_V19_V20, RISCV_V15_V16_V17_V18_V19_V20_V21, RISCV_V16_V17_V18_V19_V20_V21_V22, RISCV_V17_V18_V19_V20_V21_V22_V23, RISCV_V18_V19_V20_V21_V22_V23_V24, RISCV_V19_V20_V21_V22_V23_V24_V25, RISCV_V20_V21_V22_V23_V24_V25_V26, RISCV_V21_V22_V23_V24_V25_V26_V27, RISCV_V22_V23_V24_V25_V26_V27_V28, RISCV_V23_V24_V25_V26_V27_V28_V29, RISCV_V24_V25_V26_V27_V28_V29_V30, RISCV_V25_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6_V7, RISCV_V2_V3_V4_V5_V6_V7_V8, RISCV_V3_V4_V5_V6_V7_V8_V9, RISCV_V4_V5_V6_V7_V8_V9_V10, RISCV_V5_V6_V7_V8_V9_V10_V11, RISCV_V6_V7_V8_V9_V10_V11_V12, RISCV_V7_V8_V9_V10_V11_V12_V13,
|
|
};
|
|
|
|
// VRN7M1NoV0 Bit set.
|
|
static const uint8_t VRN7M1NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x01,
|
|
};
|
|
|
|
// VRN7M1_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN7M1_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0_V1_V2_V3_V4_V5_V6,
|
|
};
|
|
|
|
// VRN7M1_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN7M1_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
|
|
};
|
|
|
|
// VRN8M1 Register Class...
|
|
static const MCPhysReg VRN8M1[] = {
|
|
RISCV_V8_V9_V10_V11_V12_V13_V14_V15, RISCV_V9_V10_V11_V12_V13_V14_V15_V16, RISCV_V10_V11_V12_V13_V14_V15_V16_V17, RISCV_V11_V12_V13_V14_V15_V16_V17_V18, RISCV_V12_V13_V14_V15_V16_V17_V18_V19, RISCV_V13_V14_V15_V16_V17_V18_V19_V20, RISCV_V14_V15_V16_V17_V18_V19_V20_V21, RISCV_V15_V16_V17_V18_V19_V20_V21_V22, RISCV_V16_V17_V18_V19_V20_V21_V22_V23, RISCV_V17_V18_V19_V20_V21_V22_V23_V24, RISCV_V18_V19_V20_V21_V22_V23_V24_V25, RISCV_V19_V20_V21_V22_V23_V24_V25_V26, RISCV_V20_V21_V22_V23_V24_V25_V26_V27, RISCV_V21_V22_V23_V24_V25_V26_V27_V28, RISCV_V22_V23_V24_V25_V26_V27_V28_V29, RISCV_V23_V24_V25_V26_V27_V28_V29_V30, RISCV_V24_V25_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6_V7_V8, RISCV_V2_V3_V4_V5_V6_V7_V8_V9, RISCV_V3_V4_V5_V6_V7_V8_V9_V10, RISCV_V4_V5_V6_V7_V8_V9_V10_V11, RISCV_V5_V6_V7_V8_V9_V10_V11_V12, RISCV_V6_V7_V8_V9_V10_V11_V12_V13, RISCV_V7_V8_V9_V10_V11_V12_V13_V14, RISCV_V0_V1_V2_V3_V4_V5_V6_V7,
|
|
};
|
|
|
|
// VRN8M1 Bit set.
|
|
static const uint8_t VRN8M1Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x07,
|
|
};
|
|
|
|
// VRN8M1NoV0 Register Class...
|
|
static const MCPhysReg VRN8M1NoV0[] = {
|
|
RISCV_V8_V9_V10_V11_V12_V13_V14_V15, RISCV_V9_V10_V11_V12_V13_V14_V15_V16, RISCV_V10_V11_V12_V13_V14_V15_V16_V17, RISCV_V11_V12_V13_V14_V15_V16_V17_V18, RISCV_V12_V13_V14_V15_V16_V17_V18_V19, RISCV_V13_V14_V15_V16_V17_V18_V19_V20, RISCV_V14_V15_V16_V17_V18_V19_V20_V21, RISCV_V15_V16_V17_V18_V19_V20_V21_V22, RISCV_V16_V17_V18_V19_V20_V21_V22_V23, RISCV_V17_V18_V19_V20_V21_V22_V23_V24, RISCV_V18_V19_V20_V21_V22_V23_V24_V25, RISCV_V19_V20_V21_V22_V23_V24_V25_V26, RISCV_V20_V21_V22_V23_V24_V25_V26_V27, RISCV_V21_V22_V23_V24_V25_V26_V27_V28, RISCV_V22_V23_V24_V25_V26_V27_V28_V29, RISCV_V23_V24_V25_V26_V27_V28_V29_V30, RISCV_V24_V25_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6_V7_V8, RISCV_V2_V3_V4_V5_V6_V7_V8_V9, RISCV_V3_V4_V5_V6_V7_V8_V9_V10, RISCV_V4_V5_V6_V7_V8_V9_V10_V11, RISCV_V5_V6_V7_V8_V9_V10_V11_V12, RISCV_V6_V7_V8_V9_V10_V11_V12_V13, RISCV_V7_V8_V9_V10_V11_V12_V13_V14,
|
|
};
|
|
|
|
// VRN8M1NoV0 Bit set.
|
|
static const uint8_t VRN8M1NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// VRN4M2 Register Class...
|
|
static const MCPhysReg VRN4M2[] = {
|
|
RISCV_V8M2_V10M2_V12M2_V14M2, RISCV_V10M2_V12M2_V14M2_V16M2, RISCV_V12M2_V14M2_V16M2_V18M2, RISCV_V14M2_V16M2_V18M2_V20M2, RISCV_V16M2_V18M2_V20M2_V22M2, RISCV_V18M2_V20M2_V22M2_V24M2, RISCV_V20M2_V22M2_V24M2_V26M2, RISCV_V22M2_V24M2_V26M2_V28M2, RISCV_V24M2_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2_V8M2, RISCV_V4M2_V6M2_V8M2_V10M2, RISCV_V6M2_V8M2_V10M2_V12M2, RISCV_V0M2_V2M2_V4M2_V6M2,
|
|
};
|
|
|
|
// VRN4M2 Bit set.
|
|
static const uint8_t VRN4M2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
|
|
};
|
|
|
|
// VRN4M2NoV0 Register Class...
|
|
static const MCPhysReg VRN4M2NoV0[] = {
|
|
RISCV_V8M2_V10M2_V12M2_V14M2, RISCV_V10M2_V12M2_V14M2_V16M2, RISCV_V12M2_V14M2_V16M2_V18M2, RISCV_V14M2_V16M2_V18M2_V20M2, RISCV_V16M2_V18M2_V20M2_V22M2, RISCV_V18M2_V20M2_V22M2_V24M2, RISCV_V20M2_V22M2_V24M2_V26M2, RISCV_V22M2_V24M2_V26M2_V28M2, RISCV_V24M2_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2_V8M2, RISCV_V4M2_V6M2_V8M2_V10M2, RISCV_V6M2_V8M2_V10M2_V12M2,
|
|
};
|
|
|
|
// VRN4M2NoV0 Bit set.
|
|
static const uint8_t VRN4M2NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff,
|
|
};
|
|
|
|
// VRN2M4 Register Class...
|
|
static const MCPhysReg VRN2M4[] = {
|
|
RISCV_V8M4_V12M4, RISCV_V12M4_V16M4, RISCV_V16M4_V20M4, RISCV_V20M4_V24M4, RISCV_V24M4_V28M4, RISCV_V4M4_V8M4, RISCV_V0M4_V4M4,
|
|
};
|
|
|
|
// VRN2M4 Bit set.
|
|
static const uint8_t VRN2M4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
|
|
};
|
|
|
|
// VRN2M4NoV0 Register Class...
|
|
static const MCPhysReg VRN2M4NoV0[] = {
|
|
RISCV_V8M4_V12M4, RISCV_V12M4_V16M4, RISCV_V16M4_V20M4, RISCV_V20M4_V24M4, RISCV_V24M4_V28M4, RISCV_V4M4_V8M4,
|
|
};
|
|
|
|
// VRN2M4NoV0 Bit set.
|
|
static const uint8_t VRN2M4NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
|
|
};
|
|
|
|
// VRM8 Register Class...
|
|
static const MCPhysReg VRM8[] = {
|
|
RISCV_V8M8, RISCV_V16M8, RISCV_V24M8, RISCV_V0M8,
|
|
};
|
|
|
|
// VRM8 Bit set.
|
|
static const uint8_t VRM8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10, 0x08, 0x04,
|
|
};
|
|
|
|
// VRM8NoV0 Register Class...
|
|
static const MCPhysReg VRM8NoV0[] = {
|
|
RISCV_V8M8, RISCV_V16M8, RISCV_V24M8,
|
|
};
|
|
|
|
// VRM8NoV0 Bit set.
|
|
static const uint8_t VRM8NoV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x08, 0x04,
|
|
};
|
|
|
|
// VRM8_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRM8_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0M8,
|
|
};
|
|
|
|
// VRM8_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRM8_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
|
};
|
|
|
|
// VRN2M4_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN2M4_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0M4_V4M4,
|
|
};
|
|
|
|
// VRN2M4_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN2M4_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
|
};
|
|
|
|
// VRN4M2_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN4M2_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0M2_V2M2_V4M2_V6M2,
|
|
};
|
|
|
|
// VRN4M2_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN4M2_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
|
};
|
|
|
|
// VRN8M1_with_sub_vrm1_0_in_VMV0 Register Class...
|
|
static const MCPhysReg VRN8M1_with_sub_vrm1_0_in_VMV0[] = {
|
|
RISCV_V0_V1_V2_V3_V4_V5_V6_V7,
|
|
};
|
|
|
|
// VRN8M1_with_sub_vrm1_0_in_VMV0 Bit set.
|
|
static const uint8_t VRN8M1_with_sub_vrm1_0_in_VMV0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
|
};
|
|
|
|
static const MCRegisterClass RISCVMCRegisterClasses[] = {
|
|
{ FPR16, FPR16Bits, sizeof(FPR16Bits) },
|
|
{ GPRAll, GPRAllBits, sizeof(GPRAllBits) },
|
|
{ FPR32, FPR32Bits, sizeof(FPR32Bits) },
|
|
{ GPR, GPRBits, sizeof(GPRBits) },
|
|
{ GPRF16, GPRF16Bits, sizeof(GPRF16Bits) },
|
|
{ GPRF32, GPRF32Bits, sizeof(GPRF32Bits) },
|
|
{ GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits) },
|
|
{ GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits) },
|
|
{ GPRJALR, GPRJALRBits, sizeof(GPRJALRBits) },
|
|
{ GPRTC, GPRTCBits, sizeof(GPRTCBits) },
|
|
{ FPR32C, FPR32CBits, sizeof(FPR32CBits) },
|
|
{ GPRC, GPRCBits, sizeof(GPRCBits) },
|
|
{ SR07, SR07Bits, sizeof(SR07Bits) },
|
|
{ GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits) },
|
|
{ VCSR, VCSRBits, sizeof(VCSRBits) },
|
|
{ GPRC_and_SR07, GPRC_and_SR07Bits, sizeof(GPRC_and_SR07Bits) },
|
|
{ GPRX1X5, GPRX1X5Bits, sizeof(GPRX1X5Bits) },
|
|
{ GPRX0, GPRX0Bits, sizeof(GPRX0Bits) },
|
|
{ GPRX1, GPRX1Bits, sizeof(GPRX1Bits) },
|
|
{ GPRX5, GPRX5Bits, sizeof(GPRX5Bits) },
|
|
{ SP, SPBits, sizeof(SPBits) },
|
|
{ FPR64, FPR64Bits, sizeof(FPR64Bits) },
|
|
{ VM, VMBits, sizeof(VMBits) },
|
|
{ VR, VRBits, sizeof(VRBits) },
|
|
{ VRNoV0, VRNoV0Bits, sizeof(VRNoV0Bits) },
|
|
{ GPRPair, GPRPairBits, sizeof(GPRPairBits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRNoX0, GPRPair_with_sub_gpr_even_in_GPRNoX0Bits, sizeof(GPRPair_with_sub_gpr_even_in_GPRNoX0Bits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRNoX0X2, GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits, sizeof(GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRJALR, GPRPair_with_sub_gpr_even_in_GPRJALRBits, sizeof(GPRPair_with_sub_gpr_even_in_GPRJALRBits) },
|
|
{ FPR64C, FPR64CBits, sizeof(FPR64CBits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRTC, GPRPair_with_sub_gpr_even_in_GPRTCBits, sizeof(GPRPair_with_sub_gpr_even_in_GPRTCBits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRC, GPRPair_with_sub_gpr_even_in_GPRCBits, sizeof(GPRPair_with_sub_gpr_even_in_GPRCBits) },
|
|
{ GPRPair_with_sub_gpr_even_in_SR07, GPRPair_with_sub_gpr_even_in_SR07Bits, sizeof(GPRPair_with_sub_gpr_even_in_SR07Bits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC, GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits, sizeof(GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRC_and_SR07, GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits, sizeof(GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits) },
|
|
{ GPRPair_with_sub_gpr_even_in_GPRX0, GPRPair_with_sub_gpr_even_in_GPRX0Bits, sizeof(GPRPair_with_sub_gpr_even_in_GPRX0Bits) },
|
|
{ GPRPair_with_sub_gpr_even_in_SP, GPRPair_with_sub_gpr_even_in_SPBits, sizeof(GPRPair_with_sub_gpr_even_in_SPBits) },
|
|
{ GPRPair_with_sub_gpr_odd_in_GPRX1X5, GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits, sizeof(GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits) },
|
|
{ VMV0, VMV0Bits, sizeof(VMV0Bits) },
|
|
{ VRN2M1, VRN2M1Bits, sizeof(VRN2M1Bits) },
|
|
{ VRN2M1NoV0, VRN2M1NoV0Bits, sizeof(VRN2M1NoV0Bits) },
|
|
{ VRM2, VRM2Bits, sizeof(VRM2Bits) },
|
|
{ VRM2NoV0, VRM2NoV0Bits, sizeof(VRM2NoV0Bits) },
|
|
{ VRM2_with_sub_vrm1_0_in_VMV0, VRM2_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRM2_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN2M1_with_sub_vrm1_0_in_VMV0, VRN2M1_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN2M1_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN3M1, VRN3M1Bits, sizeof(VRN3M1Bits) },
|
|
{ VRN3M1NoV0, VRN3M1NoV0Bits, sizeof(VRN3M1NoV0Bits) },
|
|
{ VRN3M1_with_sub_vrm1_0_in_VMV0, VRN3M1_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN3M1_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN4M1, VRN4M1Bits, sizeof(VRN4M1Bits) },
|
|
{ VRN4M1NoV0, VRN4M1NoV0Bits, sizeof(VRN4M1NoV0Bits) },
|
|
{ VRN2M2, VRN2M2Bits, sizeof(VRN2M2Bits) },
|
|
{ VRN2M2NoV0, VRN2M2NoV0Bits, sizeof(VRN2M2NoV0Bits) },
|
|
{ VRM4, VRM4Bits, sizeof(VRM4Bits) },
|
|
{ VRM4NoV0, VRM4NoV0Bits, sizeof(VRM4NoV0Bits) },
|
|
{ VRM4_with_sub_vrm1_0_in_VMV0, VRM4_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRM4_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN2M2_with_sub_vrm1_0_in_VMV0, VRN2M2_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN2M2_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN4M1_with_sub_vrm1_0_in_VMV0, VRN4M1_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN4M1_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN5M1, VRN5M1Bits, sizeof(VRN5M1Bits) },
|
|
{ VRN5M1NoV0, VRN5M1NoV0Bits, sizeof(VRN5M1NoV0Bits) },
|
|
{ VRN5M1_with_sub_vrm1_0_in_VMV0, VRN5M1_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN5M1_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN6M1, VRN6M1Bits, sizeof(VRN6M1Bits) },
|
|
{ VRN6M1NoV0, VRN6M1NoV0Bits, sizeof(VRN6M1NoV0Bits) },
|
|
{ VRN3M2, VRN3M2Bits, sizeof(VRN3M2Bits) },
|
|
{ VRN3M2NoV0, VRN3M2NoV0Bits, sizeof(VRN3M2NoV0Bits) },
|
|
{ VRN3M2_with_sub_vrm1_0_in_VMV0, VRN3M2_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN3M2_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN6M1_with_sub_vrm1_0_in_VMV0, VRN6M1_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN6M1_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN7M1, VRN7M1Bits, sizeof(VRN7M1Bits) },
|
|
{ VRN7M1NoV0, VRN7M1NoV0Bits, sizeof(VRN7M1NoV0Bits) },
|
|
{ VRN7M1_with_sub_vrm1_0_in_VMV0, VRN7M1_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN7M1_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN8M1, VRN8M1Bits, sizeof(VRN8M1Bits) },
|
|
{ VRN8M1NoV0, VRN8M1NoV0Bits, sizeof(VRN8M1NoV0Bits) },
|
|
{ VRN4M2, VRN4M2Bits, sizeof(VRN4M2Bits) },
|
|
{ VRN4M2NoV0, VRN4M2NoV0Bits, sizeof(VRN4M2NoV0Bits) },
|
|
{ VRN2M4, VRN2M4Bits, sizeof(VRN2M4Bits) },
|
|
{ VRN2M4NoV0, VRN2M4NoV0Bits, sizeof(VRN2M4NoV0Bits) },
|
|
{ VRM8, VRM8Bits, sizeof(VRM8Bits) },
|
|
{ VRM8NoV0, VRM8NoV0Bits, sizeof(VRM8NoV0Bits) },
|
|
{ VRM8_with_sub_vrm1_0_in_VMV0, VRM8_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRM8_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN2M4_with_sub_vrm1_0_in_VMV0, VRN2M4_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN2M4_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN4M2_with_sub_vrm1_0_in_VMV0, VRN4M2_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN4M2_with_sub_vrm1_0_in_VMV0Bits) },
|
|
{ VRN8M1_with_sub_vrm1_0_in_VMV0, VRN8M1_with_sub_vrm1_0_in_VMV0Bits, sizeof(VRN8M1_with_sub_vrm1_0_in_VMV0Bits) },
|
|
};
|
|
|
|
static const uint16_t RISCVRegEncodingTable[] = {
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
2,
|
|
4,
|
|
4,
|
|
6,
|
|
8,
|
|
8,
|
|
8,
|
|
10,
|
|
12,
|
|
12,
|
|
14,
|
|
16,
|
|
16,
|
|
16,
|
|
18,
|
|
20,
|
|
20,
|
|
22,
|
|
24,
|
|
24,
|
|
24,
|
|
26,
|
|
28,
|
|
28,
|
|
30,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
14,
|
|
16,
|
|
18,
|
|
20,
|
|
22,
|
|
24,
|
|
26,
|
|
28,
|
|
30,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
0,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
14,
|
|
16,
|
|
18,
|
|
20,
|
|
22,
|
|
24,
|
|
26,
|
|
28,
|
|
0,
|
|
4,
|
|
8,
|
|
12,
|
|
16,
|
|
20,
|
|
24,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
0,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
14,
|
|
16,
|
|
18,
|
|
20,
|
|
22,
|
|
24,
|
|
26,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
0,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
14,
|
|
16,
|
|
18,
|
|
20,
|
|
22,
|
|
24,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
0,
|
|
};
|
|
#endif // GET_REGINFO_MC_DESC
|
|
|
|
|
|
|