From 360d7a7ccd1bf5a619c194ec2e7931b6afa56be5 Mon Sep 17 00:00:00 2001 From: SimoneN64 Date: Mon, 25 Dec 2023 21:59:47 +0100 Subject: [PATCH] first optimization --- src/backend/core/JIT.cpp | 1 + src/backend/core/JIT/IR.cpp | 43 +++++++++++++++++++++++++++++++++---- src/backend/core/JIT/IR.hpp | 12 ++++++++++- 3 files changed, 51 insertions(+), 5 deletions(-) diff --git a/src/backend/core/JIT.cpp b/src/backend/core/JIT.cpp index 767755b1..9fe222db 100644 --- a/src/backend/core/JIT.cpp +++ b/src/backend/core/JIT.cpp @@ -81,6 +81,7 @@ _epilogue: //ready(); //return getCode(); ir.optimize(); + ir.print(); exit(1); return nullptr; } diff --git a/src/backend/core/JIT/IR.cpp b/src/backend/core/JIT/IR.cpp index 3cf75e60..f383f696 100644 --- a/src/backend/core/JIT/IR.cpp +++ b/src/backend/core/JIT/IR.cpp @@ -151,18 +151,20 @@ template <> struct fmt::formatter : formatter { std::string op1 = fmt::format("R{}", e.op1.index_or_imm.value()); if(put_comma) { op += ", "; + } else { + put_comma = true; } op += op1; - put_comma = true; } } else { if (e.op1.index_or_imm.has_value()) { std::string op1 = fmt::format("0x{:0X}", e.op1.index_or_imm.value()); if(put_comma) { op += ", "; + } else { + put_comma = true; } op += op1; - put_comma = true; } } @@ -171,18 +173,20 @@ template <> struct fmt::formatter : formatter { std::string op2 = fmt::format("R{}", e.op2.index_or_imm.value()); if(put_comma) { op += ", "; + } else { + put_comma = true; } op += op2; - put_comma = true; } } else { if (e.op2.index_or_imm.has_value()) { std::string op2 = fmt::format("0x{:0X}", e.op2.index_or_imm.value()); if(put_comma) { op += ", "; + } else { + put_comma = true; } op += op2; - put_comma = true; } } @@ -211,6 +215,37 @@ void IR::push(const Entry& e) { } void IR::optimize() { + std::vector optimized{}; + + for(const auto& i : code) { + bool isOp1Reg = i.op1.isReg(); + bool isOp2Reg = i.op2.isReg(); + bool isDstReg = i.dst.isReg(); + + if(isDstReg) { + if(isOp1Reg) { + if(i.op1.index_or_imm == i.dst.index_or_imm + && i.zeroRendersItUseless()) continue; + } + + if(isOp2Reg) { + if(i.op2.index_or_imm == i.dst.index_or_imm + && i.zeroRendersItUseless()) continue; + } + } + + optimized.push_back(i); + } + + if(optimized.size() == code.size()) { + return; + } + + code = optimized; + optimize(); +} + +void IR::print() { for(auto e : code) { fmt::print("{}", e); } diff --git a/src/backend/core/JIT/IR.hpp b/src/backend/core/JIT/IR.hpp index b75f7eb8..77b4ff0f 100644 --- a/src/backend/core/JIT/IR.hpp +++ b/src/backend/core/JIT/IR.hpp @@ -38,11 +38,16 @@ struct Entry { LO, HI } type = NONE; - bool isReg() { + bool isReg() const { return type == REG_S64 || type == REG_F32 || type == REG_F64 || type == REG_S32 || type == REG_U64 || type == REG_U32 || type == REG_U5; } + bool isImm() const { + return type == IMM_S64 || type == IMM_F32 || type == IMM_F64 || type == IMM_S32 + || type == IMM_U64 || type == IMM_U32 || type == IMM_U5; + } + std::optional index_or_imm = std::nullopt; Operand() = default; @@ -50,6 +55,10 @@ struct Entry { : type(t), index_or_imm(imm) {} } dst, op1, op2; + bool zeroRendersItUseless() const { + return op == ADD || op == OR || op == SRL || op == SLL || op == SRA; + } + [[nodiscard]] const Operand& GetDst() const { return dst; } enum BranchCond { @@ -71,6 +80,7 @@ struct IR { void push(const Entry&); auto begin(); auto end(); + void print(); void optimize(); private: std::vector code{};