diff --git a/src/backend/core/registers/Cop0.cpp b/src/backend/core/registers/Cop0.cpp
index b79a6555..0831fa70 100644
--- a/src/backend/core/registers/Cop0.cpp
+++ b/src/backend/core/registers/Cop0.cpp
@@ -360,26 +360,13 @@ bool Cop0::ProbeTLB(const TLBAccessType accessType, const u64 vaddr, u32 &paddr)
   return true;
 }
 
-FORCE_INLINE bool Is64BitAddressing(const Cop0 &cp0, const u64 addr) {
-  switch (addr >> 62 & 3) {
-  case 0b00:
-    return cp0.status.ux;
-  case 0b01:
-    return cp0.status.sx;
-  case 0b11:
-    return cp0.status.kx;
-  default:
-    return false;
-  }
-}
-
 void Cop0::FireException(const ExceptionCode code, const int cop, s64 pc) {
   Registers& regs = Core::GetRegs();
 
   u16 vectorOffset = 0x0180;
   if(tlbError == MISS && (code == ExceptionCode::TLBLoad || code == ExceptionCode::TLBStore)) {
     if(!status.exl) {
-      if(Is64BitAddressing(*this, badVaddr)) vectorOffset = 0x0080;
+      if(is64BitAddressing) vectorOffset = 0x0080;
       else vectorOffset = 0x0000;
     }
   }