From 920b77d3819e3fb7999f0acd4f896ff21a07bff2 Mon Sep 17 00:00:00 2001 From: iris Date: Thu, 28 May 2026 17:57:46 +0200 Subject: [PATCH] wjkhasdfjhkasdf --- src/backend/core/Cache.cpp | 4 ++-- src/backend/core/Interpreter.hpp | 1 - src/backend/core/JITUtils.hpp | 2 ++ src/backend/core/RSP.hpp | 3 +++ .../core/interpreter/cop1instructions.cpp | 4 ++-- src/backend/core/interpreter/instructions.cpp | 20 +++++++++---------- 6 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/backend/core/Cache.cpp b/src/backend/core/Cache.cpp index 1f4367d..6614d09 100644 --- a/src/backend/core/Cache.cpp +++ b/src/backend/core/Cache.cpp @@ -52,7 +52,7 @@ void DataCache::WriteBack(u64 vaddr, u32 paddr) { u32 origPhysAddr = (line.ptag << 12) | (paddr & 0xfff); u32 lineStart = GetDCacheLineStart(origPhysAddr); - Core::GetInstance().interpreter.EvictCachedBlock(vaddr); + Core::GetInstance().interpreter.cachedState.EvictCachedBlock(vaddr); for (int i = 0; i < 16; i++) { mmio.rdp.WriteRDRAM(lineStart + i, line.data[i]); } @@ -87,7 +87,7 @@ void InstructionCache::WriteBack(u64 vaddr, u32 paddr, u32 ptag) { if (line.ptag == ptag && line.valid) { u32 origPhysAddr = (line.ptag << 12) | (paddr & 0xfff); u32 lineStart = GetICacheLineStart(origPhysAddr); - Core::GetInstance().interpreter.EvictCachedBlock(vaddr); + Core::GetInstance().interpreter.cachedState.EvictCachedBlock(vaddr); for (int i = 0; i < 16; i++) { mmio.rdp.WriteRDRAM(lineStart + i, line.data[i]); } diff --git a/src/backend/core/Interpreter.hpp b/src/backend/core/Interpreter.hpp index 0f02d15..a54bf0d 100644 --- a/src/backend/core/Interpreter.hpp +++ b/src/backend/core/Interpreter.hpp @@ -51,7 +51,6 @@ struct Interpreter final { u32 CacheBlock(u32 addr); void SignalException(u32 addr) { cachedState.exception = true; } - void EvictCachedBlock(u32 addr) { cachedState.blocks[CACHE_GET_BLOCK(addr)] = {}; } void Reset() { cop2Latch = {}; diff --git a/src/backend/core/JITUtils.hpp b/src/backend/core/JITUtils.hpp index fa51651..e6df973 100644 --- a/src/backend/core/JITUtils.hpp +++ b/src/backend/core/JITUtils.hpp @@ -27,6 +27,8 @@ struct CachedState { std::vector *> blocks = {}; bool exception = false; + void EvictCachedBlock(u64 addr) { blocks[addr / MAX_LINES] = {}; } + void Reset() { for (auto block : blocks) { if (block) diff --git a/src/backend/core/RSP.hpp b/src/backend/core/RSP.hpp index 1d5eec5..165f759 100644 --- a/src/backend/core/RSP.hpp +++ b/src/backend/core/RSP.hpp @@ -232,6 +232,7 @@ struct RSP { FORCE_INLINE void WriteWord(u32 addr, const u32 val) { addr &= 0xfff; + cachedState.EvictCachedBlock(addr); SET_RSP_WORD(addr, val); } @@ -242,6 +243,7 @@ struct RSP { FORCE_INLINE void WriteHalf(u32 addr, const u16 val) { addr &= 0xfff; + cachedState.EvictCachedBlock(addr); SET_RSP_HALF(addr, val); } @@ -252,6 +254,7 @@ struct RSP { FORCE_INLINE void WriteByte(u32 addr, const u8 val) { addr &= 0xfff; + cachedState.EvictCachedBlock(addr); RSP_BYTE(addr) = val; } diff --git a/src/backend/core/interpreter/cop1instructions.cpp b/src/backend/core/interpreter/cop1instructions.cpp index e4dc15d..5e7aac9 100644 --- a/src/backend/core/interpreter/cop1instructions.cpp +++ b/src/backend/core/interpreter/cop1instructions.cpp @@ -1310,7 +1310,7 @@ void Cop1::swc1(const Instruction instr) { regs.cop0.HandleTLBException(addr); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - Core::GetInstance().interpreter.EvictCachedBlock(addr); + Core::GetInstance().interpreter.cachedState.EvictCachedBlock(addr); mem.Write(physical, FGR_T(regs.cop0.status, instr.ft())); } } @@ -1338,7 +1338,7 @@ void Cop1::sdc1(const Instruction instr) { regs.cop0.HandleTLBException(addr); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - Core::GetInstance().interpreter.EvictCachedBlock(addr); + Core::GetInstance().interpreter.cachedState.EvictCachedBlock(addr); mem.Write(physical, FGR_T(regs.cop0.status, instr.ft())); } } diff --git a/src/backend/core/interpreter/instructions.cpp b/src/backend/core/interpreter/instructions.cpp index c7b0543..62871d9 100644 --- a/src/backend/core/interpreter/instructions.cpp +++ b/src/backend/core/interpreter/instructions.cpp @@ -407,7 +407,7 @@ void Interpreter::sb(const Instruction instr) { regs.cop0.HandleTLBException(address); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(paddr, regs.Read(instr.rt())); } } @@ -431,7 +431,7 @@ void Interpreter::sc(const Instruction instr) { regs.cop0.HandleTLBException(address); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(paddr, regs.Read(instr.rt())); regs.Write(instr.rt(), 1); } @@ -464,7 +464,7 @@ void Interpreter::scd(const Instruction instr) { regs.cop0.HandleTLBException(address); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(paddr, regs.Read(instr.rt())); regs.Write(instr.rt(), 1); } @@ -481,7 +481,7 @@ void Interpreter::sh(const Instruction instr) { regs.cop0.HandleTLBException(address); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(physical, regs.Read(instr.rt())); } } @@ -500,7 +500,7 @@ void Interpreter::sw(const Instruction instr) { regs.cop0.HandleTLBException(address); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(physical, regs.Read(instr.rt())); } } @@ -518,7 +518,7 @@ void Interpreter::sd(const Instruction instr) { regs.cop0.HandleTLBException(address); regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC); } else { - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(physical, regs.Read(instr.rt())); } } @@ -534,7 +534,7 @@ void Interpreter::sdl(const Instruction instr) { const u64 mask = 0xFFFFFFFFFFFFFFFF >> shift; const u64 data = mem.Read(paddr & ~7); const u64 rt = regs.Read(instr.rt()); - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(paddr & ~7, (data & ~mask) | (rt >> shift)); } } @@ -550,7 +550,7 @@ void Interpreter::sdr(const Instruction instr) { const u64 mask = 0xFFFFFFFFFFFFFFFF << shift; const u64 data = mem.Read(paddr & ~7); const u64 rt = regs.Read(instr.rt()); - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(paddr & ~7, (data & ~mask) | (rt << shift)); } } @@ -566,7 +566,7 @@ void Interpreter::swl(const Instruction instr) { const u32 mask = 0xFFFFFFFF >> shift; const u32 data = mem.Read(paddr & ~3); const u32 rt = regs.Read(instr.rt()); - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(paddr & ~3, (data & ~mask) | (rt >> shift)); } } @@ -582,7 +582,7 @@ void Interpreter::swr(const Instruction instr) { const u32 mask = 0xFFFFFFFF << shift; const u32 data = mem.Read(paddr & ~3); const u32 rt = regs.Read(instr.rt()); - EvictCachedBlock(address); + cachedState.EvictCachedBlock(address); mem.Write(paddr & ~3, (data & ~mask) | (rt << shift)); } }