diff --git a/src/backend/core/Mem.cpp b/src/backend/core/Mem.cpp
index bd53f81..0d04f71 100644
--- a/src/backend/core/Mem.cpp
+++ b/src/backend/core/Mem.cpp
@@ -312,8 +312,12 @@ void Mem::Write<u8>(u32 paddr, u32 val) {
     }
     if (ircolib::IsInsideRange(paddr, DMEM_REGION_START, RSP_MEM_REGION_END)) {
         val = val << (8 * (3 - (paddr & 3)));
-        auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+        bool is_imem = paddr & 0x1000;
+        auto &dest = is_imem ? mmio.rsp.imem : mmio.rsp.dmem;
         paddr = (paddr & 0xFFF) & ~3;
+        if (is_imem) {
+            mmio.rsp.cachedState.EvictCachedBlock(paddr);
+        }
         ircolib::WriteAccess<u32>(dest, paddr, val);
         return;
     }
@@ -361,8 +365,12 @@ void Mem::Write<u16>(u32 paddr, u32 val) {
     }
     if (ircolib::IsInsideRange(paddr, DMEM_REGION_START, RSP_MEM_REGION_END)) {
         val = val << (16 * !(paddr & 2));
-        auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+        bool is_imem = paddr & 0x1000;
+        auto &dest = is_imem ? mmio.rsp.imem : mmio.rsp.dmem;
         paddr = (paddr & 0xFFF) & ~3;
+        if (is_imem) {
+            mmio.rsp.cachedState.EvictCachedBlock(paddr);
+        }
         ircolib::WriteAccess<u32>(dest, paddr, val);
         return;
     }
@@ -409,7 +417,11 @@ void Mem::Write<u32>(const u32 paddr, const u32 val) {
         return;
     }
     if (ircolib::IsInsideRange(paddr, DMEM_REGION_START, RSP_MEM_REGION_END)) {
-        auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+        bool is_imem = paddr & 0x1000;
+        auto &dest = is_imem ? mmio.rsp.imem : mmio.rsp.dmem;
+        if (is_imem) {
+            mmio.rsp.cachedState.EvictCachedBlock(paddr & 0xfff);
+        }
         ircolib::WriteAccess<u32>(dest, paddr & 0xfff, val);
         return;
     }
@@ -455,7 +467,11 @@ void Mem::Write(const u32 paddr, u64 val) {
         return;
     }
     if (ircolib::IsInsideRange(paddr, DMEM_REGION_START, RSP_MEM_REGION_END)) {
-        auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+        bool is_imem = paddr & 0x1000;
+        auto &dest = is_imem ? mmio.rsp.imem : mmio.rsp.dmem;
+        if (is_imem) {
+            mmio.rsp.cachedState.EvictCachedBlock(paddr & 0xfff);
+        }
         val >>= 32;
         ircolib::WriteAccess<u32>(dest, paddr & 0xfff, val);
         return;
diff --git a/src/backend/core/RSP.cpp b/src/backend/core/RSP.cpp
index fa94f69..77777da 100644
--- a/src/backend/core/RSP.cpp
+++ b/src/backend/core/RSP.cpp
@@ -177,6 +177,10 @@ void RSP::DMA<false>() {
     auto &dst = spDMASPAddr.bank ? imem : dmem;
 
     u32 mem_address = spDMASPAddr.address & 0xFF8;
+    if (spDMASPAddr.bank) {
+        cachedState.EvictCachedBlock(mem_address);
+    }
+
     u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
     trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);