diff --git a/src/backend/core/RSP.cpp b/src/backend/core/RSP.cpp
index dfe61e03..ac01f44b 100644
--- a/src/backend/core/RSP.cpp
+++ b/src/backend/core/RSP.cpp
@@ -67,7 +67,7 @@ FORCE_INLINE void logRSP(const RSP& rsp, const u32 instr) {
 }
 */
 
-auto RSP::Read(u32 addr) -> u32{
+auto RSP::Read(u32 addr) -> u32 {
   switch (addr) {
     case 0x04040000: return lastSuccessfulSPAddr.raw & 0x1FF8;
     case 0x04040004: return lastSuccessfulDRAMAddr.raw & 0xFFFFF8;
@@ -130,7 +130,7 @@ template <> void RSP::DMA<true>() {
     int skip = i == spDMALen.count ? 0 : spDMALen.skip;
 
     dram_address += (length + skip);
-    dram_address &= 0xFFFFFC;
+    dram_address &= 0xFFFFFE;
     mem_address += length;
     mem_address &= 0xFF8;
   }
@@ -150,7 +150,7 @@ template <> void RSP::DMA<false>() {
   std::array<u8, DMEM_SIZE>& dst = spDMASPAddr.bank ? imem : dmem;
 
   u32 mem_address = spDMASPAddr.address & 0xFF8;
-  u32 dram_address = spDMADRAMAddr.address & 0xFFFFFC;
+  u32 dram_address = spDMADRAMAddr.address & 0xFFFFFE;
   Util::trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
 
   for (u32 i = 0; i < spDMALen.count + 1; i++) {
@@ -161,7 +161,7 @@ template <> void RSP::DMA<false>() {
     int skip = i == spDMALen.count ? 0 : spDMALen.skip;
 
     dram_address += (length + skip);
-    dram_address &= 0xFFFFFC;
+    dram_address &= 0xFFFFFE;
     mem_address += length;
     mem_address &= 0xFF8;
   }
@@ -176,7 +176,7 @@ template <> void RSP::DMA<false>() {
 void RSP::Write(u32 addr, u32 val) {
   switch (addr) {
     case 0x04040000: spDMASPAddr.raw = val & 0x1FF8; break;
-    case 0x04040004: spDMADRAMAddr.raw = val & 0xFFFFFC; break;
+    case 0x04040004: spDMADRAMAddr.raw = val & 0xFFFFFE; break;
     case 0x04040008: {
       spDMALen.raw = val;
       DMA<false>();
diff --git a/src/backend/core/mmio/PI.cpp b/src/backend/core/mmio/PI.cpp
index 37a50f6f..fb115c1d 100644
--- a/src/backend/core/mmio/PI.cpp
+++ b/src/backend/core/mmio/PI.cpp
@@ -468,7 +468,7 @@ template <> void PI::DMA<true>() {
 void PI::Write(u32 addr, u32 val) {
   MI& mi = mem.mmio.mi;
   switch(addr) {
-    case 0x04600000: dramAddr = val & 0x00FFFFFC; break;
+    case 0x04600000: dramAddr = val & 0x00FFFFFE; break;
     case 0x04600004: cartAddr = val & 0xFFFFFFFE; break;
     case 0x04600008: {
       rdLen = val & 0x00FFFFFF;