diff --git a/src/backend/core/CpuDefinitions.hpp b/src/backend/core/CpuDefinitions.hpp
new file mode 100644
index 00000000..0741168a
--- /dev/null
+++ b/src/backend/core/CpuDefinitions.hpp
@@ -0,0 +1,129 @@
+#pragma once
+#include <common.hpp>
+namespace n64 {
+constexpr u8 SPECIAL    = 0b000000;
+constexpr u8 REGIMM     = 0b000001;
+constexpr u8 J          = 0b000010;
+constexpr u8 JAL        = 0b000011;
+constexpr u8 BEQ        = 0b000100;
+constexpr u8 BNE        = 0b000101;
+constexpr u8 BLEZ       = 0b000110;
+constexpr u8 BGTZ       = 0b000111;
+constexpr u8 ADDI       = 0b001000;
+constexpr u8 ADDIU      = 0b001001;
+constexpr u8 SLTI       = 0b001010;
+constexpr u8 SLTIU      = 0b001011;
+constexpr u8 ANDI       = 0b001100;
+constexpr u8 ORI        = 0b001101;
+constexpr u8 XORI       = 0b001110;
+constexpr u8 LUI        = 0b001111;
+constexpr u8 COP0       = 0b010000;
+constexpr u8 COP1       = 0b010001;
+constexpr u8 COP2       = 0b010010;
+constexpr u8 BEQL       = 0b010100;
+constexpr u8 BNEL       = 0b010101;
+constexpr u8 BLEZL      = 0b010110;
+constexpr u8 BGTZL      = 0b010111;
+constexpr u8 DADDI      = 0b011000;
+constexpr u8 DADDIU     = 0b011001;
+constexpr u8 LDL        = 0b011010;
+constexpr u8 LDR        = 0b011011;
+constexpr u8 LB         = 0b100000;
+constexpr u8 LH         = 0b100001;
+constexpr u8 LWL        = 0b100010;
+constexpr u8 LW         = 0b100011;
+constexpr u8 LBU        = 0b100100;
+constexpr u8 LHU        = 0b100101;
+constexpr u8 LWR        = 0b100110;
+constexpr u8 LWU        = 0b100111;
+constexpr u8 SB         = 0b101000;
+constexpr u8 SH         = 0b101001;
+constexpr u8 SWL        = 0b101010;
+constexpr u8 SW         = 0b101011;
+constexpr u8 SDL        = 0b101100;
+constexpr u8 SDR        = 0b101101;
+constexpr u8 SWR        = 0b101110;
+constexpr u8 CACHE      = 0b101111;
+constexpr u8 LL         = 0b110000;
+constexpr u8 LWC1       = 0b110001;
+constexpr u8 LWC2       = 0b110010;
+constexpr u8 LLD        = 0b110100;
+constexpr u8 LDC1       = 0b110101;
+constexpr u8 LDC2       = 0b110110;
+constexpr u8 LD         = 0b110111;
+constexpr u8 SC         = 0b111000;
+constexpr u8 SWC1       = 0b111001;
+constexpr u8 SWC2       = 0b111010;
+constexpr u8 SCD        = 0b111100;
+constexpr u8 SDC1       = 0b111101;
+constexpr u8 SDC2       = 0b111110;
+constexpr u8 SD         = 0b111111;
+// special
+constexpr u8 SLL        = 0b000000;
+constexpr u8 SRL        = 0b000010;
+constexpr u8 SRA        = 0b000011;
+constexpr u8 SLLV       = 0b000100;
+constexpr u8 SRLV       = 0b000110;
+constexpr u8 SRAV       = 0b000111;
+constexpr u8 JR         = 0b001000;
+constexpr u8 JALR       = 0b001001;
+constexpr u8 SYSCALL    = 0b001100;
+constexpr u8 BREAK      = 0b001101;
+constexpr u8 SYNC       = 0b001111;
+constexpr u8 MFHI       = 0b010000;
+constexpr u8 MTHI       = 0b010001;
+constexpr u8 MFLO       = 0b010010;
+constexpr u8 MTLO       = 0b010011;
+constexpr u8 DSLLV      = 0b010100;
+constexpr u8 DSRLV      = 0b010110;
+constexpr u8 DSRAV      = 0b010111;
+constexpr u8 MULT       = 0b011000;
+constexpr u8 MULTU      = 0b011001;
+constexpr u8 DIV        = 0b011010;
+constexpr u8 DIVU       = 0b011011;
+constexpr u8 DMULT      = 0b011100;
+constexpr u8 DMULTU     = 0b011101;
+constexpr u8 DDIV       = 0b011110;
+constexpr u8 DDIVU      = 0b011111;
+constexpr u8 ADD        = 0b100000;
+constexpr u8 ADDU       = 0b100001;
+constexpr u8 SUB        = 0b100010;
+constexpr u8 SUBU       = 0b100011;
+constexpr u8 AND        = 0b100100;
+constexpr u8 OR         = 0b100101;
+constexpr u8 XOR        = 0b100110;
+constexpr u8 NOR        = 0b100111;
+constexpr u8 SLT        = 0b101010;
+constexpr u8 SLTU       = 0b101011;
+constexpr u8 DADD       = 0b101100;
+constexpr u8 DADDU      = 0b101101;
+constexpr u8 DSUB       = 0b101110;
+constexpr u8 DSUBU      = 0b101111;
+constexpr u8 TGE        = 0b110000;
+constexpr u8 TGEU       = 0b110001;
+constexpr u8 TLT        = 0b110010;
+constexpr u8 TLTU       = 0b110011;
+constexpr u8 TEQ        = 0b110100;
+constexpr u8 TNE        = 0b110110;
+constexpr u8 DSLL       = 0b111000;
+constexpr u8 DSRL       = 0b111010;
+constexpr u8 DSRA       = 0b111011;
+constexpr u8 DSLL32     = 0b111100;
+constexpr u8 DSRL32     = 0b111110;
+constexpr u8 DSRA32     = 0b111111;
+// regimm
+constexpr u8 BLTZ       = 0b00000;
+constexpr u8 BGEZ       = 0b00001;
+constexpr u8 BLTZL      = 0b00010;
+constexpr u8 BGEZL      = 0b00011;
+constexpr u8 TGEI       = 0b01000;
+constexpr u8 TGEIU      = 0b01001;
+constexpr u8 TLTI       = 0b01010;
+constexpr u8 TLTIU      = 0b01011;
+constexpr u8 TEQI       = 0b01100;
+constexpr u8 TNEI       = 0b01110;
+constexpr u8 BLTZAL     = 0b10000;
+constexpr u8 BGEZAL     = 0b10001;
+constexpr u8 BLTZALL    = 0b10010;
+constexpr u8 BGEZALL    = 0b10011;
+}
\ No newline at end of file
diff --git a/src/backend/core/interpreter/decode.cpp b/src/backend/core/interpreter/decode.cpp
index b0119ce5..6a9cbb76 100644
--- a/src/backend/core/interpreter/decode.cpp
+++ b/src/backend/core/interpreter/decode.cpp
@@ -1,67 +1,68 @@
 #include <core/Interpreter.hpp>
 #include <log.hpp>
+#include <CpuDefinitions.hpp>
 
 namespace n64 {
 void Interpreter::special(u32 instr) {
   u8 mask = (instr & 0x3F);
   // 00rr_rccc
   switch (mask) { // TODO: named constants for clearer code
-    case 0:
+    case SLL:
       if (instr != 0) {
         sll(instr);
       }
       break;
-    case 0x02: srl(instr); break;
-    case 0x03: sra(instr); break;
-    case 0x04: sllv(instr); break;
-    case 0x06: srlv(instr); break;
-    case 0x07: srav(instr); break;
-    case 0x08: jr(instr); break;
-    case 0x09: jalr(instr); break;
-    case 0x0C: FireException(regs, ExceptionCode::Syscall, 0, true); break;
-    case 0x0D: FireException(regs, ExceptionCode::Breakpoint, 0, true); break;
-    case 0x0F: break; // SYNC
-    case 0x10: mfhi(instr); break;
-    case 0x11: mthi(instr); break;
-    case 0x12: mflo(instr); break;
-    case 0x13: mtlo(instr); break;
-    case 0x14: dsllv(instr); break;
-    case 0x16: dsrlv(instr); break;
-    case 0x17: dsrav(instr); break;
-    case 0x18: mult(instr); break;
-    case 0x19: multu(instr); break;
-    case 0x1A: div(instr); break;
-    case 0x1B: divu(instr); break;
-    case 0x1C: dmult(instr); break;
-    case 0x1D: dmultu(instr); break;
-    case 0x1E: ddiv(instr); break;
-    case 0x1F: ddivu(instr); break;
-    case 0x20: add(instr); break;
-    case 0x21: addu(instr); break;
-    case 0x22: sub(instr); break;
-    case 0x23: subu(instr); break;
-    case 0x24: and_(instr); break;
-    case 0x25: or_(instr); break;
-    case 0x26: xor_(instr); break;
-    case 0x27: nor(instr); break;
-    case 0x2A: slt(instr); break;
-    case 0x2B: sltu(instr); break;
-    case 0x2C: dadd(instr); break;
-    case 0x2D: daddu(instr); break;
-    case 0x2E: dsub(instr); break;
-    case 0x2F: dsubu(instr); break;
-    case 0x30: trap(regs.gpr[RS(instr)] >= regs.gpr[RT(instr)]); break;
-    case 0x31: trap((u64)regs.gpr[RS(instr)] >= (u64)regs.gpr[RT(instr)]); break;
-    case 0x32: trap(regs.gpr[RS(instr)] < regs.gpr[RT(instr)]); break;
-    case 0x33: trap((u64)regs.gpr[RS(instr)] < (u64)regs.gpr[RT(instr)]); break;
-    case 0x34: trap(regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break;
-    case 0x36: trap(regs.gpr[RS(instr)] != regs.gpr[RT(instr)]); break;
-    case 0x38: dsll(instr); break;
-    case 0x3A: dsrl(instr); break;
-    case 0x3B: dsra(instr); break;
-    case 0x3C: dsll32(instr); break;
-    case 0x3E: dsrl32(instr); break;
-    case 0x3F: dsra32(instr); break;
+    case SRL: srl(instr); break;
+    case SRA: sra(instr); break;
+    case SLLV: sllv(instr); break;
+    case SRLV: srlv(instr); break;
+    case SRAV: srav(instr); break;
+    case JR: jr(instr); break;
+    case JALR: jalr(instr); break;
+    case SYSCALL: FireException(regs, ExceptionCode::Syscall, 0, true); break;
+    case BREAK: FireException(regs, ExceptionCode::Breakpoint, 0, true); break;
+    case SYNC: break; // SYNC
+    case MFHI: mfhi(instr); break;
+    case MTHI: mthi(instr); break;
+    case MFLO: mflo(instr); break;
+    case MTLO: mtlo(instr); break;
+    case DSLLV: dsllv(instr); break;
+    case DSRLV: dsrlv(instr); break;
+    case DSRAV: dsrav(instr); break;
+    case MULT: mult(instr); break;
+    case MULTU: multu(instr); break;
+    case DIV: div(instr); break;
+    case DIVU: divu(instr); break;
+    case DMULT: dmult(instr); break;
+    case DMULTU: dmultu(instr); break;
+    case DDIV: ddiv(instr); break;
+    case DDIVU: ddivu(instr); break;
+    case ADD: add(instr); break;
+    case ADDU: addu(instr); break;
+    case SUB: sub(instr); break;
+    case SUBU: subu(instr); break;
+    case AND: and_(instr); break;
+    case OR: or_(instr); break;
+    case XOR: xor_(instr); break;
+    case NOR: nor(instr); break;
+    case SLT: slt(instr); break;
+    case SLTU: sltu(instr); break;
+    case DADD: dadd(instr); break;
+    case DADDU: daddu(instr); break;
+    case DSUB: dsub(instr); break;
+    case DSUBU: dsubu(instr); break;
+    case TGE: trap(regs.gpr[RS(instr)] >= regs.gpr[RT(instr)]); break;
+    case TGEU: trap((u64)regs.gpr[RS(instr)] >= (u64)regs.gpr[RT(instr)]); break;
+    case TLT: trap(regs.gpr[RS(instr)] < regs.gpr[RT(instr)]); break;
+    case TLTU: trap((u64)regs.gpr[RS(instr)] < (u64)regs.gpr[RT(instr)]); break;
+    case TEQ: trap(regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break;
+    case TNE: trap(regs.gpr[RS(instr)] != regs.gpr[RT(instr)]); break;
+    case DSLL: dsll(instr); break;
+    case DSRL: dsrl(instr); break;
+    case DSRA: dsra(instr); break;
+    case DSLL32: dsll32(instr); break;
+    case DSRL32: dsrl32(instr); break;
+    case DSRA32: dsra32(instr); break;
     default:
       Util::panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 7, mask & 7, instr, (u64)regs.oldPC);
   }
@@ -71,20 +72,20 @@ void Interpreter::regimm(u32 instr) {
   u8 mask = ((instr >> 16) & 0x1F);
   // 000r_rccc
   switch (mask) { // TODO: named constants for clearer code
-    case 0x00: b(instr, regs.gpr[RS(instr)] < 0); break;
-    case 0x01: b(instr, regs.gpr[RS(instr)] >= 0); break;
-    case 0x02: bl(instr, regs.gpr[RS(instr)] < 0); break;
-    case 0x03: bl(instr, regs.gpr[RS(instr)] >= 0); break;
-    case 0x08: trap(regs.gpr[RS(instr)] >= s64(s16(instr))); break;
-    case 0x09: trap(u64(regs.gpr[RS(instr)]) >= u64(s64(s16(instr)))); break;
-    case 0x0A: trap(regs.gpr[RS(instr)] < s64(s16(instr))); break;
-    case 0x0B: trap(u64(regs.gpr[RS(instr)]) < u64(s64(s16(instr)))); break;
-    case 0x0C: trap(regs.gpr[RS(instr)] == s64(s16(instr))); break;
-    case 0x0E: trap(regs.gpr[RS(instr)] != s64(s16(instr))); break;
-    case 0x10: blink(instr, regs.gpr[RS(instr)] < 0); break;
-    case 0x11: blink(instr, regs.gpr[RS(instr)] >= 0); break;
-    case 0x12: bllink(instr, regs.gpr[RS(instr)] < 0); break;
-    case 0x13: bllink(instr, regs.gpr[RS(instr)] >= 0); break;
+    case BLTZ: b(instr, regs.gpr[RS(instr)] < 0); break;
+    case BGEZ: b(instr, regs.gpr[RS(instr)] >= 0); break;
+    case BLTZL: bl(instr, regs.gpr[RS(instr)] < 0); break;
+    case BGEZL: bl(instr, regs.gpr[RS(instr)] >= 0); break;
+    case TGEI: trap(regs.gpr[RS(instr)] >= s64(s16(instr))); break;
+    case TGEIU: trap(u64(regs.gpr[RS(instr)]) >= u64(s64(s16(instr)))); break;
+    case TLTI: trap(regs.gpr[RS(instr)] < s64(s16(instr))); break;
+    case TLTIU: trap(u64(regs.gpr[RS(instr)]) < u64(s64(s16(instr)))); break;
+    case TEQI: trap(regs.gpr[RS(instr)] == s64(s16(instr))); break;
+    case TNEI: trap(regs.gpr[RS(instr)] != s64(s16(instr))); break;
+    case BLTZAL: blink(instr, regs.gpr[RS(instr)] < 0); break;
+    case BGEZAL: blink(instr, regs.gpr[RS(instr)] >= 0); break;
+    case BLTZALL: bllink(instr, regs.gpr[RS(instr)] < 0); break;
+    case BGEZALL: bllink(instr, regs.gpr[RS(instr)] >= 0); break;
     default:
       Util::panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 3, mask & 7, instr, (u64)regs.oldPC);
   }
@@ -111,63 +112,63 @@ void Interpreter::Exec(u32 instr) {
   u8 mask = (instr >> 26) & 0x3f;
   // 00rr_rccc
   switch(mask) { // TODO: named constants for clearer code
-    case 0x00: special(instr); break;
-    case 0x01: regimm(instr); break;
-    case 0x02: j(instr); break;
-    case 0x03: jal(instr); break;
-    case 0x04: b(instr, regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break;
-    case 0x05: {
+    case SPECIAL: special(instr); break;
+    case REGIMM: regimm(instr); break;
+    case J: j(instr); break;
+    case JAL: jal(instr); break;
+    case BEQ: b(instr, regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break;
+    case BNE: {
       //fmt::print("RS: {:016X}, RT: {:016X}", (u64)regs.gpr[RS(instr)], (u64)regs.gpr[RT(instr)]);
       b(instr, regs.gpr[RS(instr)] != regs.gpr[RT(instr)]);
     } break;
-    case 0x06: b(instr, regs.gpr[RS(instr)] <= 0); break;
-    case 0x07: b(instr, regs.gpr[RS(instr)] > 0); break;
-    case 0x08: addi(instr); break;
-    case 0x09: addiu(instr); break;
-    case 0x0A: slti(instr); break;
-    case 0x0B: sltiu(instr); break;
-    case 0x0C: andi(instr); break;
-    case 0x0D: ori(instr); break;
-    case 0x0E: xori(instr); break;
-    case 0x0F: lui(instr); break;
-    case 0x10: regs.cop0.decode(regs, instr); break;
-    case 0x11: regs.cop1.decode(regs, *this, instr); break;
-    case 0x12: cop2Decode(instr); break;
-    case 0x14: bl(instr, regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break;
-    case 0x15: bl(instr, regs.gpr[RS(instr)] != regs.gpr[RT(instr)]); break;
-    case 0x16: bl(instr, regs.gpr[RS(instr)] <= 0); break;
-    case 0x17: bl(instr, regs.gpr[RS(instr)] > 0); break;
-    case 0x18: daddi(instr); break;
-    case 0x19: daddiu(instr); break;
-    case 0x1A: ldl(instr); break;
-    case 0x1B: ldr(instr); break;
+    case BLEZ: b(instr, regs.gpr[RS(instr)] <= 0); break;
+    case BGTZ: b(instr, regs.gpr[RS(instr)] > 0); break;
+    case ADDI: addi(instr); break;
+    case ADDIU: addiu(instr); break;
+    case SLTI: slti(instr); break;
+    case SLTIU: sltiu(instr); break;
+    case ANDI: andi(instr); break;
+    case ORI: ori(instr); break;
+    case XORI: xori(instr); break;
+    case LUI: lui(instr); break;
+    case COP0: regs.cop0.decode(*this, instr); break;
+    case COP1: regs.cop1.decode(*this, instr); break;
+    case COP2: cop2Decode(instr); break;
+    case BEQL: bl(instr, regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break;
+    case BNEL: bl(instr, regs.gpr[RS(instr)] != regs.gpr[RT(instr)]); break;
+    case BLEZL: bl(instr, regs.gpr[RS(instr)] <= 0); break;
+    case BGTZL: bl(instr, regs.gpr[RS(instr)] > 0); break;
+    case DADDI: daddi(instr); break;
+    case DADDIU: daddiu(instr); break;
+    case LDL: ldl(instr); break;
+    case LDR: ldr(instr); break;
     case 0x1F: FireException(regs, ExceptionCode::ReservedInstruction, 0, true); break;
-    case 0x20: lb(instr); break;
-    case 0x21: lh(instr); break;
-    case 0x22: lwl(instr); break;
-    case 0x23: lw(instr); break;
-    case 0x24: lbu(instr); break;
-    case 0x25: lhu(instr); break;
-    case 0x26: lwr(instr); break;
-    case 0x27: lwu(instr); break;
-    case 0x28: sb(instr); break;
-    case 0x29: sh(instr); break;
-    case 0x2A: swl(instr); break;
-    case 0x2B: sw(instr); break;
-    case 0x2C: sdl(instr); break;
-    case 0x2D: sdr(instr); break;
-    case 0x2E: swr(instr); break;
-    case 0x2F: break; // CACHE
-    case 0x30: ll(instr); break;
-    case 0x31: regs.cop1.lwc1(regs, mem, instr); break;
-    case 0x34: lld(instr); break;
-    case 0x35: regs.cop1.ldc1(regs, mem, instr); break;
-    case 0x37: ld(instr); break;
-    case 0x38: sc(instr); break;
-    case 0x39: regs.cop1.swc1(regs, mem, instr); break;
-    case 0x3C: scd(instr); break;
-    case 0x3D: regs.cop1.sdc1(regs, mem, instr); break;
-    case 0x3F: sd(instr); break;
+    case LB: lb(instr); break;
+    case LH: lh(instr); break;
+    case LWL: lwl(instr); break;
+    case LW: lw(instr); break;
+    case LBU: lbu(instr); break;
+    case LHU: lhu(instr); break;
+    case LWR: lwr(instr); break;
+    case LWU: lwu(instr); break;
+    case SB: sb(instr); break;
+    case SH: sh(instr); break;
+    case SWL: swl(instr); break;
+    case SW: sw(instr); break;
+    case SDL: sdl(instr); break;
+    case SDR: sdr(instr); break;
+    case SWR: swr(instr); break;
+    case CACHE: break; // CACHE
+    case LL: ll(instr); break;
+    case LWC1: regs.cop1.lwc1(*this, mem, instr); break;
+    case LLD: lld(instr); break;
+    case LDC1: regs.cop1.ldc1(*this, mem, instr); break;
+    case LD: ld(instr); break;
+    case SC: sc(instr); break;
+    case SWC1: regs.cop1.swc1(*this, mem, instr); break;
+    case SCD: scd(instr); break;
+    case SDC1: regs.cop1.sdc1(*this, mem, instr); break;
+    case SD: sd(instr); break;
     default:
       Util::panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", mask, instr, (u64)regs.oldPC);
   }