diff --git a/src/backend/Core.cpp b/src/backend/Core.cpp
index fee069f6..6b3263e6 100644
--- a/src/backend/Core.cpp
+++ b/src/backend/Core.cpp
@@ -66,7 +66,7 @@ void Core::Run(float volumeL, float volumeR) {
       mmio.vi.current = (i << 1) + field;
 
       if ((mmio.vi.current & 0x3FE) == mmio.vi.intr) {
-        InterruptRaise(mmio.mi, regs, Interrupt::VI);
+        mmio.mi.InterruptRaise(MI::Interrupt::VI);
       }
 
       for(; cycles < mem.mmio.vi.cyclesPerHalfline; cycles++, frameCycles++) {
@@ -98,7 +98,7 @@ void Core::Run(float volumeL, float volumeR) {
     }
 
     if ((mmio.vi.current & 0x3FE) == mmio.vi.intr) {
-      InterruptRaise(mmio.mi, regs, Interrupt::VI);
+      mmio.mi.InterruptRaise(MI::Interrupt::VI);
     }
 
     mmio.ai.Step(cpu->mem, regs, frameCycles, volumeL, volumeR);
diff --git a/src/backend/Scheduler.cpp b/src/backend/Scheduler.cpp
index 19b686cd..e03e4ccc 100644
--- a/src/backend/Scheduler.cpp
+++ b/src/backend/Scheduler.cpp
@@ -37,7 +37,7 @@ void Scheduler::tick(u64 t, n64::Mem& mem, n64::Registers& regs) {
         si.DMA(mem, regs);
         break;
       case PI_DMA_COMPLETE:
-        InterruptRaise(mi, regs, n64::Interrupt::PI);
+        mi.InterruptRaise(n64::MI::Interrupt::PI);
         pi.dmaBusy = false;
         break;
       case PI_BUS_WRITE_COMPLETE:
diff --git a/src/backend/core/BaseCPU.hpp b/src/backend/core/BaseCPU.hpp
index 51fa9c1a..3f8bcf0c 100644
--- a/src/backend/core/BaseCPU.hpp
+++ b/src/backend/core/BaseCPU.hpp
@@ -15,6 +15,6 @@ struct BaseCPU {
   virtual std::vector<u8> Serialize() = 0;
   virtual void Deserialize(const std::vector<u8>&) = 0;
   Registers regs;
-  Mem mem;
+  Mem mem{regs};
 };
 }
\ No newline at end of file
diff --git a/src/backend/core/Interpreter.cpp b/src/backend/core/Interpreter.cpp
index a7ccace2..046101a8 100644
--- a/src/backend/core/Interpreter.cpp
+++ b/src/backend/core/Interpreter.cpp
@@ -17,7 +17,7 @@ void Interpreter::CheckCompareInterrupt() {
   regs.cop0.count &= 0x1FFFFFFFF;
   if(regs.cop0.count == (u64)regs.cop0.compare << 1) {
     regs.cop0.cause.ip7 = 1;
-    UpdateInterrupt(mem.mmio.mi, regs);
+    mem.mmio.mi.UpdateInterrupt();
   }
 }
 
diff --git a/src/backend/core/MMIO.hpp b/src/backend/core/MMIO.hpp
index da09610f..04d6fd15 100644
--- a/src/backend/core/MMIO.hpp
+++ b/src/backend/core/MMIO.hpp
@@ -13,7 +13,7 @@ struct Mem;
 struct Registers;
 
 struct MMIO {
-  MMIO() = default;
+  MMIO(Registers& regs) : mi(regs) {}
   void Reset();
 
   VI vi;
diff --git a/src/backend/core/Mem.cpp b/src/backend/core/Mem.cpp
index cef1125e..5fe97e05 100644
--- a/src/backend/core/Mem.cpp
+++ b/src/backend/core/Mem.cpp
@@ -8,7 +8,7 @@
 #include <cassert>
 
 namespace n64 {
-Mem::Mem() : flash(saveData) {
+Mem::Mem(Registers& regs) : flash(saveData), mmio(regs) {
   memset(readPages, 0, PAGE_COUNT);
   memset(writePages, 0, PAGE_COUNT);
 
diff --git a/src/backend/core/Mem.hpp b/src/backend/core/Mem.hpp
index ee1b0597..d445b717 100644
--- a/src/backend/core/Mem.hpp
+++ b/src/backend/core/Mem.hpp
@@ -81,7 +81,7 @@ struct Flash {
 
 struct Mem {
   ~Mem() = default;
-  Mem();
+  Mem(Registers&);
   void Reset();
   void LoadSRAM(SaveType, fs::path);
   static std::vector<u8> OpenROM(const std::string&, size_t&);
diff --git a/src/backend/core/RDP.cpp b/src/backend/core/RDP.cpp
index 8cd56e4b..09a490ab 100644
--- a/src/backend/core/RDP.cpp
+++ b/src/backend/core/RDP.cpp
@@ -204,6 +204,6 @@ void RDP::OnFullSync(MI& mi, Registers& regs) {
   dpc.status.pipeBusy = false;
   dpc.status.startGclk = false;
   dpc.status.cbufReady = false;
-  InterruptRaise(mi, regs, Interrupt::DP);
+  mi.InterruptRaise(MI::Interrupt::DP);
 }
 }
diff --git a/src/backend/core/RSP.cpp b/src/backend/core/RSP.cpp
index 93107cbc..343e104c 100644
--- a/src/backend/core/RSP.cpp
+++ b/src/backend/core/RSP.cpp
@@ -94,9 +94,9 @@ void RSP::WriteStatus(MI& mi, Registers& regs, u32 value) {
   }
   if(write.clearBroke) spStatus.broke = false;
   if(write.clearIntr && !write.setIntr)
-    InterruptLower(mi, regs, Interrupt::SP);
+    mi.InterruptLower(MI::Interrupt::SP);
   if(write.setIntr && !write.clearIntr)
-    InterruptRaise(mi, regs, Interrupt::SP);
+    mi.InterruptRaise(MI::Interrupt::SP);
   CLEAR_SET(spStatus.singleStep, write.clearSstep, write.setSstep);
   CLEAR_SET(spStatus.interruptOnBreak, write.clearIntrOnBreak, write.setIntrOnBreak);
   CLEAR_SET(spStatus.signal0, write.clearSignal0, write.setSignal0);
diff --git a/src/backend/core/mmio/AI.cpp b/src/backend/core/mmio/AI.cpp
index b26fd80d..86a31094 100644
--- a/src/backend/core/mmio/AI.cpp
+++ b/src/backend/core/mmio/AI.cpp
@@ -43,7 +43,7 @@ void AI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
     case 0x04500004: {
       u32 len = (val & 0x3FFFF) & ~7;
       if(dmaCount < 2) {
-        if(dmaCount == 0) InterruptRaise(mem.mmio.mi, regs, Interrupt::AI);
+        if(dmaCount == 0) mem.mmio.mi.InterruptRaise(MI::Interrupt::AI);
         dmaLen[dmaCount] = len;
         dmaCount++;
       }
@@ -52,7 +52,7 @@ void AI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
       dmaEnable = val & 1;
       break;
     case 0x0450000C:
-      InterruptLower(mem.mmio.mi, regs, Interrupt::AI);
+      mem.mmio.mi.InterruptLower(MI::Interrupt::AI);
       break;
     case 0x04500010: {
       u32 oldDacFreq = dac.freq;
@@ -97,7 +97,7 @@ void AI::Step(Mem& mem, Registers& regs, u32 cpuCycles, float volumeL, float vol
 
     if(!dmaLen[0]) {
       if(--dmaCount > 0) {
-        InterruptRaise(mem.mmio.mi, regs, Interrupt::AI);
+        mem.mmio.mi.InterruptRaise(MI::Interrupt::AI);
         dmaAddr[0] = dmaAddr[1];
         dmaLen[0] = dmaLen[1];
       }
diff --git a/src/backend/core/mmio/Interrupt.cpp b/src/backend/core/mmio/Interrupt.cpp
index dded9c7d..ef91d770 100644
--- a/src/backend/core/mmio/Interrupt.cpp
+++ b/src/backend/core/mmio/Interrupt.cpp
@@ -3,57 +3,58 @@
 #include <core/registers/Registers.hpp>
 
 namespace n64 {
-void InterruptRaise(MI &mi, Registers &regs, Interrupt intr) {
+void MI::InterruptRaise(Interrupt intr) {
   switch(intr) {
     case Interrupt::VI:
-      mi.miIntr.vi = true;
+      miIntr.vi = true;
       break;
     case Interrupt::SI:
-      mi.miIntr.si = true;
+      miIntr.si = true;
       break;
     case Interrupt::PI:
-      mi.miIntr.pi = true;
+      miIntr.pi = true;
       break;
     case Interrupt::AI:
-      mi.miIntr.ai = true;
+      miIntr.ai = true;
       break;
     case Interrupt::DP:
-      mi.miIntr.dp = true;
+      miIntr.dp = true;
       break;
     case Interrupt::SP:
-      mi.miIntr.sp = true;
+      miIntr.sp = true;
       break;
   }
 
-  UpdateInterrupt(mi, regs);
+  UpdateInterrupt();
 }
 
-void InterruptLower(MI &mi, Registers &regs, Interrupt intr) {
+void MI::InterruptLower(Interrupt intr) {
   switch(intr) {
     case Interrupt::VI:
-      mi.miIntr.vi = false;
+      miIntr.vi = false;
       break;
     case Interrupt::SI:
-      mi.miIntr.si = false;
+      miIntr.si = false;
       break;
     case Interrupt::PI:
-      mi.miIntr.pi = false;
+      miIntr.pi = false;
       break;
     case Interrupt::AI:
-      mi.miIntr.ai = false;
+      miIntr.ai = false;
       break;
     case Interrupt::DP:
-      mi.miIntr.dp = false;
+      miIntr.dp = false;
       break;
     case Interrupt::SP:
-      mi.miIntr.sp = false;
+      miIntr.sp = false;
       break;
   }
 
-  UpdateInterrupt(mi, regs);
+  UpdateInterrupt();
 }
-void UpdateInterrupt(MI &mi, Registers &regs) {
-  bool interrupt = mi.miIntr.raw & mi.miIntrMask.raw;
+
+void MI::UpdateInterrupt() {
+  bool interrupt = miIntr.raw & miIntrMask.raw;
   regs.cop0.cause.ip2 = interrupt;
 }
 }
\ No newline at end of file
diff --git a/src/backend/core/mmio/Interrupt.hpp b/src/backend/core/mmio/Interrupt.hpp
index e5093f72..addfbdc7 100644
--- a/src/backend/core/mmio/Interrupt.hpp
+++ b/src/backend/core/mmio/Interrupt.hpp
@@ -6,11 +6,4 @@ namespace n64 {
 
 struct Registers;
 
-enum class Interrupt : u8 {
-  VI, SI, PI, AI, DP, SP
-};
-
-void InterruptRaise(MI &mi, Registers &regs, Interrupt intr);
-void InterruptLower(MI &mi, Registers &regs, Interrupt intr);
-void UpdateInterrupt(MI &mi, Registers &regs);
 }
\ No newline at end of file
diff --git a/src/backend/core/mmio/MI.cpp b/src/backend/core/mmio/MI.cpp
index 0d85c1da..9c818629 100644
--- a/src/backend/core/mmio/MI.cpp
+++ b/src/backend/core/mmio/MI.cpp
@@ -6,7 +6,7 @@
 #define MI_VERSION_REG 0x02020102
 
 namespace n64 {
-MI::MI() {
+MI::MI(Registers& regs) : regs(regs) {
   Reset();
 }
 
@@ -49,7 +49,7 @@ void MI::Write(Registers& regs, u32 paddr, u32 val) {
       }
 
       if (val & (1 << 11)) {
-        InterruptLower(*this, regs, Interrupt::DP);
+        InterruptLower(Interrupt::DP);
       }
 
       if (val & (1 << 12)) {
@@ -75,7 +75,7 @@ void MI::Write(Registers& regs, u32 paddr, u32 val) {
         }
       }
 
-      UpdateInterrupt(*this, regs);
+      UpdateInterrupt();
       break;
     default:
       Util::panic("Unhandled MI[{:08X}] write ({:08X})", val, paddr);
diff --git a/src/backend/core/mmio/MI.hpp b/src/backend/core/mmio/MI.hpp
index 1dad8bba..73d67ae1 100644
--- a/src/backend/core/mmio/MI.hpp
+++ b/src/backend/core/mmio/MI.hpp
@@ -19,12 +19,20 @@ union MIIntr {
 struct Registers;
 
 struct MI {
-  MI();
+  enum class Interrupt : u8 {
+    VI, SI, PI, AI, DP, SP
+  };
+
+  MI(Registers&);
   void Reset();
   [[nodiscard]] auto Read(u32) const -> u32;
   void Write(Registers& regs, u32, u32);
+  void InterruptRaise(Interrupt intr);
+  void InterruptLower(Interrupt intr);
+  void UpdateInterrupt();
 
   u32 miMode{};
   MIIntr miIntr{}, miIntrMask{};
+  Registers& regs;
 };
 }
\ No newline at end of file
diff --git a/src/backend/core/mmio/PI.cpp b/src/backend/core/mmio/PI.cpp
index 8eb916ff..522debc5 100644
--- a/src/backend/core/mmio/PI.cpp
+++ b/src/backend/core/mmio/PI.cpp
@@ -474,7 +474,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
     } break;
     case 0x04600010:
       if(val & 2) {
-        InterruptLower(mi, regs, Interrupt::PI);
+        mi.InterruptLower(MI::Interrupt::PI);
       } break;
     case 0x04600014: pi_bsd_dom1_lat = val & 0xff; break;
     case 0x04600018: pi_bsd_dom1_pwd = val & 0xff; break;
diff --git a/src/backend/core/mmio/SI.cpp b/src/backend/core/mmio/SI.cpp
index 8a0814d8..659f3162 100644
--- a/src/backend/core/mmio/SI.cpp
+++ b/src/backend/core/mmio/SI.cpp
@@ -48,7 +48,7 @@ void SI::DMA(Mem& mem, Registers& regs) const {
     Util::trace("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})", si.dramAddr, si.pifAddr);
     si.pif.ProcessCommands(mem);
   }
-  InterruptRaise(mem.mmio.mi, regs, Interrupt::SI);
+  mem.mmio.mi.InterruptRaise(MI::Interrupt::SI);
 }
 
 void SI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
@@ -69,7 +69,7 @@ void SI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
       scheduler.enqueueRelative(SI_DMA_DELAY, SI_DMA);
     } break;
     case 0x04800018:
-      InterruptLower(mem.mmio.mi, regs, Interrupt::SI);
+      mem.mmio.mi.InterruptLower(MI::Interrupt::SI);
       break;
     default:
       Util::panic("Unhandled SI[{:08X}] write ({:08X})", addr, val);
diff --git a/src/backend/core/mmio/VI.cpp b/src/backend/core/mmio/VI.cpp
index 9c65d477..0995602b 100644
--- a/src/backend/core/mmio/VI.cpp
+++ b/src/backend/core/mmio/VI.cpp
@@ -63,7 +63,7 @@ void VI::Write(MI& mi, Registers& regs, u32 paddr, u32 val) {
       intr = val & 0x3FF;
     } break;
     case 0x04400010:
-      InterruptLower(mi, regs, Interrupt::VI);
+      mi.InterruptLower(MI::Interrupt::VI);
       break;
     case 0x04400014: burst.raw = val; break;
     case 0x04400018: {
diff --git a/src/backend/core/rsp/decode.cpp b/src/backend/core/rsp/decode.cpp
index 89f26dee..a2553df1 100644
--- a/src/backend/core/rsp/decode.cpp
+++ b/src/backend/core/rsp/decode.cpp
@@ -26,7 +26,7 @@ FORCE_INLINE void special(MI& mi, Registers& regs, RSP& rsp, u32 instr) {
       rsp.steps = 0;
       rsp.spStatus.broke = true;
       if(rsp.spStatus.interruptOnBreak) {
-        InterruptRaise(mi, regs, Interrupt::SP);
+        mi.InterruptRaise(MI::Interrupt::SP);
       }
       break;
     case 0x20: case 0x21: