From fda755f7d888d73fbedb0d374af116ab8a8c6835 Mon Sep 17 00:00:00 2001
From: iris <iris.kaizen@pm.me>
Date: Fri, 3 Apr 2026 18:03:09 +0200
Subject: [PATCH] idk

---
 src/backend/core/Mem.hpp     |  6 +++---
 src/backend/core/mmio/PI.cpp | 32 +++++++++++++++-----------------
 2 files changed, 18 insertions(+), 20 deletions(-)

diff --git a/src/backend/core/Mem.hpp b/src/backend/core/Mem.hpp
index e719698..8c5d5e1 100644
--- a/src/backend/core/Mem.hpp
+++ b/src/backend/core/Mem.hpp
@@ -98,10 +98,10 @@ struct Mem {
   template <typename T>
   void BackupWrite(u32, T);
 
-  FORCE_INLINE void DumpRDRAM() const {
+  FORCE_INLINE void DumpRDRAM(u32 start = 0, u32 size = RDRAM_SIZE) const {
     std::vector<u8> temp{};
-    temp.resize(RDRAM_SIZE);
-    std::ranges::copy(mmio.rdp.rdram, temp.begin());
+    temp.resize(size);
+    std::copy(mmio.rdp.rdram.begin() + start, mmio.rdp.rdram.begin() + size - 1, temp.begin());
     ircolib::SwapBuffer<u32>(temp);
     ircolib::WriteFileBinary(temp, "rdram.bin");
   }
diff --git a/src/backend/core/mmio/PI.cpp b/src/backend/core/mmio/PI.cpp
index 22aa45f..e3877a2 100644
--- a/src/backend/core/mmio/PI.cpp
+++ b/src/backend/core/mmio/PI.cpp
@@ -423,9 +423,9 @@ auto PI::Read(u32 addr) const -> u32 {
   case 0x04600010:
     {
       u32 value = 0;
-      value |= (dmaBusy << 0); // Is PI DMA active? No, because it's instant
-      value |= (ioBusy << 1); // Is PI IO busy? No, because it's instant
-      value |= (0 << 2); // PI IO error?
+      value |= (dmaBusy << 0); // Is PI DMA active?
+      value |= (ioBusy << 1); // Is PI IO busy?
+      value |= (0 << 2); // PI DMA error?
       value |= (mem.mmio.mi.intr.pi << 3); // PI interrupt?
       return value;
     }
@@ -503,13 +503,10 @@ void PI::DMA<false>() {
   const s32 len = rdLen + 1;
   trace("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
 
-  if (mem.saveType == SAVE_FLASH_1m && cartAddr >= SREGION_PI_SRAM && cartAddr < (CART_REGION_START_2_2 + 1_mb)) {
-    cartAddr = SREGION_PI_SRAM | ((cartAddr & (1_mb-1)) << 1);
-  }
-
   for (int i = 0; i < len; i++) {
     BusWrite<u8, true>(cartAddr + i, mem.mmio.rdp.ReadRDRAM<u8>(dramAddr + i));
   }
+  
   dramAddr += len;
   dramAddr = (dramAddr + 7) & ~7;
   cartAddr += len;
@@ -517,7 +514,10 @@ void PI::DMA<false>() {
     cartAddr += 1;
 
   dmaBusy = true;
-  Scheduler::GetInstance().EnqueueRelative(AccessTiming(GetDomain(cartAddr), rdLen), PI_DMA_COMPLETE);
+  
+  u64 completo = AccessTiming(GetDomain(cartAddr), len);
+  trace("Will complete in {} cycles", completo);
+  Scheduler::GetInstance().EnqueueRelative(completo, PI_DMA_COMPLETE);
 }
 
 // cart -> rdram
@@ -541,7 +541,9 @@ void PI::DMA<true>() {
     cartAddr += 1;
 
   dmaBusy = true;
-  Scheduler::GetInstance().EnqueueRelative(AccessTiming(GetDomain(cartAddr), len), PI_DMA_COMPLETE);
+  u64 completo = AccessTiming(GetDomain(cartAddr), len);
+  trace("Will complete in {} cycles", completo);
+  Scheduler::GetInstance().EnqueueRelative(completo, PI_DMA_COMPLETE);
 }
 
 void PI::Write(u32 addr, u32 val) {
@@ -555,16 +557,12 @@ void PI::Write(u32 addr, u32 val) {
     cartAddr = val & 0xFFFFFFFE;
     break;
   case 0x04600008:
-    {
-      rdLen = val & 0x00FFFFFF;
-      DMA<false>();
-    }
+    rdLen = val & 0x00FFFFFF;
+    DMA<false>();
     break;
   case 0x0460000C:
-    {
-      wrLen = val & 0x00FFFFFF;
-      DMA<true>();
-    }
+    wrLen = val & 0x00FFFFFF;
+    DMA<true>();
     break;
   case 0x04600010:
     if (val & 2) {