/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM

  enum {
    ARM_PHI	= 0,
    ARM_INLINEASM	= 1,
    ARM_INLINEASM_BR	= 2,
    ARM_CFI_INSTRUCTION	= 3,
    ARM_EH_LABEL	= 4,
    ARM_GC_LABEL	= 5,
    ARM_ANNOTATION_LABEL	= 6,
    ARM_KILL	= 7,
    ARM_EXTRACT_SUBREG	= 8,
    ARM_INSERT_SUBREG	= 9,
    ARM_IMPLICIT_DEF	= 10,
    ARM_SUBREG_TO_REG	= 11,
    ARM_COPY_TO_REGCLASS	= 12,
    ARM_DBG_VALUE	= 13,
    ARM_DBG_VALUE_LIST	= 14,
    ARM_DBG_INSTR_REF	= 15,
    ARM_DBG_PHI	= 16,
    ARM_DBG_LABEL	= 17,
    ARM_REG_SEQUENCE	= 18,
    ARM_COPY	= 19,
    ARM_BUNDLE	= 20,
    ARM_LIFETIME_START	= 21,
    ARM_LIFETIME_END	= 22,
    ARM_PSEUDO_PROBE	= 23,
    ARM_ARITH_FENCE	= 24,
    ARM_STACKMAP	= 25,
    ARM_FENTRY_CALL	= 26,
    ARM_PATCHPOINT	= 27,
    ARM_LOAD_STACK_GUARD	= 28,
    ARM_PREALLOCATED_SETUP	= 29,
    ARM_PREALLOCATED_ARG	= 30,
    ARM_STATEPOINT	= 31,
    ARM_LOCAL_ESCAPE	= 32,
    ARM_FAULTING_OP	= 33,
    ARM_PATCHABLE_OP	= 34,
    ARM_PATCHABLE_FUNCTION_ENTER	= 35,
    ARM_PATCHABLE_RET	= 36,
    ARM_PATCHABLE_FUNCTION_EXIT	= 37,
    ARM_PATCHABLE_TAIL_CALL	= 38,
    ARM_PATCHABLE_EVENT_CALL	= 39,
    ARM_PATCHABLE_TYPED_EVENT_CALL	= 40,
    ARM_ICALL_BRANCH_FUNNEL	= 41,
    ARM_MEMBARRIER	= 42,
    ARM_JUMP_TABLE_DEBUG_INFO	= 43,
    ARM_G_ASSERT_SEXT	= 44,
    ARM_G_ASSERT_ZEXT	= 45,
    ARM_G_ASSERT_ALIGN	= 46,
    ARM_G_ADD	= 47,
    ARM_G_SUB	= 48,
    ARM_G_MUL	= 49,
    ARM_G_SDIV	= 50,
    ARM_G_UDIV	= 51,
    ARM_G_SREM	= 52,
    ARM_G_UREM	= 53,
    ARM_G_SDIVREM	= 54,
    ARM_G_UDIVREM	= 55,
    ARM_G_AND	= 56,
    ARM_G_OR	= 57,
    ARM_G_XOR	= 58,
    ARM_G_IMPLICIT_DEF	= 59,
    ARM_G_PHI	= 60,
    ARM_G_FRAME_INDEX	= 61,
    ARM_G_GLOBAL_VALUE	= 62,
    ARM_G_CONSTANT_POOL	= 63,
    ARM_G_EXTRACT	= 64,
    ARM_G_UNMERGE_VALUES	= 65,
    ARM_G_INSERT	= 66,
    ARM_G_MERGE_VALUES	= 67,
    ARM_G_BUILD_VECTOR	= 68,
    ARM_G_BUILD_VECTOR_TRUNC	= 69,
    ARM_G_CONCAT_VECTORS	= 70,
    ARM_G_PTRTOINT	= 71,
    ARM_G_INTTOPTR	= 72,
    ARM_G_BITCAST	= 73,
    ARM_G_FREEZE	= 74,
    ARM_G_CONSTANT_FOLD_BARRIER	= 75,
    ARM_G_INTRINSIC_FPTRUNC_ROUND	= 76,
    ARM_G_INTRINSIC_TRUNC	= 77,
    ARM_G_INTRINSIC_ROUND	= 78,
    ARM_G_INTRINSIC_LRINT	= 79,
    ARM_G_INTRINSIC_ROUNDEVEN	= 80,
    ARM_G_READCYCLECOUNTER	= 81,
    ARM_G_LOAD	= 82,
    ARM_G_SEXTLOAD	= 83,
    ARM_G_ZEXTLOAD	= 84,
    ARM_G_INDEXED_LOAD	= 85,
    ARM_G_INDEXED_SEXTLOAD	= 86,
    ARM_G_INDEXED_ZEXTLOAD	= 87,
    ARM_G_STORE	= 88,
    ARM_G_INDEXED_STORE	= 89,
    ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 90,
    ARM_G_ATOMIC_CMPXCHG	= 91,
    ARM_G_ATOMICRMW_XCHG	= 92,
    ARM_G_ATOMICRMW_ADD	= 93,
    ARM_G_ATOMICRMW_SUB	= 94,
    ARM_G_ATOMICRMW_AND	= 95,
    ARM_G_ATOMICRMW_NAND	= 96,
    ARM_G_ATOMICRMW_OR	= 97,
    ARM_G_ATOMICRMW_XOR	= 98,
    ARM_G_ATOMICRMW_MAX	= 99,
    ARM_G_ATOMICRMW_MIN	= 100,
    ARM_G_ATOMICRMW_UMAX	= 101,
    ARM_G_ATOMICRMW_UMIN	= 102,
    ARM_G_ATOMICRMW_FADD	= 103,
    ARM_G_ATOMICRMW_FSUB	= 104,
    ARM_G_ATOMICRMW_FMAX	= 105,
    ARM_G_ATOMICRMW_FMIN	= 106,
    ARM_G_ATOMICRMW_UINC_WRAP	= 107,
    ARM_G_ATOMICRMW_UDEC_WRAP	= 108,
    ARM_G_FENCE	= 109,
    ARM_G_PREFETCH	= 110,
    ARM_G_BRCOND	= 111,
    ARM_G_BRINDIRECT	= 112,
    ARM_G_INVOKE_REGION_START	= 113,
    ARM_G_INTRINSIC	= 114,
    ARM_G_INTRINSIC_W_SIDE_EFFECTS	= 115,
    ARM_G_INTRINSIC_CONVERGENT	= 116,
    ARM_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS	= 117,
    ARM_G_ANYEXT	= 118,
    ARM_G_TRUNC	= 119,
    ARM_G_CONSTANT	= 120,
    ARM_G_FCONSTANT	= 121,
    ARM_G_VASTART	= 122,
    ARM_G_VAARG	= 123,
    ARM_G_SEXT	= 124,
    ARM_G_SEXT_INREG	= 125,
    ARM_G_ZEXT	= 126,
    ARM_G_SHL	= 127,
    ARM_G_LSHR	= 128,
    ARM_G_ASHR	= 129,
    ARM_G_FSHL	= 130,
    ARM_G_FSHR	= 131,
    ARM_G_ROTR	= 132,
    ARM_G_ROTL	= 133,
    ARM_G_ICMP	= 134,
    ARM_G_FCMP	= 135,
    ARM_G_SELECT	= 136,
    ARM_G_UADDO	= 137,
    ARM_G_UADDE	= 138,
    ARM_G_USUBO	= 139,
    ARM_G_USUBE	= 140,
    ARM_G_SADDO	= 141,
    ARM_G_SADDE	= 142,
    ARM_G_SSUBO	= 143,
    ARM_G_SSUBE	= 144,
    ARM_G_UMULO	= 145,
    ARM_G_SMULO	= 146,
    ARM_G_UMULH	= 147,
    ARM_G_SMULH	= 148,
    ARM_G_UADDSAT	= 149,
    ARM_G_SADDSAT	= 150,
    ARM_G_USUBSAT	= 151,
    ARM_G_SSUBSAT	= 152,
    ARM_G_USHLSAT	= 153,
    ARM_G_SSHLSAT	= 154,
    ARM_G_SMULFIX	= 155,
    ARM_G_UMULFIX	= 156,
    ARM_G_SMULFIXSAT	= 157,
    ARM_G_UMULFIXSAT	= 158,
    ARM_G_SDIVFIX	= 159,
    ARM_G_UDIVFIX	= 160,
    ARM_G_SDIVFIXSAT	= 161,
    ARM_G_UDIVFIXSAT	= 162,
    ARM_G_FADD	= 163,
    ARM_G_FSUB	= 164,
    ARM_G_FMUL	= 165,
    ARM_G_FMA	= 166,
    ARM_G_FMAD	= 167,
    ARM_G_FDIV	= 168,
    ARM_G_FREM	= 169,
    ARM_G_FPOW	= 170,
    ARM_G_FPOWI	= 171,
    ARM_G_FEXP	= 172,
    ARM_G_FEXP2	= 173,
    ARM_G_FEXP10	= 174,
    ARM_G_FLOG	= 175,
    ARM_G_FLOG2	= 176,
    ARM_G_FLOG10	= 177,
    ARM_G_FLDEXP	= 178,
    ARM_G_FFREXP	= 179,
    ARM_G_FNEG	= 180,
    ARM_G_FPEXT	= 181,
    ARM_G_FPTRUNC	= 182,
    ARM_G_FPTOSI	= 183,
    ARM_G_FPTOUI	= 184,
    ARM_G_SITOFP	= 185,
    ARM_G_UITOFP	= 186,
    ARM_G_FABS	= 187,
    ARM_G_FCOPYSIGN	= 188,
    ARM_G_IS_FPCLASS	= 189,
    ARM_G_FCANONICALIZE	= 190,
    ARM_G_FMINNUM	= 191,
    ARM_G_FMAXNUM	= 192,
    ARM_G_FMINNUM_IEEE	= 193,
    ARM_G_FMAXNUM_IEEE	= 194,
    ARM_G_FMINIMUM	= 195,
    ARM_G_FMAXIMUM	= 196,
    ARM_G_GET_FPENV	= 197,
    ARM_G_SET_FPENV	= 198,
    ARM_G_RESET_FPENV	= 199,
    ARM_G_GET_FPMODE	= 200,
    ARM_G_SET_FPMODE	= 201,
    ARM_G_RESET_FPMODE	= 202,
    ARM_G_PTR_ADD	= 203,
    ARM_G_PTRMASK	= 204,
    ARM_G_SMIN	= 205,
    ARM_G_SMAX	= 206,
    ARM_G_UMIN	= 207,
    ARM_G_UMAX	= 208,
    ARM_G_ABS	= 209,
    ARM_G_LROUND	= 210,
    ARM_G_LLROUND	= 211,
    ARM_G_BR	= 212,
    ARM_G_BRJT	= 213,
    ARM_G_INSERT_VECTOR_ELT	= 214,
    ARM_G_EXTRACT_VECTOR_ELT	= 215,
    ARM_G_SHUFFLE_VECTOR	= 216,
    ARM_G_CTTZ	= 217,
    ARM_G_CTTZ_ZERO_UNDEF	= 218,
    ARM_G_CTLZ	= 219,
    ARM_G_CTLZ_ZERO_UNDEF	= 220,
    ARM_G_CTPOP	= 221,
    ARM_G_BSWAP	= 222,
    ARM_G_BITREVERSE	= 223,
    ARM_G_FCEIL	= 224,
    ARM_G_FCOS	= 225,
    ARM_G_FSIN	= 226,
    ARM_G_FSQRT	= 227,
    ARM_G_FFLOOR	= 228,
    ARM_G_FRINT	= 229,
    ARM_G_FNEARBYINT	= 230,
    ARM_G_ADDRSPACE_CAST	= 231,
    ARM_G_BLOCK_ADDR	= 232,
    ARM_G_JUMP_TABLE	= 233,
    ARM_G_DYN_STACKALLOC	= 234,
    ARM_G_STACKSAVE	= 235,
    ARM_G_STACKRESTORE	= 236,
    ARM_G_STRICT_FADD	= 237,
    ARM_G_STRICT_FSUB	= 238,
    ARM_G_STRICT_FMUL	= 239,
    ARM_G_STRICT_FDIV	= 240,
    ARM_G_STRICT_FREM	= 241,
    ARM_G_STRICT_FMA	= 242,
    ARM_G_STRICT_FSQRT	= 243,
    ARM_G_STRICT_FLDEXP	= 244,
    ARM_G_READ_REGISTER	= 245,
    ARM_G_WRITE_REGISTER	= 246,
    ARM_G_MEMCPY	= 247,
    ARM_G_MEMCPY_INLINE	= 248,
    ARM_G_MEMMOVE	= 249,
    ARM_G_MEMSET	= 250,
    ARM_G_BZERO	= 251,
    ARM_G_VECREDUCE_SEQ_FADD	= 252,
    ARM_G_VECREDUCE_SEQ_FMUL	= 253,
    ARM_G_VECREDUCE_FADD	= 254,
    ARM_G_VECREDUCE_FMUL	= 255,
    ARM_G_VECREDUCE_FMAX	= 256,
    ARM_G_VECREDUCE_FMIN	= 257,
    ARM_G_VECREDUCE_FMAXIMUM	= 258,
    ARM_G_VECREDUCE_FMINIMUM	= 259,
    ARM_G_VECREDUCE_ADD	= 260,
    ARM_G_VECREDUCE_MUL	= 261,
    ARM_G_VECREDUCE_AND	= 262,
    ARM_G_VECREDUCE_OR	= 263,
    ARM_G_VECREDUCE_XOR	= 264,
    ARM_G_VECREDUCE_SMAX	= 265,
    ARM_G_VECREDUCE_SMIN	= 266,
    ARM_G_VECREDUCE_UMAX	= 267,
    ARM_G_VECREDUCE_UMIN	= 268,
    ARM_G_SBFX	= 269,
    ARM_G_UBFX	= 270,
    ARM_ABS	= 271,
    ARM_ADDSri	= 272,
    ARM_ADDSrr	= 273,
    ARM_ADDSrsi	= 274,
    ARM_ADDSrsr	= 275,
    ARM_ADJCALLSTACKDOWN	= 276,
    ARM_ADJCALLSTACKUP	= 277,
    ARM_ASRi	= 278,
    ARM_ASRr	= 279,
    ARM_B	= 280,
    ARM_BCCZi64	= 281,
    ARM_BCCi64	= 282,
    ARM_BLX_noip	= 283,
    ARM_BLX_pred_noip	= 284,
    ARM_BL_PUSHLR	= 285,
    ARM_BMOVPCB_CALL	= 286,
    ARM_BMOVPCRX_CALL	= 287,
    ARM_BR_JTadd	= 288,
    ARM_BR_JTm_i12	= 289,
    ARM_BR_JTm_rs	= 290,
    ARM_BR_JTr	= 291,
    ARM_BX_CALL	= 292,
    ARM_CMP_SWAP_16	= 293,
    ARM_CMP_SWAP_32	= 294,
    ARM_CMP_SWAP_64	= 295,
    ARM_CMP_SWAP_8	= 296,
    ARM_CONSTPOOL_ENTRY	= 297,
    ARM_COPY_STRUCT_BYVAL_I32	= 298,
    ARM_ITasm	= 299,
    ARM_Int_eh_sjlj_dispatchsetup	= 300,
    ARM_Int_eh_sjlj_longjmp	= 301,
    ARM_Int_eh_sjlj_setjmp	= 302,
    ARM_Int_eh_sjlj_setjmp_nofp	= 303,
    ARM_Int_eh_sjlj_setup_dispatch	= 304,
    ARM_JUMPTABLE_ADDRS	= 305,
    ARM_JUMPTABLE_INSTS	= 306,
    ARM_JUMPTABLE_TBB	= 307,
    ARM_JUMPTABLE_TBH	= 308,
    ARM_LDMIA_RET	= 309,
    ARM_LDRBT_POST	= 310,
    ARM_LDRConstPool	= 311,
    ARM_LDRHTii	= 312,
    ARM_LDRLIT_ga_abs	= 313,
    ARM_LDRLIT_ga_pcrel	= 314,
    ARM_LDRLIT_ga_pcrel_ldr	= 315,
    ARM_LDRSBTii	= 316,
    ARM_LDRSHTii	= 317,
    ARM_LDRT_POST	= 318,
    ARM_LEApcrel	= 319,
    ARM_LEApcrelJT	= 320,
    ARM_LOADDUAL	= 321,
    ARM_LSLi	= 322,
    ARM_LSLr	= 323,
    ARM_LSRi	= 324,
    ARM_LSRr	= 325,
    ARM_MEMCPY	= 326,
    ARM_MLAv5	= 327,
    ARM_MOVCCi	= 328,
    ARM_MOVCCi16	= 329,
    ARM_MOVCCi32imm	= 330,
    ARM_MOVCCr	= 331,
    ARM_MOVCCsi	= 332,
    ARM_MOVCCsr	= 333,
    ARM_MOVPCRX	= 334,
    ARM_MOVTi16_ga_pcrel	= 335,
    ARM_MOV_ga_pcrel	= 336,
    ARM_MOV_ga_pcrel_ldr	= 337,
    ARM_MOVi16_ga_pcrel	= 338,
    ARM_MOVi32imm	= 339,
    ARM_MOVsra_glue	= 340,
    ARM_MOVsrl_glue	= 341,
    ARM_MQPRCopy	= 342,
    ARM_MQQPRLoad	= 343,
    ARM_MQQPRStore	= 344,
    ARM_MQQQQPRLoad	= 345,
    ARM_MQQQQPRStore	= 346,
    ARM_MULv5	= 347,
    ARM_MVE_MEMCPYLOOPINST	= 348,
    ARM_MVE_MEMSETLOOPINST	= 349,
    ARM_MVNCCi	= 350,
    ARM_PICADD	= 351,
    ARM_PICLDR	= 352,
    ARM_PICLDRB	= 353,
    ARM_PICLDRH	= 354,
    ARM_PICLDRSB	= 355,
    ARM_PICLDRSH	= 356,
    ARM_PICSTR	= 357,
    ARM_PICSTRB	= 358,
    ARM_PICSTRH	= 359,
    ARM_RORi	= 360,
    ARM_RORr	= 361,
    ARM_RRX	= 362,
    ARM_RRXi	= 363,
    ARM_RSBSri	= 364,
    ARM_RSBSrsi	= 365,
    ARM_RSBSrsr	= 366,
    ARM_SEH_EpilogEnd	= 367,
    ARM_SEH_EpilogStart	= 368,
    ARM_SEH_Nop	= 369,
    ARM_SEH_Nop_Ret	= 370,
    ARM_SEH_PrologEnd	= 371,
    ARM_SEH_SaveFRegs	= 372,
    ARM_SEH_SaveLR	= 373,
    ARM_SEH_SaveRegs	= 374,
    ARM_SEH_SaveRegs_Ret	= 375,
    ARM_SEH_SaveSP	= 376,
    ARM_SEH_StackAlloc	= 377,
    ARM_SMLALv5	= 378,
    ARM_SMULLv5	= 379,
    ARM_SPACE	= 380,
    ARM_STOREDUAL	= 381,
    ARM_STRBT_POST	= 382,
    ARM_STRBi_preidx	= 383,
    ARM_STRBr_preidx	= 384,
    ARM_STRH_preidx	= 385,
    ARM_STRT_POST	= 386,
    ARM_STRi_preidx	= 387,
    ARM_STRr_preidx	= 388,
    ARM_SUBS_PC_LR	= 389,
    ARM_SUBSri	= 390,
    ARM_SUBSrr	= 391,
    ARM_SUBSrsi	= 392,
    ARM_SUBSrsr	= 393,
    ARM_SpeculationBarrierISBDSBEndBB	= 394,
    ARM_SpeculationBarrierSBEndBB	= 395,
    ARM_TAILJMPd	= 396,
    ARM_TAILJMPr	= 397,
    ARM_TAILJMPr4	= 398,
    ARM_TCRETURNdi	= 399,
    ARM_TCRETURNri	= 400,
    ARM_TPsoft	= 401,
    ARM_UMLALv5	= 402,
    ARM_UMULLv5	= 403,
    ARM_VLD1LNdAsm_16	= 404,
    ARM_VLD1LNdAsm_32	= 405,
    ARM_VLD1LNdAsm_8	= 406,
    ARM_VLD1LNdWB_fixed_Asm_16	= 407,
    ARM_VLD1LNdWB_fixed_Asm_32	= 408,
    ARM_VLD1LNdWB_fixed_Asm_8	= 409,
    ARM_VLD1LNdWB_register_Asm_16	= 410,
    ARM_VLD1LNdWB_register_Asm_32	= 411,
    ARM_VLD1LNdWB_register_Asm_8	= 412,
    ARM_VLD2LNdAsm_16	= 413,
    ARM_VLD2LNdAsm_32	= 414,
    ARM_VLD2LNdAsm_8	= 415,
    ARM_VLD2LNdWB_fixed_Asm_16	= 416,
    ARM_VLD2LNdWB_fixed_Asm_32	= 417,
    ARM_VLD2LNdWB_fixed_Asm_8	= 418,
    ARM_VLD2LNdWB_register_Asm_16	= 419,
    ARM_VLD2LNdWB_register_Asm_32	= 420,
    ARM_VLD2LNdWB_register_Asm_8	= 421,
    ARM_VLD2LNqAsm_16	= 422,
    ARM_VLD2LNqAsm_32	= 423,
    ARM_VLD2LNqWB_fixed_Asm_16	= 424,
    ARM_VLD2LNqWB_fixed_Asm_32	= 425,
    ARM_VLD2LNqWB_register_Asm_16	= 426,
    ARM_VLD2LNqWB_register_Asm_32	= 427,
    ARM_VLD3DUPdAsm_16	= 428,
    ARM_VLD3DUPdAsm_32	= 429,
    ARM_VLD3DUPdAsm_8	= 430,
    ARM_VLD3DUPdWB_fixed_Asm_16	= 431,
    ARM_VLD3DUPdWB_fixed_Asm_32	= 432,
    ARM_VLD3DUPdWB_fixed_Asm_8	= 433,
    ARM_VLD3DUPdWB_register_Asm_16	= 434,
    ARM_VLD3DUPdWB_register_Asm_32	= 435,
    ARM_VLD3DUPdWB_register_Asm_8	= 436,
    ARM_VLD3DUPqAsm_16	= 437,
    ARM_VLD3DUPqAsm_32	= 438,
    ARM_VLD3DUPqAsm_8	= 439,
    ARM_VLD3DUPqWB_fixed_Asm_16	= 440,
    ARM_VLD3DUPqWB_fixed_Asm_32	= 441,
    ARM_VLD3DUPqWB_fixed_Asm_8	= 442,
    ARM_VLD3DUPqWB_register_Asm_16	= 443,
    ARM_VLD3DUPqWB_register_Asm_32	= 444,
    ARM_VLD3DUPqWB_register_Asm_8	= 445,
    ARM_VLD3LNdAsm_16	= 446,
    ARM_VLD3LNdAsm_32	= 447,
    ARM_VLD3LNdAsm_8	= 448,
    ARM_VLD3LNdWB_fixed_Asm_16	= 449,
    ARM_VLD3LNdWB_fixed_Asm_32	= 450,
    ARM_VLD3LNdWB_fixed_Asm_8	= 451,
    ARM_VLD3LNdWB_register_Asm_16	= 452,
    ARM_VLD3LNdWB_register_Asm_32	= 453,
    ARM_VLD3LNdWB_register_Asm_8	= 454,
    ARM_VLD3LNqAsm_16	= 455,
    ARM_VLD3LNqAsm_32	= 456,
    ARM_VLD3LNqWB_fixed_Asm_16	= 457,
    ARM_VLD3LNqWB_fixed_Asm_32	= 458,
    ARM_VLD3LNqWB_register_Asm_16	= 459,
    ARM_VLD3LNqWB_register_Asm_32	= 460,
    ARM_VLD3dAsm_16	= 461,
    ARM_VLD3dAsm_32	= 462,
    ARM_VLD3dAsm_8	= 463,
    ARM_VLD3dWB_fixed_Asm_16	= 464,
    ARM_VLD3dWB_fixed_Asm_32	= 465,
    ARM_VLD3dWB_fixed_Asm_8	= 466,
    ARM_VLD3dWB_register_Asm_16	= 467,
    ARM_VLD3dWB_register_Asm_32	= 468,
    ARM_VLD3dWB_register_Asm_8	= 469,
    ARM_VLD3qAsm_16	= 470,
    ARM_VLD3qAsm_32	= 471,
    ARM_VLD3qAsm_8	= 472,
    ARM_VLD3qWB_fixed_Asm_16	= 473,
    ARM_VLD3qWB_fixed_Asm_32	= 474,
    ARM_VLD3qWB_fixed_Asm_8	= 475,
    ARM_VLD3qWB_register_Asm_16	= 476,
    ARM_VLD3qWB_register_Asm_32	= 477,
    ARM_VLD3qWB_register_Asm_8	= 478,
    ARM_VLD4DUPdAsm_16	= 479,
    ARM_VLD4DUPdAsm_32	= 480,
    ARM_VLD4DUPdAsm_8	= 481,
    ARM_VLD4DUPdWB_fixed_Asm_16	= 482,
    ARM_VLD4DUPdWB_fixed_Asm_32	= 483,
    ARM_VLD4DUPdWB_fixed_Asm_8	= 484,
    ARM_VLD4DUPdWB_register_Asm_16	= 485,
    ARM_VLD4DUPdWB_register_Asm_32	= 486,
    ARM_VLD4DUPdWB_register_Asm_8	= 487,
    ARM_VLD4DUPqAsm_16	= 488,
    ARM_VLD4DUPqAsm_32	= 489,
    ARM_VLD4DUPqAsm_8	= 490,
    ARM_VLD4DUPqWB_fixed_Asm_16	= 491,
    ARM_VLD4DUPqWB_fixed_Asm_32	= 492,
    ARM_VLD4DUPqWB_fixed_Asm_8	= 493,
    ARM_VLD4DUPqWB_register_Asm_16	= 494,
    ARM_VLD4DUPqWB_register_Asm_32	= 495,
    ARM_VLD4DUPqWB_register_Asm_8	= 496,
    ARM_VLD4LNdAsm_16	= 497,
    ARM_VLD4LNdAsm_32	= 498,
    ARM_VLD4LNdAsm_8	= 499,
    ARM_VLD4LNdWB_fixed_Asm_16	= 500,
    ARM_VLD4LNdWB_fixed_Asm_32	= 501,
    ARM_VLD4LNdWB_fixed_Asm_8	= 502,
    ARM_VLD4LNdWB_register_Asm_16	= 503,
    ARM_VLD4LNdWB_register_Asm_32	= 504,
    ARM_VLD4LNdWB_register_Asm_8	= 505,
    ARM_VLD4LNqAsm_16	= 506,
    ARM_VLD4LNqAsm_32	= 507,
    ARM_VLD4LNqWB_fixed_Asm_16	= 508,
    ARM_VLD4LNqWB_fixed_Asm_32	= 509,
    ARM_VLD4LNqWB_register_Asm_16	= 510,
    ARM_VLD4LNqWB_register_Asm_32	= 511,
    ARM_VLD4dAsm_16	= 512,
    ARM_VLD4dAsm_32	= 513,
    ARM_VLD4dAsm_8	= 514,
    ARM_VLD4dWB_fixed_Asm_16	= 515,
    ARM_VLD4dWB_fixed_Asm_32	= 516,
    ARM_VLD4dWB_fixed_Asm_8	= 517,
    ARM_VLD4dWB_register_Asm_16	= 518,
    ARM_VLD4dWB_register_Asm_32	= 519,
    ARM_VLD4dWB_register_Asm_8	= 520,
    ARM_VLD4qAsm_16	= 521,
    ARM_VLD4qAsm_32	= 522,
    ARM_VLD4qAsm_8	= 523,
    ARM_VLD4qWB_fixed_Asm_16	= 524,
    ARM_VLD4qWB_fixed_Asm_32	= 525,
    ARM_VLD4qWB_fixed_Asm_8	= 526,
    ARM_VLD4qWB_register_Asm_16	= 527,
    ARM_VLD4qWB_register_Asm_32	= 528,
    ARM_VLD4qWB_register_Asm_8	= 529,
    ARM_VMOVD0	= 530,
    ARM_VMOVDcc	= 531,
    ARM_VMOVHcc	= 532,
    ARM_VMOVQ0	= 533,
    ARM_VMOVScc	= 534,
    ARM_VST1LNdAsm_16	= 535,
    ARM_VST1LNdAsm_32	= 536,
    ARM_VST1LNdAsm_8	= 537,
    ARM_VST1LNdWB_fixed_Asm_16	= 538,
    ARM_VST1LNdWB_fixed_Asm_32	= 539,
    ARM_VST1LNdWB_fixed_Asm_8	= 540,
    ARM_VST1LNdWB_register_Asm_16	= 541,
    ARM_VST1LNdWB_register_Asm_32	= 542,
    ARM_VST1LNdWB_register_Asm_8	= 543,
    ARM_VST2LNdAsm_16	= 544,
    ARM_VST2LNdAsm_32	= 545,
    ARM_VST2LNdAsm_8	= 546,
    ARM_VST2LNdWB_fixed_Asm_16	= 547,
    ARM_VST2LNdWB_fixed_Asm_32	= 548,
    ARM_VST2LNdWB_fixed_Asm_8	= 549,
    ARM_VST2LNdWB_register_Asm_16	= 550,
    ARM_VST2LNdWB_register_Asm_32	= 551,
    ARM_VST2LNdWB_register_Asm_8	= 552,
    ARM_VST2LNqAsm_16	= 553,
    ARM_VST2LNqAsm_32	= 554,
    ARM_VST2LNqWB_fixed_Asm_16	= 555,
    ARM_VST2LNqWB_fixed_Asm_32	= 556,
    ARM_VST2LNqWB_register_Asm_16	= 557,
    ARM_VST2LNqWB_register_Asm_32	= 558,
    ARM_VST3LNdAsm_16	= 559,
    ARM_VST3LNdAsm_32	= 560,
    ARM_VST3LNdAsm_8	= 561,
    ARM_VST3LNdWB_fixed_Asm_16	= 562,
    ARM_VST3LNdWB_fixed_Asm_32	= 563,
    ARM_VST3LNdWB_fixed_Asm_8	= 564,
    ARM_VST3LNdWB_register_Asm_16	= 565,
    ARM_VST3LNdWB_register_Asm_32	= 566,
    ARM_VST3LNdWB_register_Asm_8	= 567,
    ARM_VST3LNqAsm_16	= 568,
    ARM_VST3LNqAsm_32	= 569,
    ARM_VST3LNqWB_fixed_Asm_16	= 570,
    ARM_VST3LNqWB_fixed_Asm_32	= 571,
    ARM_VST3LNqWB_register_Asm_16	= 572,
    ARM_VST3LNqWB_register_Asm_32	= 573,
    ARM_VST3dAsm_16	= 574,
    ARM_VST3dAsm_32	= 575,
    ARM_VST3dAsm_8	= 576,
    ARM_VST3dWB_fixed_Asm_16	= 577,
    ARM_VST3dWB_fixed_Asm_32	= 578,
    ARM_VST3dWB_fixed_Asm_8	= 579,
    ARM_VST3dWB_register_Asm_16	= 580,
    ARM_VST3dWB_register_Asm_32	= 581,
    ARM_VST3dWB_register_Asm_8	= 582,
    ARM_VST3qAsm_16	= 583,
    ARM_VST3qAsm_32	= 584,
    ARM_VST3qAsm_8	= 585,
    ARM_VST3qWB_fixed_Asm_16	= 586,
    ARM_VST3qWB_fixed_Asm_32	= 587,
    ARM_VST3qWB_fixed_Asm_8	= 588,
    ARM_VST3qWB_register_Asm_16	= 589,
    ARM_VST3qWB_register_Asm_32	= 590,
    ARM_VST3qWB_register_Asm_8	= 591,
    ARM_VST4LNdAsm_16	= 592,
    ARM_VST4LNdAsm_32	= 593,
    ARM_VST4LNdAsm_8	= 594,
    ARM_VST4LNdWB_fixed_Asm_16	= 595,
    ARM_VST4LNdWB_fixed_Asm_32	= 596,
    ARM_VST4LNdWB_fixed_Asm_8	= 597,
    ARM_VST4LNdWB_register_Asm_16	= 598,
    ARM_VST4LNdWB_register_Asm_32	= 599,
    ARM_VST4LNdWB_register_Asm_8	= 600,
    ARM_VST4LNqAsm_16	= 601,
    ARM_VST4LNqAsm_32	= 602,
    ARM_VST4LNqWB_fixed_Asm_16	= 603,
    ARM_VST4LNqWB_fixed_Asm_32	= 604,
    ARM_VST4LNqWB_register_Asm_16	= 605,
    ARM_VST4LNqWB_register_Asm_32	= 606,
    ARM_VST4dAsm_16	= 607,
    ARM_VST4dAsm_32	= 608,
    ARM_VST4dAsm_8	= 609,
    ARM_VST4dWB_fixed_Asm_16	= 610,
    ARM_VST4dWB_fixed_Asm_32	= 611,
    ARM_VST4dWB_fixed_Asm_8	= 612,
    ARM_VST4dWB_register_Asm_16	= 613,
    ARM_VST4dWB_register_Asm_32	= 614,
    ARM_VST4dWB_register_Asm_8	= 615,
    ARM_VST4qAsm_16	= 616,
    ARM_VST4qAsm_32	= 617,
    ARM_VST4qAsm_8	= 618,
    ARM_VST4qWB_fixed_Asm_16	= 619,
    ARM_VST4qWB_fixed_Asm_32	= 620,
    ARM_VST4qWB_fixed_Asm_8	= 621,
    ARM_VST4qWB_register_Asm_16	= 622,
    ARM_VST4qWB_register_Asm_32	= 623,
    ARM_VST4qWB_register_Asm_8	= 624,
    ARM_WIN__CHKSTK	= 625,
    ARM_WIN__DBZCHK	= 626,
    ARM_t2ABS	= 627,
    ARM_t2ADDSri	= 628,
    ARM_t2ADDSrr	= 629,
    ARM_t2ADDSrs	= 630,
    ARM_t2BF_LabelPseudo	= 631,
    ARM_t2BR_JT	= 632,
    ARM_t2CALL_BTI	= 633,
    ARM_t2DoLoopStart	= 634,
    ARM_t2DoLoopStartTP	= 635,
    ARM_t2LDMIA_RET	= 636,
    ARM_t2LDRB_OFFSET_imm	= 637,
    ARM_t2LDRB_POST_imm	= 638,
    ARM_t2LDRB_PRE_imm	= 639,
    ARM_t2LDRBpcrel	= 640,
    ARM_t2LDRConstPool	= 641,
    ARM_t2LDRH_OFFSET_imm	= 642,
    ARM_t2LDRH_POST_imm	= 643,
    ARM_t2LDRH_PRE_imm	= 644,
    ARM_t2LDRHpcrel	= 645,
    ARM_t2LDRLIT_ga_pcrel	= 646,
    ARM_t2LDRSB_OFFSET_imm	= 647,
    ARM_t2LDRSB_POST_imm	= 648,
    ARM_t2LDRSB_PRE_imm	= 649,
    ARM_t2LDRSBpcrel	= 650,
    ARM_t2LDRSH_OFFSET_imm	= 651,
    ARM_t2LDRSH_POST_imm	= 652,
    ARM_t2LDRSH_PRE_imm	= 653,
    ARM_t2LDRSHpcrel	= 654,
    ARM_t2LDR_POST_imm	= 655,
    ARM_t2LDR_PRE_imm	= 656,
    ARM_t2LDRpci_pic	= 657,
    ARM_t2LDRpcrel	= 658,
    ARM_t2LEApcrel	= 659,
    ARM_t2LEApcrelJT	= 660,
    ARM_t2LoopDec	= 661,
    ARM_t2LoopEnd	= 662,
    ARM_t2LoopEndDec	= 663,
    ARM_t2MOVCCasr	= 664,
    ARM_t2MOVCCi	= 665,
    ARM_t2MOVCCi16	= 666,
    ARM_t2MOVCCi32imm	= 667,
    ARM_t2MOVCClsl	= 668,
    ARM_t2MOVCClsr	= 669,
    ARM_t2MOVCCr	= 670,
    ARM_t2MOVCCror	= 671,
    ARM_t2MOVSsi	= 672,
    ARM_t2MOVSsr	= 673,
    ARM_t2MOVTi16_ga_pcrel	= 674,
    ARM_t2MOV_ga_pcrel	= 675,
    ARM_t2MOVi16_ga_pcrel	= 676,
    ARM_t2MOVi32imm	= 677,
    ARM_t2MOVsi	= 678,
    ARM_t2MOVsr	= 679,
    ARM_t2MVNCCi	= 680,
    ARM_t2RSBSri	= 681,
    ARM_t2RSBSrs	= 682,
    ARM_t2STRB_OFFSET_imm	= 683,
    ARM_t2STRB_POST_imm	= 684,
    ARM_t2STRB_PRE_imm	= 685,
    ARM_t2STRB_preidx	= 686,
    ARM_t2STRH_OFFSET_imm	= 687,
    ARM_t2STRH_POST_imm	= 688,
    ARM_t2STRH_PRE_imm	= 689,
    ARM_t2STRH_preidx	= 690,
    ARM_t2STR_POST_imm	= 691,
    ARM_t2STR_PRE_imm	= 692,
    ARM_t2STR_preidx	= 693,
    ARM_t2SUBSri	= 694,
    ARM_t2SUBSrr	= 695,
    ARM_t2SUBSrs	= 696,
    ARM_t2SpeculationBarrierISBDSBEndBB	= 697,
    ARM_t2SpeculationBarrierSBEndBB	= 698,
    ARM_t2TBB_JT	= 699,
    ARM_t2TBH_JT	= 700,
    ARM_t2WhileLoopSetup	= 701,
    ARM_t2WhileLoopStart	= 702,
    ARM_t2WhileLoopStartLR	= 703,
    ARM_t2WhileLoopStartTP	= 704,
    ARM_tADCS	= 705,
    ARM_tADDSi3	= 706,
    ARM_tADDSi8	= 707,
    ARM_tADDSrr	= 708,
    ARM_tADDframe	= 709,
    ARM_tADJCALLSTACKDOWN	= 710,
    ARM_tADJCALLSTACKUP	= 711,
    ARM_tBLXNS_CALL	= 712,
    ARM_tBLXr_noip	= 713,
    ARM_tBL_PUSHLR	= 714,
    ARM_tBRIND	= 715,
    ARM_tBR_JTr	= 716,
    ARM_tBXNS_RET	= 717,
    ARM_tBX_CALL	= 718,
    ARM_tBX_RET	= 719,
    ARM_tBX_RET_vararg	= 720,
    ARM_tBfar	= 721,
    ARM_tCMP_SWAP_16	= 722,
    ARM_tCMP_SWAP_32	= 723,
    ARM_tCMP_SWAP_8	= 724,
    ARM_tLDMIA_UPD	= 725,
    ARM_tLDRConstPool	= 726,
    ARM_tLDRLIT_ga_abs	= 727,
    ARM_tLDRLIT_ga_pcrel	= 728,
    ARM_tLDR_postidx	= 729,
    ARM_tLDRpci_pic	= 730,
    ARM_tLEApcrel	= 731,
    ARM_tLEApcrelJT	= 732,
    ARM_tLSLSri	= 733,
    ARM_tMOVCCr_pseudo	= 734,
    ARM_tMOVi32imm	= 735,
    ARM_tPOP_RET	= 736,
    ARM_tRSBS	= 737,
    ARM_tSBCS	= 738,
    ARM_tSUBSi3	= 739,
    ARM_tSUBSi8	= 740,
    ARM_tSUBSrr	= 741,
    ARM_tTAILJMPd	= 742,
    ARM_tTAILJMPdND	= 743,
    ARM_tTAILJMPr	= 744,
    ARM_tTBB_JT	= 745,
    ARM_tTBH_JT	= 746,
    ARM_tTPsoft	= 747,
    ARM_ADCri	= 748,
    ARM_ADCrr	= 749,
    ARM_ADCrsi	= 750,
    ARM_ADCrsr	= 751,
    ARM_ADDri	= 752,
    ARM_ADDrr	= 753,
    ARM_ADDrsi	= 754,
    ARM_ADDrsr	= 755,
    ARM_ADR	= 756,
    ARM_AESD	= 757,
    ARM_AESE	= 758,
    ARM_AESIMC	= 759,
    ARM_AESMC	= 760,
    ARM_ANDri	= 761,
    ARM_ANDrr	= 762,
    ARM_ANDrsi	= 763,
    ARM_ANDrsr	= 764,
    ARM_BF16VDOTI_VDOTD	= 765,
    ARM_BF16VDOTI_VDOTQ	= 766,
    ARM_BF16VDOTS_VDOTD	= 767,
    ARM_BF16VDOTS_VDOTQ	= 768,
    ARM_BF16_VCVT	= 769,
    ARM_BF16_VCVTB	= 770,
    ARM_BF16_VCVTT	= 771,
    ARM_BFC	= 772,
    ARM_BFI	= 773,
    ARM_BICri	= 774,
    ARM_BICrr	= 775,
    ARM_BICrsi	= 776,
    ARM_BICrsr	= 777,
    ARM_BKPT	= 778,
    ARM_BL	= 779,
    ARM_BLX	= 780,
    ARM_BLX_pred	= 781,
    ARM_BLXi	= 782,
    ARM_BL_pred	= 783,
    ARM_BX	= 784,
    ARM_BXJ	= 785,
    ARM_BX_RET	= 786,
    ARM_BX_pred	= 787,
    ARM_Bcc	= 788,
    ARM_CDE_CX1	= 789,
    ARM_CDE_CX1A	= 790,
    ARM_CDE_CX1D	= 791,
    ARM_CDE_CX1DA	= 792,
    ARM_CDE_CX2	= 793,
    ARM_CDE_CX2A	= 794,
    ARM_CDE_CX2D	= 795,
    ARM_CDE_CX2DA	= 796,
    ARM_CDE_CX3	= 797,
    ARM_CDE_CX3A	= 798,
    ARM_CDE_CX3D	= 799,
    ARM_CDE_CX3DA	= 800,
    ARM_CDE_VCX1A_fpdp	= 801,
    ARM_CDE_VCX1A_fpsp	= 802,
    ARM_CDE_VCX1A_vec	= 803,
    ARM_CDE_VCX1_fpdp	= 804,
    ARM_CDE_VCX1_fpsp	= 805,
    ARM_CDE_VCX1_vec	= 806,
    ARM_CDE_VCX2A_fpdp	= 807,
    ARM_CDE_VCX2A_fpsp	= 808,
    ARM_CDE_VCX2A_vec	= 809,
    ARM_CDE_VCX2_fpdp	= 810,
    ARM_CDE_VCX2_fpsp	= 811,
    ARM_CDE_VCX2_vec	= 812,
    ARM_CDE_VCX3A_fpdp	= 813,
    ARM_CDE_VCX3A_fpsp	= 814,
    ARM_CDE_VCX3A_vec	= 815,
    ARM_CDE_VCX3_fpdp	= 816,
    ARM_CDE_VCX3_fpsp	= 817,
    ARM_CDE_VCX3_vec	= 818,
    ARM_CDP	= 819,
    ARM_CDP2	= 820,
    ARM_CLREX	= 821,
    ARM_CLZ	= 822,
    ARM_CMNri	= 823,
    ARM_CMNzrr	= 824,
    ARM_CMNzrsi	= 825,
    ARM_CMNzrsr	= 826,
    ARM_CMPri	= 827,
    ARM_CMPrr	= 828,
    ARM_CMPrsi	= 829,
    ARM_CMPrsr	= 830,
    ARM_CPS1p	= 831,
    ARM_CPS2p	= 832,
    ARM_CPS3p	= 833,
    ARM_CRC32B	= 834,
    ARM_CRC32CB	= 835,
    ARM_CRC32CH	= 836,
    ARM_CRC32CW	= 837,
    ARM_CRC32H	= 838,
    ARM_CRC32W	= 839,
    ARM_DBG	= 840,
    ARM_DMB	= 841,
    ARM_DSB	= 842,
    ARM_EORri	= 843,
    ARM_EORrr	= 844,
    ARM_EORrsi	= 845,
    ARM_EORrsr	= 846,
    ARM_ERET	= 847,
    ARM_FCONSTD	= 848,
    ARM_FCONSTH	= 849,
    ARM_FCONSTS	= 850,
    ARM_FLDMXDB_UPD	= 851,
    ARM_FLDMXIA	= 852,
    ARM_FLDMXIA_UPD	= 853,
    ARM_FMSTAT	= 854,
    ARM_FSTMXDB_UPD	= 855,
    ARM_FSTMXIA	= 856,
    ARM_FSTMXIA_UPD	= 857,
    ARM_HINT	= 858,
    ARM_HLT	= 859,
    ARM_HVC	= 860,
    ARM_ISB	= 861,
    ARM_LDA	= 862,
    ARM_LDAB	= 863,
    ARM_LDAEX	= 864,
    ARM_LDAEXB	= 865,
    ARM_LDAEXD	= 866,
    ARM_LDAEXH	= 867,
    ARM_LDAH	= 868,
    ARM_LDC2L_OFFSET	= 869,
    ARM_LDC2L_OPTION	= 870,
    ARM_LDC2L_POST	= 871,
    ARM_LDC2L_PRE	= 872,
    ARM_LDC2_OFFSET	= 873,
    ARM_LDC2_OPTION	= 874,
    ARM_LDC2_POST	= 875,
    ARM_LDC2_PRE	= 876,
    ARM_LDCL_OFFSET	= 877,
    ARM_LDCL_OPTION	= 878,
    ARM_LDCL_POST	= 879,
    ARM_LDCL_PRE	= 880,
    ARM_LDC_OFFSET	= 881,
    ARM_LDC_OPTION	= 882,
    ARM_LDC_POST	= 883,
    ARM_LDC_PRE	= 884,
    ARM_LDMDA	= 885,
    ARM_LDMDA_UPD	= 886,
    ARM_LDMDB	= 887,
    ARM_LDMDB_UPD	= 888,
    ARM_LDMIA	= 889,
    ARM_LDMIA_UPD	= 890,
    ARM_LDMIB	= 891,
    ARM_LDMIB_UPD	= 892,
    ARM_LDRBT_POST_IMM	= 893,
    ARM_LDRBT_POST_REG	= 894,
    ARM_LDRB_POST_IMM	= 895,
    ARM_LDRB_POST_REG	= 896,
    ARM_LDRB_PRE_IMM	= 897,
    ARM_LDRB_PRE_REG	= 898,
    ARM_LDRBi12	= 899,
    ARM_LDRBrs	= 900,
    ARM_LDRD	= 901,
    ARM_LDRD_POST	= 902,
    ARM_LDRD_PRE	= 903,
    ARM_LDREX	= 904,
    ARM_LDREXB	= 905,
    ARM_LDREXD	= 906,
    ARM_LDREXH	= 907,
    ARM_LDRH	= 908,
    ARM_LDRHTi	= 909,
    ARM_LDRHTr	= 910,
    ARM_LDRH_POST	= 911,
    ARM_LDRH_PRE	= 912,
    ARM_LDRSB	= 913,
    ARM_LDRSBTi	= 914,
    ARM_LDRSBTr	= 915,
    ARM_LDRSB_POST	= 916,
    ARM_LDRSB_PRE	= 917,
    ARM_LDRSH	= 918,
    ARM_LDRSHTi	= 919,
    ARM_LDRSHTr	= 920,
    ARM_LDRSH_POST	= 921,
    ARM_LDRSH_PRE	= 922,
    ARM_LDRT_POST_IMM	= 923,
    ARM_LDRT_POST_REG	= 924,
    ARM_LDR_POST_IMM	= 925,
    ARM_LDR_POST_REG	= 926,
    ARM_LDR_PRE_IMM	= 927,
    ARM_LDR_PRE_REG	= 928,
    ARM_LDRcp	= 929,
    ARM_LDRi12	= 930,
    ARM_LDRrs	= 931,
    ARM_MCR	= 932,
    ARM_MCR2	= 933,
    ARM_MCRR	= 934,
    ARM_MCRR2	= 935,
    ARM_MLA	= 936,
    ARM_MLS	= 937,
    ARM_MOVPCLR	= 938,
    ARM_MOVTi16	= 939,
    ARM_MOVi	= 940,
    ARM_MOVi16	= 941,
    ARM_MOVr	= 942,
    ARM_MOVr_TC	= 943,
    ARM_MOVsi	= 944,
    ARM_MOVsr	= 945,
    ARM_MRC	= 946,
    ARM_MRC2	= 947,
    ARM_MRRC	= 948,
    ARM_MRRC2	= 949,
    ARM_MRS	= 950,
    ARM_MRSbanked	= 951,
    ARM_MRSsys	= 952,
    ARM_MSR	= 953,
    ARM_MSRbanked	= 954,
    ARM_MSRi	= 955,
    ARM_MUL	= 956,
    ARM_MVE_ASRLi	= 957,
    ARM_MVE_ASRLr	= 958,
    ARM_MVE_DLSTP_16	= 959,
    ARM_MVE_DLSTP_32	= 960,
    ARM_MVE_DLSTP_64	= 961,
    ARM_MVE_DLSTP_8	= 962,
    ARM_MVE_LCTP	= 963,
    ARM_MVE_LETP	= 964,
    ARM_MVE_LSLLi	= 965,
    ARM_MVE_LSLLr	= 966,
    ARM_MVE_LSRL	= 967,
    ARM_MVE_SQRSHR	= 968,
    ARM_MVE_SQRSHRL	= 969,
    ARM_MVE_SQSHL	= 970,
    ARM_MVE_SQSHLL	= 971,
    ARM_MVE_SRSHR	= 972,
    ARM_MVE_SRSHRL	= 973,
    ARM_MVE_UQRSHL	= 974,
    ARM_MVE_UQRSHLL	= 975,
    ARM_MVE_UQSHL	= 976,
    ARM_MVE_UQSHLL	= 977,
    ARM_MVE_URSHR	= 978,
    ARM_MVE_URSHRL	= 979,
    ARM_MVE_VABAVs16	= 980,
    ARM_MVE_VABAVs32	= 981,
    ARM_MVE_VABAVs8	= 982,
    ARM_MVE_VABAVu16	= 983,
    ARM_MVE_VABAVu32	= 984,
    ARM_MVE_VABAVu8	= 985,
    ARM_MVE_VABDf16	= 986,
    ARM_MVE_VABDf32	= 987,
    ARM_MVE_VABDs16	= 988,
    ARM_MVE_VABDs32	= 989,
    ARM_MVE_VABDs8	= 990,
    ARM_MVE_VABDu16	= 991,
    ARM_MVE_VABDu32	= 992,
    ARM_MVE_VABDu8	= 993,
    ARM_MVE_VABSf16	= 994,
    ARM_MVE_VABSf32	= 995,
    ARM_MVE_VABSs16	= 996,
    ARM_MVE_VABSs32	= 997,
    ARM_MVE_VABSs8	= 998,
    ARM_MVE_VADC	= 999,
    ARM_MVE_VADCI	= 1000,
    ARM_MVE_VADDLVs32acc	= 1001,
    ARM_MVE_VADDLVs32no_acc	= 1002,
    ARM_MVE_VADDLVu32acc	= 1003,
    ARM_MVE_VADDLVu32no_acc	= 1004,
    ARM_MVE_VADDVs16acc	= 1005,
    ARM_MVE_VADDVs16no_acc	= 1006,
    ARM_MVE_VADDVs32acc	= 1007,
    ARM_MVE_VADDVs32no_acc	= 1008,
    ARM_MVE_VADDVs8acc	= 1009,
    ARM_MVE_VADDVs8no_acc	= 1010,
    ARM_MVE_VADDVu16acc	= 1011,
    ARM_MVE_VADDVu16no_acc	= 1012,
    ARM_MVE_VADDVu32acc	= 1013,
    ARM_MVE_VADDVu32no_acc	= 1014,
    ARM_MVE_VADDVu8acc	= 1015,
    ARM_MVE_VADDVu8no_acc	= 1016,
    ARM_MVE_VADD_qr_f16	= 1017,
    ARM_MVE_VADD_qr_f32	= 1018,
    ARM_MVE_VADD_qr_i16	= 1019,
    ARM_MVE_VADD_qr_i32	= 1020,
    ARM_MVE_VADD_qr_i8	= 1021,
    ARM_MVE_VADDf16	= 1022,
    ARM_MVE_VADDf32	= 1023,
    ARM_MVE_VADDi16	= 1024,
    ARM_MVE_VADDi32	= 1025,
    ARM_MVE_VADDi8	= 1026,
    ARM_MVE_VAND	= 1027,
    ARM_MVE_VBIC	= 1028,
    ARM_MVE_VBICimmi16	= 1029,
    ARM_MVE_VBICimmi32	= 1030,
    ARM_MVE_VBRSR16	= 1031,
    ARM_MVE_VBRSR32	= 1032,
    ARM_MVE_VBRSR8	= 1033,
    ARM_MVE_VCADDf16	= 1034,
    ARM_MVE_VCADDf32	= 1035,
    ARM_MVE_VCADDi16	= 1036,
    ARM_MVE_VCADDi32	= 1037,
    ARM_MVE_VCADDi8	= 1038,
    ARM_MVE_VCLSs16	= 1039,
    ARM_MVE_VCLSs32	= 1040,
    ARM_MVE_VCLSs8	= 1041,
    ARM_MVE_VCLZs16	= 1042,
    ARM_MVE_VCLZs32	= 1043,
    ARM_MVE_VCLZs8	= 1044,
    ARM_MVE_VCMLAf16	= 1045,
    ARM_MVE_VCMLAf32	= 1046,
    ARM_MVE_VCMPf16	= 1047,
    ARM_MVE_VCMPf16r	= 1048,
    ARM_MVE_VCMPf32	= 1049,
    ARM_MVE_VCMPf32r	= 1050,
    ARM_MVE_VCMPi16	= 1051,
    ARM_MVE_VCMPi16r	= 1052,
    ARM_MVE_VCMPi32	= 1053,
    ARM_MVE_VCMPi32r	= 1054,
    ARM_MVE_VCMPi8	= 1055,
    ARM_MVE_VCMPi8r	= 1056,
    ARM_MVE_VCMPs16	= 1057,
    ARM_MVE_VCMPs16r	= 1058,
    ARM_MVE_VCMPs32	= 1059,
    ARM_MVE_VCMPs32r	= 1060,
    ARM_MVE_VCMPs8	= 1061,
    ARM_MVE_VCMPs8r	= 1062,
    ARM_MVE_VCMPu16	= 1063,
    ARM_MVE_VCMPu16r	= 1064,
    ARM_MVE_VCMPu32	= 1065,
    ARM_MVE_VCMPu32r	= 1066,
    ARM_MVE_VCMPu8	= 1067,
    ARM_MVE_VCMPu8r	= 1068,
    ARM_MVE_VCMULf16	= 1069,
    ARM_MVE_VCMULf32	= 1070,
    ARM_MVE_VCTP16	= 1071,
    ARM_MVE_VCTP32	= 1072,
    ARM_MVE_VCTP64	= 1073,
    ARM_MVE_VCTP8	= 1074,
    ARM_MVE_VCVTf16f32bh	= 1075,
    ARM_MVE_VCVTf16f32th	= 1076,
    ARM_MVE_VCVTf16s16_fix	= 1077,
    ARM_MVE_VCVTf16s16n	= 1078,
    ARM_MVE_VCVTf16u16_fix	= 1079,
    ARM_MVE_VCVTf16u16n	= 1080,
    ARM_MVE_VCVTf32f16bh	= 1081,
    ARM_MVE_VCVTf32f16th	= 1082,
    ARM_MVE_VCVTf32s32_fix	= 1083,
    ARM_MVE_VCVTf32s32n	= 1084,
    ARM_MVE_VCVTf32u32_fix	= 1085,
    ARM_MVE_VCVTf32u32n	= 1086,
    ARM_MVE_VCVTs16f16_fix	= 1087,
    ARM_MVE_VCVTs16f16a	= 1088,
    ARM_MVE_VCVTs16f16m	= 1089,
    ARM_MVE_VCVTs16f16n	= 1090,
    ARM_MVE_VCVTs16f16p	= 1091,
    ARM_MVE_VCVTs16f16z	= 1092,
    ARM_MVE_VCVTs32f32_fix	= 1093,
    ARM_MVE_VCVTs32f32a	= 1094,
    ARM_MVE_VCVTs32f32m	= 1095,
    ARM_MVE_VCVTs32f32n	= 1096,
    ARM_MVE_VCVTs32f32p	= 1097,
    ARM_MVE_VCVTs32f32z	= 1098,
    ARM_MVE_VCVTu16f16_fix	= 1099,
    ARM_MVE_VCVTu16f16a	= 1100,
    ARM_MVE_VCVTu16f16m	= 1101,
    ARM_MVE_VCVTu16f16n	= 1102,
    ARM_MVE_VCVTu16f16p	= 1103,
    ARM_MVE_VCVTu16f16z	= 1104,
    ARM_MVE_VCVTu32f32_fix	= 1105,
    ARM_MVE_VCVTu32f32a	= 1106,
    ARM_MVE_VCVTu32f32m	= 1107,
    ARM_MVE_VCVTu32f32n	= 1108,
    ARM_MVE_VCVTu32f32p	= 1109,
    ARM_MVE_VCVTu32f32z	= 1110,
    ARM_MVE_VDDUPu16	= 1111,
    ARM_MVE_VDDUPu32	= 1112,
    ARM_MVE_VDDUPu8	= 1113,
    ARM_MVE_VDUP16	= 1114,
    ARM_MVE_VDUP32	= 1115,
    ARM_MVE_VDUP8	= 1116,
    ARM_MVE_VDWDUPu16	= 1117,
    ARM_MVE_VDWDUPu32	= 1118,
    ARM_MVE_VDWDUPu8	= 1119,
    ARM_MVE_VEOR	= 1120,
    ARM_MVE_VFMA_qr_Sf16	= 1121,
    ARM_MVE_VFMA_qr_Sf32	= 1122,
    ARM_MVE_VFMA_qr_f16	= 1123,
    ARM_MVE_VFMA_qr_f32	= 1124,
    ARM_MVE_VFMAf16	= 1125,
    ARM_MVE_VFMAf32	= 1126,
    ARM_MVE_VFMSf16	= 1127,
    ARM_MVE_VFMSf32	= 1128,
    ARM_MVE_VHADD_qr_s16	= 1129,
    ARM_MVE_VHADD_qr_s32	= 1130,
    ARM_MVE_VHADD_qr_s8	= 1131,
    ARM_MVE_VHADD_qr_u16	= 1132,
    ARM_MVE_VHADD_qr_u32	= 1133,
    ARM_MVE_VHADD_qr_u8	= 1134,
    ARM_MVE_VHADDs16	= 1135,
    ARM_MVE_VHADDs32	= 1136,
    ARM_MVE_VHADDs8	= 1137,
    ARM_MVE_VHADDu16	= 1138,
    ARM_MVE_VHADDu32	= 1139,
    ARM_MVE_VHADDu8	= 1140,
    ARM_MVE_VHCADDs16	= 1141,
    ARM_MVE_VHCADDs32	= 1142,
    ARM_MVE_VHCADDs8	= 1143,
    ARM_MVE_VHSUB_qr_s16	= 1144,
    ARM_MVE_VHSUB_qr_s32	= 1145,
    ARM_MVE_VHSUB_qr_s8	= 1146,
    ARM_MVE_VHSUB_qr_u16	= 1147,
    ARM_MVE_VHSUB_qr_u32	= 1148,
    ARM_MVE_VHSUB_qr_u8	= 1149,
    ARM_MVE_VHSUBs16	= 1150,
    ARM_MVE_VHSUBs32	= 1151,
    ARM_MVE_VHSUBs8	= 1152,
    ARM_MVE_VHSUBu16	= 1153,
    ARM_MVE_VHSUBu32	= 1154,
    ARM_MVE_VHSUBu8	= 1155,
    ARM_MVE_VIDUPu16	= 1156,
    ARM_MVE_VIDUPu32	= 1157,
    ARM_MVE_VIDUPu8	= 1158,
    ARM_MVE_VIWDUPu16	= 1159,
    ARM_MVE_VIWDUPu32	= 1160,
    ARM_MVE_VIWDUPu8	= 1161,
    ARM_MVE_VLD20_16	= 1162,
    ARM_MVE_VLD20_16_wb	= 1163,
    ARM_MVE_VLD20_32	= 1164,
    ARM_MVE_VLD20_32_wb	= 1165,
    ARM_MVE_VLD20_8	= 1166,
    ARM_MVE_VLD20_8_wb	= 1167,
    ARM_MVE_VLD21_16	= 1168,
    ARM_MVE_VLD21_16_wb	= 1169,
    ARM_MVE_VLD21_32	= 1170,
    ARM_MVE_VLD21_32_wb	= 1171,
    ARM_MVE_VLD21_8	= 1172,
    ARM_MVE_VLD21_8_wb	= 1173,
    ARM_MVE_VLD40_16	= 1174,
    ARM_MVE_VLD40_16_wb	= 1175,
    ARM_MVE_VLD40_32	= 1176,
    ARM_MVE_VLD40_32_wb	= 1177,
    ARM_MVE_VLD40_8	= 1178,
    ARM_MVE_VLD40_8_wb	= 1179,
    ARM_MVE_VLD41_16	= 1180,
    ARM_MVE_VLD41_16_wb	= 1181,
    ARM_MVE_VLD41_32	= 1182,
    ARM_MVE_VLD41_32_wb	= 1183,
    ARM_MVE_VLD41_8	= 1184,
    ARM_MVE_VLD41_8_wb	= 1185,
    ARM_MVE_VLD42_16	= 1186,
    ARM_MVE_VLD42_16_wb	= 1187,
    ARM_MVE_VLD42_32	= 1188,
    ARM_MVE_VLD42_32_wb	= 1189,
    ARM_MVE_VLD42_8	= 1190,
    ARM_MVE_VLD42_8_wb	= 1191,
    ARM_MVE_VLD43_16	= 1192,
    ARM_MVE_VLD43_16_wb	= 1193,
    ARM_MVE_VLD43_32	= 1194,
    ARM_MVE_VLD43_32_wb	= 1195,
    ARM_MVE_VLD43_8	= 1196,
    ARM_MVE_VLD43_8_wb	= 1197,
    ARM_MVE_VLDRBS16	= 1198,
    ARM_MVE_VLDRBS16_post	= 1199,
    ARM_MVE_VLDRBS16_pre	= 1200,
    ARM_MVE_VLDRBS16_rq	= 1201,
    ARM_MVE_VLDRBS32	= 1202,
    ARM_MVE_VLDRBS32_post	= 1203,
    ARM_MVE_VLDRBS32_pre	= 1204,
    ARM_MVE_VLDRBS32_rq	= 1205,
    ARM_MVE_VLDRBU16	= 1206,
    ARM_MVE_VLDRBU16_post	= 1207,
    ARM_MVE_VLDRBU16_pre	= 1208,
    ARM_MVE_VLDRBU16_rq	= 1209,
    ARM_MVE_VLDRBU32	= 1210,
    ARM_MVE_VLDRBU32_post	= 1211,
    ARM_MVE_VLDRBU32_pre	= 1212,
    ARM_MVE_VLDRBU32_rq	= 1213,
    ARM_MVE_VLDRBU8	= 1214,
    ARM_MVE_VLDRBU8_post	= 1215,
    ARM_MVE_VLDRBU8_pre	= 1216,
    ARM_MVE_VLDRBU8_rq	= 1217,
    ARM_MVE_VLDRDU64_qi	= 1218,
    ARM_MVE_VLDRDU64_qi_pre	= 1219,
    ARM_MVE_VLDRDU64_rq	= 1220,
    ARM_MVE_VLDRDU64_rq_u	= 1221,
    ARM_MVE_VLDRHS32	= 1222,
    ARM_MVE_VLDRHS32_post	= 1223,
    ARM_MVE_VLDRHS32_pre	= 1224,
    ARM_MVE_VLDRHS32_rq	= 1225,
    ARM_MVE_VLDRHS32_rq_u	= 1226,
    ARM_MVE_VLDRHU16	= 1227,
    ARM_MVE_VLDRHU16_post	= 1228,
    ARM_MVE_VLDRHU16_pre	= 1229,
    ARM_MVE_VLDRHU16_rq	= 1230,
    ARM_MVE_VLDRHU16_rq_u	= 1231,
    ARM_MVE_VLDRHU32	= 1232,
    ARM_MVE_VLDRHU32_post	= 1233,
    ARM_MVE_VLDRHU32_pre	= 1234,
    ARM_MVE_VLDRHU32_rq	= 1235,
    ARM_MVE_VLDRHU32_rq_u	= 1236,
    ARM_MVE_VLDRWU32	= 1237,
    ARM_MVE_VLDRWU32_post	= 1238,
    ARM_MVE_VLDRWU32_pre	= 1239,
    ARM_MVE_VLDRWU32_qi	= 1240,
    ARM_MVE_VLDRWU32_qi_pre	= 1241,
    ARM_MVE_VLDRWU32_rq	= 1242,
    ARM_MVE_VLDRWU32_rq_u	= 1243,
    ARM_MVE_VMAXAVs16	= 1244,
    ARM_MVE_VMAXAVs32	= 1245,
    ARM_MVE_VMAXAVs8	= 1246,
    ARM_MVE_VMAXAs16	= 1247,
    ARM_MVE_VMAXAs32	= 1248,
    ARM_MVE_VMAXAs8	= 1249,
    ARM_MVE_VMAXNMAVf16	= 1250,
    ARM_MVE_VMAXNMAVf32	= 1251,
    ARM_MVE_VMAXNMAf16	= 1252,
    ARM_MVE_VMAXNMAf32	= 1253,
    ARM_MVE_VMAXNMVf16	= 1254,
    ARM_MVE_VMAXNMVf32	= 1255,
    ARM_MVE_VMAXNMf16	= 1256,
    ARM_MVE_VMAXNMf32	= 1257,
    ARM_MVE_VMAXVs16	= 1258,
    ARM_MVE_VMAXVs32	= 1259,
    ARM_MVE_VMAXVs8	= 1260,
    ARM_MVE_VMAXVu16	= 1261,
    ARM_MVE_VMAXVu32	= 1262,
    ARM_MVE_VMAXVu8	= 1263,
    ARM_MVE_VMAXs16	= 1264,
    ARM_MVE_VMAXs32	= 1265,
    ARM_MVE_VMAXs8	= 1266,
    ARM_MVE_VMAXu16	= 1267,
    ARM_MVE_VMAXu32	= 1268,
    ARM_MVE_VMAXu8	= 1269,
    ARM_MVE_VMINAVs16	= 1270,
    ARM_MVE_VMINAVs32	= 1271,
    ARM_MVE_VMINAVs8	= 1272,
    ARM_MVE_VMINAs16	= 1273,
    ARM_MVE_VMINAs32	= 1274,
    ARM_MVE_VMINAs8	= 1275,
    ARM_MVE_VMINNMAVf16	= 1276,
    ARM_MVE_VMINNMAVf32	= 1277,
    ARM_MVE_VMINNMAf16	= 1278,
    ARM_MVE_VMINNMAf32	= 1279,
    ARM_MVE_VMINNMVf16	= 1280,
    ARM_MVE_VMINNMVf32	= 1281,
    ARM_MVE_VMINNMf16	= 1282,
    ARM_MVE_VMINNMf32	= 1283,
    ARM_MVE_VMINVs16	= 1284,
    ARM_MVE_VMINVs32	= 1285,
    ARM_MVE_VMINVs8	= 1286,
    ARM_MVE_VMINVu16	= 1287,
    ARM_MVE_VMINVu32	= 1288,
    ARM_MVE_VMINVu8	= 1289,
    ARM_MVE_VMINs16	= 1290,
    ARM_MVE_VMINs32	= 1291,
    ARM_MVE_VMINs8	= 1292,
    ARM_MVE_VMINu16	= 1293,
    ARM_MVE_VMINu32	= 1294,
    ARM_MVE_VMINu8	= 1295,
    ARM_MVE_VMLADAVas16	= 1296,
    ARM_MVE_VMLADAVas32	= 1297,
    ARM_MVE_VMLADAVas8	= 1298,
    ARM_MVE_VMLADAVau16	= 1299,
    ARM_MVE_VMLADAVau32	= 1300,
    ARM_MVE_VMLADAVau8	= 1301,
    ARM_MVE_VMLADAVaxs16	= 1302,
    ARM_MVE_VMLADAVaxs32	= 1303,
    ARM_MVE_VMLADAVaxs8	= 1304,
    ARM_MVE_VMLADAVs16	= 1305,
    ARM_MVE_VMLADAVs32	= 1306,
    ARM_MVE_VMLADAVs8	= 1307,
    ARM_MVE_VMLADAVu16	= 1308,
    ARM_MVE_VMLADAVu32	= 1309,
    ARM_MVE_VMLADAVu8	= 1310,
    ARM_MVE_VMLADAVxs16	= 1311,
    ARM_MVE_VMLADAVxs32	= 1312,
    ARM_MVE_VMLADAVxs8	= 1313,
    ARM_MVE_VMLALDAVas16	= 1314,
    ARM_MVE_VMLALDAVas32	= 1315,
    ARM_MVE_VMLALDAVau16	= 1316,
    ARM_MVE_VMLALDAVau32	= 1317,
    ARM_MVE_VMLALDAVaxs16	= 1318,
    ARM_MVE_VMLALDAVaxs32	= 1319,
    ARM_MVE_VMLALDAVs16	= 1320,
    ARM_MVE_VMLALDAVs32	= 1321,
    ARM_MVE_VMLALDAVu16	= 1322,
    ARM_MVE_VMLALDAVu32	= 1323,
    ARM_MVE_VMLALDAVxs16	= 1324,
    ARM_MVE_VMLALDAVxs32	= 1325,
    ARM_MVE_VMLAS_qr_i16	= 1326,
    ARM_MVE_VMLAS_qr_i32	= 1327,
    ARM_MVE_VMLAS_qr_i8	= 1328,
    ARM_MVE_VMLA_qr_i16	= 1329,
    ARM_MVE_VMLA_qr_i32	= 1330,
    ARM_MVE_VMLA_qr_i8	= 1331,
    ARM_MVE_VMLSDAVas16	= 1332,
    ARM_MVE_VMLSDAVas32	= 1333,
    ARM_MVE_VMLSDAVas8	= 1334,
    ARM_MVE_VMLSDAVaxs16	= 1335,
    ARM_MVE_VMLSDAVaxs32	= 1336,
    ARM_MVE_VMLSDAVaxs8	= 1337,
    ARM_MVE_VMLSDAVs16	= 1338,
    ARM_MVE_VMLSDAVs32	= 1339,
    ARM_MVE_VMLSDAVs8	= 1340,
    ARM_MVE_VMLSDAVxs16	= 1341,
    ARM_MVE_VMLSDAVxs32	= 1342,
    ARM_MVE_VMLSDAVxs8	= 1343,
    ARM_MVE_VMLSLDAVas16	= 1344,
    ARM_MVE_VMLSLDAVas32	= 1345,
    ARM_MVE_VMLSLDAVaxs16	= 1346,
    ARM_MVE_VMLSLDAVaxs32	= 1347,
    ARM_MVE_VMLSLDAVs16	= 1348,
    ARM_MVE_VMLSLDAVs32	= 1349,
    ARM_MVE_VMLSLDAVxs16	= 1350,
    ARM_MVE_VMLSLDAVxs32	= 1351,
    ARM_MVE_VMOVLs16bh	= 1352,
    ARM_MVE_VMOVLs16th	= 1353,
    ARM_MVE_VMOVLs8bh	= 1354,
    ARM_MVE_VMOVLs8th	= 1355,
    ARM_MVE_VMOVLu16bh	= 1356,
    ARM_MVE_VMOVLu16th	= 1357,
    ARM_MVE_VMOVLu8bh	= 1358,
    ARM_MVE_VMOVLu8th	= 1359,
    ARM_MVE_VMOVNi16bh	= 1360,
    ARM_MVE_VMOVNi16th	= 1361,
    ARM_MVE_VMOVNi32bh	= 1362,
    ARM_MVE_VMOVNi32th	= 1363,
    ARM_MVE_VMOV_from_lane_32	= 1364,
    ARM_MVE_VMOV_from_lane_s16	= 1365,
    ARM_MVE_VMOV_from_lane_s8	= 1366,
    ARM_MVE_VMOV_from_lane_u16	= 1367,
    ARM_MVE_VMOV_from_lane_u8	= 1368,
    ARM_MVE_VMOV_q_rr	= 1369,
    ARM_MVE_VMOV_rr_q	= 1370,
    ARM_MVE_VMOV_to_lane_16	= 1371,
    ARM_MVE_VMOV_to_lane_32	= 1372,
    ARM_MVE_VMOV_to_lane_8	= 1373,
    ARM_MVE_VMOVimmf32	= 1374,
    ARM_MVE_VMOVimmi16	= 1375,
    ARM_MVE_VMOVimmi32	= 1376,
    ARM_MVE_VMOVimmi64	= 1377,
    ARM_MVE_VMOVimmi8	= 1378,
    ARM_MVE_VMULHs16	= 1379,
    ARM_MVE_VMULHs32	= 1380,
    ARM_MVE_VMULHs8	= 1381,
    ARM_MVE_VMULHu16	= 1382,
    ARM_MVE_VMULHu32	= 1383,
    ARM_MVE_VMULHu8	= 1384,
    ARM_MVE_VMULLBp16	= 1385,
    ARM_MVE_VMULLBp8	= 1386,
    ARM_MVE_VMULLBs16	= 1387,
    ARM_MVE_VMULLBs32	= 1388,
    ARM_MVE_VMULLBs8	= 1389,
    ARM_MVE_VMULLBu16	= 1390,
    ARM_MVE_VMULLBu32	= 1391,
    ARM_MVE_VMULLBu8	= 1392,
    ARM_MVE_VMULLTp16	= 1393,
    ARM_MVE_VMULLTp8	= 1394,
    ARM_MVE_VMULLTs16	= 1395,
    ARM_MVE_VMULLTs32	= 1396,
    ARM_MVE_VMULLTs8	= 1397,
    ARM_MVE_VMULLTu16	= 1398,
    ARM_MVE_VMULLTu32	= 1399,
    ARM_MVE_VMULLTu8	= 1400,
    ARM_MVE_VMUL_qr_f16	= 1401,
    ARM_MVE_VMUL_qr_f32	= 1402,
    ARM_MVE_VMUL_qr_i16	= 1403,
    ARM_MVE_VMUL_qr_i32	= 1404,
    ARM_MVE_VMUL_qr_i8	= 1405,
    ARM_MVE_VMULf16	= 1406,
    ARM_MVE_VMULf32	= 1407,
    ARM_MVE_VMULi16	= 1408,
    ARM_MVE_VMULi32	= 1409,
    ARM_MVE_VMULi8	= 1410,
    ARM_MVE_VMVN	= 1411,
    ARM_MVE_VMVNimmi16	= 1412,
    ARM_MVE_VMVNimmi32	= 1413,
    ARM_MVE_VNEGf16	= 1414,
    ARM_MVE_VNEGf32	= 1415,
    ARM_MVE_VNEGs16	= 1416,
    ARM_MVE_VNEGs32	= 1417,
    ARM_MVE_VNEGs8	= 1418,
    ARM_MVE_VORN	= 1419,
    ARM_MVE_VORR	= 1420,
    ARM_MVE_VORRimmi16	= 1421,
    ARM_MVE_VORRimmi32	= 1422,
    ARM_MVE_VPNOT	= 1423,
    ARM_MVE_VPSEL	= 1424,
    ARM_MVE_VPST	= 1425,
    ARM_MVE_VPTv16i8	= 1426,
    ARM_MVE_VPTv16i8r	= 1427,
    ARM_MVE_VPTv16s8	= 1428,
    ARM_MVE_VPTv16s8r	= 1429,
    ARM_MVE_VPTv16u8	= 1430,
    ARM_MVE_VPTv16u8r	= 1431,
    ARM_MVE_VPTv4f32	= 1432,
    ARM_MVE_VPTv4f32r	= 1433,
    ARM_MVE_VPTv4i32	= 1434,
    ARM_MVE_VPTv4i32r	= 1435,
    ARM_MVE_VPTv4s32	= 1436,
    ARM_MVE_VPTv4s32r	= 1437,
    ARM_MVE_VPTv4u32	= 1438,
    ARM_MVE_VPTv4u32r	= 1439,
    ARM_MVE_VPTv8f16	= 1440,
    ARM_MVE_VPTv8f16r	= 1441,
    ARM_MVE_VPTv8i16	= 1442,
    ARM_MVE_VPTv8i16r	= 1443,
    ARM_MVE_VPTv8s16	= 1444,
    ARM_MVE_VPTv8s16r	= 1445,
    ARM_MVE_VPTv8u16	= 1446,
    ARM_MVE_VPTv8u16r	= 1447,
    ARM_MVE_VQABSs16	= 1448,
    ARM_MVE_VQABSs32	= 1449,
    ARM_MVE_VQABSs8	= 1450,
    ARM_MVE_VQADD_qr_s16	= 1451,
    ARM_MVE_VQADD_qr_s32	= 1452,
    ARM_MVE_VQADD_qr_s8	= 1453,
    ARM_MVE_VQADD_qr_u16	= 1454,
    ARM_MVE_VQADD_qr_u32	= 1455,
    ARM_MVE_VQADD_qr_u8	= 1456,
    ARM_MVE_VQADDs16	= 1457,
    ARM_MVE_VQADDs32	= 1458,
    ARM_MVE_VQADDs8	= 1459,
    ARM_MVE_VQADDu16	= 1460,
    ARM_MVE_VQADDu32	= 1461,
    ARM_MVE_VQADDu8	= 1462,
    ARM_MVE_VQDMLADHXs16	= 1463,
    ARM_MVE_VQDMLADHXs32	= 1464,
    ARM_MVE_VQDMLADHXs8	= 1465,
    ARM_MVE_VQDMLADHs16	= 1466,
    ARM_MVE_VQDMLADHs32	= 1467,
    ARM_MVE_VQDMLADHs8	= 1468,
    ARM_MVE_VQDMLAH_qrs16	= 1469,
    ARM_MVE_VQDMLAH_qrs32	= 1470,
    ARM_MVE_VQDMLAH_qrs8	= 1471,
    ARM_MVE_VQDMLASH_qrs16	= 1472,
    ARM_MVE_VQDMLASH_qrs32	= 1473,
    ARM_MVE_VQDMLASH_qrs8	= 1474,
    ARM_MVE_VQDMLSDHXs16	= 1475,
    ARM_MVE_VQDMLSDHXs32	= 1476,
    ARM_MVE_VQDMLSDHXs8	= 1477,
    ARM_MVE_VQDMLSDHs16	= 1478,
    ARM_MVE_VQDMLSDHs32	= 1479,
    ARM_MVE_VQDMLSDHs8	= 1480,
    ARM_MVE_VQDMULH_qr_s16	= 1481,
    ARM_MVE_VQDMULH_qr_s32	= 1482,
    ARM_MVE_VQDMULH_qr_s8	= 1483,
    ARM_MVE_VQDMULHi16	= 1484,
    ARM_MVE_VQDMULHi32	= 1485,
    ARM_MVE_VQDMULHi8	= 1486,
    ARM_MVE_VQDMULL_qr_s16bh	= 1487,
    ARM_MVE_VQDMULL_qr_s16th	= 1488,
    ARM_MVE_VQDMULL_qr_s32bh	= 1489,
    ARM_MVE_VQDMULL_qr_s32th	= 1490,
    ARM_MVE_VQDMULLs16bh	= 1491,
    ARM_MVE_VQDMULLs16th	= 1492,
    ARM_MVE_VQDMULLs32bh	= 1493,
    ARM_MVE_VQDMULLs32th	= 1494,
    ARM_MVE_VQMOVNs16bh	= 1495,
    ARM_MVE_VQMOVNs16th	= 1496,
    ARM_MVE_VQMOVNs32bh	= 1497,
    ARM_MVE_VQMOVNs32th	= 1498,
    ARM_MVE_VQMOVNu16bh	= 1499,
    ARM_MVE_VQMOVNu16th	= 1500,
    ARM_MVE_VQMOVNu32bh	= 1501,
    ARM_MVE_VQMOVNu32th	= 1502,
    ARM_MVE_VQMOVUNs16bh	= 1503,
    ARM_MVE_VQMOVUNs16th	= 1504,
    ARM_MVE_VQMOVUNs32bh	= 1505,
    ARM_MVE_VQMOVUNs32th	= 1506,
    ARM_MVE_VQNEGs16	= 1507,
    ARM_MVE_VQNEGs32	= 1508,
    ARM_MVE_VQNEGs8	= 1509,
    ARM_MVE_VQRDMLADHXs16	= 1510,
    ARM_MVE_VQRDMLADHXs32	= 1511,
    ARM_MVE_VQRDMLADHXs8	= 1512,
    ARM_MVE_VQRDMLADHs16	= 1513,
    ARM_MVE_VQRDMLADHs32	= 1514,
    ARM_MVE_VQRDMLADHs8	= 1515,
    ARM_MVE_VQRDMLAH_qrs16	= 1516,
    ARM_MVE_VQRDMLAH_qrs32	= 1517,
    ARM_MVE_VQRDMLAH_qrs8	= 1518,
    ARM_MVE_VQRDMLASH_qrs16	= 1519,
    ARM_MVE_VQRDMLASH_qrs32	= 1520,
    ARM_MVE_VQRDMLASH_qrs8	= 1521,
    ARM_MVE_VQRDMLSDHXs16	= 1522,
    ARM_MVE_VQRDMLSDHXs32	= 1523,
    ARM_MVE_VQRDMLSDHXs8	= 1524,
    ARM_MVE_VQRDMLSDHs16	= 1525,
    ARM_MVE_VQRDMLSDHs32	= 1526,
    ARM_MVE_VQRDMLSDHs8	= 1527,
    ARM_MVE_VQRDMULH_qr_s16	= 1528,
    ARM_MVE_VQRDMULH_qr_s32	= 1529,
    ARM_MVE_VQRDMULH_qr_s8	= 1530,
    ARM_MVE_VQRDMULHi16	= 1531,
    ARM_MVE_VQRDMULHi32	= 1532,
    ARM_MVE_VQRDMULHi8	= 1533,
    ARM_MVE_VQRSHL_by_vecs16	= 1534,
    ARM_MVE_VQRSHL_by_vecs32	= 1535,
    ARM_MVE_VQRSHL_by_vecs8	= 1536,
    ARM_MVE_VQRSHL_by_vecu16	= 1537,
    ARM_MVE_VQRSHL_by_vecu32	= 1538,
    ARM_MVE_VQRSHL_by_vecu8	= 1539,
    ARM_MVE_VQRSHL_qrs16	= 1540,
    ARM_MVE_VQRSHL_qrs32	= 1541,
    ARM_MVE_VQRSHL_qrs8	= 1542,
    ARM_MVE_VQRSHL_qru16	= 1543,
    ARM_MVE_VQRSHL_qru32	= 1544,
    ARM_MVE_VQRSHL_qru8	= 1545,
    ARM_MVE_VQRSHRNbhs16	= 1546,
    ARM_MVE_VQRSHRNbhs32	= 1547,
    ARM_MVE_VQRSHRNbhu16	= 1548,
    ARM_MVE_VQRSHRNbhu32	= 1549,
    ARM_MVE_VQRSHRNths16	= 1550,
    ARM_MVE_VQRSHRNths32	= 1551,
    ARM_MVE_VQRSHRNthu16	= 1552,
    ARM_MVE_VQRSHRNthu32	= 1553,
    ARM_MVE_VQRSHRUNs16bh	= 1554,
    ARM_MVE_VQRSHRUNs16th	= 1555,
    ARM_MVE_VQRSHRUNs32bh	= 1556,
    ARM_MVE_VQRSHRUNs32th	= 1557,
    ARM_MVE_VQSHLU_imms16	= 1558,
    ARM_MVE_VQSHLU_imms32	= 1559,
    ARM_MVE_VQSHLU_imms8	= 1560,
    ARM_MVE_VQSHL_by_vecs16	= 1561,
    ARM_MVE_VQSHL_by_vecs32	= 1562,
    ARM_MVE_VQSHL_by_vecs8	= 1563,
    ARM_MVE_VQSHL_by_vecu16	= 1564,
    ARM_MVE_VQSHL_by_vecu32	= 1565,
    ARM_MVE_VQSHL_by_vecu8	= 1566,
    ARM_MVE_VQSHL_qrs16	= 1567,
    ARM_MVE_VQSHL_qrs32	= 1568,
    ARM_MVE_VQSHL_qrs8	= 1569,
    ARM_MVE_VQSHL_qru16	= 1570,
    ARM_MVE_VQSHL_qru32	= 1571,
    ARM_MVE_VQSHL_qru8	= 1572,
    ARM_MVE_VQSHLimms16	= 1573,
    ARM_MVE_VQSHLimms32	= 1574,
    ARM_MVE_VQSHLimms8	= 1575,
    ARM_MVE_VQSHLimmu16	= 1576,
    ARM_MVE_VQSHLimmu32	= 1577,
    ARM_MVE_VQSHLimmu8	= 1578,
    ARM_MVE_VQSHRNbhs16	= 1579,
    ARM_MVE_VQSHRNbhs32	= 1580,
    ARM_MVE_VQSHRNbhu16	= 1581,
    ARM_MVE_VQSHRNbhu32	= 1582,
    ARM_MVE_VQSHRNths16	= 1583,
    ARM_MVE_VQSHRNths32	= 1584,
    ARM_MVE_VQSHRNthu16	= 1585,
    ARM_MVE_VQSHRNthu32	= 1586,
    ARM_MVE_VQSHRUNs16bh	= 1587,
    ARM_MVE_VQSHRUNs16th	= 1588,
    ARM_MVE_VQSHRUNs32bh	= 1589,
    ARM_MVE_VQSHRUNs32th	= 1590,
    ARM_MVE_VQSUB_qr_s16	= 1591,
    ARM_MVE_VQSUB_qr_s32	= 1592,
    ARM_MVE_VQSUB_qr_s8	= 1593,
    ARM_MVE_VQSUB_qr_u16	= 1594,
    ARM_MVE_VQSUB_qr_u32	= 1595,
    ARM_MVE_VQSUB_qr_u8	= 1596,
    ARM_MVE_VQSUBs16	= 1597,
    ARM_MVE_VQSUBs32	= 1598,
    ARM_MVE_VQSUBs8	= 1599,
    ARM_MVE_VQSUBu16	= 1600,
    ARM_MVE_VQSUBu32	= 1601,
    ARM_MVE_VQSUBu8	= 1602,
    ARM_MVE_VREV16_8	= 1603,
    ARM_MVE_VREV32_16	= 1604,
    ARM_MVE_VREV32_8	= 1605,
    ARM_MVE_VREV64_16	= 1606,
    ARM_MVE_VREV64_32	= 1607,
    ARM_MVE_VREV64_8	= 1608,
    ARM_MVE_VRHADDs16	= 1609,
    ARM_MVE_VRHADDs32	= 1610,
    ARM_MVE_VRHADDs8	= 1611,
    ARM_MVE_VRHADDu16	= 1612,
    ARM_MVE_VRHADDu32	= 1613,
    ARM_MVE_VRHADDu8	= 1614,
    ARM_MVE_VRINTf16A	= 1615,
    ARM_MVE_VRINTf16M	= 1616,
    ARM_MVE_VRINTf16N	= 1617,
    ARM_MVE_VRINTf16P	= 1618,
    ARM_MVE_VRINTf16X	= 1619,
    ARM_MVE_VRINTf16Z	= 1620,
    ARM_MVE_VRINTf32A	= 1621,
    ARM_MVE_VRINTf32M	= 1622,
    ARM_MVE_VRINTf32N	= 1623,
    ARM_MVE_VRINTf32P	= 1624,
    ARM_MVE_VRINTf32X	= 1625,
    ARM_MVE_VRINTf32Z	= 1626,
    ARM_MVE_VRMLALDAVHas32	= 1627,
    ARM_MVE_VRMLALDAVHau32	= 1628,
    ARM_MVE_VRMLALDAVHaxs32	= 1629,
    ARM_MVE_VRMLALDAVHs32	= 1630,
    ARM_MVE_VRMLALDAVHu32	= 1631,
    ARM_MVE_VRMLALDAVHxs32	= 1632,
    ARM_MVE_VRMLSLDAVHas32	= 1633,
    ARM_MVE_VRMLSLDAVHaxs32	= 1634,
    ARM_MVE_VRMLSLDAVHs32	= 1635,
    ARM_MVE_VRMLSLDAVHxs32	= 1636,
    ARM_MVE_VRMULHs16	= 1637,
    ARM_MVE_VRMULHs32	= 1638,
    ARM_MVE_VRMULHs8	= 1639,
    ARM_MVE_VRMULHu16	= 1640,
    ARM_MVE_VRMULHu32	= 1641,
    ARM_MVE_VRMULHu8	= 1642,
    ARM_MVE_VRSHL_by_vecs16	= 1643,
    ARM_MVE_VRSHL_by_vecs32	= 1644,
    ARM_MVE_VRSHL_by_vecs8	= 1645,
    ARM_MVE_VRSHL_by_vecu16	= 1646,
    ARM_MVE_VRSHL_by_vecu32	= 1647,
    ARM_MVE_VRSHL_by_vecu8	= 1648,
    ARM_MVE_VRSHL_qrs16	= 1649,
    ARM_MVE_VRSHL_qrs32	= 1650,
    ARM_MVE_VRSHL_qrs8	= 1651,
    ARM_MVE_VRSHL_qru16	= 1652,
    ARM_MVE_VRSHL_qru32	= 1653,
    ARM_MVE_VRSHL_qru8	= 1654,
    ARM_MVE_VRSHRNi16bh	= 1655,
    ARM_MVE_VRSHRNi16th	= 1656,
    ARM_MVE_VRSHRNi32bh	= 1657,
    ARM_MVE_VRSHRNi32th	= 1658,
    ARM_MVE_VRSHR_imms16	= 1659,
    ARM_MVE_VRSHR_imms32	= 1660,
    ARM_MVE_VRSHR_imms8	= 1661,
    ARM_MVE_VRSHR_immu16	= 1662,
    ARM_MVE_VRSHR_immu32	= 1663,
    ARM_MVE_VRSHR_immu8	= 1664,
    ARM_MVE_VSBC	= 1665,
    ARM_MVE_VSBCI	= 1666,
    ARM_MVE_VSHLC	= 1667,
    ARM_MVE_VSHLL_imms16bh	= 1668,
    ARM_MVE_VSHLL_imms16th	= 1669,
    ARM_MVE_VSHLL_imms8bh	= 1670,
    ARM_MVE_VSHLL_imms8th	= 1671,
    ARM_MVE_VSHLL_immu16bh	= 1672,
    ARM_MVE_VSHLL_immu16th	= 1673,
    ARM_MVE_VSHLL_immu8bh	= 1674,
    ARM_MVE_VSHLL_immu8th	= 1675,
    ARM_MVE_VSHLL_lws16bh	= 1676,
    ARM_MVE_VSHLL_lws16th	= 1677,
    ARM_MVE_VSHLL_lws8bh	= 1678,
    ARM_MVE_VSHLL_lws8th	= 1679,
    ARM_MVE_VSHLL_lwu16bh	= 1680,
    ARM_MVE_VSHLL_lwu16th	= 1681,
    ARM_MVE_VSHLL_lwu8bh	= 1682,
    ARM_MVE_VSHLL_lwu8th	= 1683,
    ARM_MVE_VSHL_by_vecs16	= 1684,
    ARM_MVE_VSHL_by_vecs32	= 1685,
    ARM_MVE_VSHL_by_vecs8	= 1686,
    ARM_MVE_VSHL_by_vecu16	= 1687,
    ARM_MVE_VSHL_by_vecu32	= 1688,
    ARM_MVE_VSHL_by_vecu8	= 1689,
    ARM_MVE_VSHL_immi16	= 1690,
    ARM_MVE_VSHL_immi32	= 1691,
    ARM_MVE_VSHL_immi8	= 1692,
    ARM_MVE_VSHL_qrs16	= 1693,
    ARM_MVE_VSHL_qrs32	= 1694,
    ARM_MVE_VSHL_qrs8	= 1695,
    ARM_MVE_VSHL_qru16	= 1696,
    ARM_MVE_VSHL_qru32	= 1697,
    ARM_MVE_VSHL_qru8	= 1698,
    ARM_MVE_VSHRNi16bh	= 1699,
    ARM_MVE_VSHRNi16th	= 1700,
    ARM_MVE_VSHRNi32bh	= 1701,
    ARM_MVE_VSHRNi32th	= 1702,
    ARM_MVE_VSHR_imms16	= 1703,
    ARM_MVE_VSHR_imms32	= 1704,
    ARM_MVE_VSHR_imms8	= 1705,
    ARM_MVE_VSHR_immu16	= 1706,
    ARM_MVE_VSHR_immu32	= 1707,
    ARM_MVE_VSHR_immu8	= 1708,
    ARM_MVE_VSLIimm16	= 1709,
    ARM_MVE_VSLIimm32	= 1710,
    ARM_MVE_VSLIimm8	= 1711,
    ARM_MVE_VSRIimm16	= 1712,
    ARM_MVE_VSRIimm32	= 1713,
    ARM_MVE_VSRIimm8	= 1714,
    ARM_MVE_VST20_16	= 1715,
    ARM_MVE_VST20_16_wb	= 1716,
    ARM_MVE_VST20_32	= 1717,
    ARM_MVE_VST20_32_wb	= 1718,
    ARM_MVE_VST20_8	= 1719,
    ARM_MVE_VST20_8_wb	= 1720,
    ARM_MVE_VST21_16	= 1721,
    ARM_MVE_VST21_16_wb	= 1722,
    ARM_MVE_VST21_32	= 1723,
    ARM_MVE_VST21_32_wb	= 1724,
    ARM_MVE_VST21_8	= 1725,
    ARM_MVE_VST21_8_wb	= 1726,
    ARM_MVE_VST40_16	= 1727,
    ARM_MVE_VST40_16_wb	= 1728,
    ARM_MVE_VST40_32	= 1729,
    ARM_MVE_VST40_32_wb	= 1730,
    ARM_MVE_VST40_8	= 1731,
    ARM_MVE_VST40_8_wb	= 1732,
    ARM_MVE_VST41_16	= 1733,
    ARM_MVE_VST41_16_wb	= 1734,
    ARM_MVE_VST41_32	= 1735,
    ARM_MVE_VST41_32_wb	= 1736,
    ARM_MVE_VST41_8	= 1737,
    ARM_MVE_VST41_8_wb	= 1738,
    ARM_MVE_VST42_16	= 1739,
    ARM_MVE_VST42_16_wb	= 1740,
    ARM_MVE_VST42_32	= 1741,
    ARM_MVE_VST42_32_wb	= 1742,
    ARM_MVE_VST42_8	= 1743,
    ARM_MVE_VST42_8_wb	= 1744,
    ARM_MVE_VST43_16	= 1745,
    ARM_MVE_VST43_16_wb	= 1746,
    ARM_MVE_VST43_32	= 1747,
    ARM_MVE_VST43_32_wb	= 1748,
    ARM_MVE_VST43_8	= 1749,
    ARM_MVE_VST43_8_wb	= 1750,
    ARM_MVE_VSTRB16	= 1751,
    ARM_MVE_VSTRB16_post	= 1752,
    ARM_MVE_VSTRB16_pre	= 1753,
    ARM_MVE_VSTRB16_rq	= 1754,
    ARM_MVE_VSTRB32	= 1755,
    ARM_MVE_VSTRB32_post	= 1756,
    ARM_MVE_VSTRB32_pre	= 1757,
    ARM_MVE_VSTRB32_rq	= 1758,
    ARM_MVE_VSTRB8_rq	= 1759,
    ARM_MVE_VSTRBU8	= 1760,
    ARM_MVE_VSTRBU8_post	= 1761,
    ARM_MVE_VSTRBU8_pre	= 1762,
    ARM_MVE_VSTRD64_qi	= 1763,
    ARM_MVE_VSTRD64_qi_pre	= 1764,
    ARM_MVE_VSTRD64_rq	= 1765,
    ARM_MVE_VSTRD64_rq_u	= 1766,
    ARM_MVE_VSTRH16_rq	= 1767,
    ARM_MVE_VSTRH16_rq_u	= 1768,
    ARM_MVE_VSTRH32	= 1769,
    ARM_MVE_VSTRH32_post	= 1770,
    ARM_MVE_VSTRH32_pre	= 1771,
    ARM_MVE_VSTRH32_rq	= 1772,
    ARM_MVE_VSTRH32_rq_u	= 1773,
    ARM_MVE_VSTRHU16	= 1774,
    ARM_MVE_VSTRHU16_post	= 1775,
    ARM_MVE_VSTRHU16_pre	= 1776,
    ARM_MVE_VSTRW32_qi	= 1777,
    ARM_MVE_VSTRW32_qi_pre	= 1778,
    ARM_MVE_VSTRW32_rq	= 1779,
    ARM_MVE_VSTRW32_rq_u	= 1780,
    ARM_MVE_VSTRWU32	= 1781,
    ARM_MVE_VSTRWU32_post	= 1782,
    ARM_MVE_VSTRWU32_pre	= 1783,
    ARM_MVE_VSUB_qr_f16	= 1784,
    ARM_MVE_VSUB_qr_f32	= 1785,
    ARM_MVE_VSUB_qr_i16	= 1786,
    ARM_MVE_VSUB_qr_i32	= 1787,
    ARM_MVE_VSUB_qr_i8	= 1788,
    ARM_MVE_VSUBf16	= 1789,
    ARM_MVE_VSUBf32	= 1790,
    ARM_MVE_VSUBi16	= 1791,
    ARM_MVE_VSUBi32	= 1792,
    ARM_MVE_VSUBi8	= 1793,
    ARM_MVE_WLSTP_16	= 1794,
    ARM_MVE_WLSTP_32	= 1795,
    ARM_MVE_WLSTP_64	= 1796,
    ARM_MVE_WLSTP_8	= 1797,
    ARM_MVNi	= 1798,
    ARM_MVNr	= 1799,
    ARM_MVNsi	= 1800,
    ARM_MVNsr	= 1801,
    ARM_NEON_VMAXNMNDf	= 1802,
    ARM_NEON_VMAXNMNDh	= 1803,
    ARM_NEON_VMAXNMNQf	= 1804,
    ARM_NEON_VMAXNMNQh	= 1805,
    ARM_NEON_VMINNMNDf	= 1806,
    ARM_NEON_VMINNMNDh	= 1807,
    ARM_NEON_VMINNMNQf	= 1808,
    ARM_NEON_VMINNMNQh	= 1809,
    ARM_ORRri	= 1810,
    ARM_ORRrr	= 1811,
    ARM_ORRrsi	= 1812,
    ARM_ORRrsr	= 1813,
    ARM_PKHBT	= 1814,
    ARM_PKHTB	= 1815,
    ARM_PLDWi12	= 1816,
    ARM_PLDWrs	= 1817,
    ARM_PLDi12	= 1818,
    ARM_PLDrs	= 1819,
    ARM_PLIi12	= 1820,
    ARM_PLIrs	= 1821,
    ARM_QADD	= 1822,
    ARM_QADD16	= 1823,
    ARM_QADD8	= 1824,
    ARM_QASX	= 1825,
    ARM_QDADD	= 1826,
    ARM_QDSUB	= 1827,
    ARM_QSAX	= 1828,
    ARM_QSUB	= 1829,
    ARM_QSUB16	= 1830,
    ARM_QSUB8	= 1831,
    ARM_RBIT	= 1832,
    ARM_REV	= 1833,
    ARM_REV16	= 1834,
    ARM_REVSH	= 1835,
    ARM_RFEDA	= 1836,
    ARM_RFEDA_UPD	= 1837,
    ARM_RFEDB	= 1838,
    ARM_RFEDB_UPD	= 1839,
    ARM_RFEIA	= 1840,
    ARM_RFEIA_UPD	= 1841,
    ARM_RFEIB	= 1842,
    ARM_RFEIB_UPD	= 1843,
    ARM_RSBri	= 1844,
    ARM_RSBrr	= 1845,
    ARM_RSBrsi	= 1846,
    ARM_RSBrsr	= 1847,
    ARM_RSCri	= 1848,
    ARM_RSCrr	= 1849,
    ARM_RSCrsi	= 1850,
    ARM_RSCrsr	= 1851,
    ARM_SADD16	= 1852,
    ARM_SADD8	= 1853,
    ARM_SASX	= 1854,
    ARM_SB	= 1855,
    ARM_SBCri	= 1856,
    ARM_SBCrr	= 1857,
    ARM_SBCrsi	= 1858,
    ARM_SBCrsr	= 1859,
    ARM_SBFX	= 1860,
    ARM_SDIV	= 1861,
    ARM_SEL	= 1862,
    ARM_SETEND	= 1863,
    ARM_SETPAN	= 1864,
    ARM_SHA1C	= 1865,
    ARM_SHA1H	= 1866,
    ARM_SHA1M	= 1867,
    ARM_SHA1P	= 1868,
    ARM_SHA1SU0	= 1869,
    ARM_SHA1SU1	= 1870,
    ARM_SHA256H	= 1871,
    ARM_SHA256H2	= 1872,
    ARM_SHA256SU0	= 1873,
    ARM_SHA256SU1	= 1874,
    ARM_SHADD16	= 1875,
    ARM_SHADD8	= 1876,
    ARM_SHASX	= 1877,
    ARM_SHSAX	= 1878,
    ARM_SHSUB16	= 1879,
    ARM_SHSUB8	= 1880,
    ARM_SMC	= 1881,
    ARM_SMLABB	= 1882,
    ARM_SMLABT	= 1883,
    ARM_SMLAD	= 1884,
    ARM_SMLADX	= 1885,
    ARM_SMLAL	= 1886,
    ARM_SMLALBB	= 1887,
    ARM_SMLALBT	= 1888,
    ARM_SMLALD	= 1889,
    ARM_SMLALDX	= 1890,
    ARM_SMLALTB	= 1891,
    ARM_SMLALTT	= 1892,
    ARM_SMLATB	= 1893,
    ARM_SMLATT	= 1894,
    ARM_SMLAWB	= 1895,
    ARM_SMLAWT	= 1896,
    ARM_SMLSD	= 1897,
    ARM_SMLSDX	= 1898,
    ARM_SMLSLD	= 1899,
    ARM_SMLSLDX	= 1900,
    ARM_SMMLA	= 1901,
    ARM_SMMLAR	= 1902,
    ARM_SMMLS	= 1903,
    ARM_SMMLSR	= 1904,
    ARM_SMMUL	= 1905,
    ARM_SMMULR	= 1906,
    ARM_SMUAD	= 1907,
    ARM_SMUADX	= 1908,
    ARM_SMULBB	= 1909,
    ARM_SMULBT	= 1910,
    ARM_SMULL	= 1911,
    ARM_SMULTB	= 1912,
    ARM_SMULTT	= 1913,
    ARM_SMULWB	= 1914,
    ARM_SMULWT	= 1915,
    ARM_SMUSD	= 1916,
    ARM_SMUSDX	= 1917,
    ARM_SRSDA	= 1918,
    ARM_SRSDA_UPD	= 1919,
    ARM_SRSDB	= 1920,
    ARM_SRSDB_UPD	= 1921,
    ARM_SRSIA	= 1922,
    ARM_SRSIA_UPD	= 1923,
    ARM_SRSIB	= 1924,
    ARM_SRSIB_UPD	= 1925,
    ARM_SSAT	= 1926,
    ARM_SSAT16	= 1927,
    ARM_SSAX	= 1928,
    ARM_SSUB16	= 1929,
    ARM_SSUB8	= 1930,
    ARM_STC2L_OFFSET	= 1931,
    ARM_STC2L_OPTION	= 1932,
    ARM_STC2L_POST	= 1933,
    ARM_STC2L_PRE	= 1934,
    ARM_STC2_OFFSET	= 1935,
    ARM_STC2_OPTION	= 1936,
    ARM_STC2_POST	= 1937,
    ARM_STC2_PRE	= 1938,
    ARM_STCL_OFFSET	= 1939,
    ARM_STCL_OPTION	= 1940,
    ARM_STCL_POST	= 1941,
    ARM_STCL_PRE	= 1942,
    ARM_STC_OFFSET	= 1943,
    ARM_STC_OPTION	= 1944,
    ARM_STC_POST	= 1945,
    ARM_STC_PRE	= 1946,
    ARM_STL	= 1947,
    ARM_STLB	= 1948,
    ARM_STLEX	= 1949,
    ARM_STLEXB	= 1950,
    ARM_STLEXD	= 1951,
    ARM_STLEXH	= 1952,
    ARM_STLH	= 1953,
    ARM_STMDA	= 1954,
    ARM_STMDA_UPD	= 1955,
    ARM_STMDB	= 1956,
    ARM_STMDB_UPD	= 1957,
    ARM_STMIA	= 1958,
    ARM_STMIA_UPD	= 1959,
    ARM_STMIB	= 1960,
    ARM_STMIB_UPD	= 1961,
    ARM_STRBT_POST_IMM	= 1962,
    ARM_STRBT_POST_REG	= 1963,
    ARM_STRB_POST_IMM	= 1964,
    ARM_STRB_POST_REG	= 1965,
    ARM_STRB_PRE_IMM	= 1966,
    ARM_STRB_PRE_REG	= 1967,
    ARM_STRBi12	= 1968,
    ARM_STRBrs	= 1969,
    ARM_STRD	= 1970,
    ARM_STRD_POST	= 1971,
    ARM_STRD_PRE	= 1972,
    ARM_STREX	= 1973,
    ARM_STREXB	= 1974,
    ARM_STREXD	= 1975,
    ARM_STREXH	= 1976,
    ARM_STRH	= 1977,
    ARM_STRHTi	= 1978,
    ARM_STRHTr	= 1979,
    ARM_STRH_POST	= 1980,
    ARM_STRH_PRE	= 1981,
    ARM_STRT_POST_IMM	= 1982,
    ARM_STRT_POST_REG	= 1983,
    ARM_STR_POST_IMM	= 1984,
    ARM_STR_POST_REG	= 1985,
    ARM_STR_PRE_IMM	= 1986,
    ARM_STR_PRE_REG	= 1987,
    ARM_STRi12	= 1988,
    ARM_STRrs	= 1989,
    ARM_SUBri	= 1990,
    ARM_SUBrr	= 1991,
    ARM_SUBrsi	= 1992,
    ARM_SUBrsr	= 1993,
    ARM_SVC	= 1994,
    ARM_SWP	= 1995,
    ARM_SWPB	= 1996,
    ARM_SXTAB	= 1997,
    ARM_SXTAB16	= 1998,
    ARM_SXTAH	= 1999,
    ARM_SXTB	= 2000,
    ARM_SXTB16	= 2001,
    ARM_SXTH	= 2002,
    ARM_TEQri	= 2003,
    ARM_TEQrr	= 2004,
    ARM_TEQrsi	= 2005,
    ARM_TEQrsr	= 2006,
    ARM_TRAP	= 2007,
    ARM_TRAPNaCl	= 2008,
    ARM_TSB	= 2009,
    ARM_TSTri	= 2010,
    ARM_TSTrr	= 2011,
    ARM_TSTrsi	= 2012,
    ARM_TSTrsr	= 2013,
    ARM_UADD16	= 2014,
    ARM_UADD8	= 2015,
    ARM_UASX	= 2016,
    ARM_UBFX	= 2017,
    ARM_UDF	= 2018,
    ARM_UDIV	= 2019,
    ARM_UHADD16	= 2020,
    ARM_UHADD8	= 2021,
    ARM_UHASX	= 2022,
    ARM_UHSAX	= 2023,
    ARM_UHSUB16	= 2024,
    ARM_UHSUB8	= 2025,
    ARM_UMAAL	= 2026,
    ARM_UMLAL	= 2027,
    ARM_UMULL	= 2028,
    ARM_UQADD16	= 2029,
    ARM_UQADD8	= 2030,
    ARM_UQASX	= 2031,
    ARM_UQSAX	= 2032,
    ARM_UQSUB16	= 2033,
    ARM_UQSUB8	= 2034,
    ARM_USAD8	= 2035,
    ARM_USADA8	= 2036,
    ARM_USAT	= 2037,
    ARM_USAT16	= 2038,
    ARM_USAX	= 2039,
    ARM_USUB16	= 2040,
    ARM_USUB8	= 2041,
    ARM_UXTAB	= 2042,
    ARM_UXTAB16	= 2043,
    ARM_UXTAH	= 2044,
    ARM_UXTB	= 2045,
    ARM_UXTB16	= 2046,
    ARM_UXTH	= 2047,
    ARM_VABALsv2i64	= 2048,
    ARM_VABALsv4i32	= 2049,
    ARM_VABALsv8i16	= 2050,
    ARM_VABALuv2i64	= 2051,
    ARM_VABALuv4i32	= 2052,
    ARM_VABALuv8i16	= 2053,
    ARM_VABAsv16i8	= 2054,
    ARM_VABAsv2i32	= 2055,
    ARM_VABAsv4i16	= 2056,
    ARM_VABAsv4i32	= 2057,
    ARM_VABAsv8i16	= 2058,
    ARM_VABAsv8i8	= 2059,
    ARM_VABAuv16i8	= 2060,
    ARM_VABAuv2i32	= 2061,
    ARM_VABAuv4i16	= 2062,
    ARM_VABAuv4i32	= 2063,
    ARM_VABAuv8i16	= 2064,
    ARM_VABAuv8i8	= 2065,
    ARM_VABDLsv2i64	= 2066,
    ARM_VABDLsv4i32	= 2067,
    ARM_VABDLsv8i16	= 2068,
    ARM_VABDLuv2i64	= 2069,
    ARM_VABDLuv4i32	= 2070,
    ARM_VABDLuv8i16	= 2071,
    ARM_VABDfd	= 2072,
    ARM_VABDfq	= 2073,
    ARM_VABDhd	= 2074,
    ARM_VABDhq	= 2075,
    ARM_VABDsv16i8	= 2076,
    ARM_VABDsv2i32	= 2077,
    ARM_VABDsv4i16	= 2078,
    ARM_VABDsv4i32	= 2079,
    ARM_VABDsv8i16	= 2080,
    ARM_VABDsv8i8	= 2081,
    ARM_VABDuv16i8	= 2082,
    ARM_VABDuv2i32	= 2083,
    ARM_VABDuv4i16	= 2084,
    ARM_VABDuv4i32	= 2085,
    ARM_VABDuv8i16	= 2086,
    ARM_VABDuv8i8	= 2087,
    ARM_VABSD	= 2088,
    ARM_VABSH	= 2089,
    ARM_VABSS	= 2090,
    ARM_VABSfd	= 2091,
    ARM_VABSfq	= 2092,
    ARM_VABShd	= 2093,
    ARM_VABShq	= 2094,
    ARM_VABSv16i8	= 2095,
    ARM_VABSv2i32	= 2096,
    ARM_VABSv4i16	= 2097,
    ARM_VABSv4i32	= 2098,
    ARM_VABSv8i16	= 2099,
    ARM_VABSv8i8	= 2100,
    ARM_VACGEfd	= 2101,
    ARM_VACGEfq	= 2102,
    ARM_VACGEhd	= 2103,
    ARM_VACGEhq	= 2104,
    ARM_VACGTfd	= 2105,
    ARM_VACGTfq	= 2106,
    ARM_VACGThd	= 2107,
    ARM_VACGThq	= 2108,
    ARM_VADDD	= 2109,
    ARM_VADDH	= 2110,
    ARM_VADDHNv2i32	= 2111,
    ARM_VADDHNv4i16	= 2112,
    ARM_VADDHNv8i8	= 2113,
    ARM_VADDLsv2i64	= 2114,
    ARM_VADDLsv4i32	= 2115,
    ARM_VADDLsv8i16	= 2116,
    ARM_VADDLuv2i64	= 2117,
    ARM_VADDLuv4i32	= 2118,
    ARM_VADDLuv8i16	= 2119,
    ARM_VADDS	= 2120,
    ARM_VADDWsv2i64	= 2121,
    ARM_VADDWsv4i32	= 2122,
    ARM_VADDWsv8i16	= 2123,
    ARM_VADDWuv2i64	= 2124,
    ARM_VADDWuv4i32	= 2125,
    ARM_VADDWuv8i16	= 2126,
    ARM_VADDfd	= 2127,
    ARM_VADDfq	= 2128,
    ARM_VADDhd	= 2129,
    ARM_VADDhq	= 2130,
    ARM_VADDv16i8	= 2131,
    ARM_VADDv1i64	= 2132,
    ARM_VADDv2i32	= 2133,
    ARM_VADDv2i64	= 2134,
    ARM_VADDv4i16	= 2135,
    ARM_VADDv4i32	= 2136,
    ARM_VADDv8i16	= 2137,
    ARM_VADDv8i8	= 2138,
    ARM_VANDd	= 2139,
    ARM_VANDq	= 2140,
    ARM_VBF16MALBQ	= 2141,
    ARM_VBF16MALBQI	= 2142,
    ARM_VBF16MALTQ	= 2143,
    ARM_VBF16MALTQI	= 2144,
    ARM_VBICd	= 2145,
    ARM_VBICiv2i32	= 2146,
    ARM_VBICiv4i16	= 2147,
    ARM_VBICiv4i32	= 2148,
    ARM_VBICiv8i16	= 2149,
    ARM_VBICq	= 2150,
    ARM_VBIFd	= 2151,
    ARM_VBIFq	= 2152,
    ARM_VBITd	= 2153,
    ARM_VBITq	= 2154,
    ARM_VBSLd	= 2155,
    ARM_VBSLq	= 2156,
    ARM_VBSPd	= 2157,
    ARM_VBSPq	= 2158,
    ARM_VCADDv2f32	= 2159,
    ARM_VCADDv4f16	= 2160,
    ARM_VCADDv4f32	= 2161,
    ARM_VCADDv8f16	= 2162,
    ARM_VCEQfd	= 2163,
    ARM_VCEQfq	= 2164,
    ARM_VCEQhd	= 2165,
    ARM_VCEQhq	= 2166,
    ARM_VCEQv16i8	= 2167,
    ARM_VCEQv2i32	= 2168,
    ARM_VCEQv4i16	= 2169,
    ARM_VCEQv4i32	= 2170,
    ARM_VCEQv8i16	= 2171,
    ARM_VCEQv8i8	= 2172,
    ARM_VCEQzv16i8	= 2173,
    ARM_VCEQzv2f32	= 2174,
    ARM_VCEQzv2i32	= 2175,
    ARM_VCEQzv4f16	= 2176,
    ARM_VCEQzv4f32	= 2177,
    ARM_VCEQzv4i16	= 2178,
    ARM_VCEQzv4i32	= 2179,
    ARM_VCEQzv8f16	= 2180,
    ARM_VCEQzv8i16	= 2181,
    ARM_VCEQzv8i8	= 2182,
    ARM_VCGEfd	= 2183,
    ARM_VCGEfq	= 2184,
    ARM_VCGEhd	= 2185,
    ARM_VCGEhq	= 2186,
    ARM_VCGEsv16i8	= 2187,
    ARM_VCGEsv2i32	= 2188,
    ARM_VCGEsv4i16	= 2189,
    ARM_VCGEsv4i32	= 2190,
    ARM_VCGEsv8i16	= 2191,
    ARM_VCGEsv8i8	= 2192,
    ARM_VCGEuv16i8	= 2193,
    ARM_VCGEuv2i32	= 2194,
    ARM_VCGEuv4i16	= 2195,
    ARM_VCGEuv4i32	= 2196,
    ARM_VCGEuv8i16	= 2197,
    ARM_VCGEuv8i8	= 2198,
    ARM_VCGEzv16i8	= 2199,
    ARM_VCGEzv2f32	= 2200,
    ARM_VCGEzv2i32	= 2201,
    ARM_VCGEzv4f16	= 2202,
    ARM_VCGEzv4f32	= 2203,
    ARM_VCGEzv4i16	= 2204,
    ARM_VCGEzv4i32	= 2205,
    ARM_VCGEzv8f16	= 2206,
    ARM_VCGEzv8i16	= 2207,
    ARM_VCGEzv8i8	= 2208,
    ARM_VCGTfd	= 2209,
    ARM_VCGTfq	= 2210,
    ARM_VCGThd	= 2211,
    ARM_VCGThq	= 2212,
    ARM_VCGTsv16i8	= 2213,
    ARM_VCGTsv2i32	= 2214,
    ARM_VCGTsv4i16	= 2215,
    ARM_VCGTsv4i32	= 2216,
    ARM_VCGTsv8i16	= 2217,
    ARM_VCGTsv8i8	= 2218,
    ARM_VCGTuv16i8	= 2219,
    ARM_VCGTuv2i32	= 2220,
    ARM_VCGTuv4i16	= 2221,
    ARM_VCGTuv4i32	= 2222,
    ARM_VCGTuv8i16	= 2223,
    ARM_VCGTuv8i8	= 2224,
    ARM_VCGTzv16i8	= 2225,
    ARM_VCGTzv2f32	= 2226,
    ARM_VCGTzv2i32	= 2227,
    ARM_VCGTzv4f16	= 2228,
    ARM_VCGTzv4f32	= 2229,
    ARM_VCGTzv4i16	= 2230,
    ARM_VCGTzv4i32	= 2231,
    ARM_VCGTzv8f16	= 2232,
    ARM_VCGTzv8i16	= 2233,
    ARM_VCGTzv8i8	= 2234,
    ARM_VCLEzv16i8	= 2235,
    ARM_VCLEzv2f32	= 2236,
    ARM_VCLEzv2i32	= 2237,
    ARM_VCLEzv4f16	= 2238,
    ARM_VCLEzv4f32	= 2239,
    ARM_VCLEzv4i16	= 2240,
    ARM_VCLEzv4i32	= 2241,
    ARM_VCLEzv8f16	= 2242,
    ARM_VCLEzv8i16	= 2243,
    ARM_VCLEzv8i8	= 2244,
    ARM_VCLSv16i8	= 2245,
    ARM_VCLSv2i32	= 2246,
    ARM_VCLSv4i16	= 2247,
    ARM_VCLSv4i32	= 2248,
    ARM_VCLSv8i16	= 2249,
    ARM_VCLSv8i8	= 2250,
    ARM_VCLTzv16i8	= 2251,
    ARM_VCLTzv2f32	= 2252,
    ARM_VCLTzv2i32	= 2253,
    ARM_VCLTzv4f16	= 2254,
    ARM_VCLTzv4f32	= 2255,
    ARM_VCLTzv4i16	= 2256,
    ARM_VCLTzv4i32	= 2257,
    ARM_VCLTzv8f16	= 2258,
    ARM_VCLTzv8i16	= 2259,
    ARM_VCLTzv8i8	= 2260,
    ARM_VCLZv16i8	= 2261,
    ARM_VCLZv2i32	= 2262,
    ARM_VCLZv4i16	= 2263,
    ARM_VCLZv4i32	= 2264,
    ARM_VCLZv8i16	= 2265,
    ARM_VCLZv8i8	= 2266,
    ARM_VCMLAv2f32	= 2267,
    ARM_VCMLAv2f32_indexed	= 2268,
    ARM_VCMLAv4f16	= 2269,
    ARM_VCMLAv4f16_indexed	= 2270,
    ARM_VCMLAv4f32	= 2271,
    ARM_VCMLAv4f32_indexed	= 2272,
    ARM_VCMLAv8f16	= 2273,
    ARM_VCMLAv8f16_indexed	= 2274,
    ARM_VCMPD	= 2275,
    ARM_VCMPED	= 2276,
    ARM_VCMPEH	= 2277,
    ARM_VCMPES	= 2278,
    ARM_VCMPEZD	= 2279,
    ARM_VCMPEZH	= 2280,
    ARM_VCMPEZS	= 2281,
    ARM_VCMPH	= 2282,
    ARM_VCMPS	= 2283,
    ARM_VCMPZD	= 2284,
    ARM_VCMPZH	= 2285,
    ARM_VCMPZS	= 2286,
    ARM_VCNTd	= 2287,
    ARM_VCNTq	= 2288,
    ARM_VCVTANSDf	= 2289,
    ARM_VCVTANSDh	= 2290,
    ARM_VCVTANSQf	= 2291,
    ARM_VCVTANSQh	= 2292,
    ARM_VCVTANUDf	= 2293,
    ARM_VCVTANUDh	= 2294,
    ARM_VCVTANUQf	= 2295,
    ARM_VCVTANUQh	= 2296,
    ARM_VCVTASD	= 2297,
    ARM_VCVTASH	= 2298,
    ARM_VCVTASS	= 2299,
    ARM_VCVTAUD	= 2300,
    ARM_VCVTAUH	= 2301,
    ARM_VCVTAUS	= 2302,
    ARM_VCVTBDH	= 2303,
    ARM_VCVTBHD	= 2304,
    ARM_VCVTBHS	= 2305,
    ARM_VCVTBSH	= 2306,
    ARM_VCVTDS	= 2307,
    ARM_VCVTMNSDf	= 2308,
    ARM_VCVTMNSDh	= 2309,
    ARM_VCVTMNSQf	= 2310,
    ARM_VCVTMNSQh	= 2311,
    ARM_VCVTMNUDf	= 2312,
    ARM_VCVTMNUDh	= 2313,
    ARM_VCVTMNUQf	= 2314,
    ARM_VCVTMNUQh	= 2315,
    ARM_VCVTMSD	= 2316,
    ARM_VCVTMSH	= 2317,
    ARM_VCVTMSS	= 2318,
    ARM_VCVTMUD	= 2319,
    ARM_VCVTMUH	= 2320,
    ARM_VCVTMUS	= 2321,
    ARM_VCVTNNSDf	= 2322,
    ARM_VCVTNNSDh	= 2323,
    ARM_VCVTNNSQf	= 2324,
    ARM_VCVTNNSQh	= 2325,
    ARM_VCVTNNUDf	= 2326,
    ARM_VCVTNNUDh	= 2327,
    ARM_VCVTNNUQf	= 2328,
    ARM_VCVTNNUQh	= 2329,
    ARM_VCVTNSD	= 2330,
    ARM_VCVTNSH	= 2331,
    ARM_VCVTNSS	= 2332,
    ARM_VCVTNUD	= 2333,
    ARM_VCVTNUH	= 2334,
    ARM_VCVTNUS	= 2335,
    ARM_VCVTPNSDf	= 2336,
    ARM_VCVTPNSDh	= 2337,
    ARM_VCVTPNSQf	= 2338,
    ARM_VCVTPNSQh	= 2339,
    ARM_VCVTPNUDf	= 2340,
    ARM_VCVTPNUDh	= 2341,
    ARM_VCVTPNUQf	= 2342,
    ARM_VCVTPNUQh	= 2343,
    ARM_VCVTPSD	= 2344,
    ARM_VCVTPSH	= 2345,
    ARM_VCVTPSS	= 2346,
    ARM_VCVTPUD	= 2347,
    ARM_VCVTPUH	= 2348,
    ARM_VCVTPUS	= 2349,
    ARM_VCVTSD	= 2350,
    ARM_VCVTTDH	= 2351,
    ARM_VCVTTHD	= 2352,
    ARM_VCVTTHS	= 2353,
    ARM_VCVTTSH	= 2354,
    ARM_VCVTf2h	= 2355,
    ARM_VCVTf2sd	= 2356,
    ARM_VCVTf2sq	= 2357,
    ARM_VCVTf2ud	= 2358,
    ARM_VCVTf2uq	= 2359,
    ARM_VCVTf2xsd	= 2360,
    ARM_VCVTf2xsq	= 2361,
    ARM_VCVTf2xud	= 2362,
    ARM_VCVTf2xuq	= 2363,
    ARM_VCVTh2f	= 2364,
    ARM_VCVTh2sd	= 2365,
    ARM_VCVTh2sq	= 2366,
    ARM_VCVTh2ud	= 2367,
    ARM_VCVTh2uq	= 2368,
    ARM_VCVTh2xsd	= 2369,
    ARM_VCVTh2xsq	= 2370,
    ARM_VCVTh2xud	= 2371,
    ARM_VCVTh2xuq	= 2372,
    ARM_VCVTs2fd	= 2373,
    ARM_VCVTs2fq	= 2374,
    ARM_VCVTs2hd	= 2375,
    ARM_VCVTs2hq	= 2376,
    ARM_VCVTu2fd	= 2377,
    ARM_VCVTu2fq	= 2378,
    ARM_VCVTu2hd	= 2379,
    ARM_VCVTu2hq	= 2380,
    ARM_VCVTxs2fd	= 2381,
    ARM_VCVTxs2fq	= 2382,
    ARM_VCVTxs2hd	= 2383,
    ARM_VCVTxs2hq	= 2384,
    ARM_VCVTxu2fd	= 2385,
    ARM_VCVTxu2fq	= 2386,
    ARM_VCVTxu2hd	= 2387,
    ARM_VCVTxu2hq	= 2388,
    ARM_VDIVD	= 2389,
    ARM_VDIVH	= 2390,
    ARM_VDIVS	= 2391,
    ARM_VDUP16d	= 2392,
    ARM_VDUP16q	= 2393,
    ARM_VDUP32d	= 2394,
    ARM_VDUP32q	= 2395,
    ARM_VDUP8d	= 2396,
    ARM_VDUP8q	= 2397,
    ARM_VDUPLN16d	= 2398,
    ARM_VDUPLN16q	= 2399,
    ARM_VDUPLN32d	= 2400,
    ARM_VDUPLN32q	= 2401,
    ARM_VDUPLN8d	= 2402,
    ARM_VDUPLN8q	= 2403,
    ARM_VEORd	= 2404,
    ARM_VEORq	= 2405,
    ARM_VEXTd16	= 2406,
    ARM_VEXTd32	= 2407,
    ARM_VEXTd8	= 2408,
    ARM_VEXTq16	= 2409,
    ARM_VEXTq32	= 2410,
    ARM_VEXTq64	= 2411,
    ARM_VEXTq8	= 2412,
    ARM_VFMAD	= 2413,
    ARM_VFMAH	= 2414,
    ARM_VFMALD	= 2415,
    ARM_VFMALDI	= 2416,
    ARM_VFMALQ	= 2417,
    ARM_VFMALQI	= 2418,
    ARM_VFMAS	= 2419,
    ARM_VFMAfd	= 2420,
    ARM_VFMAfq	= 2421,
    ARM_VFMAhd	= 2422,
    ARM_VFMAhq	= 2423,
    ARM_VFMSD	= 2424,
    ARM_VFMSH	= 2425,
    ARM_VFMSLD	= 2426,
    ARM_VFMSLDI	= 2427,
    ARM_VFMSLQ	= 2428,
    ARM_VFMSLQI	= 2429,
    ARM_VFMSS	= 2430,
    ARM_VFMSfd	= 2431,
    ARM_VFMSfq	= 2432,
    ARM_VFMShd	= 2433,
    ARM_VFMShq	= 2434,
    ARM_VFNMAD	= 2435,
    ARM_VFNMAH	= 2436,
    ARM_VFNMAS	= 2437,
    ARM_VFNMSD	= 2438,
    ARM_VFNMSH	= 2439,
    ARM_VFNMSS	= 2440,
    ARM_VFP_VMAXNMD	= 2441,
    ARM_VFP_VMAXNMH	= 2442,
    ARM_VFP_VMAXNMS	= 2443,
    ARM_VFP_VMINNMD	= 2444,
    ARM_VFP_VMINNMH	= 2445,
    ARM_VFP_VMINNMS	= 2446,
    ARM_VGETLNi32	= 2447,
    ARM_VGETLNs16	= 2448,
    ARM_VGETLNs8	= 2449,
    ARM_VGETLNu16	= 2450,
    ARM_VGETLNu8	= 2451,
    ARM_VHADDsv16i8	= 2452,
    ARM_VHADDsv2i32	= 2453,
    ARM_VHADDsv4i16	= 2454,
    ARM_VHADDsv4i32	= 2455,
    ARM_VHADDsv8i16	= 2456,
    ARM_VHADDsv8i8	= 2457,
    ARM_VHADDuv16i8	= 2458,
    ARM_VHADDuv2i32	= 2459,
    ARM_VHADDuv4i16	= 2460,
    ARM_VHADDuv4i32	= 2461,
    ARM_VHADDuv8i16	= 2462,
    ARM_VHADDuv8i8	= 2463,
    ARM_VHSUBsv16i8	= 2464,
    ARM_VHSUBsv2i32	= 2465,
    ARM_VHSUBsv4i16	= 2466,
    ARM_VHSUBsv4i32	= 2467,
    ARM_VHSUBsv8i16	= 2468,
    ARM_VHSUBsv8i8	= 2469,
    ARM_VHSUBuv16i8	= 2470,
    ARM_VHSUBuv2i32	= 2471,
    ARM_VHSUBuv4i16	= 2472,
    ARM_VHSUBuv4i32	= 2473,
    ARM_VHSUBuv8i16	= 2474,
    ARM_VHSUBuv8i8	= 2475,
    ARM_VINSH	= 2476,
    ARM_VJCVT	= 2477,
    ARM_VLD1DUPd16	= 2478,
    ARM_VLD1DUPd16wb_fixed	= 2479,
    ARM_VLD1DUPd16wb_register	= 2480,
    ARM_VLD1DUPd32	= 2481,
    ARM_VLD1DUPd32wb_fixed	= 2482,
    ARM_VLD1DUPd32wb_register	= 2483,
    ARM_VLD1DUPd8	= 2484,
    ARM_VLD1DUPd8wb_fixed	= 2485,
    ARM_VLD1DUPd8wb_register	= 2486,
    ARM_VLD1DUPq16	= 2487,
    ARM_VLD1DUPq16wb_fixed	= 2488,
    ARM_VLD1DUPq16wb_register	= 2489,
    ARM_VLD1DUPq32	= 2490,
    ARM_VLD1DUPq32wb_fixed	= 2491,
    ARM_VLD1DUPq32wb_register	= 2492,
    ARM_VLD1DUPq8	= 2493,
    ARM_VLD1DUPq8wb_fixed	= 2494,
    ARM_VLD1DUPq8wb_register	= 2495,
    ARM_VLD1LNd16	= 2496,
    ARM_VLD1LNd16_UPD	= 2497,
    ARM_VLD1LNd32	= 2498,
    ARM_VLD1LNd32_UPD	= 2499,
    ARM_VLD1LNd8	= 2500,
    ARM_VLD1LNd8_UPD	= 2501,
    ARM_VLD1LNq16Pseudo	= 2502,
    ARM_VLD1LNq16Pseudo_UPD	= 2503,
    ARM_VLD1LNq32Pseudo	= 2504,
    ARM_VLD1LNq32Pseudo_UPD	= 2505,
    ARM_VLD1LNq8Pseudo	= 2506,
    ARM_VLD1LNq8Pseudo_UPD	= 2507,
    ARM_VLD1d16	= 2508,
    ARM_VLD1d16Q	= 2509,
    ARM_VLD1d16QPseudo	= 2510,
    ARM_VLD1d16QPseudoWB_fixed	= 2511,
    ARM_VLD1d16QPseudoWB_register	= 2512,
    ARM_VLD1d16Qwb_fixed	= 2513,
    ARM_VLD1d16Qwb_register	= 2514,
    ARM_VLD1d16T	= 2515,
    ARM_VLD1d16TPseudo	= 2516,
    ARM_VLD1d16TPseudoWB_fixed	= 2517,
    ARM_VLD1d16TPseudoWB_register	= 2518,
    ARM_VLD1d16Twb_fixed	= 2519,
    ARM_VLD1d16Twb_register	= 2520,
    ARM_VLD1d16wb_fixed	= 2521,
    ARM_VLD1d16wb_register	= 2522,
    ARM_VLD1d32	= 2523,
    ARM_VLD1d32Q	= 2524,
    ARM_VLD1d32QPseudo	= 2525,
    ARM_VLD1d32QPseudoWB_fixed	= 2526,
    ARM_VLD1d32QPseudoWB_register	= 2527,
    ARM_VLD1d32Qwb_fixed	= 2528,
    ARM_VLD1d32Qwb_register	= 2529,
    ARM_VLD1d32T	= 2530,
    ARM_VLD1d32TPseudo	= 2531,
    ARM_VLD1d32TPseudoWB_fixed	= 2532,
    ARM_VLD1d32TPseudoWB_register	= 2533,
    ARM_VLD1d32Twb_fixed	= 2534,
    ARM_VLD1d32Twb_register	= 2535,
    ARM_VLD1d32wb_fixed	= 2536,
    ARM_VLD1d32wb_register	= 2537,
    ARM_VLD1d64	= 2538,
    ARM_VLD1d64Q	= 2539,
    ARM_VLD1d64QPseudo	= 2540,
    ARM_VLD1d64QPseudoWB_fixed	= 2541,
    ARM_VLD1d64QPseudoWB_register	= 2542,
    ARM_VLD1d64Qwb_fixed	= 2543,
    ARM_VLD1d64Qwb_register	= 2544,
    ARM_VLD1d64T	= 2545,
    ARM_VLD1d64TPseudo	= 2546,
    ARM_VLD1d64TPseudoWB_fixed	= 2547,
    ARM_VLD1d64TPseudoWB_register	= 2548,
    ARM_VLD1d64Twb_fixed	= 2549,
    ARM_VLD1d64Twb_register	= 2550,
    ARM_VLD1d64wb_fixed	= 2551,
    ARM_VLD1d64wb_register	= 2552,
    ARM_VLD1d8	= 2553,
    ARM_VLD1d8Q	= 2554,
    ARM_VLD1d8QPseudo	= 2555,
    ARM_VLD1d8QPseudoWB_fixed	= 2556,
    ARM_VLD1d8QPseudoWB_register	= 2557,
    ARM_VLD1d8Qwb_fixed	= 2558,
    ARM_VLD1d8Qwb_register	= 2559,
    ARM_VLD1d8T	= 2560,
    ARM_VLD1d8TPseudo	= 2561,
    ARM_VLD1d8TPseudoWB_fixed	= 2562,
    ARM_VLD1d8TPseudoWB_register	= 2563,
    ARM_VLD1d8Twb_fixed	= 2564,
    ARM_VLD1d8Twb_register	= 2565,
    ARM_VLD1d8wb_fixed	= 2566,
    ARM_VLD1d8wb_register	= 2567,
    ARM_VLD1q16	= 2568,
    ARM_VLD1q16HighQPseudo	= 2569,
    ARM_VLD1q16HighQPseudo_UPD	= 2570,
    ARM_VLD1q16HighTPseudo	= 2571,
    ARM_VLD1q16HighTPseudo_UPD	= 2572,
    ARM_VLD1q16LowQPseudo_UPD	= 2573,
    ARM_VLD1q16LowTPseudo_UPD	= 2574,
    ARM_VLD1q16wb_fixed	= 2575,
    ARM_VLD1q16wb_register	= 2576,
    ARM_VLD1q32	= 2577,
    ARM_VLD1q32HighQPseudo	= 2578,
    ARM_VLD1q32HighQPseudo_UPD	= 2579,
    ARM_VLD1q32HighTPseudo	= 2580,
    ARM_VLD1q32HighTPseudo_UPD	= 2581,
    ARM_VLD1q32LowQPseudo_UPD	= 2582,
    ARM_VLD1q32LowTPseudo_UPD	= 2583,
    ARM_VLD1q32wb_fixed	= 2584,
    ARM_VLD1q32wb_register	= 2585,
    ARM_VLD1q64	= 2586,
    ARM_VLD1q64HighQPseudo	= 2587,
    ARM_VLD1q64HighQPseudo_UPD	= 2588,
    ARM_VLD1q64HighTPseudo	= 2589,
    ARM_VLD1q64HighTPseudo_UPD	= 2590,
    ARM_VLD1q64LowQPseudo_UPD	= 2591,
    ARM_VLD1q64LowTPseudo_UPD	= 2592,
    ARM_VLD1q64wb_fixed	= 2593,
    ARM_VLD1q64wb_register	= 2594,
    ARM_VLD1q8	= 2595,
    ARM_VLD1q8HighQPseudo	= 2596,
    ARM_VLD1q8HighQPseudo_UPD	= 2597,
    ARM_VLD1q8HighTPseudo	= 2598,
    ARM_VLD1q8HighTPseudo_UPD	= 2599,
    ARM_VLD1q8LowQPseudo_UPD	= 2600,
    ARM_VLD1q8LowTPseudo_UPD	= 2601,
    ARM_VLD1q8wb_fixed	= 2602,
    ARM_VLD1q8wb_register	= 2603,
    ARM_VLD2DUPd16	= 2604,
    ARM_VLD2DUPd16wb_fixed	= 2605,
    ARM_VLD2DUPd16wb_register	= 2606,
    ARM_VLD2DUPd16x2	= 2607,
    ARM_VLD2DUPd16x2wb_fixed	= 2608,
    ARM_VLD2DUPd16x2wb_register	= 2609,
    ARM_VLD2DUPd32	= 2610,
    ARM_VLD2DUPd32wb_fixed	= 2611,
    ARM_VLD2DUPd32wb_register	= 2612,
    ARM_VLD2DUPd32x2	= 2613,
    ARM_VLD2DUPd32x2wb_fixed	= 2614,
    ARM_VLD2DUPd32x2wb_register	= 2615,
    ARM_VLD2DUPd8	= 2616,
    ARM_VLD2DUPd8wb_fixed	= 2617,
    ARM_VLD2DUPd8wb_register	= 2618,
    ARM_VLD2DUPd8x2	= 2619,
    ARM_VLD2DUPd8x2wb_fixed	= 2620,
    ARM_VLD2DUPd8x2wb_register	= 2621,
    ARM_VLD2DUPq16EvenPseudo	= 2622,
    ARM_VLD2DUPq16OddPseudo	= 2623,
    ARM_VLD2DUPq16OddPseudoWB_fixed	= 2624,
    ARM_VLD2DUPq16OddPseudoWB_register	= 2625,
    ARM_VLD2DUPq32EvenPseudo	= 2626,
    ARM_VLD2DUPq32OddPseudo	= 2627,
    ARM_VLD2DUPq32OddPseudoWB_fixed	= 2628,
    ARM_VLD2DUPq32OddPseudoWB_register	= 2629,
    ARM_VLD2DUPq8EvenPseudo	= 2630,
    ARM_VLD2DUPq8OddPseudo	= 2631,
    ARM_VLD2DUPq8OddPseudoWB_fixed	= 2632,
    ARM_VLD2DUPq8OddPseudoWB_register	= 2633,
    ARM_VLD2LNd16	= 2634,
    ARM_VLD2LNd16Pseudo	= 2635,
    ARM_VLD2LNd16Pseudo_UPD	= 2636,
    ARM_VLD2LNd16_UPD	= 2637,
    ARM_VLD2LNd32	= 2638,
    ARM_VLD2LNd32Pseudo	= 2639,
    ARM_VLD2LNd32Pseudo_UPD	= 2640,
    ARM_VLD2LNd32_UPD	= 2641,
    ARM_VLD2LNd8	= 2642,
    ARM_VLD2LNd8Pseudo	= 2643,
    ARM_VLD2LNd8Pseudo_UPD	= 2644,
    ARM_VLD2LNd8_UPD	= 2645,
    ARM_VLD2LNq16	= 2646,
    ARM_VLD2LNq16Pseudo	= 2647,
    ARM_VLD2LNq16Pseudo_UPD	= 2648,
    ARM_VLD2LNq16_UPD	= 2649,
    ARM_VLD2LNq32	= 2650,
    ARM_VLD2LNq32Pseudo	= 2651,
    ARM_VLD2LNq32Pseudo_UPD	= 2652,
    ARM_VLD2LNq32_UPD	= 2653,
    ARM_VLD2b16	= 2654,
    ARM_VLD2b16wb_fixed	= 2655,
    ARM_VLD2b16wb_register	= 2656,
    ARM_VLD2b32	= 2657,
    ARM_VLD2b32wb_fixed	= 2658,
    ARM_VLD2b32wb_register	= 2659,
    ARM_VLD2b8	= 2660,
    ARM_VLD2b8wb_fixed	= 2661,
    ARM_VLD2b8wb_register	= 2662,
    ARM_VLD2d16	= 2663,
    ARM_VLD2d16wb_fixed	= 2664,
    ARM_VLD2d16wb_register	= 2665,
    ARM_VLD2d32	= 2666,
    ARM_VLD2d32wb_fixed	= 2667,
    ARM_VLD2d32wb_register	= 2668,
    ARM_VLD2d8	= 2669,
    ARM_VLD2d8wb_fixed	= 2670,
    ARM_VLD2d8wb_register	= 2671,
    ARM_VLD2q16	= 2672,
    ARM_VLD2q16Pseudo	= 2673,
    ARM_VLD2q16PseudoWB_fixed	= 2674,
    ARM_VLD2q16PseudoWB_register	= 2675,
    ARM_VLD2q16wb_fixed	= 2676,
    ARM_VLD2q16wb_register	= 2677,
    ARM_VLD2q32	= 2678,
    ARM_VLD2q32Pseudo	= 2679,
    ARM_VLD2q32PseudoWB_fixed	= 2680,
    ARM_VLD2q32PseudoWB_register	= 2681,
    ARM_VLD2q32wb_fixed	= 2682,
    ARM_VLD2q32wb_register	= 2683,
    ARM_VLD2q8	= 2684,
    ARM_VLD2q8Pseudo	= 2685,
    ARM_VLD2q8PseudoWB_fixed	= 2686,
    ARM_VLD2q8PseudoWB_register	= 2687,
    ARM_VLD2q8wb_fixed	= 2688,
    ARM_VLD2q8wb_register	= 2689,
    ARM_VLD3DUPd16	= 2690,
    ARM_VLD3DUPd16Pseudo	= 2691,
    ARM_VLD3DUPd16Pseudo_UPD	= 2692,
    ARM_VLD3DUPd16_UPD	= 2693,
    ARM_VLD3DUPd32	= 2694,
    ARM_VLD3DUPd32Pseudo	= 2695,
    ARM_VLD3DUPd32Pseudo_UPD	= 2696,
    ARM_VLD3DUPd32_UPD	= 2697,
    ARM_VLD3DUPd8	= 2698,
    ARM_VLD3DUPd8Pseudo	= 2699,
    ARM_VLD3DUPd8Pseudo_UPD	= 2700,
    ARM_VLD3DUPd8_UPD	= 2701,
    ARM_VLD3DUPq16	= 2702,
    ARM_VLD3DUPq16EvenPseudo	= 2703,
    ARM_VLD3DUPq16OddPseudo	= 2704,
    ARM_VLD3DUPq16OddPseudo_UPD	= 2705,
    ARM_VLD3DUPq16_UPD	= 2706,
    ARM_VLD3DUPq32	= 2707,
    ARM_VLD3DUPq32EvenPseudo	= 2708,
    ARM_VLD3DUPq32OddPseudo	= 2709,
    ARM_VLD3DUPq32OddPseudo_UPD	= 2710,
    ARM_VLD3DUPq32_UPD	= 2711,
    ARM_VLD3DUPq8	= 2712,
    ARM_VLD3DUPq8EvenPseudo	= 2713,
    ARM_VLD3DUPq8OddPseudo	= 2714,
    ARM_VLD3DUPq8OddPseudo_UPD	= 2715,
    ARM_VLD3DUPq8_UPD	= 2716,
    ARM_VLD3LNd16	= 2717,
    ARM_VLD3LNd16Pseudo	= 2718,
    ARM_VLD3LNd16Pseudo_UPD	= 2719,
    ARM_VLD3LNd16_UPD	= 2720,
    ARM_VLD3LNd32	= 2721,
    ARM_VLD3LNd32Pseudo	= 2722,
    ARM_VLD3LNd32Pseudo_UPD	= 2723,
    ARM_VLD3LNd32_UPD	= 2724,
    ARM_VLD3LNd8	= 2725,
    ARM_VLD3LNd8Pseudo	= 2726,
    ARM_VLD3LNd8Pseudo_UPD	= 2727,
    ARM_VLD3LNd8_UPD	= 2728,
    ARM_VLD3LNq16	= 2729,
    ARM_VLD3LNq16Pseudo	= 2730,
    ARM_VLD3LNq16Pseudo_UPD	= 2731,
    ARM_VLD3LNq16_UPD	= 2732,
    ARM_VLD3LNq32	= 2733,
    ARM_VLD3LNq32Pseudo	= 2734,
    ARM_VLD3LNq32Pseudo_UPD	= 2735,
    ARM_VLD3LNq32_UPD	= 2736,
    ARM_VLD3d16	= 2737,
    ARM_VLD3d16Pseudo	= 2738,
    ARM_VLD3d16Pseudo_UPD	= 2739,
    ARM_VLD3d16_UPD	= 2740,
    ARM_VLD3d32	= 2741,
    ARM_VLD3d32Pseudo	= 2742,
    ARM_VLD3d32Pseudo_UPD	= 2743,
    ARM_VLD3d32_UPD	= 2744,
    ARM_VLD3d8	= 2745,
    ARM_VLD3d8Pseudo	= 2746,
    ARM_VLD3d8Pseudo_UPD	= 2747,
    ARM_VLD3d8_UPD	= 2748,
    ARM_VLD3q16	= 2749,
    ARM_VLD3q16Pseudo_UPD	= 2750,
    ARM_VLD3q16_UPD	= 2751,
    ARM_VLD3q16oddPseudo	= 2752,
    ARM_VLD3q16oddPseudo_UPD	= 2753,
    ARM_VLD3q32	= 2754,
    ARM_VLD3q32Pseudo_UPD	= 2755,
    ARM_VLD3q32_UPD	= 2756,
    ARM_VLD3q32oddPseudo	= 2757,
    ARM_VLD3q32oddPseudo_UPD	= 2758,
    ARM_VLD3q8	= 2759,
    ARM_VLD3q8Pseudo_UPD	= 2760,
    ARM_VLD3q8_UPD	= 2761,
    ARM_VLD3q8oddPseudo	= 2762,
    ARM_VLD3q8oddPseudo_UPD	= 2763,
    ARM_VLD4DUPd16	= 2764,
    ARM_VLD4DUPd16Pseudo	= 2765,
    ARM_VLD4DUPd16Pseudo_UPD	= 2766,
    ARM_VLD4DUPd16_UPD	= 2767,
    ARM_VLD4DUPd32	= 2768,
    ARM_VLD4DUPd32Pseudo	= 2769,
    ARM_VLD4DUPd32Pseudo_UPD	= 2770,
    ARM_VLD4DUPd32_UPD	= 2771,
    ARM_VLD4DUPd8	= 2772,
    ARM_VLD4DUPd8Pseudo	= 2773,
    ARM_VLD4DUPd8Pseudo_UPD	= 2774,
    ARM_VLD4DUPd8_UPD	= 2775,
    ARM_VLD4DUPq16	= 2776,
    ARM_VLD4DUPq16EvenPseudo	= 2777,
    ARM_VLD4DUPq16OddPseudo	= 2778,
    ARM_VLD4DUPq16OddPseudo_UPD	= 2779,
    ARM_VLD4DUPq16_UPD	= 2780,
    ARM_VLD4DUPq32	= 2781,
    ARM_VLD4DUPq32EvenPseudo	= 2782,
    ARM_VLD4DUPq32OddPseudo	= 2783,
    ARM_VLD4DUPq32OddPseudo_UPD	= 2784,
    ARM_VLD4DUPq32_UPD	= 2785,
    ARM_VLD4DUPq8	= 2786,
    ARM_VLD4DUPq8EvenPseudo	= 2787,
    ARM_VLD4DUPq8OddPseudo	= 2788,
    ARM_VLD4DUPq8OddPseudo_UPD	= 2789,
    ARM_VLD4DUPq8_UPD	= 2790,
    ARM_VLD4LNd16	= 2791,
    ARM_VLD4LNd16Pseudo	= 2792,
    ARM_VLD4LNd16Pseudo_UPD	= 2793,
    ARM_VLD4LNd16_UPD	= 2794,
    ARM_VLD4LNd32	= 2795,
    ARM_VLD4LNd32Pseudo	= 2796,
    ARM_VLD4LNd32Pseudo_UPD	= 2797,
    ARM_VLD4LNd32_UPD	= 2798,
    ARM_VLD4LNd8	= 2799,
    ARM_VLD4LNd8Pseudo	= 2800,
    ARM_VLD4LNd8Pseudo_UPD	= 2801,
    ARM_VLD4LNd8_UPD	= 2802,
    ARM_VLD4LNq16	= 2803,
    ARM_VLD4LNq16Pseudo	= 2804,
    ARM_VLD4LNq16Pseudo_UPD	= 2805,
    ARM_VLD4LNq16_UPD	= 2806,
    ARM_VLD4LNq32	= 2807,
    ARM_VLD4LNq32Pseudo	= 2808,
    ARM_VLD4LNq32Pseudo_UPD	= 2809,
    ARM_VLD4LNq32_UPD	= 2810,
    ARM_VLD4d16	= 2811,
    ARM_VLD4d16Pseudo	= 2812,
    ARM_VLD4d16Pseudo_UPD	= 2813,
    ARM_VLD4d16_UPD	= 2814,
    ARM_VLD4d32	= 2815,
    ARM_VLD4d32Pseudo	= 2816,
    ARM_VLD4d32Pseudo_UPD	= 2817,
    ARM_VLD4d32_UPD	= 2818,
    ARM_VLD4d8	= 2819,
    ARM_VLD4d8Pseudo	= 2820,
    ARM_VLD4d8Pseudo_UPD	= 2821,
    ARM_VLD4d8_UPD	= 2822,
    ARM_VLD4q16	= 2823,
    ARM_VLD4q16Pseudo_UPD	= 2824,
    ARM_VLD4q16_UPD	= 2825,
    ARM_VLD4q16oddPseudo	= 2826,
    ARM_VLD4q16oddPseudo_UPD	= 2827,
    ARM_VLD4q32	= 2828,
    ARM_VLD4q32Pseudo_UPD	= 2829,
    ARM_VLD4q32_UPD	= 2830,
    ARM_VLD4q32oddPseudo	= 2831,
    ARM_VLD4q32oddPseudo_UPD	= 2832,
    ARM_VLD4q8	= 2833,
    ARM_VLD4q8Pseudo_UPD	= 2834,
    ARM_VLD4q8_UPD	= 2835,
    ARM_VLD4q8oddPseudo	= 2836,
    ARM_VLD4q8oddPseudo_UPD	= 2837,
    ARM_VLDMDDB_UPD	= 2838,
    ARM_VLDMDIA	= 2839,
    ARM_VLDMDIA_UPD	= 2840,
    ARM_VLDMQIA	= 2841,
    ARM_VLDMSDB_UPD	= 2842,
    ARM_VLDMSIA	= 2843,
    ARM_VLDMSIA_UPD	= 2844,
    ARM_VLDRD	= 2845,
    ARM_VLDRH	= 2846,
    ARM_VLDRS	= 2847,
    ARM_VLDR_FPCXTNS_off	= 2848,
    ARM_VLDR_FPCXTNS_post	= 2849,
    ARM_VLDR_FPCXTNS_pre	= 2850,
    ARM_VLDR_FPCXTS_off	= 2851,
    ARM_VLDR_FPCXTS_post	= 2852,
    ARM_VLDR_FPCXTS_pre	= 2853,
    ARM_VLDR_FPSCR_NZCVQC_off	= 2854,
    ARM_VLDR_FPSCR_NZCVQC_post	= 2855,
    ARM_VLDR_FPSCR_NZCVQC_pre	= 2856,
    ARM_VLDR_FPSCR_off	= 2857,
    ARM_VLDR_FPSCR_post	= 2858,
    ARM_VLDR_FPSCR_pre	= 2859,
    ARM_VLDR_P0_off	= 2860,
    ARM_VLDR_P0_post	= 2861,
    ARM_VLDR_P0_pre	= 2862,
    ARM_VLDR_VPR_off	= 2863,
    ARM_VLDR_VPR_post	= 2864,
    ARM_VLDR_VPR_pre	= 2865,
    ARM_VLLDM	= 2866,
    ARM_VLSTM	= 2867,
    ARM_VMAXfd	= 2868,
    ARM_VMAXfq	= 2869,
    ARM_VMAXhd	= 2870,
    ARM_VMAXhq	= 2871,
    ARM_VMAXsv16i8	= 2872,
    ARM_VMAXsv2i32	= 2873,
    ARM_VMAXsv4i16	= 2874,
    ARM_VMAXsv4i32	= 2875,
    ARM_VMAXsv8i16	= 2876,
    ARM_VMAXsv8i8	= 2877,
    ARM_VMAXuv16i8	= 2878,
    ARM_VMAXuv2i32	= 2879,
    ARM_VMAXuv4i16	= 2880,
    ARM_VMAXuv4i32	= 2881,
    ARM_VMAXuv8i16	= 2882,
    ARM_VMAXuv8i8	= 2883,
    ARM_VMINfd	= 2884,
    ARM_VMINfq	= 2885,
    ARM_VMINhd	= 2886,
    ARM_VMINhq	= 2887,
    ARM_VMINsv16i8	= 2888,
    ARM_VMINsv2i32	= 2889,
    ARM_VMINsv4i16	= 2890,
    ARM_VMINsv4i32	= 2891,
    ARM_VMINsv8i16	= 2892,
    ARM_VMINsv8i8	= 2893,
    ARM_VMINuv16i8	= 2894,
    ARM_VMINuv2i32	= 2895,
    ARM_VMINuv4i16	= 2896,
    ARM_VMINuv4i32	= 2897,
    ARM_VMINuv8i16	= 2898,
    ARM_VMINuv8i8	= 2899,
    ARM_VMLAD	= 2900,
    ARM_VMLAH	= 2901,
    ARM_VMLALslsv2i32	= 2902,
    ARM_VMLALslsv4i16	= 2903,
    ARM_VMLALsluv2i32	= 2904,
    ARM_VMLALsluv4i16	= 2905,
    ARM_VMLALsv2i64	= 2906,
    ARM_VMLALsv4i32	= 2907,
    ARM_VMLALsv8i16	= 2908,
    ARM_VMLALuv2i64	= 2909,
    ARM_VMLALuv4i32	= 2910,
    ARM_VMLALuv8i16	= 2911,
    ARM_VMLAS	= 2912,
    ARM_VMLAfd	= 2913,
    ARM_VMLAfq	= 2914,
    ARM_VMLAhd	= 2915,
    ARM_VMLAhq	= 2916,
    ARM_VMLAslfd	= 2917,
    ARM_VMLAslfq	= 2918,
    ARM_VMLAslhd	= 2919,
    ARM_VMLAslhq	= 2920,
    ARM_VMLAslv2i32	= 2921,
    ARM_VMLAslv4i16	= 2922,
    ARM_VMLAslv4i32	= 2923,
    ARM_VMLAslv8i16	= 2924,
    ARM_VMLAv16i8	= 2925,
    ARM_VMLAv2i32	= 2926,
    ARM_VMLAv4i16	= 2927,
    ARM_VMLAv4i32	= 2928,
    ARM_VMLAv8i16	= 2929,
    ARM_VMLAv8i8	= 2930,
    ARM_VMLSD	= 2931,
    ARM_VMLSH	= 2932,
    ARM_VMLSLslsv2i32	= 2933,
    ARM_VMLSLslsv4i16	= 2934,
    ARM_VMLSLsluv2i32	= 2935,
    ARM_VMLSLsluv4i16	= 2936,
    ARM_VMLSLsv2i64	= 2937,
    ARM_VMLSLsv4i32	= 2938,
    ARM_VMLSLsv8i16	= 2939,
    ARM_VMLSLuv2i64	= 2940,
    ARM_VMLSLuv4i32	= 2941,
    ARM_VMLSLuv8i16	= 2942,
    ARM_VMLSS	= 2943,
    ARM_VMLSfd	= 2944,
    ARM_VMLSfq	= 2945,
    ARM_VMLShd	= 2946,
    ARM_VMLShq	= 2947,
    ARM_VMLSslfd	= 2948,
    ARM_VMLSslfq	= 2949,
    ARM_VMLSslhd	= 2950,
    ARM_VMLSslhq	= 2951,
    ARM_VMLSslv2i32	= 2952,
    ARM_VMLSslv4i16	= 2953,
    ARM_VMLSslv4i32	= 2954,
    ARM_VMLSslv8i16	= 2955,
    ARM_VMLSv16i8	= 2956,
    ARM_VMLSv2i32	= 2957,
    ARM_VMLSv4i16	= 2958,
    ARM_VMLSv4i32	= 2959,
    ARM_VMLSv8i16	= 2960,
    ARM_VMLSv8i8	= 2961,
    ARM_VMMLA	= 2962,
    ARM_VMOVD	= 2963,
    ARM_VMOVDRR	= 2964,
    ARM_VMOVH	= 2965,
    ARM_VMOVHR	= 2966,
    ARM_VMOVLsv2i64	= 2967,
    ARM_VMOVLsv4i32	= 2968,
    ARM_VMOVLsv8i16	= 2969,
    ARM_VMOVLuv2i64	= 2970,
    ARM_VMOVLuv4i32	= 2971,
    ARM_VMOVLuv8i16	= 2972,
    ARM_VMOVNv2i32	= 2973,
    ARM_VMOVNv4i16	= 2974,
    ARM_VMOVNv8i8	= 2975,
    ARM_VMOVRH	= 2976,
    ARM_VMOVRRD	= 2977,
    ARM_VMOVRRS	= 2978,
    ARM_VMOVRS	= 2979,
    ARM_VMOVS	= 2980,
    ARM_VMOVSR	= 2981,
    ARM_VMOVSRR	= 2982,
    ARM_VMOVv16i8	= 2983,
    ARM_VMOVv1i64	= 2984,
    ARM_VMOVv2f32	= 2985,
    ARM_VMOVv2i32	= 2986,
    ARM_VMOVv2i64	= 2987,
    ARM_VMOVv4f32	= 2988,
    ARM_VMOVv4i16	= 2989,
    ARM_VMOVv4i32	= 2990,
    ARM_VMOVv8i16	= 2991,
    ARM_VMOVv8i8	= 2992,
    ARM_VMRS	= 2993,
    ARM_VMRS_FPCXTNS	= 2994,
    ARM_VMRS_FPCXTS	= 2995,
    ARM_VMRS_FPEXC	= 2996,
    ARM_VMRS_FPINST	= 2997,
    ARM_VMRS_FPINST2	= 2998,
    ARM_VMRS_FPSCR_NZCVQC	= 2999,
    ARM_VMRS_FPSID	= 3000,
    ARM_VMRS_MVFR0	= 3001,
    ARM_VMRS_MVFR1	= 3002,
    ARM_VMRS_MVFR2	= 3003,
    ARM_VMRS_P0	= 3004,
    ARM_VMRS_VPR	= 3005,
    ARM_VMSR	= 3006,
    ARM_VMSR_FPCXTNS	= 3007,
    ARM_VMSR_FPCXTS	= 3008,
    ARM_VMSR_FPEXC	= 3009,
    ARM_VMSR_FPINST	= 3010,
    ARM_VMSR_FPINST2	= 3011,
    ARM_VMSR_FPSCR_NZCVQC	= 3012,
    ARM_VMSR_FPSID	= 3013,
    ARM_VMSR_P0	= 3014,
    ARM_VMSR_VPR	= 3015,
    ARM_VMULD	= 3016,
    ARM_VMULH	= 3017,
    ARM_VMULLp64	= 3018,
    ARM_VMULLp8	= 3019,
    ARM_VMULLslsv2i32	= 3020,
    ARM_VMULLslsv4i16	= 3021,
    ARM_VMULLsluv2i32	= 3022,
    ARM_VMULLsluv4i16	= 3023,
    ARM_VMULLsv2i64	= 3024,
    ARM_VMULLsv4i32	= 3025,
    ARM_VMULLsv8i16	= 3026,
    ARM_VMULLuv2i64	= 3027,
    ARM_VMULLuv4i32	= 3028,
    ARM_VMULLuv8i16	= 3029,
    ARM_VMULS	= 3030,
    ARM_VMULfd	= 3031,
    ARM_VMULfq	= 3032,
    ARM_VMULhd	= 3033,
    ARM_VMULhq	= 3034,
    ARM_VMULpd	= 3035,
    ARM_VMULpq	= 3036,
    ARM_VMULslfd	= 3037,
    ARM_VMULslfq	= 3038,
    ARM_VMULslhd	= 3039,
    ARM_VMULslhq	= 3040,
    ARM_VMULslv2i32	= 3041,
    ARM_VMULslv4i16	= 3042,
    ARM_VMULslv4i32	= 3043,
    ARM_VMULslv8i16	= 3044,
    ARM_VMULv16i8	= 3045,
    ARM_VMULv2i32	= 3046,
    ARM_VMULv4i16	= 3047,
    ARM_VMULv4i32	= 3048,
    ARM_VMULv8i16	= 3049,
    ARM_VMULv8i8	= 3050,
    ARM_VMVNd	= 3051,
    ARM_VMVNq	= 3052,
    ARM_VMVNv2i32	= 3053,
    ARM_VMVNv4i16	= 3054,
    ARM_VMVNv4i32	= 3055,
    ARM_VMVNv8i16	= 3056,
    ARM_VNEGD	= 3057,
    ARM_VNEGH	= 3058,
    ARM_VNEGS	= 3059,
    ARM_VNEGf32q	= 3060,
    ARM_VNEGfd	= 3061,
    ARM_VNEGhd	= 3062,
    ARM_VNEGhq	= 3063,
    ARM_VNEGs16d	= 3064,
    ARM_VNEGs16q	= 3065,
    ARM_VNEGs32d	= 3066,
    ARM_VNEGs32q	= 3067,
    ARM_VNEGs8d	= 3068,
    ARM_VNEGs8q	= 3069,
    ARM_VNMLAD	= 3070,
    ARM_VNMLAH	= 3071,
    ARM_VNMLAS	= 3072,
    ARM_VNMLSD	= 3073,
    ARM_VNMLSH	= 3074,
    ARM_VNMLSS	= 3075,
    ARM_VNMULD	= 3076,
    ARM_VNMULH	= 3077,
    ARM_VNMULS	= 3078,
    ARM_VORNd	= 3079,
    ARM_VORNq	= 3080,
    ARM_VORRd	= 3081,
    ARM_VORRiv2i32	= 3082,
    ARM_VORRiv4i16	= 3083,
    ARM_VORRiv4i32	= 3084,
    ARM_VORRiv8i16	= 3085,
    ARM_VORRq	= 3086,
    ARM_VPADALsv16i8	= 3087,
    ARM_VPADALsv2i32	= 3088,
    ARM_VPADALsv4i16	= 3089,
    ARM_VPADALsv4i32	= 3090,
    ARM_VPADALsv8i16	= 3091,
    ARM_VPADALsv8i8	= 3092,
    ARM_VPADALuv16i8	= 3093,
    ARM_VPADALuv2i32	= 3094,
    ARM_VPADALuv4i16	= 3095,
    ARM_VPADALuv4i32	= 3096,
    ARM_VPADALuv8i16	= 3097,
    ARM_VPADALuv8i8	= 3098,
    ARM_VPADDLsv16i8	= 3099,
    ARM_VPADDLsv2i32	= 3100,
    ARM_VPADDLsv4i16	= 3101,
    ARM_VPADDLsv4i32	= 3102,
    ARM_VPADDLsv8i16	= 3103,
    ARM_VPADDLsv8i8	= 3104,
    ARM_VPADDLuv16i8	= 3105,
    ARM_VPADDLuv2i32	= 3106,
    ARM_VPADDLuv4i16	= 3107,
    ARM_VPADDLuv4i32	= 3108,
    ARM_VPADDLuv8i16	= 3109,
    ARM_VPADDLuv8i8	= 3110,
    ARM_VPADDf	= 3111,
    ARM_VPADDh	= 3112,
    ARM_VPADDi16	= 3113,
    ARM_VPADDi32	= 3114,
    ARM_VPADDi8	= 3115,
    ARM_VPMAXf	= 3116,
    ARM_VPMAXh	= 3117,
    ARM_VPMAXs16	= 3118,
    ARM_VPMAXs32	= 3119,
    ARM_VPMAXs8	= 3120,
    ARM_VPMAXu16	= 3121,
    ARM_VPMAXu32	= 3122,
    ARM_VPMAXu8	= 3123,
    ARM_VPMINf	= 3124,
    ARM_VPMINh	= 3125,
    ARM_VPMINs16	= 3126,
    ARM_VPMINs32	= 3127,
    ARM_VPMINs8	= 3128,
    ARM_VPMINu16	= 3129,
    ARM_VPMINu32	= 3130,
    ARM_VPMINu8	= 3131,
    ARM_VQABSv16i8	= 3132,
    ARM_VQABSv2i32	= 3133,
    ARM_VQABSv4i16	= 3134,
    ARM_VQABSv4i32	= 3135,
    ARM_VQABSv8i16	= 3136,
    ARM_VQABSv8i8	= 3137,
    ARM_VQADDsv16i8	= 3138,
    ARM_VQADDsv1i64	= 3139,
    ARM_VQADDsv2i32	= 3140,
    ARM_VQADDsv2i64	= 3141,
    ARM_VQADDsv4i16	= 3142,
    ARM_VQADDsv4i32	= 3143,
    ARM_VQADDsv8i16	= 3144,
    ARM_VQADDsv8i8	= 3145,
    ARM_VQADDuv16i8	= 3146,
    ARM_VQADDuv1i64	= 3147,
    ARM_VQADDuv2i32	= 3148,
    ARM_VQADDuv2i64	= 3149,
    ARM_VQADDuv4i16	= 3150,
    ARM_VQADDuv4i32	= 3151,
    ARM_VQADDuv8i16	= 3152,
    ARM_VQADDuv8i8	= 3153,
    ARM_VQDMLALslv2i32	= 3154,
    ARM_VQDMLALslv4i16	= 3155,
    ARM_VQDMLALv2i64	= 3156,
    ARM_VQDMLALv4i32	= 3157,
    ARM_VQDMLSLslv2i32	= 3158,
    ARM_VQDMLSLslv4i16	= 3159,
    ARM_VQDMLSLv2i64	= 3160,
    ARM_VQDMLSLv4i32	= 3161,
    ARM_VQDMULHslv2i32	= 3162,
    ARM_VQDMULHslv4i16	= 3163,
    ARM_VQDMULHslv4i32	= 3164,
    ARM_VQDMULHslv8i16	= 3165,
    ARM_VQDMULHv2i32	= 3166,
    ARM_VQDMULHv4i16	= 3167,
    ARM_VQDMULHv4i32	= 3168,
    ARM_VQDMULHv8i16	= 3169,
    ARM_VQDMULLslv2i32	= 3170,
    ARM_VQDMULLslv4i16	= 3171,
    ARM_VQDMULLv2i64	= 3172,
    ARM_VQDMULLv4i32	= 3173,
    ARM_VQMOVNsuv2i32	= 3174,
    ARM_VQMOVNsuv4i16	= 3175,
    ARM_VQMOVNsuv8i8	= 3176,
    ARM_VQMOVNsv2i32	= 3177,
    ARM_VQMOVNsv4i16	= 3178,
    ARM_VQMOVNsv8i8	= 3179,
    ARM_VQMOVNuv2i32	= 3180,
    ARM_VQMOVNuv4i16	= 3181,
    ARM_VQMOVNuv8i8	= 3182,
    ARM_VQNEGv16i8	= 3183,
    ARM_VQNEGv2i32	= 3184,
    ARM_VQNEGv4i16	= 3185,
    ARM_VQNEGv4i32	= 3186,
    ARM_VQNEGv8i16	= 3187,
    ARM_VQNEGv8i8	= 3188,
    ARM_VQRDMLAHslv2i32	= 3189,
    ARM_VQRDMLAHslv4i16	= 3190,
    ARM_VQRDMLAHslv4i32	= 3191,
    ARM_VQRDMLAHslv8i16	= 3192,
    ARM_VQRDMLAHv2i32	= 3193,
    ARM_VQRDMLAHv4i16	= 3194,
    ARM_VQRDMLAHv4i32	= 3195,
    ARM_VQRDMLAHv8i16	= 3196,
    ARM_VQRDMLSHslv2i32	= 3197,
    ARM_VQRDMLSHslv4i16	= 3198,
    ARM_VQRDMLSHslv4i32	= 3199,
    ARM_VQRDMLSHslv8i16	= 3200,
    ARM_VQRDMLSHv2i32	= 3201,
    ARM_VQRDMLSHv4i16	= 3202,
    ARM_VQRDMLSHv4i32	= 3203,
    ARM_VQRDMLSHv8i16	= 3204,
    ARM_VQRDMULHslv2i32	= 3205,
    ARM_VQRDMULHslv4i16	= 3206,
    ARM_VQRDMULHslv4i32	= 3207,
    ARM_VQRDMULHslv8i16	= 3208,
    ARM_VQRDMULHv2i32	= 3209,
    ARM_VQRDMULHv4i16	= 3210,
    ARM_VQRDMULHv4i32	= 3211,
    ARM_VQRDMULHv8i16	= 3212,
    ARM_VQRSHLsv16i8	= 3213,
    ARM_VQRSHLsv1i64	= 3214,
    ARM_VQRSHLsv2i32	= 3215,
    ARM_VQRSHLsv2i64	= 3216,
    ARM_VQRSHLsv4i16	= 3217,
    ARM_VQRSHLsv4i32	= 3218,
    ARM_VQRSHLsv8i16	= 3219,
    ARM_VQRSHLsv8i8	= 3220,
    ARM_VQRSHLuv16i8	= 3221,
    ARM_VQRSHLuv1i64	= 3222,
    ARM_VQRSHLuv2i32	= 3223,
    ARM_VQRSHLuv2i64	= 3224,
    ARM_VQRSHLuv4i16	= 3225,
    ARM_VQRSHLuv4i32	= 3226,
    ARM_VQRSHLuv8i16	= 3227,
    ARM_VQRSHLuv8i8	= 3228,
    ARM_VQRSHRNsv2i32	= 3229,
    ARM_VQRSHRNsv4i16	= 3230,
    ARM_VQRSHRNsv8i8	= 3231,
    ARM_VQRSHRNuv2i32	= 3232,
    ARM_VQRSHRNuv4i16	= 3233,
    ARM_VQRSHRNuv8i8	= 3234,
    ARM_VQRSHRUNv2i32	= 3235,
    ARM_VQRSHRUNv4i16	= 3236,
    ARM_VQRSHRUNv8i8	= 3237,
    ARM_VQSHLsiv16i8	= 3238,
    ARM_VQSHLsiv1i64	= 3239,
    ARM_VQSHLsiv2i32	= 3240,
    ARM_VQSHLsiv2i64	= 3241,
    ARM_VQSHLsiv4i16	= 3242,
    ARM_VQSHLsiv4i32	= 3243,
    ARM_VQSHLsiv8i16	= 3244,
    ARM_VQSHLsiv8i8	= 3245,
    ARM_VQSHLsuv16i8	= 3246,
    ARM_VQSHLsuv1i64	= 3247,
    ARM_VQSHLsuv2i32	= 3248,
    ARM_VQSHLsuv2i64	= 3249,
    ARM_VQSHLsuv4i16	= 3250,
    ARM_VQSHLsuv4i32	= 3251,
    ARM_VQSHLsuv8i16	= 3252,
    ARM_VQSHLsuv8i8	= 3253,
    ARM_VQSHLsv16i8	= 3254,
    ARM_VQSHLsv1i64	= 3255,
    ARM_VQSHLsv2i32	= 3256,
    ARM_VQSHLsv2i64	= 3257,
    ARM_VQSHLsv4i16	= 3258,
    ARM_VQSHLsv4i32	= 3259,
    ARM_VQSHLsv8i16	= 3260,
    ARM_VQSHLsv8i8	= 3261,
    ARM_VQSHLuiv16i8	= 3262,
    ARM_VQSHLuiv1i64	= 3263,
    ARM_VQSHLuiv2i32	= 3264,
    ARM_VQSHLuiv2i64	= 3265,
    ARM_VQSHLuiv4i16	= 3266,
    ARM_VQSHLuiv4i32	= 3267,
    ARM_VQSHLuiv8i16	= 3268,
    ARM_VQSHLuiv8i8	= 3269,
    ARM_VQSHLuv16i8	= 3270,
    ARM_VQSHLuv1i64	= 3271,
    ARM_VQSHLuv2i32	= 3272,
    ARM_VQSHLuv2i64	= 3273,
    ARM_VQSHLuv4i16	= 3274,
    ARM_VQSHLuv4i32	= 3275,
    ARM_VQSHLuv8i16	= 3276,
    ARM_VQSHLuv8i8	= 3277,
    ARM_VQSHRNsv2i32	= 3278,
    ARM_VQSHRNsv4i16	= 3279,
    ARM_VQSHRNsv8i8	= 3280,
    ARM_VQSHRNuv2i32	= 3281,
    ARM_VQSHRNuv4i16	= 3282,
    ARM_VQSHRNuv8i8	= 3283,
    ARM_VQSHRUNv2i32	= 3284,
    ARM_VQSHRUNv4i16	= 3285,
    ARM_VQSHRUNv8i8	= 3286,
    ARM_VQSUBsv16i8	= 3287,
    ARM_VQSUBsv1i64	= 3288,
    ARM_VQSUBsv2i32	= 3289,
    ARM_VQSUBsv2i64	= 3290,
    ARM_VQSUBsv4i16	= 3291,
    ARM_VQSUBsv4i32	= 3292,
    ARM_VQSUBsv8i16	= 3293,
    ARM_VQSUBsv8i8	= 3294,
    ARM_VQSUBuv16i8	= 3295,
    ARM_VQSUBuv1i64	= 3296,
    ARM_VQSUBuv2i32	= 3297,
    ARM_VQSUBuv2i64	= 3298,
    ARM_VQSUBuv4i16	= 3299,
    ARM_VQSUBuv4i32	= 3300,
    ARM_VQSUBuv8i16	= 3301,
    ARM_VQSUBuv8i8	= 3302,
    ARM_VRADDHNv2i32	= 3303,
    ARM_VRADDHNv4i16	= 3304,
    ARM_VRADDHNv8i8	= 3305,
    ARM_VRECPEd	= 3306,
    ARM_VRECPEfd	= 3307,
    ARM_VRECPEfq	= 3308,
    ARM_VRECPEhd	= 3309,
    ARM_VRECPEhq	= 3310,
    ARM_VRECPEq	= 3311,
    ARM_VRECPSfd	= 3312,
    ARM_VRECPSfq	= 3313,
    ARM_VRECPShd	= 3314,
    ARM_VRECPShq	= 3315,
    ARM_VREV16d8	= 3316,
    ARM_VREV16q8	= 3317,
    ARM_VREV32d16	= 3318,
    ARM_VREV32d8	= 3319,
    ARM_VREV32q16	= 3320,
    ARM_VREV32q8	= 3321,
    ARM_VREV64d16	= 3322,
    ARM_VREV64d32	= 3323,
    ARM_VREV64d8	= 3324,
    ARM_VREV64q16	= 3325,
    ARM_VREV64q32	= 3326,
    ARM_VREV64q8	= 3327,
    ARM_VRHADDsv16i8	= 3328,
    ARM_VRHADDsv2i32	= 3329,
    ARM_VRHADDsv4i16	= 3330,
    ARM_VRHADDsv4i32	= 3331,
    ARM_VRHADDsv8i16	= 3332,
    ARM_VRHADDsv8i8	= 3333,
    ARM_VRHADDuv16i8	= 3334,
    ARM_VRHADDuv2i32	= 3335,
    ARM_VRHADDuv4i16	= 3336,
    ARM_VRHADDuv4i32	= 3337,
    ARM_VRHADDuv8i16	= 3338,
    ARM_VRHADDuv8i8	= 3339,
    ARM_VRINTAD	= 3340,
    ARM_VRINTAH	= 3341,
    ARM_VRINTANDf	= 3342,
    ARM_VRINTANDh	= 3343,
    ARM_VRINTANQf	= 3344,
    ARM_VRINTANQh	= 3345,
    ARM_VRINTAS	= 3346,
    ARM_VRINTMD	= 3347,
    ARM_VRINTMH	= 3348,
    ARM_VRINTMNDf	= 3349,
    ARM_VRINTMNDh	= 3350,
    ARM_VRINTMNQf	= 3351,
    ARM_VRINTMNQh	= 3352,
    ARM_VRINTMS	= 3353,
    ARM_VRINTND	= 3354,
    ARM_VRINTNH	= 3355,
    ARM_VRINTNNDf	= 3356,
    ARM_VRINTNNDh	= 3357,
    ARM_VRINTNNQf	= 3358,
    ARM_VRINTNNQh	= 3359,
    ARM_VRINTNS	= 3360,
    ARM_VRINTPD	= 3361,
    ARM_VRINTPH	= 3362,
    ARM_VRINTPNDf	= 3363,
    ARM_VRINTPNDh	= 3364,
    ARM_VRINTPNQf	= 3365,
    ARM_VRINTPNQh	= 3366,
    ARM_VRINTPS	= 3367,
    ARM_VRINTRD	= 3368,
    ARM_VRINTRH	= 3369,
    ARM_VRINTRS	= 3370,
    ARM_VRINTXD	= 3371,
    ARM_VRINTXH	= 3372,
    ARM_VRINTXNDf	= 3373,
    ARM_VRINTXNDh	= 3374,
    ARM_VRINTXNQf	= 3375,
    ARM_VRINTXNQh	= 3376,
    ARM_VRINTXS	= 3377,
    ARM_VRINTZD	= 3378,
    ARM_VRINTZH	= 3379,
    ARM_VRINTZNDf	= 3380,
    ARM_VRINTZNDh	= 3381,
    ARM_VRINTZNQf	= 3382,
    ARM_VRINTZNQh	= 3383,
    ARM_VRINTZS	= 3384,
    ARM_VRSHLsv16i8	= 3385,
    ARM_VRSHLsv1i64	= 3386,
    ARM_VRSHLsv2i32	= 3387,
    ARM_VRSHLsv2i64	= 3388,
    ARM_VRSHLsv4i16	= 3389,
    ARM_VRSHLsv4i32	= 3390,
    ARM_VRSHLsv8i16	= 3391,
    ARM_VRSHLsv8i8	= 3392,
    ARM_VRSHLuv16i8	= 3393,
    ARM_VRSHLuv1i64	= 3394,
    ARM_VRSHLuv2i32	= 3395,
    ARM_VRSHLuv2i64	= 3396,
    ARM_VRSHLuv4i16	= 3397,
    ARM_VRSHLuv4i32	= 3398,
    ARM_VRSHLuv8i16	= 3399,
    ARM_VRSHLuv8i8	= 3400,
    ARM_VRSHRNv2i32	= 3401,
    ARM_VRSHRNv4i16	= 3402,
    ARM_VRSHRNv8i8	= 3403,
    ARM_VRSHRsv16i8	= 3404,
    ARM_VRSHRsv1i64	= 3405,
    ARM_VRSHRsv2i32	= 3406,
    ARM_VRSHRsv2i64	= 3407,
    ARM_VRSHRsv4i16	= 3408,
    ARM_VRSHRsv4i32	= 3409,
    ARM_VRSHRsv8i16	= 3410,
    ARM_VRSHRsv8i8	= 3411,
    ARM_VRSHRuv16i8	= 3412,
    ARM_VRSHRuv1i64	= 3413,
    ARM_VRSHRuv2i32	= 3414,
    ARM_VRSHRuv2i64	= 3415,
    ARM_VRSHRuv4i16	= 3416,
    ARM_VRSHRuv4i32	= 3417,
    ARM_VRSHRuv8i16	= 3418,
    ARM_VRSHRuv8i8	= 3419,
    ARM_VRSQRTEd	= 3420,
    ARM_VRSQRTEfd	= 3421,
    ARM_VRSQRTEfq	= 3422,
    ARM_VRSQRTEhd	= 3423,
    ARM_VRSQRTEhq	= 3424,
    ARM_VRSQRTEq	= 3425,
    ARM_VRSQRTSfd	= 3426,
    ARM_VRSQRTSfq	= 3427,
    ARM_VRSQRTShd	= 3428,
    ARM_VRSQRTShq	= 3429,
    ARM_VRSRAsv16i8	= 3430,
    ARM_VRSRAsv1i64	= 3431,
    ARM_VRSRAsv2i32	= 3432,
    ARM_VRSRAsv2i64	= 3433,
    ARM_VRSRAsv4i16	= 3434,
    ARM_VRSRAsv4i32	= 3435,
    ARM_VRSRAsv8i16	= 3436,
    ARM_VRSRAsv8i8	= 3437,
    ARM_VRSRAuv16i8	= 3438,
    ARM_VRSRAuv1i64	= 3439,
    ARM_VRSRAuv2i32	= 3440,
    ARM_VRSRAuv2i64	= 3441,
    ARM_VRSRAuv4i16	= 3442,
    ARM_VRSRAuv4i32	= 3443,
    ARM_VRSRAuv8i16	= 3444,
    ARM_VRSRAuv8i8	= 3445,
    ARM_VRSUBHNv2i32	= 3446,
    ARM_VRSUBHNv4i16	= 3447,
    ARM_VRSUBHNv8i8	= 3448,
    ARM_VSCCLRMD	= 3449,
    ARM_VSCCLRMS	= 3450,
    ARM_VSDOTD	= 3451,
    ARM_VSDOTDI	= 3452,
    ARM_VSDOTQ	= 3453,
    ARM_VSDOTQI	= 3454,
    ARM_VSELEQD	= 3455,
    ARM_VSELEQH	= 3456,
    ARM_VSELEQS	= 3457,
    ARM_VSELGED	= 3458,
    ARM_VSELGEH	= 3459,
    ARM_VSELGES	= 3460,
    ARM_VSELGTD	= 3461,
    ARM_VSELGTH	= 3462,
    ARM_VSELGTS	= 3463,
    ARM_VSELVSD	= 3464,
    ARM_VSELVSH	= 3465,
    ARM_VSELVSS	= 3466,
    ARM_VSETLNi16	= 3467,
    ARM_VSETLNi32	= 3468,
    ARM_VSETLNi8	= 3469,
    ARM_VSHLLi16	= 3470,
    ARM_VSHLLi32	= 3471,
    ARM_VSHLLi8	= 3472,
    ARM_VSHLLsv2i64	= 3473,
    ARM_VSHLLsv4i32	= 3474,
    ARM_VSHLLsv8i16	= 3475,
    ARM_VSHLLuv2i64	= 3476,
    ARM_VSHLLuv4i32	= 3477,
    ARM_VSHLLuv8i16	= 3478,
    ARM_VSHLiv16i8	= 3479,
    ARM_VSHLiv1i64	= 3480,
    ARM_VSHLiv2i32	= 3481,
    ARM_VSHLiv2i64	= 3482,
    ARM_VSHLiv4i16	= 3483,
    ARM_VSHLiv4i32	= 3484,
    ARM_VSHLiv8i16	= 3485,
    ARM_VSHLiv8i8	= 3486,
    ARM_VSHLsv16i8	= 3487,
    ARM_VSHLsv1i64	= 3488,
    ARM_VSHLsv2i32	= 3489,
    ARM_VSHLsv2i64	= 3490,
    ARM_VSHLsv4i16	= 3491,
    ARM_VSHLsv4i32	= 3492,
    ARM_VSHLsv8i16	= 3493,
    ARM_VSHLsv8i8	= 3494,
    ARM_VSHLuv16i8	= 3495,
    ARM_VSHLuv1i64	= 3496,
    ARM_VSHLuv2i32	= 3497,
    ARM_VSHLuv2i64	= 3498,
    ARM_VSHLuv4i16	= 3499,
    ARM_VSHLuv4i32	= 3500,
    ARM_VSHLuv8i16	= 3501,
    ARM_VSHLuv8i8	= 3502,
    ARM_VSHRNv2i32	= 3503,
    ARM_VSHRNv4i16	= 3504,
    ARM_VSHRNv8i8	= 3505,
    ARM_VSHRsv16i8	= 3506,
    ARM_VSHRsv1i64	= 3507,
    ARM_VSHRsv2i32	= 3508,
    ARM_VSHRsv2i64	= 3509,
    ARM_VSHRsv4i16	= 3510,
    ARM_VSHRsv4i32	= 3511,
    ARM_VSHRsv8i16	= 3512,
    ARM_VSHRsv8i8	= 3513,
    ARM_VSHRuv16i8	= 3514,
    ARM_VSHRuv1i64	= 3515,
    ARM_VSHRuv2i32	= 3516,
    ARM_VSHRuv2i64	= 3517,
    ARM_VSHRuv4i16	= 3518,
    ARM_VSHRuv4i32	= 3519,
    ARM_VSHRuv8i16	= 3520,
    ARM_VSHRuv8i8	= 3521,
    ARM_VSHTOD	= 3522,
    ARM_VSHTOH	= 3523,
    ARM_VSHTOS	= 3524,
    ARM_VSITOD	= 3525,
    ARM_VSITOH	= 3526,
    ARM_VSITOS	= 3527,
    ARM_VSLIv16i8	= 3528,
    ARM_VSLIv1i64	= 3529,
    ARM_VSLIv2i32	= 3530,
    ARM_VSLIv2i64	= 3531,
    ARM_VSLIv4i16	= 3532,
    ARM_VSLIv4i32	= 3533,
    ARM_VSLIv8i16	= 3534,
    ARM_VSLIv8i8	= 3535,
    ARM_VSLTOD	= 3536,
    ARM_VSLTOH	= 3537,
    ARM_VSLTOS	= 3538,
    ARM_VSMMLA	= 3539,
    ARM_VSQRTD	= 3540,
    ARM_VSQRTH	= 3541,
    ARM_VSQRTS	= 3542,
    ARM_VSRAsv16i8	= 3543,
    ARM_VSRAsv1i64	= 3544,
    ARM_VSRAsv2i32	= 3545,
    ARM_VSRAsv2i64	= 3546,
    ARM_VSRAsv4i16	= 3547,
    ARM_VSRAsv4i32	= 3548,
    ARM_VSRAsv8i16	= 3549,
    ARM_VSRAsv8i8	= 3550,
    ARM_VSRAuv16i8	= 3551,
    ARM_VSRAuv1i64	= 3552,
    ARM_VSRAuv2i32	= 3553,
    ARM_VSRAuv2i64	= 3554,
    ARM_VSRAuv4i16	= 3555,
    ARM_VSRAuv4i32	= 3556,
    ARM_VSRAuv8i16	= 3557,
    ARM_VSRAuv8i8	= 3558,
    ARM_VSRIv16i8	= 3559,
    ARM_VSRIv1i64	= 3560,
    ARM_VSRIv2i32	= 3561,
    ARM_VSRIv2i64	= 3562,
    ARM_VSRIv4i16	= 3563,
    ARM_VSRIv4i32	= 3564,
    ARM_VSRIv8i16	= 3565,
    ARM_VSRIv8i8	= 3566,
    ARM_VST1LNd16	= 3567,
    ARM_VST1LNd16_UPD	= 3568,
    ARM_VST1LNd32	= 3569,
    ARM_VST1LNd32_UPD	= 3570,
    ARM_VST1LNd8	= 3571,
    ARM_VST1LNd8_UPD	= 3572,
    ARM_VST1LNq16Pseudo	= 3573,
    ARM_VST1LNq16Pseudo_UPD	= 3574,
    ARM_VST1LNq32Pseudo	= 3575,
    ARM_VST1LNq32Pseudo_UPD	= 3576,
    ARM_VST1LNq8Pseudo	= 3577,
    ARM_VST1LNq8Pseudo_UPD	= 3578,
    ARM_VST1d16	= 3579,
    ARM_VST1d16Q	= 3580,
    ARM_VST1d16QPseudo	= 3581,
    ARM_VST1d16QPseudoWB_fixed	= 3582,
    ARM_VST1d16QPseudoWB_register	= 3583,
    ARM_VST1d16Qwb_fixed	= 3584,
    ARM_VST1d16Qwb_register	= 3585,
    ARM_VST1d16T	= 3586,
    ARM_VST1d16TPseudo	= 3587,
    ARM_VST1d16TPseudoWB_fixed	= 3588,
    ARM_VST1d16TPseudoWB_register	= 3589,
    ARM_VST1d16Twb_fixed	= 3590,
    ARM_VST1d16Twb_register	= 3591,
    ARM_VST1d16wb_fixed	= 3592,
    ARM_VST1d16wb_register	= 3593,
    ARM_VST1d32	= 3594,
    ARM_VST1d32Q	= 3595,
    ARM_VST1d32QPseudo	= 3596,
    ARM_VST1d32QPseudoWB_fixed	= 3597,
    ARM_VST1d32QPseudoWB_register	= 3598,
    ARM_VST1d32Qwb_fixed	= 3599,
    ARM_VST1d32Qwb_register	= 3600,
    ARM_VST1d32T	= 3601,
    ARM_VST1d32TPseudo	= 3602,
    ARM_VST1d32TPseudoWB_fixed	= 3603,
    ARM_VST1d32TPseudoWB_register	= 3604,
    ARM_VST1d32Twb_fixed	= 3605,
    ARM_VST1d32Twb_register	= 3606,
    ARM_VST1d32wb_fixed	= 3607,
    ARM_VST1d32wb_register	= 3608,
    ARM_VST1d64	= 3609,
    ARM_VST1d64Q	= 3610,
    ARM_VST1d64QPseudo	= 3611,
    ARM_VST1d64QPseudoWB_fixed	= 3612,
    ARM_VST1d64QPseudoWB_register	= 3613,
    ARM_VST1d64Qwb_fixed	= 3614,
    ARM_VST1d64Qwb_register	= 3615,
    ARM_VST1d64T	= 3616,
    ARM_VST1d64TPseudo	= 3617,
    ARM_VST1d64TPseudoWB_fixed	= 3618,
    ARM_VST1d64TPseudoWB_register	= 3619,
    ARM_VST1d64Twb_fixed	= 3620,
    ARM_VST1d64Twb_register	= 3621,
    ARM_VST1d64wb_fixed	= 3622,
    ARM_VST1d64wb_register	= 3623,
    ARM_VST1d8	= 3624,
    ARM_VST1d8Q	= 3625,
    ARM_VST1d8QPseudo	= 3626,
    ARM_VST1d8QPseudoWB_fixed	= 3627,
    ARM_VST1d8QPseudoWB_register	= 3628,
    ARM_VST1d8Qwb_fixed	= 3629,
    ARM_VST1d8Qwb_register	= 3630,
    ARM_VST1d8T	= 3631,
    ARM_VST1d8TPseudo	= 3632,
    ARM_VST1d8TPseudoWB_fixed	= 3633,
    ARM_VST1d8TPseudoWB_register	= 3634,
    ARM_VST1d8Twb_fixed	= 3635,
    ARM_VST1d8Twb_register	= 3636,
    ARM_VST1d8wb_fixed	= 3637,
    ARM_VST1d8wb_register	= 3638,
    ARM_VST1q16	= 3639,
    ARM_VST1q16HighQPseudo	= 3640,
    ARM_VST1q16HighQPseudo_UPD	= 3641,
    ARM_VST1q16HighTPseudo	= 3642,
    ARM_VST1q16HighTPseudo_UPD	= 3643,
    ARM_VST1q16LowQPseudo_UPD	= 3644,
    ARM_VST1q16LowTPseudo_UPD	= 3645,
    ARM_VST1q16wb_fixed	= 3646,
    ARM_VST1q16wb_register	= 3647,
    ARM_VST1q32	= 3648,
    ARM_VST1q32HighQPseudo	= 3649,
    ARM_VST1q32HighQPseudo_UPD	= 3650,
    ARM_VST1q32HighTPseudo	= 3651,
    ARM_VST1q32HighTPseudo_UPD	= 3652,
    ARM_VST1q32LowQPseudo_UPD	= 3653,
    ARM_VST1q32LowTPseudo_UPD	= 3654,
    ARM_VST1q32wb_fixed	= 3655,
    ARM_VST1q32wb_register	= 3656,
    ARM_VST1q64	= 3657,
    ARM_VST1q64HighQPseudo	= 3658,
    ARM_VST1q64HighQPseudo_UPD	= 3659,
    ARM_VST1q64HighTPseudo	= 3660,
    ARM_VST1q64HighTPseudo_UPD	= 3661,
    ARM_VST1q64LowQPseudo_UPD	= 3662,
    ARM_VST1q64LowTPseudo_UPD	= 3663,
    ARM_VST1q64wb_fixed	= 3664,
    ARM_VST1q64wb_register	= 3665,
    ARM_VST1q8	= 3666,
    ARM_VST1q8HighQPseudo	= 3667,
    ARM_VST1q8HighQPseudo_UPD	= 3668,
    ARM_VST1q8HighTPseudo	= 3669,
    ARM_VST1q8HighTPseudo_UPD	= 3670,
    ARM_VST1q8LowQPseudo_UPD	= 3671,
    ARM_VST1q8LowTPseudo_UPD	= 3672,
    ARM_VST1q8wb_fixed	= 3673,
    ARM_VST1q8wb_register	= 3674,
    ARM_VST2LNd16	= 3675,
    ARM_VST2LNd16Pseudo	= 3676,
    ARM_VST2LNd16Pseudo_UPD	= 3677,
    ARM_VST2LNd16_UPD	= 3678,
    ARM_VST2LNd32	= 3679,
    ARM_VST2LNd32Pseudo	= 3680,
    ARM_VST2LNd32Pseudo_UPD	= 3681,
    ARM_VST2LNd32_UPD	= 3682,
    ARM_VST2LNd8	= 3683,
    ARM_VST2LNd8Pseudo	= 3684,
    ARM_VST2LNd8Pseudo_UPD	= 3685,
    ARM_VST2LNd8_UPD	= 3686,
    ARM_VST2LNq16	= 3687,
    ARM_VST2LNq16Pseudo	= 3688,
    ARM_VST2LNq16Pseudo_UPD	= 3689,
    ARM_VST2LNq16_UPD	= 3690,
    ARM_VST2LNq32	= 3691,
    ARM_VST2LNq32Pseudo	= 3692,
    ARM_VST2LNq32Pseudo_UPD	= 3693,
    ARM_VST2LNq32_UPD	= 3694,
    ARM_VST2b16	= 3695,
    ARM_VST2b16wb_fixed	= 3696,
    ARM_VST2b16wb_register	= 3697,
    ARM_VST2b32	= 3698,
    ARM_VST2b32wb_fixed	= 3699,
    ARM_VST2b32wb_register	= 3700,
    ARM_VST2b8	= 3701,
    ARM_VST2b8wb_fixed	= 3702,
    ARM_VST2b8wb_register	= 3703,
    ARM_VST2d16	= 3704,
    ARM_VST2d16wb_fixed	= 3705,
    ARM_VST2d16wb_register	= 3706,
    ARM_VST2d32	= 3707,
    ARM_VST2d32wb_fixed	= 3708,
    ARM_VST2d32wb_register	= 3709,
    ARM_VST2d8	= 3710,
    ARM_VST2d8wb_fixed	= 3711,
    ARM_VST2d8wb_register	= 3712,
    ARM_VST2q16	= 3713,
    ARM_VST2q16Pseudo	= 3714,
    ARM_VST2q16PseudoWB_fixed	= 3715,
    ARM_VST2q16PseudoWB_register	= 3716,
    ARM_VST2q16wb_fixed	= 3717,
    ARM_VST2q16wb_register	= 3718,
    ARM_VST2q32	= 3719,
    ARM_VST2q32Pseudo	= 3720,
    ARM_VST2q32PseudoWB_fixed	= 3721,
    ARM_VST2q32PseudoWB_register	= 3722,
    ARM_VST2q32wb_fixed	= 3723,
    ARM_VST2q32wb_register	= 3724,
    ARM_VST2q8	= 3725,
    ARM_VST2q8Pseudo	= 3726,
    ARM_VST2q8PseudoWB_fixed	= 3727,
    ARM_VST2q8PseudoWB_register	= 3728,
    ARM_VST2q8wb_fixed	= 3729,
    ARM_VST2q8wb_register	= 3730,
    ARM_VST3LNd16	= 3731,
    ARM_VST3LNd16Pseudo	= 3732,
    ARM_VST3LNd16Pseudo_UPD	= 3733,
    ARM_VST3LNd16_UPD	= 3734,
    ARM_VST3LNd32	= 3735,
    ARM_VST3LNd32Pseudo	= 3736,
    ARM_VST3LNd32Pseudo_UPD	= 3737,
    ARM_VST3LNd32_UPD	= 3738,
    ARM_VST3LNd8	= 3739,
    ARM_VST3LNd8Pseudo	= 3740,
    ARM_VST3LNd8Pseudo_UPD	= 3741,
    ARM_VST3LNd8_UPD	= 3742,
    ARM_VST3LNq16	= 3743,
    ARM_VST3LNq16Pseudo	= 3744,
    ARM_VST3LNq16Pseudo_UPD	= 3745,
    ARM_VST3LNq16_UPD	= 3746,
    ARM_VST3LNq32	= 3747,
    ARM_VST3LNq32Pseudo	= 3748,
    ARM_VST3LNq32Pseudo_UPD	= 3749,
    ARM_VST3LNq32_UPD	= 3750,
    ARM_VST3d16	= 3751,
    ARM_VST3d16Pseudo	= 3752,
    ARM_VST3d16Pseudo_UPD	= 3753,
    ARM_VST3d16_UPD	= 3754,
    ARM_VST3d32	= 3755,
    ARM_VST3d32Pseudo	= 3756,
    ARM_VST3d32Pseudo_UPD	= 3757,
    ARM_VST3d32_UPD	= 3758,
    ARM_VST3d8	= 3759,
    ARM_VST3d8Pseudo	= 3760,
    ARM_VST3d8Pseudo_UPD	= 3761,
    ARM_VST3d8_UPD	= 3762,
    ARM_VST3q16	= 3763,
    ARM_VST3q16Pseudo_UPD	= 3764,
    ARM_VST3q16_UPD	= 3765,
    ARM_VST3q16oddPseudo	= 3766,
    ARM_VST3q16oddPseudo_UPD	= 3767,
    ARM_VST3q32	= 3768,
    ARM_VST3q32Pseudo_UPD	= 3769,
    ARM_VST3q32_UPD	= 3770,
    ARM_VST3q32oddPseudo	= 3771,
    ARM_VST3q32oddPseudo_UPD	= 3772,
    ARM_VST3q8	= 3773,
    ARM_VST3q8Pseudo_UPD	= 3774,
    ARM_VST3q8_UPD	= 3775,
    ARM_VST3q8oddPseudo	= 3776,
    ARM_VST3q8oddPseudo_UPD	= 3777,
    ARM_VST4LNd16	= 3778,
    ARM_VST4LNd16Pseudo	= 3779,
    ARM_VST4LNd16Pseudo_UPD	= 3780,
    ARM_VST4LNd16_UPD	= 3781,
    ARM_VST4LNd32	= 3782,
    ARM_VST4LNd32Pseudo	= 3783,
    ARM_VST4LNd32Pseudo_UPD	= 3784,
    ARM_VST4LNd32_UPD	= 3785,
    ARM_VST4LNd8	= 3786,
    ARM_VST4LNd8Pseudo	= 3787,
    ARM_VST4LNd8Pseudo_UPD	= 3788,
    ARM_VST4LNd8_UPD	= 3789,
    ARM_VST4LNq16	= 3790,
    ARM_VST4LNq16Pseudo	= 3791,
    ARM_VST4LNq16Pseudo_UPD	= 3792,
    ARM_VST4LNq16_UPD	= 3793,
    ARM_VST4LNq32	= 3794,
    ARM_VST4LNq32Pseudo	= 3795,
    ARM_VST4LNq32Pseudo_UPD	= 3796,
    ARM_VST4LNq32_UPD	= 3797,
    ARM_VST4d16	= 3798,
    ARM_VST4d16Pseudo	= 3799,
    ARM_VST4d16Pseudo_UPD	= 3800,
    ARM_VST4d16_UPD	= 3801,
    ARM_VST4d32	= 3802,
    ARM_VST4d32Pseudo	= 3803,
    ARM_VST4d32Pseudo_UPD	= 3804,
    ARM_VST4d32_UPD	= 3805,
    ARM_VST4d8	= 3806,
    ARM_VST4d8Pseudo	= 3807,
    ARM_VST4d8Pseudo_UPD	= 3808,
    ARM_VST4d8_UPD	= 3809,
    ARM_VST4q16	= 3810,
    ARM_VST4q16Pseudo_UPD	= 3811,
    ARM_VST4q16_UPD	= 3812,
    ARM_VST4q16oddPseudo	= 3813,
    ARM_VST4q16oddPseudo_UPD	= 3814,
    ARM_VST4q32	= 3815,
    ARM_VST4q32Pseudo_UPD	= 3816,
    ARM_VST4q32_UPD	= 3817,
    ARM_VST4q32oddPseudo	= 3818,
    ARM_VST4q32oddPseudo_UPD	= 3819,
    ARM_VST4q8	= 3820,
    ARM_VST4q8Pseudo_UPD	= 3821,
    ARM_VST4q8_UPD	= 3822,
    ARM_VST4q8oddPseudo	= 3823,
    ARM_VST4q8oddPseudo_UPD	= 3824,
    ARM_VSTMDDB_UPD	= 3825,
    ARM_VSTMDIA	= 3826,
    ARM_VSTMDIA_UPD	= 3827,
    ARM_VSTMQIA	= 3828,
    ARM_VSTMSDB_UPD	= 3829,
    ARM_VSTMSIA	= 3830,
    ARM_VSTMSIA_UPD	= 3831,
    ARM_VSTRD	= 3832,
    ARM_VSTRH	= 3833,
    ARM_VSTRS	= 3834,
    ARM_VSTR_FPCXTNS_off	= 3835,
    ARM_VSTR_FPCXTNS_post	= 3836,
    ARM_VSTR_FPCXTNS_pre	= 3837,
    ARM_VSTR_FPCXTS_off	= 3838,
    ARM_VSTR_FPCXTS_post	= 3839,
    ARM_VSTR_FPCXTS_pre	= 3840,
    ARM_VSTR_FPSCR_NZCVQC_off	= 3841,
    ARM_VSTR_FPSCR_NZCVQC_post	= 3842,
    ARM_VSTR_FPSCR_NZCVQC_pre	= 3843,
    ARM_VSTR_FPSCR_off	= 3844,
    ARM_VSTR_FPSCR_post	= 3845,
    ARM_VSTR_FPSCR_pre	= 3846,
    ARM_VSTR_P0_off	= 3847,
    ARM_VSTR_P0_post	= 3848,
    ARM_VSTR_P0_pre	= 3849,
    ARM_VSTR_VPR_off	= 3850,
    ARM_VSTR_VPR_post	= 3851,
    ARM_VSTR_VPR_pre	= 3852,
    ARM_VSUBD	= 3853,
    ARM_VSUBH	= 3854,
    ARM_VSUBHNv2i32	= 3855,
    ARM_VSUBHNv4i16	= 3856,
    ARM_VSUBHNv8i8	= 3857,
    ARM_VSUBLsv2i64	= 3858,
    ARM_VSUBLsv4i32	= 3859,
    ARM_VSUBLsv8i16	= 3860,
    ARM_VSUBLuv2i64	= 3861,
    ARM_VSUBLuv4i32	= 3862,
    ARM_VSUBLuv8i16	= 3863,
    ARM_VSUBS	= 3864,
    ARM_VSUBWsv2i64	= 3865,
    ARM_VSUBWsv4i32	= 3866,
    ARM_VSUBWsv8i16	= 3867,
    ARM_VSUBWuv2i64	= 3868,
    ARM_VSUBWuv4i32	= 3869,
    ARM_VSUBWuv8i16	= 3870,
    ARM_VSUBfd	= 3871,
    ARM_VSUBfq	= 3872,
    ARM_VSUBhd	= 3873,
    ARM_VSUBhq	= 3874,
    ARM_VSUBv16i8	= 3875,
    ARM_VSUBv1i64	= 3876,
    ARM_VSUBv2i32	= 3877,
    ARM_VSUBv2i64	= 3878,
    ARM_VSUBv4i16	= 3879,
    ARM_VSUBv4i32	= 3880,
    ARM_VSUBv8i16	= 3881,
    ARM_VSUBv8i8	= 3882,
    ARM_VSUDOTDI	= 3883,
    ARM_VSUDOTQI	= 3884,
    ARM_VSWPd	= 3885,
    ARM_VSWPq	= 3886,
    ARM_VTBL1	= 3887,
    ARM_VTBL2	= 3888,
    ARM_VTBL3	= 3889,
    ARM_VTBL3Pseudo	= 3890,
    ARM_VTBL4	= 3891,
    ARM_VTBL4Pseudo	= 3892,
    ARM_VTBX1	= 3893,
    ARM_VTBX2	= 3894,
    ARM_VTBX3	= 3895,
    ARM_VTBX3Pseudo	= 3896,
    ARM_VTBX4	= 3897,
    ARM_VTBX4Pseudo	= 3898,
    ARM_VTOSHD	= 3899,
    ARM_VTOSHH	= 3900,
    ARM_VTOSHS	= 3901,
    ARM_VTOSIRD	= 3902,
    ARM_VTOSIRH	= 3903,
    ARM_VTOSIRS	= 3904,
    ARM_VTOSIZD	= 3905,
    ARM_VTOSIZH	= 3906,
    ARM_VTOSIZS	= 3907,
    ARM_VTOSLD	= 3908,
    ARM_VTOSLH	= 3909,
    ARM_VTOSLS	= 3910,
    ARM_VTOUHD	= 3911,
    ARM_VTOUHH	= 3912,
    ARM_VTOUHS	= 3913,
    ARM_VTOUIRD	= 3914,
    ARM_VTOUIRH	= 3915,
    ARM_VTOUIRS	= 3916,
    ARM_VTOUIZD	= 3917,
    ARM_VTOUIZH	= 3918,
    ARM_VTOUIZS	= 3919,
    ARM_VTOULD	= 3920,
    ARM_VTOULH	= 3921,
    ARM_VTOULS	= 3922,
    ARM_VTRNd16	= 3923,
    ARM_VTRNd32	= 3924,
    ARM_VTRNd8	= 3925,
    ARM_VTRNq16	= 3926,
    ARM_VTRNq32	= 3927,
    ARM_VTRNq8	= 3928,
    ARM_VTSTv16i8	= 3929,
    ARM_VTSTv2i32	= 3930,
    ARM_VTSTv4i16	= 3931,
    ARM_VTSTv4i32	= 3932,
    ARM_VTSTv8i16	= 3933,
    ARM_VTSTv8i8	= 3934,
    ARM_VUDOTD	= 3935,
    ARM_VUDOTDI	= 3936,
    ARM_VUDOTQ	= 3937,
    ARM_VUDOTQI	= 3938,
    ARM_VUHTOD	= 3939,
    ARM_VUHTOH	= 3940,
    ARM_VUHTOS	= 3941,
    ARM_VUITOD	= 3942,
    ARM_VUITOH	= 3943,
    ARM_VUITOS	= 3944,
    ARM_VULTOD	= 3945,
    ARM_VULTOH	= 3946,
    ARM_VULTOS	= 3947,
    ARM_VUMMLA	= 3948,
    ARM_VUSDOTD	= 3949,
    ARM_VUSDOTDI	= 3950,
    ARM_VUSDOTQ	= 3951,
    ARM_VUSDOTQI	= 3952,
    ARM_VUSMMLA	= 3953,
    ARM_VUZPd16	= 3954,
    ARM_VUZPd8	= 3955,
    ARM_VUZPq16	= 3956,
    ARM_VUZPq32	= 3957,
    ARM_VUZPq8	= 3958,
    ARM_VZIPd16	= 3959,
    ARM_VZIPd8	= 3960,
    ARM_VZIPq16	= 3961,
    ARM_VZIPq32	= 3962,
    ARM_VZIPq8	= 3963,
    ARM_sysLDMDA	= 3964,
    ARM_sysLDMDA_UPD	= 3965,
    ARM_sysLDMDB	= 3966,
    ARM_sysLDMDB_UPD	= 3967,
    ARM_sysLDMIA	= 3968,
    ARM_sysLDMIA_UPD	= 3969,
    ARM_sysLDMIB	= 3970,
    ARM_sysLDMIB_UPD	= 3971,
    ARM_sysSTMDA	= 3972,
    ARM_sysSTMDA_UPD	= 3973,
    ARM_sysSTMDB	= 3974,
    ARM_sysSTMDB_UPD	= 3975,
    ARM_sysSTMIA	= 3976,
    ARM_sysSTMIA_UPD	= 3977,
    ARM_sysSTMIB	= 3978,
    ARM_sysSTMIB_UPD	= 3979,
    ARM_t2ADCri	= 3980,
    ARM_t2ADCrr	= 3981,
    ARM_t2ADCrs	= 3982,
    ARM_t2ADDri	= 3983,
    ARM_t2ADDri12	= 3984,
    ARM_t2ADDrr	= 3985,
    ARM_t2ADDrs	= 3986,
    ARM_t2ADDspImm	= 3987,
    ARM_t2ADDspImm12	= 3988,
    ARM_t2ADR	= 3989,
    ARM_t2ANDri	= 3990,
    ARM_t2ANDrr	= 3991,
    ARM_t2ANDrs	= 3992,
    ARM_t2ASRri	= 3993,
    ARM_t2ASRrr	= 3994,
    ARM_t2AUT	= 3995,
    ARM_t2AUTG	= 3996,
    ARM_t2B	= 3997,
    ARM_t2BFC	= 3998,
    ARM_t2BFI	= 3999,
    ARM_t2BFLi	= 4000,
    ARM_t2BFLr	= 4001,
    ARM_t2BFi	= 4002,
    ARM_t2BFic	= 4003,
    ARM_t2BFr	= 4004,
    ARM_t2BICri	= 4005,
    ARM_t2BICrr	= 4006,
    ARM_t2BICrs	= 4007,
    ARM_t2BTI	= 4008,
    ARM_t2BXAUT	= 4009,
    ARM_t2BXJ	= 4010,
    ARM_t2Bcc	= 4011,
    ARM_t2CDP	= 4012,
    ARM_t2CDP2	= 4013,
    ARM_t2CLREX	= 4014,
    ARM_t2CLRM	= 4015,
    ARM_t2CLZ	= 4016,
    ARM_t2CMNri	= 4017,
    ARM_t2CMNzrr	= 4018,
    ARM_t2CMNzrs	= 4019,
    ARM_t2CMPri	= 4020,
    ARM_t2CMPrr	= 4021,
    ARM_t2CMPrs	= 4022,
    ARM_t2CPS1p	= 4023,
    ARM_t2CPS2p	= 4024,
    ARM_t2CPS3p	= 4025,
    ARM_t2CRC32B	= 4026,
    ARM_t2CRC32CB	= 4027,
    ARM_t2CRC32CH	= 4028,
    ARM_t2CRC32CW	= 4029,
    ARM_t2CRC32H	= 4030,
    ARM_t2CRC32W	= 4031,
    ARM_t2CSEL	= 4032,
    ARM_t2CSINC	= 4033,
    ARM_t2CSINV	= 4034,
    ARM_t2CSNEG	= 4035,
    ARM_t2DBG	= 4036,
    ARM_t2DCPS1	= 4037,
    ARM_t2DCPS2	= 4038,
    ARM_t2DCPS3	= 4039,
    ARM_t2DLS	= 4040,
    ARM_t2DMB	= 4041,
    ARM_t2DSB	= 4042,
    ARM_t2EORri	= 4043,
    ARM_t2EORrr	= 4044,
    ARM_t2EORrs	= 4045,
    ARM_t2HINT	= 4046,
    ARM_t2HVC	= 4047,
    ARM_t2ISB	= 4048,
    ARM_t2IT	= 4049,
    ARM_t2Int_eh_sjlj_setjmp	= 4050,
    ARM_t2Int_eh_sjlj_setjmp_nofp	= 4051,
    ARM_t2LDA	= 4052,
    ARM_t2LDAB	= 4053,
    ARM_t2LDAEX	= 4054,
    ARM_t2LDAEXB	= 4055,
    ARM_t2LDAEXD	= 4056,
    ARM_t2LDAEXH	= 4057,
    ARM_t2LDAH	= 4058,
    ARM_t2LDC2L_OFFSET	= 4059,
    ARM_t2LDC2L_OPTION	= 4060,
    ARM_t2LDC2L_POST	= 4061,
    ARM_t2LDC2L_PRE	= 4062,
    ARM_t2LDC2_OFFSET	= 4063,
    ARM_t2LDC2_OPTION	= 4064,
    ARM_t2LDC2_POST	= 4065,
    ARM_t2LDC2_PRE	= 4066,
    ARM_t2LDCL_OFFSET	= 4067,
    ARM_t2LDCL_OPTION	= 4068,
    ARM_t2LDCL_POST	= 4069,
    ARM_t2LDCL_PRE	= 4070,
    ARM_t2LDC_OFFSET	= 4071,
    ARM_t2LDC_OPTION	= 4072,
    ARM_t2LDC_POST	= 4073,
    ARM_t2LDC_PRE	= 4074,
    ARM_t2LDMDB	= 4075,
    ARM_t2LDMDB_UPD	= 4076,
    ARM_t2LDMIA	= 4077,
    ARM_t2LDMIA_UPD	= 4078,
    ARM_t2LDRBT	= 4079,
    ARM_t2LDRB_POST	= 4080,
    ARM_t2LDRB_PRE	= 4081,
    ARM_t2LDRBi12	= 4082,
    ARM_t2LDRBi8	= 4083,
    ARM_t2LDRBpci	= 4084,
    ARM_t2LDRBs	= 4085,
    ARM_t2LDRD_POST	= 4086,
    ARM_t2LDRD_PRE	= 4087,
    ARM_t2LDRDi8	= 4088,
    ARM_t2LDREX	= 4089,
    ARM_t2LDREXB	= 4090,
    ARM_t2LDREXD	= 4091,
    ARM_t2LDREXH	= 4092,
    ARM_t2LDRHT	= 4093,
    ARM_t2LDRH_POST	= 4094,
    ARM_t2LDRH_PRE	= 4095,
    ARM_t2LDRHi12	= 4096,
    ARM_t2LDRHi8	= 4097,
    ARM_t2LDRHpci	= 4098,
    ARM_t2LDRHs	= 4099,
    ARM_t2LDRSBT	= 4100,
    ARM_t2LDRSB_POST	= 4101,
    ARM_t2LDRSB_PRE	= 4102,
    ARM_t2LDRSBi12	= 4103,
    ARM_t2LDRSBi8	= 4104,
    ARM_t2LDRSBpci	= 4105,
    ARM_t2LDRSBs	= 4106,
    ARM_t2LDRSHT	= 4107,
    ARM_t2LDRSH_POST	= 4108,
    ARM_t2LDRSH_PRE	= 4109,
    ARM_t2LDRSHi12	= 4110,
    ARM_t2LDRSHi8	= 4111,
    ARM_t2LDRSHpci	= 4112,
    ARM_t2LDRSHs	= 4113,
    ARM_t2LDRT	= 4114,
    ARM_t2LDR_POST	= 4115,
    ARM_t2LDR_PRE	= 4116,
    ARM_t2LDRi12	= 4117,
    ARM_t2LDRi8	= 4118,
    ARM_t2LDRpci	= 4119,
    ARM_t2LDRs	= 4120,
    ARM_t2LE	= 4121,
    ARM_t2LEUpdate	= 4122,
    ARM_t2LSLri	= 4123,
    ARM_t2LSLrr	= 4124,
    ARM_t2LSRri	= 4125,
    ARM_t2LSRrr	= 4126,
    ARM_t2MCR	= 4127,
    ARM_t2MCR2	= 4128,
    ARM_t2MCRR	= 4129,
    ARM_t2MCRR2	= 4130,
    ARM_t2MLA	= 4131,
    ARM_t2MLS	= 4132,
    ARM_t2MOVTi16	= 4133,
    ARM_t2MOVi	= 4134,
    ARM_t2MOVi16	= 4135,
    ARM_t2MOVr	= 4136,
    ARM_t2MOVsra_glue	= 4137,
    ARM_t2MOVsrl_glue	= 4138,
    ARM_t2MRC	= 4139,
    ARM_t2MRC2	= 4140,
    ARM_t2MRRC	= 4141,
    ARM_t2MRRC2	= 4142,
    ARM_t2MRS_AR	= 4143,
    ARM_t2MRS_M	= 4144,
    ARM_t2MRSbanked	= 4145,
    ARM_t2MRSsys_AR	= 4146,
    ARM_t2MSR_AR	= 4147,
    ARM_t2MSR_M	= 4148,
    ARM_t2MSRbanked	= 4149,
    ARM_t2MUL	= 4150,
    ARM_t2MVNi	= 4151,
    ARM_t2MVNr	= 4152,
    ARM_t2MVNs	= 4153,
    ARM_t2ORNri	= 4154,
    ARM_t2ORNrr	= 4155,
    ARM_t2ORNrs	= 4156,
    ARM_t2ORRri	= 4157,
    ARM_t2ORRrr	= 4158,
    ARM_t2ORRrs	= 4159,
    ARM_t2PAC	= 4160,
    ARM_t2PACBTI	= 4161,
    ARM_t2PACG	= 4162,
    ARM_t2PKHBT	= 4163,
    ARM_t2PKHTB	= 4164,
    ARM_t2PLDWi12	= 4165,
    ARM_t2PLDWi8	= 4166,
    ARM_t2PLDWs	= 4167,
    ARM_t2PLDi12	= 4168,
    ARM_t2PLDi8	= 4169,
    ARM_t2PLDpci	= 4170,
    ARM_t2PLDs	= 4171,
    ARM_t2PLIi12	= 4172,
    ARM_t2PLIi8	= 4173,
    ARM_t2PLIpci	= 4174,
    ARM_t2PLIs	= 4175,
    ARM_t2QADD	= 4176,
    ARM_t2QADD16	= 4177,
    ARM_t2QADD8	= 4178,
    ARM_t2QASX	= 4179,
    ARM_t2QDADD	= 4180,
    ARM_t2QDSUB	= 4181,
    ARM_t2QSAX	= 4182,
    ARM_t2QSUB	= 4183,
    ARM_t2QSUB16	= 4184,
    ARM_t2QSUB8	= 4185,
    ARM_t2RBIT	= 4186,
    ARM_t2REV	= 4187,
    ARM_t2REV16	= 4188,
    ARM_t2REVSH	= 4189,
    ARM_t2RFEDB	= 4190,
    ARM_t2RFEDBW	= 4191,
    ARM_t2RFEIA	= 4192,
    ARM_t2RFEIAW	= 4193,
    ARM_t2RORri	= 4194,
    ARM_t2RORrr	= 4195,
    ARM_t2RRX	= 4196,
    ARM_t2RSBri	= 4197,
    ARM_t2RSBrr	= 4198,
    ARM_t2RSBrs	= 4199,
    ARM_t2SADD16	= 4200,
    ARM_t2SADD8	= 4201,
    ARM_t2SASX	= 4202,
    ARM_t2SB	= 4203,
    ARM_t2SBCri	= 4204,
    ARM_t2SBCrr	= 4205,
    ARM_t2SBCrs	= 4206,
    ARM_t2SBFX	= 4207,
    ARM_t2SDIV	= 4208,
    ARM_t2SEL	= 4209,
    ARM_t2SETPAN	= 4210,
    ARM_t2SG	= 4211,
    ARM_t2SHADD16	= 4212,
    ARM_t2SHADD8	= 4213,
    ARM_t2SHASX	= 4214,
    ARM_t2SHSAX	= 4215,
    ARM_t2SHSUB16	= 4216,
    ARM_t2SHSUB8	= 4217,
    ARM_t2SMC	= 4218,
    ARM_t2SMLABB	= 4219,
    ARM_t2SMLABT	= 4220,
    ARM_t2SMLAD	= 4221,
    ARM_t2SMLADX	= 4222,
    ARM_t2SMLAL	= 4223,
    ARM_t2SMLALBB	= 4224,
    ARM_t2SMLALBT	= 4225,
    ARM_t2SMLALD	= 4226,
    ARM_t2SMLALDX	= 4227,
    ARM_t2SMLALTB	= 4228,
    ARM_t2SMLALTT	= 4229,
    ARM_t2SMLATB	= 4230,
    ARM_t2SMLATT	= 4231,
    ARM_t2SMLAWB	= 4232,
    ARM_t2SMLAWT	= 4233,
    ARM_t2SMLSD	= 4234,
    ARM_t2SMLSDX	= 4235,
    ARM_t2SMLSLD	= 4236,
    ARM_t2SMLSLDX	= 4237,
    ARM_t2SMMLA	= 4238,
    ARM_t2SMMLAR	= 4239,
    ARM_t2SMMLS	= 4240,
    ARM_t2SMMLSR	= 4241,
    ARM_t2SMMUL	= 4242,
    ARM_t2SMMULR	= 4243,
    ARM_t2SMUAD	= 4244,
    ARM_t2SMUADX	= 4245,
    ARM_t2SMULBB	= 4246,
    ARM_t2SMULBT	= 4247,
    ARM_t2SMULL	= 4248,
    ARM_t2SMULTB	= 4249,
    ARM_t2SMULTT	= 4250,
    ARM_t2SMULWB	= 4251,
    ARM_t2SMULWT	= 4252,
    ARM_t2SMUSD	= 4253,
    ARM_t2SMUSDX	= 4254,
    ARM_t2SRSDB	= 4255,
    ARM_t2SRSDB_UPD	= 4256,
    ARM_t2SRSIA	= 4257,
    ARM_t2SRSIA_UPD	= 4258,
    ARM_t2SSAT	= 4259,
    ARM_t2SSAT16	= 4260,
    ARM_t2SSAX	= 4261,
    ARM_t2SSUB16	= 4262,
    ARM_t2SSUB8	= 4263,
    ARM_t2STC2L_OFFSET	= 4264,
    ARM_t2STC2L_OPTION	= 4265,
    ARM_t2STC2L_POST	= 4266,
    ARM_t2STC2L_PRE	= 4267,
    ARM_t2STC2_OFFSET	= 4268,
    ARM_t2STC2_OPTION	= 4269,
    ARM_t2STC2_POST	= 4270,
    ARM_t2STC2_PRE	= 4271,
    ARM_t2STCL_OFFSET	= 4272,
    ARM_t2STCL_OPTION	= 4273,
    ARM_t2STCL_POST	= 4274,
    ARM_t2STCL_PRE	= 4275,
    ARM_t2STC_OFFSET	= 4276,
    ARM_t2STC_OPTION	= 4277,
    ARM_t2STC_POST	= 4278,
    ARM_t2STC_PRE	= 4279,
    ARM_t2STL	= 4280,
    ARM_t2STLB	= 4281,
    ARM_t2STLEX	= 4282,
    ARM_t2STLEXB	= 4283,
    ARM_t2STLEXD	= 4284,
    ARM_t2STLEXH	= 4285,
    ARM_t2STLH	= 4286,
    ARM_t2STMDB	= 4287,
    ARM_t2STMDB_UPD	= 4288,
    ARM_t2STMIA	= 4289,
    ARM_t2STMIA_UPD	= 4290,
    ARM_t2STRBT	= 4291,
    ARM_t2STRB_POST	= 4292,
    ARM_t2STRB_PRE	= 4293,
    ARM_t2STRBi12	= 4294,
    ARM_t2STRBi8	= 4295,
    ARM_t2STRBs	= 4296,
    ARM_t2STRD_POST	= 4297,
    ARM_t2STRD_PRE	= 4298,
    ARM_t2STRDi8	= 4299,
    ARM_t2STREX	= 4300,
    ARM_t2STREXB	= 4301,
    ARM_t2STREXD	= 4302,
    ARM_t2STREXH	= 4303,
    ARM_t2STRHT	= 4304,
    ARM_t2STRH_POST	= 4305,
    ARM_t2STRH_PRE	= 4306,
    ARM_t2STRHi12	= 4307,
    ARM_t2STRHi8	= 4308,
    ARM_t2STRHs	= 4309,
    ARM_t2STRT	= 4310,
    ARM_t2STR_POST	= 4311,
    ARM_t2STR_PRE	= 4312,
    ARM_t2STRi12	= 4313,
    ARM_t2STRi8	= 4314,
    ARM_t2STRs	= 4315,
    ARM_t2SUBS_PC_LR	= 4316,
    ARM_t2SUBri	= 4317,
    ARM_t2SUBri12	= 4318,
    ARM_t2SUBrr	= 4319,
    ARM_t2SUBrs	= 4320,
    ARM_t2SUBspImm	= 4321,
    ARM_t2SUBspImm12	= 4322,
    ARM_t2SXTAB	= 4323,
    ARM_t2SXTAB16	= 4324,
    ARM_t2SXTAH	= 4325,
    ARM_t2SXTB	= 4326,
    ARM_t2SXTB16	= 4327,
    ARM_t2SXTH	= 4328,
    ARM_t2TBB	= 4329,
    ARM_t2TBH	= 4330,
    ARM_t2TEQri	= 4331,
    ARM_t2TEQrr	= 4332,
    ARM_t2TEQrs	= 4333,
    ARM_t2TSB	= 4334,
    ARM_t2TSTri	= 4335,
    ARM_t2TSTrr	= 4336,
    ARM_t2TSTrs	= 4337,
    ARM_t2TT	= 4338,
    ARM_t2TTA	= 4339,
    ARM_t2TTAT	= 4340,
    ARM_t2TTT	= 4341,
    ARM_t2UADD16	= 4342,
    ARM_t2UADD8	= 4343,
    ARM_t2UASX	= 4344,
    ARM_t2UBFX	= 4345,
    ARM_t2UDF	= 4346,
    ARM_t2UDIV	= 4347,
    ARM_t2UHADD16	= 4348,
    ARM_t2UHADD8	= 4349,
    ARM_t2UHASX	= 4350,
    ARM_t2UHSAX	= 4351,
    ARM_t2UHSUB16	= 4352,
    ARM_t2UHSUB8	= 4353,
    ARM_t2UMAAL	= 4354,
    ARM_t2UMLAL	= 4355,
    ARM_t2UMULL	= 4356,
    ARM_t2UQADD16	= 4357,
    ARM_t2UQADD8	= 4358,
    ARM_t2UQASX	= 4359,
    ARM_t2UQSAX	= 4360,
    ARM_t2UQSUB16	= 4361,
    ARM_t2UQSUB8	= 4362,
    ARM_t2USAD8	= 4363,
    ARM_t2USADA8	= 4364,
    ARM_t2USAT	= 4365,
    ARM_t2USAT16	= 4366,
    ARM_t2USAX	= 4367,
    ARM_t2USUB16	= 4368,
    ARM_t2USUB8	= 4369,
    ARM_t2UXTAB	= 4370,
    ARM_t2UXTAB16	= 4371,
    ARM_t2UXTAH	= 4372,
    ARM_t2UXTB	= 4373,
    ARM_t2UXTB16	= 4374,
    ARM_t2UXTH	= 4375,
    ARM_t2WLS	= 4376,
    ARM_tADC	= 4377,
    ARM_tADDhirr	= 4378,
    ARM_tADDi3	= 4379,
    ARM_tADDi8	= 4380,
    ARM_tADDrSP	= 4381,
    ARM_tADDrSPi	= 4382,
    ARM_tADDrr	= 4383,
    ARM_tADDspi	= 4384,
    ARM_tADDspr	= 4385,
    ARM_tADR	= 4386,
    ARM_tAND	= 4387,
    ARM_tASRri	= 4388,
    ARM_tASRrr	= 4389,
    ARM_tB	= 4390,
    ARM_tBIC	= 4391,
    ARM_tBKPT	= 4392,
    ARM_tBL	= 4393,
    ARM_tBLXNSr	= 4394,
    ARM_tBLXi	= 4395,
    ARM_tBLXr	= 4396,
    ARM_tBX	= 4397,
    ARM_tBXNS	= 4398,
    ARM_tBcc	= 4399,
    ARM_tCBNZ	= 4400,
    ARM_tCBZ	= 4401,
    ARM_tCMNz	= 4402,
    ARM_tCMPhir	= 4403,
    ARM_tCMPi8	= 4404,
    ARM_tCMPr	= 4405,
    ARM_tCPS	= 4406,
    ARM_tEOR	= 4407,
    ARM_tHINT	= 4408,
    ARM_tHLT	= 4409,
    ARM_tInt_WIN_eh_sjlj_longjmp	= 4410,
    ARM_tInt_eh_sjlj_longjmp	= 4411,
    ARM_tInt_eh_sjlj_setjmp	= 4412,
    ARM_tLDMIA	= 4413,
    ARM_tLDRBi	= 4414,
    ARM_tLDRBr	= 4415,
    ARM_tLDRHi	= 4416,
    ARM_tLDRHr	= 4417,
    ARM_tLDRSB	= 4418,
    ARM_tLDRSH	= 4419,
    ARM_tLDRi	= 4420,
    ARM_tLDRpci	= 4421,
    ARM_tLDRr	= 4422,
    ARM_tLDRspi	= 4423,
    ARM_tLSLri	= 4424,
    ARM_tLSLrr	= 4425,
    ARM_tLSRri	= 4426,
    ARM_tLSRrr	= 4427,
    ARM_tMOVSr	= 4428,
    ARM_tMOVi8	= 4429,
    ARM_tMOVr	= 4430,
    ARM_tMUL	= 4431,
    ARM_tMVN	= 4432,
    ARM_tORR	= 4433,
    ARM_tPICADD	= 4434,
    ARM_tPOP	= 4435,
    ARM_tPUSH	= 4436,
    ARM_tREV	= 4437,
    ARM_tREV16	= 4438,
    ARM_tREVSH	= 4439,
    ARM_tROR	= 4440,
    ARM_tRSB	= 4441,
    ARM_tSBC	= 4442,
    ARM_tSETEND	= 4443,
    ARM_tSTMIA_UPD	= 4444,
    ARM_tSTRBi	= 4445,
    ARM_tSTRBr	= 4446,
    ARM_tSTRHi	= 4447,
    ARM_tSTRHr	= 4448,
    ARM_tSTRi	= 4449,
    ARM_tSTRr	= 4450,
    ARM_tSTRspi	= 4451,
    ARM_tSUBi3	= 4452,
    ARM_tSUBi8	= 4453,
    ARM_tSUBrr	= 4454,
    ARM_tSUBspi	= 4455,
    ARM_tSVC	= 4456,
    ARM_tSXTB	= 4457,
    ARM_tSXTH	= 4458,
    ARM_tTRAP	= 4459,
    ARM_tTST	= 4460,
    ARM_tUDF	= 4461,
    ARM_tUXTB	= 4462,
    ARM_tUXTH	= 4463,
    ARM_t__brkdiv0	= 4464,
    INSTRUCTION_LIST_END = 4465
  };

#endif // GET_INSTRINFO_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
typedef struct ARMInstrTable {
  MCInstrDesc Insts[4465];
  MCOperandInfo OperandInfo[3035];
  MCPhysReg ImplicitOps[130];
} ARMInstrTable;

#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC

static const unsigned ARMImpOpBase = sizeof(MCOperandInfo) / (sizeof(MCPhysReg));

static const ARMInstrTable ARMDescs = {
  {
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #4464 = t__brkdiv0
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4463 = tUXTH
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4462 = tUXTB
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4461 = tUDF
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4460 = tTST
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #4459 = tTRAP
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4458 = tSXTH
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4457 = tSXTB
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4456 = tSVC
  { 5, &ARMDescs.OperandInfo[2967] },  // Inst #4455 = tSUBspi
  { 6, &ARMDescs.OperandInfo[2961] },  // Inst #4454 = tSUBrr
  { 6, &ARMDescs.OperandInfo[2945] },  // Inst #4453 = tSUBi8
  { 6, &ARMDescs.OperandInfo[2939] },  // Inst #4452 = tSUBi3
  { 5, &ARMDescs.OperandInfo[3011] },  // Inst #4451 = tSTRspi
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4450 = tSTRr
  { 5, &ARMDescs.OperandInfo[2997] },  // Inst #4449 = tSTRi
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4448 = tSTRHr
  { 5, &ARMDescs.OperandInfo[2997] },  // Inst #4447 = tSTRHi
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4446 = tSTRBr
  { 5, &ARMDescs.OperandInfo[2997] },  // Inst #4445 = tSTRBi
  { 5, &ARMDescs.OperandInfo[544] },  // Inst #4444 = tSTMIA_UPD
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4443 = tSETEND
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4442 = tSBC
  { 5, &ARMDescs.OperandInfo[3027] },  // Inst #4441 = tRSB
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4440 = tROR
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4439 = tREVSH
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4438 = tREV16
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4437 = tREV
  { 3, &ARMDescs.OperandInfo[570] },  // Inst #4436 = tPUSH
  { 3, &ARMDescs.OperandInfo[570] },  // Inst #4435 = tPOP
  { 3, &ARMDescs.OperandInfo[3032] },  // Inst #4434 = tPICADD
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4433 = tORR
  { 5, &ARMDescs.OperandInfo[3027] },  // Inst #4432 = tMVN
  { 6, &ARMDescs.OperandInfo[3021] },  // Inst #4431 = tMUL
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #4430 = tMOVr
  { 5, &ARMDescs.OperandInfo[3016] },  // Inst #4429 = tMOVi8
  { 2, &ARMDescs.OperandInfo[573] },  // Inst #4428 = tMOVSr
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4427 = tLSRrr
  { 6, &ARMDescs.OperandInfo[2939] },  // Inst #4426 = tLSRri
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4425 = tLSLrr
  { 6, &ARMDescs.OperandInfo[2939] },  // Inst #4424 = tLSLri
  { 5, &ARMDescs.OperandInfo[3011] },  // Inst #4423 = tLDRspi
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4422 = tLDRr
  { 4, &ARMDescs.OperandInfo[3007] },  // Inst #4421 = tLDRpci
  { 5, &ARMDescs.OperandInfo[2997] },  // Inst #4420 = tLDRi
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4419 = tLDRSH
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4418 = tLDRSB
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4417 = tLDRHr
  { 5, &ARMDescs.OperandInfo[2997] },  // Inst #4416 = tLDRHi
  { 5, &ARMDescs.OperandInfo[3002] },  // Inst #4415 = tLDRBr
  { 5, &ARMDescs.OperandInfo[2997] },  // Inst #4414 = tLDRBi
  { 4, &ARMDescs.OperandInfo[2993] },  // Inst #4413 = tLDMIA
  { 2, &ARMDescs.OperandInfo[573] },  // Inst #4412 = tInt_eh_sjlj_setjmp
  { 2, &ARMDescs.OperandInfo[573] },  // Inst #4411 = tInt_eh_sjlj_longjmp
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #4410 = tInt_WIN_eh_sjlj_longjmp
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4409 = tHLT
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4408 = tHINT
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4407 = tEOR
  { 2, &ARMDescs.OperandInfo[13] },  // Inst #4406 = tCPS
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4405 = tCMPr
  { 4, &ARMDescs.OperandInfo[549] },  // Inst #4404 = tCMPi8
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #4403 = tCMPhir
  { 4, &ARMDescs.OperandInfo[2989] },  // Inst #4402 = tCMNz
  { 2, &ARMDescs.OperandInfo[2987] },  // Inst #4401 = tCBZ
  { 2, &ARMDescs.OperandInfo[2987] },  // Inst #4400 = tCBNZ
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #4399 = tBcc
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4398 = tBXNS
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4397 = tBX
  { 3, &ARMDescs.OperandInfo[2984] },  // Inst #4396 = tBLXr
  { 3, &ARMDescs.OperandInfo[417] },  // Inst #4395 = tBLXi
  { 3, &ARMDescs.OperandInfo[2981] },  // Inst #4394 = tBLXNSr
  { 3, &ARMDescs.OperandInfo[417] },  // Inst #4393 = tBL
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4392 = tBKPT
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4391 = tBIC
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #4390 = tB
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4389 = tASRrr
  { 6, &ARMDescs.OperandInfo[2939] },  // Inst #4388 = tASRri
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4387 = tAND
  { 4, &ARMDescs.OperandInfo[2977] },  // Inst #4386 = tADR
  { 5, &ARMDescs.OperandInfo[2972] },  // Inst #4385 = tADDspr
  { 5, &ARMDescs.OperandInfo[2967] },  // Inst #4384 = tADDspi
  { 6, &ARMDescs.OperandInfo[2961] },  // Inst #4383 = tADDrr
  { 5, &ARMDescs.OperandInfo[2956] },  // Inst #4382 = tADDrSPi
  { 5, &ARMDescs.OperandInfo[2951] },  // Inst #4381 = tADDrSP
  { 6, &ARMDescs.OperandInfo[2945] },  // Inst #4380 = tADDi8
  { 6, &ARMDescs.OperandInfo[2939] },  // Inst #4379 = tADDi3
  { 5, &ARMDescs.OperandInfo[265] },  // Inst #4378 = tADDhirr
  { 6, &ARMDescs.OperandInfo[2933] },  // Inst #4377 = tADC
  { 3, &ARMDescs.OperandInfo[497] },  // Inst #4376 = t2WLS
  { 5, &ARMDescs.OperandInfo[480] },  // Inst #4375 = t2UXTH
  { 5, &ARMDescs.OperandInfo[480] },  // Inst #4374 = t2UXTB16
  { 5, &ARMDescs.OperandInfo[480] },  // Inst #4373 = t2UXTB
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4372 = t2UXTAH
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4371 = t2UXTAB16
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4370 = t2UXTAB
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4369 = t2USUB8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4368 = t2USUB16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4367 = t2USAX
  { 5, &ARMDescs.OperandInfo[2878] },  // Inst #4366 = t2USAT16
  { 6, &ARMDescs.OperandInfo[2872] },  // Inst #4365 = t2USAT
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4364 = t2USADA8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4363 = t2USAD8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4362 = t2UQSUB8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4361 = t2UQSUB16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4360 = t2UQSAX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4359 = t2UQASX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4358 = t2UQADD8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4357 = t2UQADD16
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4356 = t2UMULL
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4355 = t2UMLAL
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4354 = t2UMAAL
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4353 = t2UHSUB8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4352 = t2UHSUB16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4351 = t2UHSAX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4350 = t2UHASX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4349 = t2UHADD8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4348 = t2UHADD16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4347 = t2UDIV
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4346 = t2UDF
  { 6, &ARMDescs.OperandInfo[2858] },  // Inst #4345 = t2UBFX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4344 = t2UASX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4343 = t2UADD8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4342 = t2UADD16
  { 4, &ARMDescs.OperandInfo[2929] },  // Inst #4341 = t2TTT
  { 4, &ARMDescs.OperandInfo[2929] },  // Inst #4340 = t2TTAT
  { 4, &ARMDescs.OperandInfo[2929] },  // Inst #4339 = t2TTA
  { 4, &ARMDescs.OperandInfo[2929] },  // Inst #4338 = t2TT
  { 5, &ARMDescs.OperandInfo[465] },  // Inst #4337 = t2TSTrs
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4336 = t2TSTrr
  { 4, &ARMDescs.OperandInfo[2684] },  // Inst #4335 = t2TSTri
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4334 = t2TSB
  { 5, &ARMDescs.OperandInfo[465] },  // Inst #4333 = t2TEQrs
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4332 = t2TEQrr
  { 4, &ARMDescs.OperandInfo[2684] },  // Inst #4331 = t2TEQri
  { 4, &ARMDescs.OperandInfo[2925] },  // Inst #4330 = t2TBH
  { 4, &ARMDescs.OperandInfo[2925] },  // Inst #4329 = t2TBB
  { 5, &ARMDescs.OperandInfo[480] },  // Inst #4328 = t2SXTH
  { 5, &ARMDescs.OperandInfo[480] },  // Inst #4327 = t2SXTB16
  { 5, &ARMDescs.OperandInfo[480] },  // Inst #4326 = t2SXTB
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4325 = t2SXTAH
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4324 = t2SXTAB16
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4323 = t2SXTAB
  { 5, &ARMDescs.OperandInfo[2679] },  // Inst #4322 = t2SUBspImm12
  { 6, &ARMDescs.OperandInfo[2673] },  // Inst #4321 = t2SUBspImm
  { 7, &ARMDescs.OperandInfo[2666] },  // Inst #4320 = t2SUBrs
  { 6, &ARMDescs.OperandInfo[2660] },  // Inst #4319 = t2SUBrr
  { 5, &ARMDescs.OperandInfo[2655] },  // Inst #4318 = t2SUBri12
  { 6, &ARMDescs.OperandInfo[2649] },  // Inst #4317 = t2SUBri
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4316 = t2SUBS_PC_LR
  { 6, &ARMDescs.OperandInfo[2779] },  // Inst #4315 = t2STRs
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #4314 = t2STRi8
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #4313 = t2STRi12
  { 6, &ARMDescs.OperandInfo[2919] },  // Inst #4312 = t2STR_PRE
  { 6, &ARMDescs.OperandInfo[2919] },  // Inst #4311 = t2STR_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4310 = t2STRT
  { 6, &ARMDescs.OperandInfo[2900] },  // Inst #4309 = t2STRHs
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4308 = t2STRHi8
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4307 = t2STRHi12
  { 6, &ARMDescs.OperandInfo[2894] },  // Inst #4306 = t2STRH_PRE
  { 6, &ARMDescs.OperandInfo[2894] },  // Inst #4305 = t2STRH_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4304 = t2STRHT
  { 5, &ARMDescs.OperandInfo[2883] },  // Inst #4303 = t2STREXH
  { 6, &ARMDescs.OperandInfo[2888] },  // Inst #4302 = t2STREXD
  { 5, &ARMDescs.OperandInfo[2883] },  // Inst #4301 = t2STREXB
  { 6, &ARMDescs.OperandInfo[2913] },  // Inst #4300 = t2STREX
  { 6, &ARMDescs.OperandInfo[2764] },  // Inst #4299 = t2STRDi8
  { 7, &ARMDescs.OperandInfo[2906] },  // Inst #4298 = t2STRD_PRE
  { 7, &ARMDescs.OperandInfo[2906] },  // Inst #4297 = t2STRD_POST
  { 6, &ARMDescs.OperandInfo[2900] },  // Inst #4296 = t2STRBs
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4295 = t2STRBi8
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4294 = t2STRBi12
  { 6, &ARMDescs.OperandInfo[2894] },  // Inst #4293 = t2STRB_PRE
  { 6, &ARMDescs.OperandInfo[2894] },  // Inst #4292 = t2STRB_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4291 = t2STRBT
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #4290 = t2STMIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #4289 = t2STMIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #4288 = t2STMDB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #4287 = t2STMDB
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4286 = t2STLH
  { 5, &ARMDescs.OperandInfo[2883] },  // Inst #4285 = t2STLEXH
  { 6, &ARMDescs.OperandInfo[2888] },  // Inst #4284 = t2STLEXD
  { 5, &ARMDescs.OperandInfo[2883] },  // Inst #4283 = t2STLEXB
  { 5, &ARMDescs.OperandInfo[2883] },  // Inst #4282 = t2STLEX
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4281 = t2STLB
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4280 = t2STL
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4279 = t2STC_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4278 = t2STC_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4277 = t2STC_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4276 = t2STC_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4275 = t2STCL_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4274 = t2STCL_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4273 = t2STCL_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4272 = t2STCL_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4271 = t2STC2_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4270 = t2STC2_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4269 = t2STC2_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4268 = t2STC2_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4267 = t2STC2L_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4266 = t2STC2L_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4265 = t2STC2L_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4264 = t2STC2L_OFFSET
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4263 = t2SSUB8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4262 = t2SSUB16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4261 = t2SSAX
  { 5, &ARMDescs.OperandInfo[2878] },  // Inst #4260 = t2SSAT16
  { 6, &ARMDescs.OperandInfo[2872] },  // Inst #4259 = t2SSAT
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4258 = t2SRSIA_UPD
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4257 = t2SRSIA
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4256 = t2SRSDB_UPD
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4255 = t2SRSDB
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4254 = t2SMUSDX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4253 = t2SMUSD
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4252 = t2SMULWT
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4251 = t2SMULWB
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4250 = t2SMULTT
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4249 = t2SMULTB
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4248 = t2SMULL
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4247 = t2SMULBT
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4246 = t2SMULBB
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4245 = t2SMUADX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4244 = t2SMUAD
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4243 = t2SMMULR
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4242 = t2SMMUL
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4241 = t2SMMLSR
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4240 = t2SMMLS
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4239 = t2SMMLAR
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4238 = t2SMMLA
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4237 = t2SMLSLDX
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4236 = t2SMLSLD
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4235 = t2SMLSDX
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4234 = t2SMLSD
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4233 = t2SMLAWT
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4232 = t2SMLAWB
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4231 = t2SMLATT
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4230 = t2SMLATB
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4229 = t2SMLALTT
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4228 = t2SMLALTB
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4227 = t2SMLALDX
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4226 = t2SMLALD
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4225 = t2SMLALBT
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4224 = t2SMLALBB
  { 8, &ARMDescs.OperandInfo[2864] },  // Inst #4223 = t2SMLAL
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4222 = t2SMLADX
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4221 = t2SMLAD
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4220 = t2SMLABT
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4219 = t2SMLABB
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4218 = t2SMC
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4217 = t2SHSUB8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4216 = t2SHSUB16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4215 = t2SHSAX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4214 = t2SHASX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4213 = t2SHADD8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4212 = t2SHADD16
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #4211 = t2SG
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4210 = t2SETPAN
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #4209 = t2SEL
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4208 = t2SDIV
  { 6, &ARMDescs.OperandInfo[2858] },  // Inst #4207 = t2SBFX
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #4206 = t2SBCrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4205 = t2SBCrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4204 = t2SBCri
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #4203 = t2SB
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4202 = t2SASX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4201 = t2SADD8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4200 = t2SADD16
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #4199 = t2RSBrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4198 = t2RSBrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4197 = t2RSBri
  { 5, &ARMDescs.OperandInfo[2824] },  // Inst #4196 = t2RRX
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4195 = t2RORrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4194 = t2RORri
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4193 = t2RFEIAW
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4192 = t2RFEIA
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4191 = t2RFEDBW
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4190 = t2RFEDB
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4189 = t2REVSH
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4188 = t2REV16
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4187 = t2REV
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4186 = t2RBIT
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4185 = t2QSUB8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4184 = t2QSUB16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4183 = t2QSUB
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4182 = t2QSAX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4181 = t2QDSUB
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4180 = t2QDADD
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4179 = t2QASX
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4178 = t2QADD8
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4177 = t2QADD16
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4176 = t2QADD
  { 5, &ARMDescs.OperandInfo[2850] },  // Inst #4175 = t2PLIs
  { 3, &ARMDescs.OperandInfo[2855] },  // Inst #4174 = t2PLIpci
  { 4, &ARMDescs.OperandInfo[2846] },  // Inst #4173 = t2PLIi8
  { 4, &ARMDescs.OperandInfo[2846] },  // Inst #4172 = t2PLIi12
  { 5, &ARMDescs.OperandInfo[2850] },  // Inst #4171 = t2PLDs
  { 3, &ARMDescs.OperandInfo[2855] },  // Inst #4170 = t2PLDpci
  { 4, &ARMDescs.OperandInfo[2846] },  // Inst #4169 = t2PLDi8
  { 4, &ARMDescs.OperandInfo[2846] },  // Inst #4168 = t2PLDi12
  { 5, &ARMDescs.OperandInfo[2850] },  // Inst #4167 = t2PLDWs
  { 4, &ARMDescs.OperandInfo[2846] },  // Inst #4166 = t2PLDWi8
  { 4, &ARMDescs.OperandInfo[2846] },  // Inst #4165 = t2PLDWi12
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4164 = t2PKHTB
  { 6, &ARMDescs.OperandInfo[2840] },  // Inst #4163 = t2PKHBT
  { 5, &ARMDescs.OperandInfo[2835] },  // Inst #4162 = t2PACG
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #4161 = t2PACBTI
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #4160 = t2PAC
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #4159 = t2ORRrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4158 = t2ORRrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4157 = t2ORRri
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #4156 = t2ORNrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4155 = t2ORNrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4154 = t2ORNri
  { 6, &ARMDescs.OperandInfo[2829] },  // Inst #4153 = t2MVNs
  { 5, &ARMDescs.OperandInfo[2824] },  // Inst #4152 = t2MVNr
  { 5, &ARMDescs.OperandInfo[2798] },  // Inst #4151 = t2MVNi
  { 5, &ARMDescs.OperandInfo[2819] },  // Inst #4150 = t2MUL
  { 4, &ARMDescs.OperandInfo[2815] },  // Inst #4149 = t2MSRbanked
  { 4, &ARMDescs.OperandInfo[2815] },  // Inst #4148 = t2MSR_M
  { 4, &ARMDescs.OperandInfo[2815] },  // Inst #4147 = t2MSR_AR
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4146 = t2MRSsys_AR
  { 4, &ARMDescs.OperandInfo[2684] },  // Inst #4145 = t2MRSbanked
  { 4, &ARMDescs.OperandInfo[2684] },  // Inst #4144 = t2MRS_M
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #4143 = t2MRS_AR
  { 7, &ARMDescs.OperandInfo[2808] },  // Inst #4142 = t2MRRC2
  { 7, &ARMDescs.OperandInfo[2808] },  // Inst #4141 = t2MRRC
  { 8, &ARMDescs.OperandInfo[1019] },  // Inst #4140 = t2MRC2
  { 8, &ARMDescs.OperandInfo[1019] },  // Inst #4139 = t2MRC
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4138 = t2MOVsrl_glue
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4137 = t2MOVsra_glue
  { 5, &ARMDescs.OperandInfo[2803] },  // Inst #4136 = t2MOVr
  { 4, &ARMDescs.OperandInfo[2684] },  // Inst #4135 = t2MOVi16
  { 5, &ARMDescs.OperandInfo[2798] },  // Inst #4134 = t2MOVi
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #4133 = t2MOVTi16
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4132 = t2MLS
  { 6, &ARMDescs.OperandInfo[2792] },  // Inst #4131 = t2MLA
  { 7, &ARMDescs.OperandInfo[2785] },  // Inst #4130 = t2MCRR2
  { 7, &ARMDescs.OperandInfo[2785] },  // Inst #4129 = t2MCRR
  { 8, &ARMDescs.OperandInfo[952] },  // Inst #4128 = t2MCR2
  { 8, &ARMDescs.OperandInfo[952] },  // Inst #4127 = t2MCR
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4126 = t2LSRrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4125 = t2LSRri
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4124 = t2LSLrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4123 = t2LSLri
  { 3, &ARMDescs.OperandInfo[441] },  // Inst #4122 = t2LEUpdate
  { 1, &ARMDescs.OperandInfo[181] },  // Inst #4121 = t2LE
  { 6, &ARMDescs.OperandInfo[2779] },  // Inst #4120 = t2LDRs
  { 4, &ARMDescs.OperandInfo[2775] },  // Inst #4119 = t2LDRpci
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #4118 = t2LDRi8
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #4117 = t2LDRi12
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4116 = t2LDR_PRE
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4115 = t2LDR_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4114 = t2LDRT
  { 6, &ARMDescs.OperandInfo[2751] },  // Inst #4113 = t2LDRSHs
  { 4, &ARMDescs.OperandInfo[2747] },  // Inst #4112 = t2LDRSHpci
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4111 = t2LDRSHi8
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4110 = t2LDRSHi12
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4109 = t2LDRSH_PRE
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4108 = t2LDRSH_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4107 = t2LDRSHT
  { 6, &ARMDescs.OperandInfo[2751] },  // Inst #4106 = t2LDRSBs
  { 4, &ARMDescs.OperandInfo[2747] },  // Inst #4105 = t2LDRSBpci
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4104 = t2LDRSBi8
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4103 = t2LDRSBi12
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4102 = t2LDRSB_PRE
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4101 = t2LDRSB_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4100 = t2LDRSBT
  { 6, &ARMDescs.OperandInfo[2751] },  // Inst #4099 = t2LDRHs
  { 4, &ARMDescs.OperandInfo[2747] },  // Inst #4098 = t2LDRHpci
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4097 = t2LDRHi8
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4096 = t2LDRHi12
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4095 = t2LDRH_PRE
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4094 = t2LDRH_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4093 = t2LDRHT
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4092 = t2LDREXH
  { 5, &ARMDescs.OperandInfo[2737] },  // Inst #4091 = t2LDREXD
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4090 = t2LDREXB
  { 5, &ARMDescs.OperandInfo[2770] },  // Inst #4089 = t2LDREX
  { 6, &ARMDescs.OperandInfo[2764] },  // Inst #4088 = t2LDRDi8
  { 7, &ARMDescs.OperandInfo[2757] },  // Inst #4087 = t2LDRD_PRE
  { 7, &ARMDescs.OperandInfo[2757] },  // Inst #4086 = t2LDRD_POST
  { 6, &ARMDescs.OperandInfo[2751] },  // Inst #4085 = t2LDRBs
  { 4, &ARMDescs.OperandInfo[2747] },  // Inst #4084 = t2LDRBpci
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4083 = t2LDRBi8
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #4082 = t2LDRBi12
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4081 = t2LDRB_PRE
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #4080 = t2LDRB_POST
  { 5, &ARMDescs.OperandInfo[2742] },  // Inst #4079 = t2LDRBT
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #4078 = t2LDMIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #4077 = t2LDMIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #4076 = t2LDMDB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #4075 = t2LDMDB
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4074 = t2LDC_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4073 = t2LDC_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4072 = t2LDC_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4071 = t2LDC_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4070 = t2LDCL_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4069 = t2LDCL_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4068 = t2LDCL_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4067 = t2LDCL_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4066 = t2LDC2_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4065 = t2LDC2_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4064 = t2LDC2_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4063 = t2LDC2_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4062 = t2LDC2L_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4061 = t2LDC2L_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #4060 = t2LDC2L_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #4059 = t2LDC2L_OFFSET
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4058 = t2LDAH
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4057 = t2LDAEXH
  { 5, &ARMDescs.OperandInfo[2737] },  // Inst #4056 = t2LDAEXD
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4055 = t2LDAEXB
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4054 = t2LDAEX
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4053 = t2LDAB
  { 4, &ARMDescs.OperandInfo[2733] },  // Inst #4052 = t2LDA
  { 2, &ARMDescs.OperandInfo[573] },  // Inst #4051 = t2Int_eh_sjlj_setjmp_nofp
  { 2, &ARMDescs.OperandInfo[573] },  // Inst #4050 = t2Int_eh_sjlj_setjmp
  { 2, &ARMDescs.OperandInfo[13] },  // Inst #4049 = t2IT
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4048 = t2ISB
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4047 = t2HVC
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4046 = t2HINT
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #4045 = t2EORrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4044 = t2EORrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4043 = t2EORri
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4042 = t2DSB
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4041 = t2DMB
  { 2, &ARMDescs.OperandInfo[420] },  // Inst #4040 = t2DLS
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #4039 = t2DCPS3
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #4038 = t2DCPS2
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #4037 = t2DCPS1
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #4036 = t2DBG
  { 4, &ARMDescs.OperandInfo[2729] },  // Inst #4035 = t2CSNEG
  { 4, &ARMDescs.OperandInfo[2729] },  // Inst #4034 = t2CSINV
  { 4, &ARMDescs.OperandInfo[2729] },  // Inst #4033 = t2CSINC
  { 4, &ARMDescs.OperandInfo[2729] },  // Inst #4032 = t2CSEL
  { 3, &ARMDescs.OperandInfo[303] },  // Inst #4031 = t2CRC32W
  { 3, &ARMDescs.OperandInfo[303] },  // Inst #4030 = t2CRC32H
  { 3, &ARMDescs.OperandInfo[303] },  // Inst #4029 = t2CRC32CW
  { 3, &ARMDescs.OperandInfo[303] },  // Inst #4028 = t2CRC32CH
  { 3, &ARMDescs.OperandInfo[303] },  // Inst #4027 = t2CRC32CB
  { 3, &ARMDescs.OperandInfo[303] },  // Inst #4026 = t2CRC32B
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #4025 = t2CPS3p
  { 2, &ARMDescs.OperandInfo[13] },  // Inst #4024 = t2CPS2p
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #4023 = t2CPS1p
  { 5, &ARMDescs.OperandInfo[2724] },  // Inst #4022 = t2CMPrs
  { 4, &ARMDescs.OperandInfo[2720] },  // Inst #4021 = t2CMPrr
  { 4, &ARMDescs.OperandInfo[425] },  // Inst #4020 = t2CMPri
  { 5, &ARMDescs.OperandInfo[2724] },  // Inst #4019 = t2CMNzrs
  { 4, &ARMDescs.OperandInfo[2720] },  // Inst #4018 = t2CMNzrr
  { 4, &ARMDescs.OperandInfo[425] },  // Inst #4017 = t2CMNri
  { 4, &ARMDescs.OperandInfo[2716] },  // Inst #4016 = t2CLZ
  { 3, &ARMDescs.OperandInfo[570] },  // Inst #4015 = t2CLRM
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #4014 = t2CLREX
  { 8, &ARMDescs.OperandInfo[809] },  // Inst #4013 = t2CDP2
  { 8, &ARMDescs.OperandInfo[809] },  // Inst #4012 = t2CDP
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #4011 = t2Bcc
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #4010 = t2BXJ
  { 5, &ARMDescs.OperandInfo[2711] },  // Inst #4009 = t2BXAUT
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #4008 = t2BTI
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #4007 = t2BICrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #4006 = t2BICrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #4005 = t2BICri
  { 4, &ARMDescs.OperandInfo[2703] },  // Inst #4004 = t2BFr
  { 4, &ARMDescs.OperandInfo[2707] },  // Inst #4003 = t2BFic
  { 4, &ARMDescs.OperandInfo[2699] },  // Inst #4002 = t2BFi
  { 4, &ARMDescs.OperandInfo[2703] },  // Inst #4001 = t2BFLr
  { 4, &ARMDescs.OperandInfo[2699] },  // Inst #4000 = t2BFLi
  { 6, &ARMDescs.OperandInfo[2693] },  // Inst #3999 = t2BFI
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #3998 = t2BFC
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #3997 = t2B
  { 5, &ARMDescs.OperandInfo[2688] },  // Inst #3996 = t2AUTG
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #3995 = t2AUT
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #3994 = t2ASRrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #3993 = t2ASRri
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #3992 = t2ANDrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #3991 = t2ANDrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #3990 = t2ANDri
  { 4, &ARMDescs.OperandInfo[2684] },  // Inst #3989 = t2ADR
  { 5, &ARMDescs.OperandInfo[2679] },  // Inst #3988 = t2ADDspImm12
  { 6, &ARMDescs.OperandInfo[2673] },  // Inst #3987 = t2ADDspImm
  { 7, &ARMDescs.OperandInfo[2666] },  // Inst #3986 = t2ADDrs
  { 6, &ARMDescs.OperandInfo[2660] },  // Inst #3985 = t2ADDrr
  { 5, &ARMDescs.OperandInfo[2655] },  // Inst #3984 = t2ADDri12
  { 6, &ARMDescs.OperandInfo[2649] },  // Inst #3983 = t2ADDri
  { 7, &ARMDescs.OperandInfo[2642] },  // Inst #3982 = t2ADCrs
  { 6, &ARMDescs.OperandInfo[2636] },  // Inst #3981 = t2ADCrr
  { 6, &ARMDescs.OperandInfo[2630] },  // Inst #3980 = t2ADCri
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3979 = sysSTMIB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3978 = sysSTMIB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3977 = sysSTMIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3976 = sysSTMIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3975 = sysSTMDB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3974 = sysSTMDB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3973 = sysSTMDA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3972 = sysSTMDA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3971 = sysLDMIB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3970 = sysLDMIB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3969 = sysLDMIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3968 = sysLDMIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3967 = sysLDMDB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3966 = sysLDMDB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3965 = sysLDMDA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3964 = sysLDMDA
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3963 = VZIPq8
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3962 = VZIPq32
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3961 = VZIPq16
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3960 = VZIPd8
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3959 = VZIPd16
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3958 = VUZPq8
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3957 = VUZPq32
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3956 = VUZPq16
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3955 = VUZPd8
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3954 = VUZPd16
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #3953 = VUSMMLA
  { 5, &ARMDescs.OperandInfo[618] },  // Inst #3952 = VUSDOTQI
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #3951 = VUSDOTQ
  { 5, &ARMDescs.OperandInfo[613] },  // Inst #3950 = VUSDOTDI
  { 4, &ARMDescs.OperandInfo[623] },  // Inst #3949 = VUSDOTD
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #3948 = VUMMLA
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3947 = VULTOS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3946 = VULTOH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3945 = VULTOD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3944 = VUITOS
  { 4, &ARMDescs.OperandInfo[2353] },  // Inst #3943 = VUITOH
  { 4, &ARMDescs.OperandInfo[1788] },  // Inst #3942 = VUITOD
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3941 = VUHTOS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3940 = VUHTOH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3939 = VUHTOD
  { 5, &ARMDescs.OperandInfo[618] },  // Inst #3938 = VUDOTQI
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #3937 = VUDOTQ
  { 5, &ARMDescs.OperandInfo[613] },  // Inst #3936 = VUDOTDI
  { 4, &ARMDescs.OperandInfo[623] },  // Inst #3935 = VUDOTD
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3934 = VTSTv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3933 = VTSTv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3932 = VTSTv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3931 = VTSTv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3930 = VTSTv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3929 = VTSTv16i8
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3928 = VTRNq8
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3927 = VTRNq32
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3926 = VTRNq16
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3925 = VTRNd8
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3924 = VTRNd32
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3923 = VTRNd16
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3922 = VTOULS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3921 = VTOULH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3920 = VTOULD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3919 = VTOUIZS
  { 4, &ARMDescs.OperandInfo[2626] },  // Inst #3918 = VTOUIZH
  { 4, &ARMDescs.OperandInfo[1792] },  // Inst #3917 = VTOUIZD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3916 = VTOUIRS
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3915 = VTOUIRH
  { 4, &ARMDescs.OperandInfo[1792] },  // Inst #3914 = VTOUIRD
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3913 = VTOUHS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3912 = VTOUHH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3911 = VTOUHD
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3910 = VTOSLS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3909 = VTOSLH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3908 = VTOSLD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3907 = VTOSIZS
  { 4, &ARMDescs.OperandInfo[2626] },  // Inst #3906 = VTOSIZH
  { 4, &ARMDescs.OperandInfo[1792] },  // Inst #3905 = VTOSIZD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3904 = VTOSIRS
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3903 = VTOSIRH
  { 4, &ARMDescs.OperandInfo[1792] },  // Inst #3902 = VTOSIRD
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3901 = VTOSHS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3900 = VTOSHH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3899 = VTOSHD
  { 6, &ARMDescs.OperandInfo[2620] },  // Inst #3898 = VTBX4Pseudo
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3897 = VTBX4
  { 6, &ARMDescs.OperandInfo[2620] },  // Inst #3896 = VTBX3Pseudo
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3895 = VTBX3
  { 6, &ARMDescs.OperandInfo[2614] },  // Inst #3894 = VTBX2
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3893 = VTBX1
  { 5, &ARMDescs.OperandInfo[2609] },  // Inst #3892 = VTBL4Pseudo
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3891 = VTBL4
  { 5, &ARMDescs.OperandInfo[2609] },  // Inst #3890 = VTBL3Pseudo
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3889 = VTBL3
  { 5, &ARMDescs.OperandInfo[2604] },  // Inst #3888 = VTBL2
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3887 = VTBL1
  { 6, &ARMDescs.OperandInfo[2598] },  // Inst #3886 = VSWPq
  { 6, &ARMDescs.OperandInfo[2592] },  // Inst #3885 = VSWPd
  { 5, &ARMDescs.OperandInfo[618] },  // Inst #3884 = VSUDOTQI
  { 5, &ARMDescs.OperandInfo[613] },  // Inst #3883 = VSUDOTDI
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3882 = VSUBv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3881 = VSUBv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3880 = VSUBv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3879 = VSUBv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3878 = VSUBv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3877 = VSUBv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3876 = VSUBv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3875 = VSUBv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3874 = VSUBhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3873 = VSUBhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3872 = VSUBfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3871 = VSUBfd
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #3870 = VSUBWuv8i16
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #3869 = VSUBWuv4i32
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #3868 = VSUBWuv2i64
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #3867 = VSUBWsv8i16
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #3866 = VSUBWsv4i32
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #3865 = VSUBWsv2i64
  { 5, &ARMDescs.OperandInfo[1687] },  // Inst #3864 = VSUBS
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3863 = VSUBLuv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3862 = VSUBLuv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3861 = VSUBLuv2i64
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3860 = VSUBLsv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3859 = VSUBLsv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3858 = VSUBLsv2i64
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3857 = VSUBHNv8i8
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3856 = VSUBHNv4i16
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3855 = VSUBHNv2i32
  { 5, &ARMDescs.OperandInfo[1677] },  // Inst #3854 = VSUBH
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3853 = VSUBD
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3852 = VSTR_VPR_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3851 = VSTR_VPR_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #3850 = VSTR_VPR_off
  { 6, &ARMDescs.OperandInfo[2586] },  // Inst #3849 = VSTR_P0_pre
  { 6, &ARMDescs.OperandInfo[2586] },  // Inst #3848 = VSTR_P0_post
  { 5, &ARMDescs.OperandInfo[2156] },  // Inst #3847 = VSTR_P0_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3846 = VSTR_FPSCR_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3845 = VSTR_FPSCR_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #3844 = VSTR_FPSCR_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3843 = VSTR_FPSCR_NZCVQC_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3842 = VSTR_FPSCR_NZCVQC_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #3841 = VSTR_FPSCR_NZCVQC_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3840 = VSTR_FPCXTS_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3839 = VSTR_FPCXTS_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #3838 = VSTR_FPCXTS_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3837 = VSTR_FPCXTNS_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #3836 = VSTR_FPCXTNS_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #3835 = VSTR_FPCXTNS_off
  { 5, &ARMDescs.OperandInfo[2142] },  // Inst #3834 = VSTRS
  { 5, &ARMDescs.OperandInfo[2137] },  // Inst #3833 = VSTRH
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #3832 = VSTRD
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3831 = VSTMSIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3830 = VSTMSIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3829 = VSTMSDB_UPD
  { 4, &ARMDescs.OperandInfo[2133] },  // Inst #3828 = VSTMQIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3827 = VSTMDIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #3826 = VSTMDIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #3825 = VSTMDDB_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3824 = VST4q8oddPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3823 = VST4q8oddPseudo
  { 10, &ARMDescs.OperandInfo[2576] },  // Inst #3822 = VST4q8_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3821 = VST4q8Pseudo_UPD
  { 8, &ARMDescs.OperandInfo[2568] },  // Inst #3820 = VST4q8
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3819 = VST4q32oddPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3818 = VST4q32oddPseudo
  { 10, &ARMDescs.OperandInfo[2576] },  // Inst #3817 = VST4q32_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3816 = VST4q32Pseudo_UPD
  { 8, &ARMDescs.OperandInfo[2568] },  // Inst #3815 = VST4q32
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3814 = VST4q16oddPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3813 = VST4q16oddPseudo
  { 10, &ARMDescs.OperandInfo[2576] },  // Inst #3812 = VST4q16_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3811 = VST4q16Pseudo_UPD
  { 8, &ARMDescs.OperandInfo[2568] },  // Inst #3810 = VST4q16
  { 10, &ARMDescs.OperandInfo[2576] },  // Inst #3809 = VST4d8_UPD
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3808 = VST4d8Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3807 = VST4d8Pseudo
  { 8, &ARMDescs.OperandInfo[2568] },  // Inst #3806 = VST4d8
  { 10, &ARMDescs.OperandInfo[2576] },  // Inst #3805 = VST4d32_UPD
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3804 = VST4d32Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3803 = VST4d32Pseudo
  { 8, &ARMDescs.OperandInfo[2568] },  // Inst #3802 = VST4d32
  { 10, &ARMDescs.OperandInfo[2576] },  // Inst #3801 = VST4d16_UPD
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3800 = VST4d16Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3799 = VST4d16Pseudo
  { 8, &ARMDescs.OperandInfo[2568] },  // Inst #3798 = VST4d16
  { 11, &ARMDescs.OperandInfo[2557] },  // Inst #3797 = VST4LNq32_UPD
  { 8, &ARMDescs.OperandInfo[2524] },  // Inst #3796 = VST4LNq32Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2518] },  // Inst #3795 = VST4LNq32Pseudo
  { 9, &ARMDescs.OperandInfo[2548] },  // Inst #3794 = VST4LNq32
  { 11, &ARMDescs.OperandInfo[2557] },  // Inst #3793 = VST4LNq16_UPD
  { 8, &ARMDescs.OperandInfo[2524] },  // Inst #3792 = VST4LNq16Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2518] },  // Inst #3791 = VST4LNq16Pseudo
  { 9, &ARMDescs.OperandInfo[2548] },  // Inst #3790 = VST4LNq16
  { 11, &ARMDescs.OperandInfo[2557] },  // Inst #3789 = VST4LNd8_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3788 = VST4LNd8Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3787 = VST4LNd8Pseudo
  { 9, &ARMDescs.OperandInfo[2548] },  // Inst #3786 = VST4LNd8
  { 11, &ARMDescs.OperandInfo[2557] },  // Inst #3785 = VST4LNd32_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3784 = VST4LNd32Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3783 = VST4LNd32Pseudo
  { 9, &ARMDescs.OperandInfo[2548] },  // Inst #3782 = VST4LNd32
  { 11, &ARMDescs.OperandInfo[2557] },  // Inst #3781 = VST4LNd16_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3780 = VST4LNd16Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3779 = VST4LNd16Pseudo
  { 9, &ARMDescs.OperandInfo[2548] },  // Inst #3778 = VST4LNd16
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3777 = VST3q8oddPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3776 = VST3q8oddPseudo
  { 9, &ARMDescs.OperandInfo[2539] },  // Inst #3775 = VST3q8_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3774 = VST3q8Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2532] },  // Inst #3773 = VST3q8
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3772 = VST3q32oddPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3771 = VST3q32oddPseudo
  { 9, &ARMDescs.OperandInfo[2539] },  // Inst #3770 = VST3q32_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3769 = VST3q32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2532] },  // Inst #3768 = VST3q32
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3767 = VST3q16oddPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3766 = VST3q16oddPseudo
  { 9, &ARMDescs.OperandInfo[2539] },  // Inst #3765 = VST3q16_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3764 = VST3q16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2532] },  // Inst #3763 = VST3q16
  { 9, &ARMDescs.OperandInfo[2539] },  // Inst #3762 = VST3d8_UPD
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3761 = VST3d8Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3760 = VST3d8Pseudo
  { 7, &ARMDescs.OperandInfo[2532] },  // Inst #3759 = VST3d8
  { 9, &ARMDescs.OperandInfo[2539] },  // Inst #3758 = VST3d32_UPD
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3757 = VST3d32Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3756 = VST3d32Pseudo
  { 7, &ARMDescs.OperandInfo[2532] },  // Inst #3755 = VST3d32
  { 9, &ARMDescs.OperandInfo[2539] },  // Inst #3754 = VST3d16_UPD
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3753 = VST3d16Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3752 = VST3d16Pseudo
  { 7, &ARMDescs.OperandInfo[2532] },  // Inst #3751 = VST3d16
  { 10, &ARMDescs.OperandInfo[2508] },  // Inst #3750 = VST3LNq32_UPD
  { 8, &ARMDescs.OperandInfo[2524] },  // Inst #3749 = VST3LNq32Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2518] },  // Inst #3748 = VST3LNq32Pseudo
  { 8, &ARMDescs.OperandInfo[2500] },  // Inst #3747 = VST3LNq32
  { 10, &ARMDescs.OperandInfo[2508] },  // Inst #3746 = VST3LNq16_UPD
  { 8, &ARMDescs.OperandInfo[2524] },  // Inst #3745 = VST3LNq16Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2518] },  // Inst #3744 = VST3LNq16Pseudo
  { 8, &ARMDescs.OperandInfo[2500] },  // Inst #3743 = VST3LNq16
  { 10, &ARMDescs.OperandInfo[2508] },  // Inst #3742 = VST3LNd8_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3741 = VST3LNd8Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3740 = VST3LNd8Pseudo
  { 8, &ARMDescs.OperandInfo[2500] },  // Inst #3739 = VST3LNd8
  { 10, &ARMDescs.OperandInfo[2508] },  // Inst #3738 = VST3LNd32_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3737 = VST3LNd32Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3736 = VST3LNd32Pseudo
  { 8, &ARMDescs.OperandInfo[2500] },  // Inst #3735 = VST3LNd32
  { 10, &ARMDescs.OperandInfo[2508] },  // Inst #3734 = VST3LNd16_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3733 = VST3LNd16Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3732 = VST3LNd16Pseudo
  { 8, &ARMDescs.OperandInfo[2500] },  // Inst #3731 = VST3LNd16
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3730 = VST2q8wb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3729 = VST2q8wb_fixed
  { 7, &ARMDescs.OperandInfo[2493] },  // Inst #3728 = VST2q8PseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3727 = VST2q8PseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3726 = VST2q8Pseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3725 = VST2q8
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3724 = VST2q32wb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3723 = VST2q32wb_fixed
  { 7, &ARMDescs.OperandInfo[2493] },  // Inst #3722 = VST2q32PseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3721 = VST2q32PseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3720 = VST2q32Pseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3719 = VST2q32
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3718 = VST2q16wb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3717 = VST2q16wb_fixed
  { 7, &ARMDescs.OperandInfo[2493] },  // Inst #3716 = VST2q16PseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3715 = VST2q16PseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3714 = VST2q16Pseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3713 = VST2q16
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3712 = VST2d8wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3711 = VST2d8wb_fixed
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3710 = VST2d8
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3709 = VST2d32wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3708 = VST2d32wb_fixed
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3707 = VST2d32
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3706 = VST2d16wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3705 = VST2d16wb_fixed
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3704 = VST2d16
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3703 = VST2b8wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3702 = VST2b8wb_fixed
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3701 = VST2b8
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3700 = VST2b32wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3699 = VST2b32wb_fixed
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3698 = VST2b32
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3697 = VST2b16wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3696 = VST2b16wb_fixed
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3695 = VST2b16
  { 9, &ARMDescs.OperandInfo[2470] },  // Inst #3694 = VST2LNq32_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3693 = VST2LNq32Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3692 = VST2LNq32Pseudo
  { 7, &ARMDescs.OperandInfo[2463] },  // Inst #3691 = VST2LNq32
  { 9, &ARMDescs.OperandInfo[2470] },  // Inst #3690 = VST2LNq16_UPD
  { 8, &ARMDescs.OperandInfo[2485] },  // Inst #3689 = VST2LNq16Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2479] },  // Inst #3688 = VST2LNq16Pseudo
  { 7, &ARMDescs.OperandInfo[2463] },  // Inst #3687 = VST2LNq16
  { 9, &ARMDescs.OperandInfo[2470] },  // Inst #3686 = VST2LNd8_UPD
  { 8, &ARMDescs.OperandInfo[2389] },  // Inst #3685 = VST2LNd8Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2383] },  // Inst #3684 = VST2LNd8Pseudo
  { 7, &ARMDescs.OperandInfo[2463] },  // Inst #3683 = VST2LNd8
  { 9, &ARMDescs.OperandInfo[2470] },  // Inst #3682 = VST2LNd32_UPD
  { 8, &ARMDescs.OperandInfo[2389] },  // Inst #3681 = VST2LNd32Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2383] },  // Inst #3680 = VST2LNd32Pseudo
  { 7, &ARMDescs.OperandInfo[2463] },  // Inst #3679 = VST2LNd32
  { 9, &ARMDescs.OperandInfo[2470] },  // Inst #3678 = VST2LNd16_UPD
  { 8, &ARMDescs.OperandInfo[2389] },  // Inst #3677 = VST2LNd16Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2383] },  // Inst #3676 = VST2LNd16Pseudo
  { 7, &ARMDescs.OperandInfo[2463] },  // Inst #3675 = VST2LNd16
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3674 = VST1q8wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3673 = VST1q8wb_fixed
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3672 = VST1q8LowTPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3671 = VST1q8LowQPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3670 = VST1q8HighTPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3669 = VST1q8HighTPseudo
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3668 = VST1q8HighQPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3667 = VST1q8HighQPseudo
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3666 = VST1q8
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3665 = VST1q64wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3664 = VST1q64wb_fixed
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3663 = VST1q64LowTPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3662 = VST1q64LowQPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3661 = VST1q64HighTPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3660 = VST1q64HighTPseudo
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3659 = VST1q64HighQPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3658 = VST1q64HighQPseudo
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3657 = VST1q64
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3656 = VST1q32wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3655 = VST1q32wb_fixed
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3654 = VST1q32LowTPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3653 = VST1q32LowQPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3652 = VST1q32HighTPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3651 = VST1q32HighTPseudo
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3650 = VST1q32HighQPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3649 = VST1q32HighQPseudo
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3648 = VST1q32
  { 7, &ARMDescs.OperandInfo[2456] },  // Inst #3647 = VST1q16wb_register
  { 6, &ARMDescs.OperandInfo[2450] },  // Inst #3646 = VST1q16wb_fixed
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3645 = VST1q16LowTPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3644 = VST1q16LowQPseudo_UPD
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3643 = VST1q16HighTPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3642 = VST1q16HighTPseudo
  { 7, &ARMDescs.OperandInfo[2443] },  // Inst #3641 = VST1q16HighQPseudo_UPD
  { 5, &ARMDescs.OperandInfo[2438] },  // Inst #3640 = VST1q16HighQPseudo
  { 5, &ARMDescs.OperandInfo[2433] },  // Inst #3639 = VST1q16
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3638 = VST1d8wb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3637 = VST1d8wb_fixed
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3636 = VST1d8Twb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3635 = VST1d8Twb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3634 = VST1d8TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3633 = VST1d8TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3632 = VST1d8TPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3631 = VST1d8T
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3630 = VST1d8Qwb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3629 = VST1d8Qwb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3628 = VST1d8QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3627 = VST1d8QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3626 = VST1d8QPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3625 = VST1d8Q
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3624 = VST1d8
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3623 = VST1d64wb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3622 = VST1d64wb_fixed
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3621 = VST1d64Twb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3620 = VST1d64Twb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3619 = VST1d64TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3618 = VST1d64TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3617 = VST1d64TPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3616 = VST1d64T
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3615 = VST1d64Qwb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3614 = VST1d64Qwb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3613 = VST1d64QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3612 = VST1d64QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3611 = VST1d64QPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3610 = VST1d64Q
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3609 = VST1d64
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3608 = VST1d32wb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3607 = VST1d32wb_fixed
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3606 = VST1d32Twb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3605 = VST1d32Twb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3604 = VST1d32TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3603 = VST1d32TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3602 = VST1d32TPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3601 = VST1d32T
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3600 = VST1d32Qwb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3599 = VST1d32Qwb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3598 = VST1d32QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3597 = VST1d32QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3596 = VST1d32QPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3595 = VST1d32Q
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3594 = VST1d32
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3593 = VST1d16wb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3592 = VST1d16wb_fixed
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3591 = VST1d16Twb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3590 = VST1d16Twb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3589 = VST1d16TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3588 = VST1d16TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3587 = VST1d16TPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3586 = VST1d16T
  { 7, &ARMDescs.OperandInfo[2426] },  // Inst #3585 = VST1d16Qwb_register
  { 6, &ARMDescs.OperandInfo[2420] },  // Inst #3584 = VST1d16Qwb_fixed
  { 7, &ARMDescs.OperandInfo[2413] },  // Inst #3583 = VST1d16QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[2407] },  // Inst #3582 = VST1d16QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[2402] },  // Inst #3581 = VST1d16QPseudo
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3580 = VST1d16Q
  { 5, &ARMDescs.OperandInfo[2397] },  // Inst #3579 = VST1d16
  { 8, &ARMDescs.OperandInfo[2389] },  // Inst #3578 = VST1LNq8Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2383] },  // Inst #3577 = VST1LNq8Pseudo
  { 8, &ARMDescs.OperandInfo[2389] },  // Inst #3576 = VST1LNq32Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2383] },  // Inst #3575 = VST1LNq32Pseudo
  { 8, &ARMDescs.OperandInfo[2389] },  // Inst #3574 = VST1LNq16Pseudo_UPD
  { 6, &ARMDescs.OperandInfo[2383] },  // Inst #3573 = VST1LNq16Pseudo
  { 8, &ARMDescs.OperandInfo[2375] },  // Inst #3572 = VST1LNd8_UPD
  { 6, &ARMDescs.OperandInfo[2369] },  // Inst #3571 = VST1LNd8
  { 8, &ARMDescs.OperandInfo[2375] },  // Inst #3570 = VST1LNd32_UPD
  { 6, &ARMDescs.OperandInfo[2369] },  // Inst #3569 = VST1LNd32
  { 8, &ARMDescs.OperandInfo[2375] },  // Inst #3568 = VST1LNd16_UPD
  { 6, &ARMDescs.OperandInfo[2369] },  // Inst #3567 = VST1LNd16
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3566 = VSRIv8i8
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3565 = VSRIv8i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3564 = VSRIv4i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3563 = VSRIv4i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3562 = VSRIv2i64
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3561 = VSRIv2i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3560 = VSRIv1i64
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3559 = VSRIv16i8
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3558 = VSRAuv8i8
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3557 = VSRAuv8i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3556 = VSRAuv4i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3555 = VSRAuv4i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3554 = VSRAuv2i64
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3553 = VSRAuv2i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3552 = VSRAuv1i64
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3551 = VSRAuv16i8
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3550 = VSRAsv8i8
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3549 = VSRAsv8i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3548 = VSRAsv4i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3547 = VSRAsv4i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3546 = VSRAsv2i64
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3545 = VSRAsv2i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3544 = VSRAsv1i64
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3543 = VSRAsv16i8
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3542 = VSQRTS
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #3541 = VSQRTH
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3540 = VSQRTD
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #3539 = VSMMLA
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3538 = VSLTOS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3537 = VSLTOH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3536 = VSLTOD
  { 6, &ARMDescs.OperandInfo[2363] },  // Inst #3535 = VSLIv8i8
  { 6, &ARMDescs.OperandInfo[2357] },  // Inst #3534 = VSLIv8i16
  { 6, &ARMDescs.OperandInfo[2357] },  // Inst #3533 = VSLIv4i32
  { 6, &ARMDescs.OperandInfo[2363] },  // Inst #3532 = VSLIv4i16
  { 6, &ARMDescs.OperandInfo[2357] },  // Inst #3531 = VSLIv2i64
  { 6, &ARMDescs.OperandInfo[2363] },  // Inst #3530 = VSLIv2i32
  { 6, &ARMDescs.OperandInfo[2363] },  // Inst #3529 = VSLIv1i64
  { 6, &ARMDescs.OperandInfo[2357] },  // Inst #3528 = VSLIv16i8
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3527 = VSITOS
  { 4, &ARMDescs.OperandInfo[2353] },  // Inst #3526 = VSITOH
  { 4, &ARMDescs.OperandInfo[1788] },  // Inst #3525 = VSITOD
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3524 = VSHTOS
  { 5, &ARMDescs.OperandInfo[2348] },  // Inst #3523 = VSHTOH
  { 5, &ARMDescs.OperandInfo[2343] },  // Inst #3522 = VSHTOD
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3521 = VSHRuv8i8
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3520 = VSHRuv8i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3519 = VSHRuv4i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3518 = VSHRuv4i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3517 = VSHRuv2i64
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3516 = VSHRuv2i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3515 = VSHRuv1i64
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3514 = VSHRuv16i8
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3513 = VSHRsv8i8
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3512 = VSHRsv8i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3511 = VSHRsv4i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3510 = VSHRsv4i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3509 = VSHRsv2i64
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3508 = VSHRsv2i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3507 = VSHRsv1i64
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3506 = VSHRsv16i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3505 = VSHRNv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3504 = VSHRNv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3503 = VSHRNv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3502 = VSHLuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3501 = VSHLuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3500 = VSHLuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3499 = VSHLuv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3498 = VSHLuv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3497 = VSHLuv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3496 = VSHLuv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3495 = VSHLuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3494 = VSHLsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3493 = VSHLsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3492 = VSHLsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3491 = VSHLsv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3490 = VSHLsv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3489 = VSHLsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3488 = VSHLsv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3487 = VSHLsv16i8
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3486 = VSHLiv8i8
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3485 = VSHLiv8i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3484 = VSHLiv4i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3483 = VSHLiv4i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3482 = VSHLiv2i64
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3481 = VSHLiv2i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3480 = VSHLiv1i64
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3479 = VSHLiv16i8
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3478 = VSHLLuv8i16
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3477 = VSHLLuv4i32
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3476 = VSHLLuv2i64
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3475 = VSHLLsv8i16
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3474 = VSHLLsv4i32
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3473 = VSHLLsv2i64
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3472 = VSHLLi8
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3471 = VSHLLi32
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #3470 = VSHLLi16
  { 6, &ARMDescs.OperandInfo[2337] },  // Inst #3469 = VSETLNi8
  { 6, &ARMDescs.OperandInfo[2337] },  // Inst #3468 = VSETLNi32
  { 6, &ARMDescs.OperandInfo[2337] },  // Inst #3467 = VSETLNi16
  { 3, &ARMDescs.OperandInfo[1864] },  // Inst #3466 = VSELVSS
  { 3, &ARMDescs.OperandInfo[1861] },  // Inst #3465 = VSELVSH
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #3464 = VSELVSD
  { 3, &ARMDescs.OperandInfo[1864] },  // Inst #3463 = VSELGTS
  { 3, &ARMDescs.OperandInfo[1861] },  // Inst #3462 = VSELGTH
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #3461 = VSELGTD
  { 3, &ARMDescs.OperandInfo[1864] },  // Inst #3460 = VSELGES
  { 3, &ARMDescs.OperandInfo[1861] },  // Inst #3459 = VSELGEH
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #3458 = VSELGED
  { 3, &ARMDescs.OperandInfo[1864] },  // Inst #3457 = VSELEQS
  { 3, &ARMDescs.OperandInfo[1861] },  // Inst #3456 = VSELEQH
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #3455 = VSELEQD
  { 5, &ARMDescs.OperandInfo[618] },  // Inst #3454 = VSDOTQI
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #3453 = VSDOTQ
  { 5, &ARMDescs.OperandInfo[613] },  // Inst #3452 = VSDOTDI
  { 4, &ARMDescs.OperandInfo[623] },  // Inst #3451 = VSDOTD
  { 3, &ARMDescs.OperandInfo[570] },  // Inst #3450 = VSCCLRMS
  { 3, &ARMDescs.OperandInfo[570] },  // Inst #3449 = VSCCLRMD
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3448 = VRSUBHNv8i8
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3447 = VRSUBHNv4i16
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3446 = VRSUBHNv2i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3445 = VRSRAuv8i8
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3444 = VRSRAuv8i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3443 = VRSRAuv4i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3442 = VRSRAuv4i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3441 = VRSRAuv2i64
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3440 = VRSRAuv2i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3439 = VRSRAuv1i64
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3438 = VRSRAuv16i8
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3437 = VRSRAsv8i8
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3436 = VRSRAsv8i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3435 = VRSRAsv4i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3434 = VRSRAsv4i16
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3433 = VRSRAsv2i64
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3432 = VRSRAsv2i32
  { 6, &ARMDescs.OperandInfo[2331] },  // Inst #3431 = VRSRAsv1i64
  { 6, &ARMDescs.OperandInfo[2325] },  // Inst #3430 = VRSRAsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3429 = VRSQRTShq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3428 = VRSQRTShd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3427 = VRSQRTSfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3426 = VRSQRTSfd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3425 = VRSQRTEq
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3424 = VRSQRTEhq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3423 = VRSQRTEhd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3422 = VRSQRTEfq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3421 = VRSQRTEfd
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3420 = VRSQRTEd
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3419 = VRSHRuv8i8
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3418 = VRSHRuv8i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3417 = VRSHRuv4i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3416 = VRSHRuv4i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3415 = VRSHRuv2i64
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3414 = VRSHRuv2i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3413 = VRSHRuv1i64
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3412 = VRSHRuv16i8
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3411 = VRSHRsv8i8
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3410 = VRSHRsv8i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3409 = VRSHRsv4i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3408 = VRSHRsv4i16
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3407 = VRSHRsv2i64
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3406 = VRSHRsv2i32
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #3405 = VRSHRsv1i64
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #3404 = VRSHRsv16i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3403 = VRSHRNv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3402 = VRSHRNv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3401 = VRSHRNv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3400 = VRSHLuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3399 = VRSHLuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3398 = VRSHLuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3397 = VRSHLuv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3396 = VRSHLuv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3395 = VRSHLuv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3394 = VRSHLuv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3393 = VRSHLuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3392 = VRSHLsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3391 = VRSHLsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3390 = VRSHLsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3389 = VRSHLsv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3388 = VRSHLsv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3387 = VRSHLsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3386 = VRSHLsv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3385 = VRSHLsv16i8
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3384 = VRINTZS
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3383 = VRINTZNQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3382 = VRINTZNQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3381 = VRINTZNDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3380 = VRINTZNDf
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #3379 = VRINTZH
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3378 = VRINTZD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3377 = VRINTXS
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3376 = VRINTXNQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3375 = VRINTXNQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3374 = VRINTXNDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3373 = VRINTXNDf
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #3372 = VRINTXH
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3371 = VRINTXD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3370 = VRINTRS
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #3369 = VRINTRH
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3368 = VRINTRD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #3367 = VRINTPS
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3366 = VRINTPNQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3365 = VRINTPNQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3364 = VRINTPNDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3363 = VRINTPNDf
  { 2, &ARMDescs.OperandInfo[2323] },  // Inst #3362 = VRINTPH
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3361 = VRINTPD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #3360 = VRINTNS
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3359 = VRINTNNQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3358 = VRINTNNQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3357 = VRINTNNDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3356 = VRINTNNDf
  { 2, &ARMDescs.OperandInfo[2323] },  // Inst #3355 = VRINTNH
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3354 = VRINTND
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #3353 = VRINTMS
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3352 = VRINTMNQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3351 = VRINTMNQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3350 = VRINTMNDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3349 = VRINTMNDf
  { 2, &ARMDescs.OperandInfo[2323] },  // Inst #3348 = VRINTMH
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3347 = VRINTMD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #3346 = VRINTAS
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3345 = VRINTANQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #3344 = VRINTANQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3343 = VRINTANDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3342 = VRINTANDf
  { 2, &ARMDescs.OperandInfo[2323] },  // Inst #3341 = VRINTAH
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #3340 = VRINTAD
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3339 = VRHADDuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3338 = VRHADDuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3337 = VRHADDuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3336 = VRHADDuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3335 = VRHADDuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3334 = VRHADDuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3333 = VRHADDsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3332 = VRHADDsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3331 = VRHADDsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3330 = VRHADDsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3329 = VRHADDsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3328 = VRHADDsv16i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3327 = VREV64q8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3326 = VREV64q32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3325 = VREV64q16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3324 = VREV64d8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3323 = VREV64d32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3322 = VREV64d16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3321 = VREV32q8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3320 = VREV32q16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3319 = VREV32d8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3318 = VREV32d16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3317 = VREV16q8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3316 = VREV16d8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3315 = VRECPShq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3314 = VRECPShd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3313 = VRECPSfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3312 = VRECPSfd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3311 = VRECPEq
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3310 = VRECPEhq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3309 = VRECPEhd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3308 = VRECPEfq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3307 = VRECPEfd
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3306 = VRECPEd
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3305 = VRADDHNv8i8
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3304 = VRADDHNv4i16
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #3303 = VRADDHNv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3302 = VQSUBuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3301 = VQSUBuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3300 = VQSUBuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3299 = VQSUBuv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3298 = VQSUBuv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3297 = VQSUBuv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3296 = VQSUBuv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3295 = VQSUBuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3294 = VQSUBsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3293 = VQSUBsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3292 = VQSUBsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3291 = VQSUBsv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3290 = VQSUBsv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3289 = VQSUBsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3288 = VQSUBsv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3287 = VQSUBsv16i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3286 = VQSHRUNv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3285 = VQSHRUNv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3284 = VQSHRUNv2i32
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3283 = VQSHRNuv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3282 = VQSHRNuv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3281 = VQSHRNuv2i32
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3280 = VQSHRNsv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3279 = VQSHRNsv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3278 = VQSHRNsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3277 = VQSHLuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3276 = VQSHLuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3275 = VQSHLuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3274 = VQSHLuv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3273 = VQSHLuv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3272 = VQSHLuv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3271 = VQSHLuv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3270 = VQSHLuv16i8
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3269 = VQSHLuiv8i8
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3268 = VQSHLuiv8i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3267 = VQSHLuiv4i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3266 = VQSHLuiv4i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3265 = VQSHLuiv2i64
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3264 = VQSHLuiv2i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3263 = VQSHLuiv1i64
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3262 = VQSHLuiv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3261 = VQSHLsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3260 = VQSHLsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3259 = VQSHLsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3258 = VQSHLsv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3257 = VQSHLsv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3256 = VQSHLsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3255 = VQSHLsv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3254 = VQSHLsv16i8
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3253 = VQSHLsuv8i8
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3252 = VQSHLsuv8i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3251 = VQSHLsuv4i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3250 = VQSHLsuv4i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3249 = VQSHLsuv2i64
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3248 = VQSHLsuv2i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3247 = VQSHLsuv1i64
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3246 = VQSHLsuv16i8
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3245 = VQSHLsiv8i8
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3244 = VQSHLsiv8i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3243 = VQSHLsiv4i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3242 = VQSHLsiv4i16
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3241 = VQSHLsiv2i64
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3240 = VQSHLsiv2i32
  { 5, &ARMDescs.OperandInfo[2318] },  // Inst #3239 = VQSHLsiv1i64
  { 5, &ARMDescs.OperandInfo[2313] },  // Inst #3238 = VQSHLsiv16i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3237 = VQRSHRUNv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3236 = VQRSHRUNv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3235 = VQRSHRUNv2i32
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3234 = VQRSHRNuv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3233 = VQRSHRNuv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3232 = VQRSHRNuv2i32
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3231 = VQRSHRNsv8i8
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3230 = VQRSHRNsv4i16
  { 5, &ARMDescs.OperandInfo[2308] },  // Inst #3229 = VQRSHRNsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3228 = VQRSHLuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3227 = VQRSHLuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3226 = VQRSHLuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3225 = VQRSHLuv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3224 = VQRSHLuv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3223 = VQRSHLuv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3222 = VQRSHLuv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3221 = VQRSHLuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3220 = VQRSHLsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3219 = VQRSHLsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3218 = VQRSHLsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3217 = VQRSHLsv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3216 = VQRSHLsv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3215 = VQRSHLsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3214 = VQRSHLsv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3213 = VQRSHLsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3212 = VQRDMULHv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3211 = VQRDMULHv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3210 = VQRDMULHv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3209 = VQRDMULHv2i32
  { 6, &ARMDescs.OperandInfo[2297] },  // Inst #3208 = VQRDMULHslv8i16
  { 6, &ARMDescs.OperandInfo[2285] },  // Inst #3207 = VQRDMULHslv4i32
  { 6, &ARMDescs.OperandInfo[2291] },  // Inst #3206 = VQRDMULHslv4i16
  { 6, &ARMDescs.OperandInfo[2279] },  // Inst #3205 = VQRDMULHslv2i32
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #3204 = VQRDMLSHv8i16
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #3203 = VQRDMLSHv4i32
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3202 = VQRDMLSHv4i16
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3201 = VQRDMLSHv2i32
  { 7, &ARMDescs.OperandInfo[2202] },  // Inst #3200 = VQRDMLSHslv8i16
  { 7, &ARMDescs.OperandInfo[2188] },  // Inst #3199 = VQRDMLSHslv4i32
  { 7, &ARMDescs.OperandInfo[2195] },  // Inst #3198 = VQRDMLSHslv4i16
  { 7, &ARMDescs.OperandInfo[2181] },  // Inst #3197 = VQRDMLSHslv2i32
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #3196 = VQRDMLAHv8i16
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #3195 = VQRDMLAHv4i32
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3194 = VQRDMLAHv4i16
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3193 = VQRDMLAHv2i32
  { 7, &ARMDescs.OperandInfo[2202] },  // Inst #3192 = VQRDMLAHslv8i16
  { 7, &ARMDescs.OperandInfo[2188] },  // Inst #3191 = VQRDMLAHslv4i32
  { 7, &ARMDescs.OperandInfo[2195] },  // Inst #3190 = VQRDMLAHslv4i16
  { 7, &ARMDescs.OperandInfo[2181] },  // Inst #3189 = VQRDMLAHslv2i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3188 = VQNEGv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3187 = VQNEGv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3186 = VQNEGv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3185 = VQNEGv4i16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3184 = VQNEGv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3183 = VQNEGv16i8
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3182 = VQMOVNuv8i8
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3181 = VQMOVNuv4i16
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3180 = VQMOVNuv2i32
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3179 = VQMOVNsv8i8
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3178 = VQMOVNsv4i16
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3177 = VQMOVNsv2i32
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3176 = VQMOVNsuv8i8
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3175 = VQMOVNsuv4i16
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #3174 = VQMOVNsuv2i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3173 = VQDMULLv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3172 = VQDMULLv2i64
  { 6, &ARMDescs.OperandInfo[2273] },  // Inst #3171 = VQDMULLslv4i16
  { 6, &ARMDescs.OperandInfo[2267] },  // Inst #3170 = VQDMULLslv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3169 = VQDMULHv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3168 = VQDMULHv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3167 = VQDMULHv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3166 = VQDMULHv2i32
  { 6, &ARMDescs.OperandInfo[2297] },  // Inst #3165 = VQDMULHslv8i16
  { 6, &ARMDescs.OperandInfo[2285] },  // Inst #3164 = VQDMULHslv4i32
  { 6, &ARMDescs.OperandInfo[2291] },  // Inst #3163 = VQDMULHslv4i16
  { 6, &ARMDescs.OperandInfo[2279] },  // Inst #3162 = VQDMULHslv2i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #3161 = VQDMLSLv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #3160 = VQDMLSLv2i64
  { 7, &ARMDescs.OperandInfo[2174] },  // Inst #3159 = VQDMLSLslv4i16
  { 7, &ARMDescs.OperandInfo[2167] },  // Inst #3158 = VQDMLSLslv2i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #3157 = VQDMLALv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #3156 = VQDMLALv2i64
  { 7, &ARMDescs.OperandInfo[2174] },  // Inst #3155 = VQDMLALslv4i16
  { 7, &ARMDescs.OperandInfo[2167] },  // Inst #3154 = VQDMLALslv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3153 = VQADDuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3152 = VQADDuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3151 = VQADDuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3150 = VQADDuv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3149 = VQADDuv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3148 = VQADDuv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3147 = VQADDuv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3146 = VQADDuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3145 = VQADDsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3144 = VQADDsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3143 = VQADDsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3142 = VQADDsv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3141 = VQADDsv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3140 = VQADDsv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3139 = VQADDsv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3138 = VQADDsv16i8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3137 = VQABSv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3136 = VQABSv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3135 = VQABSv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3134 = VQABSv4i16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3133 = VQABSv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3132 = VQABSv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3131 = VPMINu8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3130 = VPMINu32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3129 = VPMINu16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3128 = VPMINs8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3127 = VPMINs32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3126 = VPMINs16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3125 = VPMINh
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3124 = VPMINf
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3123 = VPMAXu8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3122 = VPMAXu32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3121 = VPMAXu16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3120 = VPMAXs8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3119 = VPMAXs32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3118 = VPMAXs16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3117 = VPMAXh
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3116 = VPMAXf
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3115 = VPADDi8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3114 = VPADDi32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3113 = VPADDi16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3112 = VPADDh
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3111 = VPADDf
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3110 = VPADDLuv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3109 = VPADDLuv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3108 = VPADDLuv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3107 = VPADDLuv4i16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3106 = VPADDLuv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3105 = VPADDLuv16i8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3104 = VPADDLsv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3103 = VPADDLsv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3102 = VPADDLsv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3101 = VPADDLsv4i16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3100 = VPADDLsv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3099 = VPADDLsv16i8
  { 5, &ARMDescs.OperandInfo[383] },  // Inst #3098 = VPADALuv8i8
  { 5, &ARMDescs.OperandInfo[2303] },  // Inst #3097 = VPADALuv8i16
  { 5, &ARMDescs.OperandInfo[2303] },  // Inst #3096 = VPADALuv4i32
  { 5, &ARMDescs.OperandInfo[383] },  // Inst #3095 = VPADALuv4i16
  { 5, &ARMDescs.OperandInfo[383] },  // Inst #3094 = VPADALuv2i32
  { 5, &ARMDescs.OperandInfo[2303] },  // Inst #3093 = VPADALuv16i8
  { 5, &ARMDescs.OperandInfo[383] },  // Inst #3092 = VPADALsv8i8
  { 5, &ARMDescs.OperandInfo[2303] },  // Inst #3091 = VPADALsv8i16
  { 5, &ARMDescs.OperandInfo[2303] },  // Inst #3090 = VPADALsv4i32
  { 5, &ARMDescs.OperandInfo[383] },  // Inst #3089 = VPADALsv4i16
  { 5, &ARMDescs.OperandInfo[383] },  // Inst #3088 = VPADALsv2i32
  { 5, &ARMDescs.OperandInfo[2303] },  // Inst #3087 = VPADALsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3086 = VORRq
  { 5, &ARMDescs.OperandInfo[1707] },  // Inst #3085 = VORRiv8i16
  { 5, &ARMDescs.OperandInfo[1707] },  // Inst #3084 = VORRiv4i32
  { 5, &ARMDescs.OperandInfo[1702] },  // Inst #3083 = VORRiv4i16
  { 5, &ARMDescs.OperandInfo[1702] },  // Inst #3082 = VORRiv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3081 = VORRd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3080 = VORNq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3079 = VORNd
  { 5, &ARMDescs.OperandInfo[1687] },  // Inst #3078 = VNMULS
  { 5, &ARMDescs.OperandInfo[1677] },  // Inst #3077 = VNMULH
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3076 = VNMULD
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #3075 = VNMLSS
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #3074 = VNMLSH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3073 = VNMLSD
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #3072 = VNMLAS
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #3071 = VNMLAH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #3070 = VNMLAD
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3069 = VNEGs8q
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3068 = VNEGs8d
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3067 = VNEGs32q
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3066 = VNEGs32d
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3065 = VNEGs16q
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3064 = VNEGs16d
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3063 = VNEGhq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3062 = VNEGhd
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3061 = VNEGfd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3060 = VNEGf32q
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #3059 = VNEGS
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #3058 = VNEGH
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3057 = VNEGD
  { 4, &ARMDescs.OperandInfo[2247] },  // Inst #3056 = VMVNv8i16
  { 4, &ARMDescs.OperandInfo[2247] },  // Inst #3055 = VMVNv4i32
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #3054 = VMVNv4i16
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #3053 = VMVNv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #3052 = VMVNq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #3051 = VMVNd
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3050 = VMULv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3049 = VMULv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3048 = VMULv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3047 = VMULv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3046 = VMULv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3045 = VMULv16i8
  { 6, &ARMDescs.OperandInfo[2297] },  // Inst #3044 = VMULslv8i16
  { 6, &ARMDescs.OperandInfo[2285] },  // Inst #3043 = VMULslv4i32
  { 6, &ARMDescs.OperandInfo[2291] },  // Inst #3042 = VMULslv4i16
  { 6, &ARMDescs.OperandInfo[2279] },  // Inst #3041 = VMULslv2i32
  { 6, &ARMDescs.OperandInfo[2297] },  // Inst #3040 = VMULslhq
  { 6, &ARMDescs.OperandInfo[2291] },  // Inst #3039 = VMULslhd
  { 6, &ARMDescs.OperandInfo[2285] },  // Inst #3038 = VMULslfq
  { 6, &ARMDescs.OperandInfo[2279] },  // Inst #3037 = VMULslfd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3036 = VMULpq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3035 = VMULpd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3034 = VMULhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3033 = VMULhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #3032 = VMULfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3031 = VMULfd
  { 5, &ARMDescs.OperandInfo[1687] },  // Inst #3030 = VMULS
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3029 = VMULLuv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3028 = VMULLuv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3027 = VMULLuv2i64
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3026 = VMULLsv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3025 = VMULLsv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3024 = VMULLsv2i64
  { 6, &ARMDescs.OperandInfo[2273] },  // Inst #3023 = VMULLsluv4i16
  { 6, &ARMDescs.OperandInfo[2267] },  // Inst #3022 = VMULLsluv2i32
  { 6, &ARMDescs.OperandInfo[2273] },  // Inst #3021 = VMULLslsv4i16
  { 6, &ARMDescs.OperandInfo[2267] },  // Inst #3020 = VMULLslsv2i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #3019 = VMULLp8
  { 3, &ARMDescs.OperandInfo[1848] },  // Inst #3018 = VMULLp64
  { 5, &ARMDescs.OperandInfo[1677] },  // Inst #3017 = VMULH
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #3016 = VMULD
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #3015 = VMSR_VPR
  { 4, &ARMDescs.OperandInfo[2263] },  // Inst #3014 = VMSR_P0
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3013 = VMSR_FPSID
  { 4, &ARMDescs.OperandInfo[2259] },  // Inst #3012 = VMSR_FPSCR_NZCVQC
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3011 = VMSR_FPINST2
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3010 = VMSR_FPINST
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3009 = VMSR_FPEXC
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #3008 = VMSR_FPCXTS
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #3007 = VMSR_FPCXTNS
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3006 = VMSR
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #3005 = VMRS_VPR
  { 4, &ARMDescs.OperandInfo[2255] },  // Inst #3004 = VMRS_P0
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3003 = VMRS_MVFR2
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3002 = VMRS_MVFR1
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3001 = VMRS_MVFR0
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #3000 = VMRS_FPSID
  { 4, &ARMDescs.OperandInfo[2251] },  // Inst #2999 = VMRS_FPSCR_NZCVQC
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #2998 = VMRS_FPINST2
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #2997 = VMRS_FPINST
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #2996 = VMRS_FPEXC
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #2995 = VMRS_FPCXTS
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #2994 = VMRS_FPCXTNS
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #2993 = VMRS
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #2992 = VMOVv8i8
  { 4, &ARMDescs.OperandInfo[2247] },  // Inst #2991 = VMOVv8i16
  { 4, &ARMDescs.OperandInfo[2247] },  // Inst #2990 = VMOVv4i32
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #2989 = VMOVv4i16
  { 4, &ARMDescs.OperandInfo[2247] },  // Inst #2988 = VMOVv4f32
  { 4, &ARMDescs.OperandInfo[2247] },  // Inst #2987 = VMOVv2i64
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #2986 = VMOVv2i32
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #2985 = VMOVv2f32
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #2984 = VMOVv1i64
  { 4, &ARMDescs.OperandInfo[2247] },  // Inst #2983 = VMOVv16i8
  { 6, &ARMDescs.OperandInfo[2241] },  // Inst #2982 = VMOVSRR
  { 4, &ARMDescs.OperandInfo[2237] },  // Inst #2981 = VMOVSR
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #2980 = VMOVS
  { 4, &ARMDescs.OperandInfo[2233] },  // Inst #2979 = VMOVRS
  { 6, &ARMDescs.OperandInfo[2227] },  // Inst #2978 = VMOVRRS
  { 5, &ARMDescs.OperandInfo[2222] },  // Inst #2977 = VMOVRRD
  { 4, &ARMDescs.OperandInfo[2218] },  // Inst #2976 = VMOVRH
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #2975 = VMOVNv8i8
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #2974 = VMOVNv4i16
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #2973 = VMOVNv2i32
  { 4, &ARMDescs.OperandInfo[1806] },  // Inst #2972 = VMOVLuv8i16
  { 4, &ARMDescs.OperandInfo[1806] },  // Inst #2971 = VMOVLuv4i32
  { 4, &ARMDescs.OperandInfo[1806] },  // Inst #2970 = VMOVLuv2i64
  { 4, &ARMDescs.OperandInfo[1806] },  // Inst #2969 = VMOVLsv8i16
  { 4, &ARMDescs.OperandInfo[1806] },  // Inst #2968 = VMOVLsv4i32
  { 4, &ARMDescs.OperandInfo[1806] },  // Inst #2967 = VMOVLsv2i64
  { 4, &ARMDescs.OperandInfo[2214] },  // Inst #2966 = VMOVHR
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2965 = VMOVH
  { 5, &ARMDescs.OperandInfo[2209] },  // Inst #2964 = VMOVDRR
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2963 = VMOVD
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #2962 = VMMLA
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2961 = VMLSv8i8
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2960 = VMLSv8i16
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2959 = VMLSv4i32
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2958 = VMLSv4i16
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2957 = VMLSv2i32
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2956 = VMLSv16i8
  { 7, &ARMDescs.OperandInfo[2202] },  // Inst #2955 = VMLSslv8i16
  { 7, &ARMDescs.OperandInfo[2188] },  // Inst #2954 = VMLSslv4i32
  { 7, &ARMDescs.OperandInfo[2195] },  // Inst #2953 = VMLSslv4i16
  { 7, &ARMDescs.OperandInfo[2181] },  // Inst #2952 = VMLSslv2i32
  { 7, &ARMDescs.OperandInfo[2202] },  // Inst #2951 = VMLSslhq
  { 7, &ARMDescs.OperandInfo[2195] },  // Inst #2950 = VMLSslhd
  { 7, &ARMDescs.OperandInfo[2188] },  // Inst #2949 = VMLSslfq
  { 7, &ARMDescs.OperandInfo[2181] },  // Inst #2948 = VMLSslfd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2947 = VMLShq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2946 = VMLShd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2945 = VMLSfq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2944 = VMLSfd
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #2943 = VMLSS
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2942 = VMLSLuv8i16
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2941 = VMLSLuv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2940 = VMLSLuv2i64
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2939 = VMLSLsv8i16
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2938 = VMLSLsv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2937 = VMLSLsv2i64
  { 7, &ARMDescs.OperandInfo[2174] },  // Inst #2936 = VMLSLsluv4i16
  { 7, &ARMDescs.OperandInfo[2167] },  // Inst #2935 = VMLSLsluv2i32
  { 7, &ARMDescs.OperandInfo[2174] },  // Inst #2934 = VMLSLslsv4i16
  { 7, &ARMDescs.OperandInfo[2167] },  // Inst #2933 = VMLSLslsv2i32
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #2932 = VMLSH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2931 = VMLSD
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2930 = VMLAv8i8
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2929 = VMLAv8i16
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2928 = VMLAv4i32
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2927 = VMLAv4i16
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2926 = VMLAv2i32
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2925 = VMLAv16i8
  { 7, &ARMDescs.OperandInfo[2202] },  // Inst #2924 = VMLAslv8i16
  { 7, &ARMDescs.OperandInfo[2188] },  // Inst #2923 = VMLAslv4i32
  { 7, &ARMDescs.OperandInfo[2195] },  // Inst #2922 = VMLAslv4i16
  { 7, &ARMDescs.OperandInfo[2181] },  // Inst #2921 = VMLAslv2i32
  { 7, &ARMDescs.OperandInfo[2202] },  // Inst #2920 = VMLAslhq
  { 7, &ARMDescs.OperandInfo[2195] },  // Inst #2919 = VMLAslhd
  { 7, &ARMDescs.OperandInfo[2188] },  // Inst #2918 = VMLAslfq
  { 7, &ARMDescs.OperandInfo[2181] },  // Inst #2917 = VMLAslfd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2916 = VMLAhq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2915 = VMLAhd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2914 = VMLAfq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2913 = VMLAfd
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #2912 = VMLAS
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2911 = VMLALuv8i16
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2910 = VMLALuv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2909 = VMLALuv2i64
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2908 = VMLALsv8i16
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2907 = VMLALsv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2906 = VMLALsv2i64
  { 7, &ARMDescs.OperandInfo[2174] },  // Inst #2905 = VMLALsluv4i16
  { 7, &ARMDescs.OperandInfo[2167] },  // Inst #2904 = VMLALsluv2i32
  { 7, &ARMDescs.OperandInfo[2174] },  // Inst #2903 = VMLALslsv4i16
  { 7, &ARMDescs.OperandInfo[2167] },  // Inst #2902 = VMLALslsv2i32
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #2901 = VMLAH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2900 = VMLAD
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2899 = VMINuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2898 = VMINuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2897 = VMINuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2896 = VMINuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2895 = VMINuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2894 = VMINuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2893 = VMINsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2892 = VMINsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2891 = VMINsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2890 = VMINsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2889 = VMINsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2888 = VMINsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2887 = VMINhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2886 = VMINhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2885 = VMINfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2884 = VMINfd
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2883 = VMAXuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2882 = VMAXuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2881 = VMAXuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2880 = VMAXuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2879 = VMAXuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2878 = VMAXuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2877 = VMAXsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2876 = VMAXsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2875 = VMAXsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2874 = VMAXsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2873 = VMAXsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2872 = VMAXsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2871 = VMAXhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2870 = VMAXhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2869 = VMAXfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2868 = VMAXfd
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #2867 = VLSTM
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #2866 = VLLDM
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2865 = VLDR_VPR_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2864 = VLDR_VPR_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #2863 = VLDR_VPR_off
  { 6, &ARMDescs.OperandInfo[2161] },  // Inst #2862 = VLDR_P0_pre
  { 6, &ARMDescs.OperandInfo[2161] },  // Inst #2861 = VLDR_P0_post
  { 5, &ARMDescs.OperandInfo[2156] },  // Inst #2860 = VLDR_P0_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2859 = VLDR_FPSCR_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2858 = VLDR_FPSCR_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #2857 = VLDR_FPSCR_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2856 = VLDR_FPSCR_NZCVQC_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2855 = VLDR_FPSCR_NZCVQC_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #2854 = VLDR_FPSCR_NZCVQC_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2853 = VLDR_FPCXTS_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2852 = VLDR_FPCXTS_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #2851 = VLDR_FPCXTS_off
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2850 = VLDR_FPCXTNS_pre
  { 5, &ARMDescs.OperandInfo[2151] },  // Inst #2849 = VLDR_FPCXTNS_post
  { 4, &ARMDescs.OperandInfo[2147] },  // Inst #2848 = VLDR_FPCXTNS_off
  { 5, &ARMDescs.OperandInfo[2142] },  // Inst #2847 = VLDRS
  { 5, &ARMDescs.OperandInfo[2137] },  // Inst #2846 = VLDRH
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2845 = VLDRD
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #2844 = VLDMSIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #2843 = VLDMSIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #2842 = VLDMSDB_UPD
  { 4, &ARMDescs.OperandInfo[2133] },  // Inst #2841 = VLDMQIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #2840 = VLDMDIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #2839 = VLDMDIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #2838 = VLDMDDB_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2837 = VLD4q8oddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2836 = VLD4q8oddPseudo
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2835 = VLD4q8_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2834 = VLD4q8Pseudo_UPD
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2833 = VLD4q8
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2832 = VLD4q32oddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2831 = VLD4q32oddPseudo
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2830 = VLD4q32_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2829 = VLD4q32Pseudo_UPD
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2828 = VLD4q32
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2827 = VLD4q16oddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2826 = VLD4q16oddPseudo
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2825 = VLD4q16_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2824 = VLD4q16Pseudo_UPD
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2823 = VLD4q16
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2822 = VLD4d8_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2821 = VLD4d8Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2820 = VLD4d8Pseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2819 = VLD4d8
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2818 = VLD4d32_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2817 = VLD4d32Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2816 = VLD4d32Pseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2815 = VLD4d32
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2814 = VLD4d16_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2813 = VLD4d16Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2812 = VLD4d16Pseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2811 = VLD4d16
  { 15, &ARMDescs.OperandInfo[2118] },  // Inst #2810 = VLD4LNq32_UPD
  { 9, &ARMDescs.OperandInfo[2078] },  // Inst #2809 = VLD4LNq32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2071] },  // Inst #2808 = VLD4LNq32Pseudo
  { 13, &ARMDescs.OperandInfo[2105] },  // Inst #2807 = VLD4LNq32
  { 15, &ARMDescs.OperandInfo[2118] },  // Inst #2806 = VLD4LNq16_UPD
  { 9, &ARMDescs.OperandInfo[2078] },  // Inst #2805 = VLD4LNq16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2071] },  // Inst #2804 = VLD4LNq16Pseudo
  { 13, &ARMDescs.OperandInfo[2105] },  // Inst #2803 = VLD4LNq16
  { 15, &ARMDescs.OperandInfo[2118] },  // Inst #2802 = VLD4LNd8_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2801 = VLD4LNd8Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2800 = VLD4LNd8Pseudo
  { 13, &ARMDescs.OperandInfo[2105] },  // Inst #2799 = VLD4LNd8
  { 15, &ARMDescs.OperandInfo[2118] },  // Inst #2798 = VLD4LNd32_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2797 = VLD4LNd32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2796 = VLD4LNd32Pseudo
  { 13, &ARMDescs.OperandInfo[2105] },  // Inst #2795 = VLD4LNd32
  { 15, &ARMDescs.OperandInfo[2118] },  // Inst #2794 = VLD4LNd16_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2793 = VLD4LNd16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2792 = VLD4LNd16Pseudo
  { 13, &ARMDescs.OperandInfo[2105] },  // Inst #2791 = VLD4LNd16
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2790 = VLD4DUPq8_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2789 = VLD4DUPq8OddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2788 = VLD4DUPq8OddPseudo
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2787 = VLD4DUPq8EvenPseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2786 = VLD4DUPq8
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2785 = VLD4DUPq32_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2784 = VLD4DUPq32OddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2783 = VLD4DUPq32OddPseudo
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2782 = VLD4DUPq32EvenPseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2781 = VLD4DUPq32
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2780 = VLD4DUPq16_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2779 = VLD4DUPq16OddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2778 = VLD4DUPq16OddPseudo
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2777 = VLD4DUPq16EvenPseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2776 = VLD4DUPq16
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2775 = VLD4DUPd8_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2774 = VLD4DUPd8Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2773 = VLD4DUPd8Pseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2772 = VLD4DUPd8
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2771 = VLD4DUPd32_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2770 = VLD4DUPd32Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2769 = VLD4DUPd32Pseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2768 = VLD4DUPd32
  { 10, &ARMDescs.OperandInfo[2095] },  // Inst #2767 = VLD4DUPd16_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2766 = VLD4DUPd16Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2765 = VLD4DUPd16Pseudo
  { 8, &ARMDescs.OperandInfo[2087] },  // Inst #2764 = VLD4DUPd16
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2763 = VLD3q8oddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2762 = VLD3q8oddPseudo
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2761 = VLD3q8_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2760 = VLD3q8Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2759 = VLD3q8
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2758 = VLD3q32oddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2757 = VLD3q32oddPseudo
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2756 = VLD3q32_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2755 = VLD3q32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2754 = VLD3q32
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2753 = VLD3q16oddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2752 = VLD3q16oddPseudo
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2751 = VLD3q16_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2750 = VLD3q16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2749 = VLD3q16
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2748 = VLD3d8_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2747 = VLD3d8Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2746 = VLD3d8Pseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2745 = VLD3d8
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2744 = VLD3d32_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2743 = VLD3d32Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2742 = VLD3d32Pseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2741 = VLD3d32
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2740 = VLD3d16_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2739 = VLD3d16Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2738 = VLD3d16Pseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2737 = VLD3d16
  { 13, &ARMDescs.OperandInfo[2058] },  // Inst #2736 = VLD3LNq32_UPD
  { 9, &ARMDescs.OperandInfo[2078] },  // Inst #2735 = VLD3LNq32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2071] },  // Inst #2734 = VLD3LNq32Pseudo
  { 11, &ARMDescs.OperandInfo[2047] },  // Inst #2733 = VLD3LNq32
  { 13, &ARMDescs.OperandInfo[2058] },  // Inst #2732 = VLD3LNq16_UPD
  { 9, &ARMDescs.OperandInfo[2078] },  // Inst #2731 = VLD3LNq16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2071] },  // Inst #2730 = VLD3LNq16Pseudo
  { 11, &ARMDescs.OperandInfo[2047] },  // Inst #2729 = VLD3LNq16
  { 13, &ARMDescs.OperandInfo[2058] },  // Inst #2728 = VLD3LNd8_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2727 = VLD3LNd8Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2726 = VLD3LNd8Pseudo
  { 11, &ARMDescs.OperandInfo[2047] },  // Inst #2725 = VLD3LNd8
  { 13, &ARMDescs.OperandInfo[2058] },  // Inst #2724 = VLD3LNd32_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2723 = VLD3LNd32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2722 = VLD3LNd32Pseudo
  { 11, &ARMDescs.OperandInfo[2047] },  // Inst #2721 = VLD3LNd32
  { 13, &ARMDescs.OperandInfo[2058] },  // Inst #2720 = VLD3LNd16_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2719 = VLD3LNd16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2718 = VLD3LNd16Pseudo
  { 11, &ARMDescs.OperandInfo[2047] },  // Inst #2717 = VLD3LNd16
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2716 = VLD3DUPq8_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2715 = VLD3DUPq8OddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2714 = VLD3DUPq8OddPseudo
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2713 = VLD3DUPq8EvenPseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2712 = VLD3DUPq8
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2711 = VLD3DUPq32_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2710 = VLD3DUPq32OddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2709 = VLD3DUPq32OddPseudo
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2708 = VLD3DUPq32EvenPseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2707 = VLD3DUPq32
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2706 = VLD3DUPq16_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2705 = VLD3DUPq16OddPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2704 = VLD3DUPq16OddPseudo
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2703 = VLD3DUPq16EvenPseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2702 = VLD3DUPq16
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2701 = VLD3DUPd8_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2700 = VLD3DUPd8Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2699 = VLD3DUPd8Pseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2698 = VLD3DUPd8
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2697 = VLD3DUPd32_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2696 = VLD3DUPd32Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2695 = VLD3DUPd32Pseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2694 = VLD3DUPd32
  { 9, &ARMDescs.OperandInfo[2038] },  // Inst #2693 = VLD3DUPd16_UPD
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2692 = VLD3DUPd16Pseudo_UPD
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2691 = VLD3DUPd16Pseudo
  { 7, &ARMDescs.OperandInfo[2031] },  // Inst #2690 = VLD3DUPd16
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2689 = VLD2q8wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2688 = VLD2q8wb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2687 = VLD2q8PseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2686 = VLD2q8PseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2685 = VLD2q8Pseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2684 = VLD2q8
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2683 = VLD2q32wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2682 = VLD2q32wb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2681 = VLD2q32PseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2680 = VLD2q32PseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2679 = VLD2q32Pseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2678 = VLD2q32
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2677 = VLD2q16wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2676 = VLD2q16wb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2675 = VLD2q16PseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2674 = VLD2q16PseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2673 = VLD2q16Pseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2672 = VLD2q16
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2671 = VLD2d8wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2670 = VLD2d8wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2669 = VLD2d8
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2668 = VLD2d32wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2667 = VLD2d32wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2666 = VLD2d32
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2665 = VLD2d16wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2664 = VLD2d16wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2663 = VLD2d16
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2662 = VLD2b8wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2661 = VLD2b8wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2660 = VLD2b8
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2659 = VLD2b32wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2658 = VLD2b32wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2657 = VLD2b32
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2656 = VLD2b16wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2655 = VLD2b16wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2654 = VLD2b16
  { 11, &ARMDescs.OperandInfo[2004] },  // Inst #2653 = VLD2LNq32_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2652 = VLD2LNq32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2651 = VLD2LNq32Pseudo
  { 9, &ARMDescs.OperandInfo[1995] },  // Inst #2650 = VLD2LNq32
  { 11, &ARMDescs.OperandInfo[2004] },  // Inst #2649 = VLD2LNq16_UPD
  { 9, &ARMDescs.OperandInfo[2022] },  // Inst #2648 = VLD2LNq16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[2015] },  // Inst #2647 = VLD2LNq16Pseudo
  { 9, &ARMDescs.OperandInfo[1995] },  // Inst #2646 = VLD2LNq16
  { 11, &ARMDescs.OperandInfo[2004] },  // Inst #2645 = VLD2LNd8_UPD
  { 9, &ARMDescs.OperandInfo[1929] },  // Inst #2644 = VLD2LNd8Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[1922] },  // Inst #2643 = VLD2LNd8Pseudo
  { 9, &ARMDescs.OperandInfo[1995] },  // Inst #2642 = VLD2LNd8
  { 11, &ARMDescs.OperandInfo[2004] },  // Inst #2641 = VLD2LNd32_UPD
  { 9, &ARMDescs.OperandInfo[1929] },  // Inst #2640 = VLD2LNd32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[1922] },  // Inst #2639 = VLD2LNd32Pseudo
  { 9, &ARMDescs.OperandInfo[1995] },  // Inst #2638 = VLD2LNd32
  { 11, &ARMDescs.OperandInfo[2004] },  // Inst #2637 = VLD2LNd16_UPD
  { 9, &ARMDescs.OperandInfo[1929] },  // Inst #2636 = VLD2LNd16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[1922] },  // Inst #2635 = VLD2LNd16Pseudo
  { 9, &ARMDescs.OperandInfo[1995] },  // Inst #2634 = VLD2LNd16
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2633 = VLD2DUPq8OddPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2632 = VLD2DUPq8OddPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2631 = VLD2DUPq8OddPseudo
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2630 = VLD2DUPq8EvenPseudo
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2629 = VLD2DUPq32OddPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2628 = VLD2DUPq32OddPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2627 = VLD2DUPq32OddPseudo
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2626 = VLD2DUPq32EvenPseudo
  { 7, &ARMDescs.OperandInfo[1988] },  // Inst #2625 = VLD2DUPq16OddPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2624 = VLD2DUPq16OddPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2623 = VLD2DUPq16OddPseudo
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2622 = VLD2DUPq16EvenPseudo
  { 7, &ARMDescs.OperandInfo[1981] },  // Inst #2621 = VLD2DUPd8x2wb_register
  { 6, &ARMDescs.OperandInfo[1975] },  // Inst #2620 = VLD2DUPd8x2wb_fixed
  { 5, &ARMDescs.OperandInfo[1970] },  // Inst #2619 = VLD2DUPd8x2
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2618 = VLD2DUPd8wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2617 = VLD2DUPd8wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2616 = VLD2DUPd8
  { 7, &ARMDescs.OperandInfo[1981] },  // Inst #2615 = VLD2DUPd32x2wb_register
  { 6, &ARMDescs.OperandInfo[1975] },  // Inst #2614 = VLD2DUPd32x2wb_fixed
  { 5, &ARMDescs.OperandInfo[1970] },  // Inst #2613 = VLD2DUPd32x2
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2612 = VLD2DUPd32wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2611 = VLD2DUPd32wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2610 = VLD2DUPd32
  { 7, &ARMDescs.OperandInfo[1981] },  // Inst #2609 = VLD2DUPd16x2wb_register
  { 6, &ARMDescs.OperandInfo[1975] },  // Inst #2608 = VLD2DUPd16x2wb_fixed
  { 5, &ARMDescs.OperandInfo[1970] },  // Inst #2607 = VLD2DUPd16x2
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2606 = VLD2DUPd16wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2605 = VLD2DUPd16wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2604 = VLD2DUPd16
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2603 = VLD1q8wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2602 = VLD1q8wb_fixed
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2601 = VLD1q8LowTPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2600 = VLD1q8LowQPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2599 = VLD1q8HighTPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2598 = VLD1q8HighTPseudo
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2597 = VLD1q8HighQPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2596 = VLD1q8HighQPseudo
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2595 = VLD1q8
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2594 = VLD1q64wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2593 = VLD1q64wb_fixed
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2592 = VLD1q64LowTPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2591 = VLD1q64LowQPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2590 = VLD1q64HighTPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2589 = VLD1q64HighTPseudo
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2588 = VLD1q64HighQPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2587 = VLD1q64HighQPseudo
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2586 = VLD1q64
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2585 = VLD1q32wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2584 = VLD1q32wb_fixed
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2583 = VLD1q32LowTPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2582 = VLD1q32LowQPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2581 = VLD1q32HighTPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2580 = VLD1q32HighTPseudo
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2579 = VLD1q32HighQPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2578 = VLD1q32HighQPseudo
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2577 = VLD1q32
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2576 = VLD1q16wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2575 = VLD1q16wb_fixed
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2574 = VLD1q16LowTPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2573 = VLD1q16LowQPseudo_UPD
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2572 = VLD1q16HighTPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2571 = VLD1q16HighTPseudo
  { 8, &ARMDescs.OperandInfo[1962] },  // Inst #2570 = VLD1q16HighQPseudo_UPD
  { 6, &ARMDescs.OperandInfo[1956] },  // Inst #2569 = VLD1q16HighQPseudo
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2568 = VLD1q16
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2567 = VLD1d8wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2566 = VLD1d8wb_fixed
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2565 = VLD1d8Twb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2564 = VLD1d8Twb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2563 = VLD1d8TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2562 = VLD1d8TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2561 = VLD1d8TPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2560 = VLD1d8T
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2559 = VLD1d8Qwb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2558 = VLD1d8Qwb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2557 = VLD1d8QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2556 = VLD1d8QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2555 = VLD1d8QPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2554 = VLD1d8Q
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2553 = VLD1d8
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2552 = VLD1d64wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2551 = VLD1d64wb_fixed
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2550 = VLD1d64Twb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2549 = VLD1d64Twb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2548 = VLD1d64TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2547 = VLD1d64TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2546 = VLD1d64TPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2545 = VLD1d64T
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2544 = VLD1d64Qwb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2543 = VLD1d64Qwb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2542 = VLD1d64QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2541 = VLD1d64QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2540 = VLD1d64QPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2539 = VLD1d64Q
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2538 = VLD1d64
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2537 = VLD1d32wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2536 = VLD1d32wb_fixed
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2535 = VLD1d32Twb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2534 = VLD1d32Twb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2533 = VLD1d32TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2532 = VLD1d32TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2531 = VLD1d32TPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2530 = VLD1d32T
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2529 = VLD1d32Qwb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2528 = VLD1d32Qwb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2527 = VLD1d32QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2526 = VLD1d32QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2525 = VLD1d32QPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2524 = VLD1d32Q
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2523 = VLD1d32
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2522 = VLD1d16wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2521 = VLD1d16wb_fixed
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2520 = VLD1d16Twb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2519 = VLD1d16Twb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2518 = VLD1d16TPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2517 = VLD1d16TPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2516 = VLD1d16TPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2515 = VLD1d16T
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2514 = VLD1d16Qwb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2513 = VLD1d16Qwb_fixed
  { 7, &ARMDescs.OperandInfo[1949] },  // Inst #2512 = VLD1d16QPseudoWB_register
  { 6, &ARMDescs.OperandInfo[1943] },  // Inst #2511 = VLD1d16QPseudoWB_fixed
  { 5, &ARMDescs.OperandInfo[1938] },  // Inst #2510 = VLD1d16QPseudo
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2509 = VLD1d16Q
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2508 = VLD1d16
  { 9, &ARMDescs.OperandInfo[1929] },  // Inst #2507 = VLD1LNq8Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[1922] },  // Inst #2506 = VLD1LNq8Pseudo
  { 9, &ARMDescs.OperandInfo[1929] },  // Inst #2505 = VLD1LNq32Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[1922] },  // Inst #2504 = VLD1LNq32Pseudo
  { 9, &ARMDescs.OperandInfo[1929] },  // Inst #2503 = VLD1LNq16Pseudo_UPD
  { 7, &ARMDescs.OperandInfo[1922] },  // Inst #2502 = VLD1LNq16Pseudo
  { 9, &ARMDescs.OperandInfo[1913] },  // Inst #2501 = VLD1LNd8_UPD
  { 7, &ARMDescs.OperandInfo[1906] },  // Inst #2500 = VLD1LNd8
  { 9, &ARMDescs.OperandInfo[1913] },  // Inst #2499 = VLD1LNd32_UPD
  { 7, &ARMDescs.OperandInfo[1906] },  // Inst #2498 = VLD1LNd32
  { 9, &ARMDescs.OperandInfo[1913] },  // Inst #2497 = VLD1LNd16_UPD
  { 7, &ARMDescs.OperandInfo[1906] },  // Inst #2496 = VLD1LNd16
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2495 = VLD1DUPq8wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2494 = VLD1DUPq8wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2493 = VLD1DUPq8
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2492 = VLD1DUPq32wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2491 = VLD1DUPq32wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2490 = VLD1DUPq32
  { 7, &ARMDescs.OperandInfo[1899] },  // Inst #2489 = VLD1DUPq16wb_register
  { 6, &ARMDescs.OperandInfo[1893] },  // Inst #2488 = VLD1DUPq16wb_fixed
  { 5, &ARMDescs.OperandInfo[1888] },  // Inst #2487 = VLD1DUPq16
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2486 = VLD1DUPd8wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2485 = VLD1DUPd8wb_fixed
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2484 = VLD1DUPd8
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2483 = VLD1DUPd32wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2482 = VLD1DUPd32wb_fixed
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2481 = VLD1DUPd32
  { 7, &ARMDescs.OperandInfo[1881] },  // Inst #2480 = VLD1DUPd16wb_register
  { 6, &ARMDescs.OperandInfo[1875] },  // Inst #2479 = VLD1DUPd16wb_fixed
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #2478 = VLD1DUPd16
  { 4, &ARMDescs.OperandInfo[1792] },  // Inst #2477 = VJCVT
  { 3, &ARMDescs.OperandInfo[1872] },  // Inst #2476 = VINSH
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2475 = VHSUBuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2474 = VHSUBuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2473 = VHSUBuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2472 = VHSUBuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2471 = VHSUBuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2470 = VHSUBuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2469 = VHSUBsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2468 = VHSUBsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2467 = VHSUBsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2466 = VHSUBsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2465 = VHSUBsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2464 = VHSUBsv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2463 = VHADDuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2462 = VHADDuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2461 = VHADDuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2460 = VHADDuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2459 = VHADDuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2458 = VHADDuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2457 = VHADDsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2456 = VHADDsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2455 = VHADDsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2454 = VHADDsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2453 = VHADDsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2452 = VHADDsv16i8
  { 5, &ARMDescs.OperandInfo[1867] },  // Inst #2451 = VGETLNu8
  { 5, &ARMDescs.OperandInfo[1867] },  // Inst #2450 = VGETLNu16
  { 5, &ARMDescs.OperandInfo[1867] },  // Inst #2449 = VGETLNs8
  { 5, &ARMDescs.OperandInfo[1867] },  // Inst #2448 = VGETLNs16
  { 5, &ARMDescs.OperandInfo[1867] },  // Inst #2447 = VGETLNi32
  { 3, &ARMDescs.OperandInfo[1864] },  // Inst #2446 = VFP_VMINNMS
  { 3, &ARMDescs.OperandInfo[1861] },  // Inst #2445 = VFP_VMINNMH
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #2444 = VFP_VMINNMD
  { 3, &ARMDescs.OperandInfo[1864] },  // Inst #2443 = VFP_VMAXNMS
  { 3, &ARMDescs.OperandInfo[1861] },  // Inst #2442 = VFP_VMAXNMH
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #2441 = VFP_VMAXNMD
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #2440 = VFNMSS
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #2439 = VFNMSH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2438 = VFNMSD
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #2437 = VFNMAS
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #2436 = VFNMAH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2435 = VFNMAD
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2434 = VFMShq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2433 = VFMShd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2432 = VFMSfq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2431 = VFMSfd
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #2430 = VFMSS
  { 4, &ARMDescs.OperandInfo[1851] },  // Inst #2429 = VFMSLQI
  { 3, &ARMDescs.OperandInfo[1848] },  // Inst #2428 = VFMSLQ
  { 4, &ARMDescs.OperandInfo[1844] },  // Inst #2427 = VFMSLDI
  { 3, &ARMDescs.OperandInfo[1841] },  // Inst #2426 = VFMSLD
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #2425 = VFMSH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2424 = VFMSD
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2423 = VFMAhq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2422 = VFMAhd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2421 = VFMAfq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2420 = VFMAfd
  { 6, &ARMDescs.OperandInfo[1855] },  // Inst #2419 = VFMAS
  { 4, &ARMDescs.OperandInfo[1851] },  // Inst #2418 = VFMALQI
  { 3, &ARMDescs.OperandInfo[1848] },  // Inst #2417 = VFMALQ
  { 4, &ARMDescs.OperandInfo[1844] },  // Inst #2416 = VFMALDI
  { 3, &ARMDescs.OperandInfo[1841] },  // Inst #2415 = VFMALD
  { 6, &ARMDescs.OperandInfo[1835] },  // Inst #2414 = VFMAH
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2413 = VFMAD
  { 6, &ARMDescs.OperandInfo[1829] },  // Inst #2412 = VEXTq8
  { 6, &ARMDescs.OperandInfo[1829] },  // Inst #2411 = VEXTq64
  { 6, &ARMDescs.OperandInfo[1829] },  // Inst #2410 = VEXTq32
  { 6, &ARMDescs.OperandInfo[1829] },  // Inst #2409 = VEXTq16
  { 6, &ARMDescs.OperandInfo[1823] },  // Inst #2408 = VEXTd8
  { 6, &ARMDescs.OperandInfo[1823] },  // Inst #2407 = VEXTd32
  { 6, &ARMDescs.OperandInfo[1823] },  // Inst #2406 = VEXTd16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2405 = VEORq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2404 = VEORd
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #2403 = VDUPLN8q
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2402 = VDUPLN8d
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #2401 = VDUPLN32q
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2400 = VDUPLN32d
  { 5, &ARMDescs.OperandInfo[1818] },  // Inst #2399 = VDUPLN16q
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2398 = VDUPLN16d
  { 4, &ARMDescs.OperandInfo[1814] },  // Inst #2397 = VDUP8q
  { 4, &ARMDescs.OperandInfo[1810] },  // Inst #2396 = VDUP8d
  { 4, &ARMDescs.OperandInfo[1814] },  // Inst #2395 = VDUP32q
  { 4, &ARMDescs.OperandInfo[1810] },  // Inst #2394 = VDUP32d
  { 4, &ARMDescs.OperandInfo[1814] },  // Inst #2393 = VDUP16q
  { 4, &ARMDescs.OperandInfo[1810] },  // Inst #2392 = VDUP16d
  { 5, &ARMDescs.OperandInfo[1687] },  // Inst #2391 = VDIVS
  { 5, &ARMDescs.OperandInfo[1677] },  // Inst #2390 = VDIVH
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2389 = VDIVD
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2388 = VCVTxu2hq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2387 = VCVTxu2hd
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2386 = VCVTxu2fq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2385 = VCVTxu2fd
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2384 = VCVTxs2hq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2383 = VCVTxs2hd
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2382 = VCVTxs2fq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2381 = VCVTxs2fd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2380 = VCVTu2hq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2379 = VCVTu2hd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2378 = VCVTu2fq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2377 = VCVTu2fd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2376 = VCVTs2hq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2375 = VCVTs2hd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2374 = VCVTs2fq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2373 = VCVTs2fd
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2372 = VCVTh2xuq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2371 = VCVTh2xud
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2370 = VCVTh2xsq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2369 = VCVTh2xsd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2368 = VCVTh2uq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2367 = VCVTh2ud
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2366 = VCVTh2sq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2365 = VCVTh2sd
  { 4, &ARMDescs.OperandInfo[1806] },  // Inst #2364 = VCVTh2f
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2363 = VCVTf2xuq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2362 = VCVTf2xud
  { 5, &ARMDescs.OperandInfo[1801] },  // Inst #2361 = VCVTf2xsq
  { 5, &ARMDescs.OperandInfo[1796] },  // Inst #2360 = VCVTf2xsd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2359 = VCVTf2uq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2358 = VCVTf2ud
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2357 = VCVTf2sq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2356 = VCVTf2sd
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #2355 = VCVTf2h
  { 5, &ARMDescs.OperandInfo[394] },  // Inst #2354 = VCVTTSH
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #2353 = VCVTTHS
  { 4, &ARMDescs.OperandInfo[1788] },  // Inst #2352 = VCVTTHD
  { 5, &ARMDescs.OperandInfo[1783] },  // Inst #2351 = VCVTTDH
  { 4, &ARMDescs.OperandInfo[1792] },  // Inst #2350 = VCVTSD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2349 = VCVTPUS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2348 = VCVTPUH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2347 = VCVTPUD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2346 = VCVTPSS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2345 = VCVTPSH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2344 = VCVTPSD
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2343 = VCVTPNUQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2342 = VCVTPNUQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2341 = VCVTPNUDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2340 = VCVTPNUDf
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2339 = VCVTPNSQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2338 = VCVTPNSQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2337 = VCVTPNSDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2336 = VCVTPNSDf
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2335 = VCVTNUS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2334 = VCVTNUH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2333 = VCVTNUD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2332 = VCVTNSS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2331 = VCVTNSH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2330 = VCVTNSD
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2329 = VCVTNNUQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2328 = VCVTNNUQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2327 = VCVTNNUDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2326 = VCVTNNUDf
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2325 = VCVTNNSQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2324 = VCVTNNSQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2323 = VCVTNNSDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2322 = VCVTNNSDf
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2321 = VCVTMUS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2320 = VCVTMUH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2319 = VCVTMUD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2318 = VCVTMSS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2317 = VCVTMSH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2316 = VCVTMSD
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2315 = VCVTMNUQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2314 = VCVTMNUQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2313 = VCVTMNUDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2312 = VCVTMNUDf
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2311 = VCVTMNSQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2310 = VCVTMNSQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2309 = VCVTMNSDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2308 = VCVTMNSDf
  { 4, &ARMDescs.OperandInfo[1788] },  // Inst #2307 = VCVTDS
  { 5, &ARMDescs.OperandInfo[394] },  // Inst #2306 = VCVTBSH
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #2305 = VCVTBHS
  { 4, &ARMDescs.OperandInfo[1788] },  // Inst #2304 = VCVTBHD
  { 5, &ARMDescs.OperandInfo[1783] },  // Inst #2303 = VCVTBDH
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2302 = VCVTAUS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2301 = VCVTAUH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2300 = VCVTAUD
  { 2, &ARMDescs.OperandInfo[1781] },  // Inst #2299 = VCVTASS
  { 2, &ARMDescs.OperandInfo[1779] },  // Inst #2298 = VCVTASH
  { 2, &ARMDescs.OperandInfo[1777] },  // Inst #2297 = VCVTASD
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2296 = VCVTANUQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2295 = VCVTANUQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2294 = VCVTANUDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2293 = VCVTANUDf
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2292 = VCVTANSQh
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #2291 = VCVTANSQf
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2290 = VCVTANSDh
  { 2, &ARMDescs.OperandInfo[1775] },  // Inst #2289 = VCVTANSDf
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2288 = VCNTq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2287 = VCNTd
  { 3, &ARMDescs.OperandInfo[1772] },  // Inst #2286 = VCMPZS
  { 3, &ARMDescs.OperandInfo[1769] },  // Inst #2285 = VCMPZH
  { 3, &ARMDescs.OperandInfo[1766] },  // Inst #2284 = VCMPZD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #2283 = VCMPS
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #2282 = VCMPH
  { 3, &ARMDescs.OperandInfo[1772] },  // Inst #2281 = VCMPEZS
  { 3, &ARMDescs.OperandInfo[1769] },  // Inst #2280 = VCMPEZH
  { 3, &ARMDescs.OperandInfo[1766] },  // Inst #2279 = VCMPEZD
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #2278 = VCMPES
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #2277 = VCMPEH
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2276 = VCMPED
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2275 = VCMPD
  { 6, &ARMDescs.OperandInfo[1760] },  // Inst #2274 = VCMLAv8f16_indexed
  { 5, &ARMDescs.OperandInfo[1749] },  // Inst #2273 = VCMLAv8f16
  { 6, &ARMDescs.OperandInfo[1754] },  // Inst #2272 = VCMLAv4f32_indexed
  { 5, &ARMDescs.OperandInfo[1749] },  // Inst #2271 = VCMLAv4f32
  { 6, &ARMDescs.OperandInfo[1743] },  // Inst #2270 = VCMLAv4f16_indexed
  { 5, &ARMDescs.OperandInfo[1732] },  // Inst #2269 = VCMLAv4f16
  { 6, &ARMDescs.OperandInfo[1737] },  // Inst #2268 = VCMLAv2f32_indexed
  { 5, &ARMDescs.OperandInfo[1732] },  // Inst #2267 = VCMLAv2f32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2266 = VCLZv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2265 = VCLZv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2264 = VCLZv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2263 = VCLZv4i16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2262 = VCLZv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2261 = VCLZv16i8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2260 = VCLTzv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2259 = VCLTzv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2258 = VCLTzv8f16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2257 = VCLTzv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2256 = VCLTzv4i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2255 = VCLTzv4f32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2254 = VCLTzv4f16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2253 = VCLTzv2i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2252 = VCLTzv2f32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2251 = VCLTzv16i8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2250 = VCLSv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2249 = VCLSv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2248 = VCLSv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2247 = VCLSv4i16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2246 = VCLSv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2245 = VCLSv16i8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2244 = VCLEzv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2243 = VCLEzv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2242 = VCLEzv8f16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2241 = VCLEzv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2240 = VCLEzv4i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2239 = VCLEzv4f32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2238 = VCLEzv4f16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2237 = VCLEzv2i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2236 = VCLEzv2f32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2235 = VCLEzv16i8
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2234 = VCGTzv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2233 = VCGTzv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2232 = VCGTzv8f16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2231 = VCGTzv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2230 = VCGTzv4i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2229 = VCGTzv4f32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2228 = VCGTzv4f16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2227 = VCGTzv2i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2226 = VCGTzv2f32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2225 = VCGTzv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2224 = VCGTuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2223 = VCGTuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2222 = VCGTuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2221 = VCGTuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2220 = VCGTuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2219 = VCGTuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2218 = VCGTsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2217 = VCGTsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2216 = VCGTsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2215 = VCGTsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2214 = VCGTsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2213 = VCGTsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2212 = VCGThq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2211 = VCGThd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2210 = VCGTfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2209 = VCGTfd
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2208 = VCGEzv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2207 = VCGEzv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2206 = VCGEzv8f16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2205 = VCGEzv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2204 = VCGEzv4i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2203 = VCGEzv4f32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2202 = VCGEzv4f16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2201 = VCGEzv2i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2200 = VCGEzv2f32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2199 = VCGEzv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2198 = VCGEuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2197 = VCGEuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2196 = VCGEuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2195 = VCGEuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2194 = VCGEuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2193 = VCGEuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2192 = VCGEsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2191 = VCGEsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2190 = VCGEsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2189 = VCGEsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2188 = VCGEsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2187 = VCGEsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2186 = VCGEhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2185 = VCGEhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2184 = VCGEfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2183 = VCGEfd
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2182 = VCEQzv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2181 = VCEQzv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2180 = VCEQzv8f16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2179 = VCEQzv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2178 = VCEQzv4i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2177 = VCEQzv4f32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2176 = VCEQzv4f16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2175 = VCEQzv2i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2174 = VCEQzv2f32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2173 = VCEQzv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2172 = VCEQv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2171 = VCEQv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2170 = VCEQv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2169 = VCEQv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2168 = VCEQv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2167 = VCEQv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2166 = VCEQhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2165 = VCEQhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2164 = VCEQfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2163 = VCEQfd
  { 4, &ARMDescs.OperandInfo[1728] },  // Inst #2162 = VCADDv8f16
  { 4, &ARMDescs.OperandInfo[1728] },  // Inst #2161 = VCADDv4f32
  { 4, &ARMDescs.OperandInfo[1724] },  // Inst #2160 = VCADDv4f16
  { 4, &ARMDescs.OperandInfo[1724] },  // Inst #2159 = VCADDv2f32
  { 6, &ARMDescs.OperandInfo[1718] },  // Inst #2158 = VBSPq
  { 6, &ARMDescs.OperandInfo[1712] },  // Inst #2157 = VBSPd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2156 = VBSLq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2155 = VBSLd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2154 = VBITq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2153 = VBITd
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2152 = VBIFq
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2151 = VBIFd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2150 = VBICq
  { 5, &ARMDescs.OperandInfo[1707] },  // Inst #2149 = VBICiv8i16
  { 5, &ARMDescs.OperandInfo[1707] },  // Inst #2148 = VBICiv4i32
  { 5, &ARMDescs.OperandInfo[1702] },  // Inst #2147 = VBICiv4i16
  { 5, &ARMDescs.OperandInfo[1702] },  // Inst #2146 = VBICiv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2145 = VBICd
  { 5, &ARMDescs.OperandInfo[1697] },  // Inst #2144 = VBF16MALTQI
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #2143 = VBF16MALTQ
  { 5, &ARMDescs.OperandInfo[1697] },  // Inst #2142 = VBF16MALBQI
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #2141 = VBF16MALBQ
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2140 = VANDq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2139 = VANDd
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2138 = VADDv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2137 = VADDv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2136 = VADDv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2135 = VADDv4i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2134 = VADDv2i64
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2133 = VADDv2i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2132 = VADDv1i64
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2131 = VADDv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2130 = VADDhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2129 = VADDhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2128 = VADDfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2127 = VADDfd
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #2126 = VADDWuv8i16
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #2125 = VADDWuv4i32
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #2124 = VADDWuv2i64
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #2123 = VADDWsv8i16
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #2122 = VADDWsv4i32
  { 5, &ARMDescs.OperandInfo[1692] },  // Inst #2121 = VADDWsv2i64
  { 5, &ARMDescs.OperandInfo[1687] },  // Inst #2120 = VADDS
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2119 = VADDLuv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2118 = VADDLuv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2117 = VADDLuv2i64
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2116 = VADDLsv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2115 = VADDLsv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2114 = VADDLsv2i64
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #2113 = VADDHNv8i8
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #2112 = VADDHNv4i16
  { 5, &ARMDescs.OperandInfo[1682] },  // Inst #2111 = VADDHNv2i32
  { 5, &ARMDescs.OperandInfo[1677] },  // Inst #2110 = VADDH
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2109 = VADDD
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2108 = VACGThq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2107 = VACGThd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2106 = VACGTfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2105 = VACGTfd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2104 = VACGEhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2103 = VACGEhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2102 = VACGEfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2101 = VACGEfd
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2100 = VABSv8i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2099 = VABSv8i16
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2098 = VABSv4i32
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2097 = VABSv4i16
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2096 = VABSv2i32
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2095 = VABSv16i8
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2094 = VABShq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2093 = VABShd
  { 4, &ARMDescs.OperandInfo[1673] },  // Inst #2092 = VABSfq
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2091 = VABSfd
  { 4, &ARMDescs.OperandInfo[1669] },  // Inst #2090 = VABSS
  { 4, &ARMDescs.OperandInfo[1665] },  // Inst #2089 = VABSH
  { 4, &ARMDescs.OperandInfo[1661] },  // Inst #2088 = VABSD
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2087 = VABDuv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2086 = VABDuv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2085 = VABDuv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2084 = VABDuv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2083 = VABDuv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2082 = VABDuv16i8
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2081 = VABDsv8i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2080 = VABDsv8i16
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2079 = VABDsv4i32
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2078 = VABDsv4i16
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2077 = VABDsv2i32
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2076 = VABDsv16i8
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2075 = VABDhq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2074 = VABDhd
  { 5, &ARMDescs.OperandInfo[1656] },  // Inst #2073 = VABDfq
  { 5, &ARMDescs.OperandInfo[1651] },  // Inst #2072 = VABDfd
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2071 = VABDLuv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2070 = VABDLuv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2069 = VABDLuv2i64
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2068 = VABDLsv8i16
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2067 = VABDLsv4i32
  { 5, &ARMDescs.OperandInfo[1646] },  // Inst #2066 = VABDLsv2i64
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2065 = VABAuv8i8
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2064 = VABAuv8i16
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2063 = VABAuv4i32
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2062 = VABAuv4i16
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2061 = VABAuv2i32
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2060 = VABAuv16i8
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2059 = VABAsv8i8
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2058 = VABAsv8i16
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2057 = VABAsv4i32
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2056 = VABAsv4i16
  { 6, &ARMDescs.OperandInfo[1640] },  // Inst #2055 = VABAsv2i32
  { 6, &ARMDescs.OperandInfo[1634] },  // Inst #2054 = VABAsv16i8
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2053 = VABALuv8i16
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2052 = VABALuv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2051 = VABALuv2i64
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2050 = VABALsv8i16
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2049 = VABALsv4i32
  { 6, &ARMDescs.OperandInfo[1628] },  // Inst #2048 = VABALsv2i64
  { 5, &ARMDescs.OperandInfo[1615] },  // Inst #2047 = UXTH
  { 5, &ARMDescs.OperandInfo[1615] },  // Inst #2046 = UXTB16
  { 5, &ARMDescs.OperandInfo[1615] },  // Inst #2045 = UXTB
  { 6, &ARMDescs.OperandInfo[1609] },  // Inst #2044 = UXTAH
  { 6, &ARMDescs.OperandInfo[1609] },  // Inst #2043 = UXTAB16
  { 6, &ARMDescs.OperandInfo[1609] },  // Inst #2042 = UXTAB
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2041 = USUB8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2040 = USUB16
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2039 = USAX
  { 5, &ARMDescs.OperandInfo[1548] },  // Inst #2038 = USAT16
  { 6, &ARMDescs.OperandInfo[1542] },  // Inst #2037 = USAT
  { 6, &ARMDescs.OperandInfo[985] },  // Inst #2036 = USADA8
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #2035 = USAD8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2034 = UQSUB8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2033 = UQSUB16
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2032 = UQSAX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2031 = UQASX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2030 = UQADD8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2029 = UQADD16
  { 7, &ARMDescs.OperandInfo[1535] },  // Inst #2028 = UMULL
  { 9, &ARMDescs.OperandInfo[1518] },  // Inst #2027 = UMLAL
  { 8, &ARMDescs.OperandInfo[1620] },  // Inst #2026 = UMAAL
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2025 = UHSUB8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2024 = UHSUB16
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2023 = UHSAX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2022 = UHASX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2021 = UHADD8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2020 = UHADD16
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #2019 = UDIV
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #2018 = UDF
  { 6, &ARMDescs.OperandInfo[1506] },  // Inst #2017 = UBFX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2016 = UASX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2015 = UADD8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #2014 = UADD16
  { 6, &ARMDescs.OperandInfo[832] },  // Inst #2013 = TSTrsr
  { 5, &ARMDescs.OperandInfo[827] },  // Inst #2012 = TSTrsi
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #2011 = TSTrr
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #2010 = TSTri
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #2009 = TSB
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #2008 = TRAPNaCl
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #2007 = TRAP
  { 6, &ARMDescs.OperandInfo[832] },  // Inst #2006 = TEQrsr
  { 5, &ARMDescs.OperandInfo[827] },  // Inst #2005 = TEQrsi
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #2004 = TEQrr
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #2003 = TEQri
  { 5, &ARMDescs.OperandInfo[1615] },  // Inst #2002 = SXTH
  { 5, &ARMDescs.OperandInfo[1615] },  // Inst #2001 = SXTB16
  { 5, &ARMDescs.OperandInfo[1615] },  // Inst #2000 = SXTB
  { 6, &ARMDescs.OperandInfo[1609] },  // Inst #1999 = SXTAH
  { 6, &ARMDescs.OperandInfo[1609] },  // Inst #1998 = SXTAB16
  { 6, &ARMDescs.OperandInfo[1609] },  // Inst #1997 = SXTAB
  { 5, &ARMDescs.OperandInfo[1604] },  // Inst #1996 = SWPB
  { 5, &ARMDescs.OperandInfo[1604] },  // Inst #1995 = SWP
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #1994 = SVC
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #1993 = SUBrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #1992 = SUBrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #1991 = SUBrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #1990 = SUBri
  { 6, &ARMDescs.OperandInfo[946] },  // Inst #1989 = STRrs
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #1988 = STRi12
  { 7, &ARMDescs.OperandInfo[1570] },  // Inst #1987 = STR_PRE_REG
  { 6, &ARMDescs.OperandInfo[1577] },  // Inst #1986 = STR_PRE_IMM
  { 7, &ARMDescs.OperandInfo[1570] },  // Inst #1985 = STR_POST_REG
  { 7, &ARMDescs.OperandInfo[1570] },  // Inst #1984 = STR_POST_IMM
  { 7, &ARMDescs.OperandInfo[1563] },  // Inst #1983 = STRT_POST_REG
  { 7, &ARMDescs.OperandInfo[1563] },  // Inst #1982 = STRT_POST_IMM
  { 7, &ARMDescs.OperandInfo[1597] },  // Inst #1981 = STRH_PRE
  { 7, &ARMDescs.OperandInfo[1597] },  // Inst #1980 = STRH_POST
  { 7, &ARMDescs.OperandInfo[1563] },  // Inst #1979 = STRHTr
  { 6, &ARMDescs.OperandInfo[1591] },  // Inst #1978 = STRHTi
  { 6, &ARMDescs.OperandInfo[926] },  // Inst #1977 = STRH
  { 5, &ARMDescs.OperandInfo[1553] },  // Inst #1976 = STREXH
  { 5, &ARMDescs.OperandInfo[1558] },  // Inst #1975 = STREXD
  { 5, &ARMDescs.OperandInfo[1553] },  // Inst #1974 = STREXB
  { 5, &ARMDescs.OperandInfo[1553] },  // Inst #1973 = STREX
  { 8, &ARMDescs.OperandInfo[1583] },  // Inst #1972 = STRD_PRE
  { 8, &ARMDescs.OperandInfo[1583] },  // Inst #1971 = STRD_POST
  { 7, &ARMDescs.OperandInfo[911] },  // Inst #1970 = STRD
  { 6, &ARMDescs.OperandInfo[905] },  // Inst #1969 = STRBrs
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #1968 = STRBi12
  { 7, &ARMDescs.OperandInfo[1570] },  // Inst #1967 = STRB_PRE_REG
  { 6, &ARMDescs.OperandInfo[1577] },  // Inst #1966 = STRB_PRE_IMM
  { 7, &ARMDescs.OperandInfo[1570] },  // Inst #1965 = STRB_POST_REG
  { 7, &ARMDescs.OperandInfo[1570] },  // Inst #1964 = STRB_POST_IMM
  { 7, &ARMDescs.OperandInfo[1563] },  // Inst #1963 = STRBT_POST_REG
  { 7, &ARMDescs.OperandInfo[1563] },  // Inst #1962 = STRBT_POST_IMM
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #1961 = STMIB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #1960 = STMIB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #1959 = STMIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #1958 = STMIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #1957 = STMDB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #1956 = STMDB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #1955 = STMDA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #1954 = STMDA
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #1953 = STLH
  { 5, &ARMDescs.OperandInfo[1553] },  // Inst #1952 = STLEXH
  { 5, &ARMDescs.OperandInfo[1558] },  // Inst #1951 = STLEXD
  { 5, &ARMDescs.OperandInfo[1553] },  // Inst #1950 = STLEXB
  { 5, &ARMDescs.OperandInfo[1553] },  // Inst #1949 = STLEX
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #1948 = STLB
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #1947 = STL
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #1946 = STC_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #1945 = STC_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #1944 = STC_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #1943 = STC_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #1942 = STCL_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #1941 = STCL_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #1940 = STCL_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #1939 = STCL_OFFSET
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #1938 = STC2_PRE
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #1937 = STC2_POST
  { 4, &ARMDescs.OperandInfo[871] },  // Inst #1936 = STC2_OPTION
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #1935 = STC2_OFFSET
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #1934 = STC2L_PRE
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #1933 = STC2L_POST
  { 4, &ARMDescs.OperandInfo[871] },  // Inst #1932 = STC2L_OPTION
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #1931 = STC2L_OFFSET
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1930 = SSUB8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1929 = SSUB16
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1928 = SSAX
  { 5, &ARMDescs.OperandInfo[1548] },  // Inst #1927 = SSAT16
  { 6, &ARMDescs.OperandInfo[1542] },  // Inst #1926 = SSAT
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1925 = SRSIB_UPD
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1924 = SRSIB
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1923 = SRSIA_UPD
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1922 = SRSIA
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1921 = SRSDB_UPD
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1920 = SRSDB
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1919 = SRSDA_UPD
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1918 = SRSDA
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1917 = SMUSDX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1916 = SMUSD
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1915 = SMULWT
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1914 = SMULWB
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1913 = SMULTT
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1912 = SMULTB
  { 7, &ARMDescs.OperandInfo[1535] },  // Inst #1911 = SMULL
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1910 = SMULBT
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1909 = SMULBB
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1908 = SMUADX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1907 = SMUAD
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1906 = SMMULR
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1905 = SMMUL
  { 6, &ARMDescs.OperandInfo[985] },  // Inst #1904 = SMMLSR
  { 6, &ARMDescs.OperandInfo[985] },  // Inst #1903 = SMMLS
  { 6, &ARMDescs.OperandInfo[985] },  // Inst #1902 = SMMLAR
  { 6, &ARMDescs.OperandInfo[985] },  // Inst #1901 = SMMLA
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1900 = SMLSLDX
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1899 = SMLSLD
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1898 = SMLSDX
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1897 = SMLSD
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1896 = SMLAWT
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1895 = SMLAWB
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1894 = SMLATT
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1893 = SMLATB
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1892 = SMLALTT
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1891 = SMLALTB
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1890 = SMLALDX
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1889 = SMLALD
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1888 = SMLALBT
  { 8, &ARMDescs.OperandInfo[1527] },  // Inst #1887 = SMLALBB
  { 9, &ARMDescs.OperandInfo[1518] },  // Inst #1886 = SMLAL
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1885 = SMLADX
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1884 = SMLAD
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1883 = SMLABT
  { 6, &ARMDescs.OperandInfo[1512] },  // Inst #1882 = SMLABB
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #1881 = SMC
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1880 = SHSUB8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1879 = SHSUB16
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1878 = SHSAX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1877 = SHASX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1876 = SHADD8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1875 = SHADD16
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #1874 = SHA256SU1
  { 3, &ARMDescs.OperandInfo[608] },  // Inst #1873 = SHA256SU0
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #1872 = SHA256H2
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #1871 = SHA256H
  { 3, &ARMDescs.OperandInfo[608] },  // Inst #1870 = SHA1SU1
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #1869 = SHA1SU0
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #1868 = SHA1P
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #1867 = SHA1M
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #1866 = SHA1H
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #1865 = SHA1C
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1864 = SETPAN
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1863 = SETEND
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1862 = SEL
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #1861 = SDIV
  { 6, &ARMDescs.OperandInfo[1506] },  // Inst #1860 = SBFX
  { 8, &ARMDescs.OperandInfo[592] },  // Inst #1859 = SBCrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #1858 = SBCrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #1857 = SBCrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #1856 = SBCri
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #1855 = SB
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1854 = SASX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1853 = SADD8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1852 = SADD16
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #1851 = RSCrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #1850 = RSCrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #1849 = RSCrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #1848 = RSCri
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #1847 = RSBrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #1846 = RSBrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #1845 = RSBrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #1844 = RSBri
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1843 = RFEIB_UPD
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1842 = RFEIB
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1841 = RFEIA_UPD
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1840 = RFEIA
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1839 = RFEDB_UPD
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1838 = RFEDB
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1837 = RFEDA_UPD
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #1836 = RFEDA
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #1835 = REVSH
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #1834 = REV16
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #1833 = REV
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #1832 = RBIT
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1831 = QSUB8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1830 = QSUB16
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1829 = QSUB
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1828 = QSAX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1827 = QDSUB
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1826 = QDADD
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1825 = QASX
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1824 = QADD8
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1823 = QADD16
  { 5, &ARMDescs.OperandInfo[1501] },  // Inst #1822 = QADD
  { 3, &ARMDescs.OperandInfo[1498] },  // Inst #1821 = PLIrs
  { 2, &ARMDescs.OperandInfo[1496] },  // Inst #1820 = PLIi12
  { 3, &ARMDescs.OperandInfo[1498] },  // Inst #1819 = PLDrs
  { 2, &ARMDescs.OperandInfo[1496] },  // Inst #1818 = PLDi12
  { 3, &ARMDescs.OperandInfo[1498] },  // Inst #1817 = PLDWrs
  { 2, &ARMDescs.OperandInfo[1496] },  // Inst #1816 = PLDWi12
  { 6, &ARMDescs.OperandInfo[1490] },  // Inst #1815 = PKHTB
  { 6, &ARMDescs.OperandInfo[1490] },  // Inst #1814 = PKHBT
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #1813 = ORRrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #1812 = ORRrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #1811 = ORRrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #1810 = ORRri
  { 3, &ARMDescs.OperandInfo[1487] },  // Inst #1809 = NEON_VMINNMNQh
  { 3, &ARMDescs.OperandInfo[1487] },  // Inst #1808 = NEON_VMINNMNQf
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #1807 = NEON_VMINNMNDh
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #1806 = NEON_VMINNMNDf
  { 3, &ARMDescs.OperandInfo[1487] },  // Inst #1805 = NEON_VMAXNMNQh
  { 3, &ARMDescs.OperandInfo[1487] },  // Inst #1804 = NEON_VMAXNMNQf
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #1803 = NEON_VMAXNMNDh
  { 3, &ARMDescs.OperandInfo[1484] },  // Inst #1802 = NEON_VMAXNMNDf
  { 7, &ARMDescs.OperandInfo[1477] },  // Inst #1801 = MVNsr
  { 6, &ARMDescs.OperandInfo[1006] },  // Inst #1800 = MVNsi
  { 5, &ARMDescs.OperandInfo[314] },  // Inst #1799 = MVNr
  { 5, &ARMDescs.OperandInfo[996] },  // Inst #1798 = MVNi
  { 3, &ARMDescs.OperandInfo[497] },  // Inst #1797 = MVE_WLSTP_8
  { 3, &ARMDescs.OperandInfo[497] },  // Inst #1796 = MVE_WLSTP_64
  { 3, &ARMDescs.OperandInfo[497] },  // Inst #1795 = MVE_WLSTP_32
  { 3, &ARMDescs.OperandInfo[497] },  // Inst #1794 = MVE_WLSTP_16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1793 = MVE_VSUBi8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1792 = MVE_VSUBi32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1791 = MVE_VSUBi16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1790 = MVE_VSUBf32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1789 = MVE_VSUBf16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1788 = MVE_VSUB_qr_i8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1787 = MVE_VSUB_qr_i32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1786 = MVE_VSUB_qr_i16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1785 = MVE_VSUB_qr_f32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1784 = MVE_VSUB_qr_f16
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1783 = MVE_VSTRWU32_pre
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1782 = MVE_VSTRWU32_post
  { 6, &ARMDescs.OperandInfo[1288] },  // Inst #1781 = MVE_VSTRWU32
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1780 = MVE_VSTRW32_rq_u
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1779 = MVE_VSTRW32_rq
  { 7, &ARMDescs.OperandInfo[1470] },  // Inst #1778 = MVE_VSTRW32_qi_pre
  { 6, &ARMDescs.OperandInfo[1464] },  // Inst #1777 = MVE_VSTRW32_qi
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1776 = MVE_VSTRHU16_pre
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1775 = MVE_VSTRHU16_post
  { 6, &ARMDescs.OperandInfo[1288] },  // Inst #1774 = MVE_VSTRHU16
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1773 = MVE_VSTRH32_rq_u
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1772 = MVE_VSTRH32_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1771 = MVE_VSTRH32_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1770 = MVE_VSTRH32_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1769 = MVE_VSTRH32
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1768 = MVE_VSTRH16_rq_u
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1767 = MVE_VSTRH16_rq
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1766 = MVE_VSTRD64_rq_u
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1765 = MVE_VSTRD64_rq
  { 7, &ARMDescs.OperandInfo[1470] },  // Inst #1764 = MVE_VSTRD64_qi_pre
  { 6, &ARMDescs.OperandInfo[1464] },  // Inst #1763 = MVE_VSTRD64_qi
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1762 = MVE_VSTRBU8_pre
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1761 = MVE_VSTRBU8_post
  { 6, &ARMDescs.OperandInfo[1288] },  // Inst #1760 = MVE_VSTRBU8
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1759 = MVE_VSTRB8_rq
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1758 = MVE_VSTRB32_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1757 = MVE_VSTRB32_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1756 = MVE_VSTRB32_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1755 = MVE_VSTRB32
  { 6, &ARMDescs.OperandInfo[1458] },  // Inst #1754 = MVE_VSTRB16_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1753 = MVE_VSTRB16_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1752 = MVE_VSTRB16_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1751 = MVE_VSTRB16
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1750 = MVE_VST43_8_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1749 = MVE_VST43_8
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1748 = MVE_VST43_32_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1747 = MVE_VST43_32
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1746 = MVE_VST43_16_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1745 = MVE_VST43_16
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1744 = MVE_VST42_8_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1743 = MVE_VST42_8
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1742 = MVE_VST42_32_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1741 = MVE_VST42_32
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1740 = MVE_VST42_16_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1739 = MVE_VST42_16
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1738 = MVE_VST41_8_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1737 = MVE_VST41_8
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1736 = MVE_VST41_32_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1735 = MVE_VST41_32
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1734 = MVE_VST41_16_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1733 = MVE_VST41_16
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1732 = MVE_VST40_8_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1731 = MVE_VST40_8
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1730 = MVE_VST40_32_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1729 = MVE_VST40_32
  { 3, &ARMDescs.OperandInfo[1455] },  // Inst #1728 = MVE_VST40_16_wb
  { 2, &ARMDescs.OperandInfo[1453] },  // Inst #1727 = MVE_VST40_16
  { 3, &ARMDescs.OperandInfo[1450] },  // Inst #1726 = MVE_VST21_8_wb
  { 2, &ARMDescs.OperandInfo[1448] },  // Inst #1725 = MVE_VST21_8
  { 3, &ARMDescs.OperandInfo[1450] },  // Inst #1724 = MVE_VST21_32_wb
  { 2, &ARMDescs.OperandInfo[1448] },  // Inst #1723 = MVE_VST21_32
  { 3, &ARMDescs.OperandInfo[1450] },  // Inst #1722 = MVE_VST21_16_wb
  { 2, &ARMDescs.OperandInfo[1448] },  // Inst #1721 = MVE_VST21_16
  { 3, &ARMDescs.OperandInfo[1450] },  // Inst #1720 = MVE_VST20_8_wb
  { 2, &ARMDescs.OperandInfo[1448] },  // Inst #1719 = MVE_VST20_8
  { 3, &ARMDescs.OperandInfo[1450] },  // Inst #1718 = MVE_VST20_32_wb
  { 2, &ARMDescs.OperandInfo[1448] },  // Inst #1717 = MVE_VST20_32
  { 3, &ARMDescs.OperandInfo[1450] },  // Inst #1716 = MVE_VST20_16_wb
  { 2, &ARMDescs.OperandInfo[1448] },  // Inst #1715 = MVE_VST20_16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1714 = MVE_VSRIimm8
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1713 = MVE_VSRIimm32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1712 = MVE_VSRIimm16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1711 = MVE_VSLIimm8
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1710 = MVE_VSLIimm32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1709 = MVE_VSLIimm16
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1708 = MVE_VSHR_immu8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1707 = MVE_VSHR_immu32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1706 = MVE_VSHR_immu16
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1705 = MVE_VSHR_imms8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1704 = MVE_VSHR_imms32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1703 = MVE_VSHR_imms16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1702 = MVE_VSHRNi32th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1701 = MVE_VSHRNi32bh
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1700 = MVE_VSHRNi16th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1699 = MVE_VSHRNi16bh
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1698 = MVE_VSHL_qru8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1697 = MVE_VSHL_qru32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1696 = MVE_VSHL_qru16
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1695 = MVE_VSHL_qrs8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1694 = MVE_VSHL_qrs32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1693 = MVE_VSHL_qrs16
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1692 = MVE_VSHL_immi8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1691 = MVE_VSHL_immi32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1690 = MVE_VSHL_immi16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1689 = MVE_VSHL_by_vecu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1688 = MVE_VSHL_by_vecu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1687 = MVE_VSHL_by_vecu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1686 = MVE_VSHL_by_vecs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1685 = MVE_VSHL_by_vecs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1684 = MVE_VSHL_by_vecs16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1683 = MVE_VSHLL_lwu8th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1682 = MVE_VSHLL_lwu8bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1681 = MVE_VSHLL_lwu16th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1680 = MVE_VSHLL_lwu16bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1679 = MVE_VSHLL_lws8th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1678 = MVE_VSHLL_lws8bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1677 = MVE_VSHLL_lws16th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1676 = MVE_VSHLL_lws16bh
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1675 = MVE_VSHLL_immu8th
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1674 = MVE_VSHLL_immu8bh
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1673 = MVE_VSHLL_immu16th
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1672 = MVE_VSHLL_immu16bh
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1671 = MVE_VSHLL_imms8th
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1670 = MVE_VSHLL_imms8bh
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1669 = MVE_VSHLL_imms16th
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1668 = MVE_VSHLL_imms16bh
  { 8, &ARMDescs.OperandInfo[1440] },  // Inst #1667 = MVE_VSHLC
  { 8, &ARMDescs.OperandInfo[1116] },  // Inst #1666 = MVE_VSBCI
  { 9, &ARMDescs.OperandInfo[1107] },  // Inst #1665 = MVE_VSBC
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1664 = MVE_VRSHR_immu8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1663 = MVE_VRSHR_immu32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1662 = MVE_VRSHR_immu16
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1661 = MVE_VRSHR_imms8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1660 = MVE_VRSHR_imms32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1659 = MVE_VRSHR_imms16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1658 = MVE_VRSHRNi32th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1657 = MVE_VRSHRNi32bh
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1656 = MVE_VRSHRNi16th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1655 = MVE_VRSHRNi16bh
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1654 = MVE_VRSHL_qru8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1653 = MVE_VRSHL_qru32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1652 = MVE_VRSHL_qru16
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1651 = MVE_VRSHL_qrs8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1650 = MVE_VRSHL_qrs32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1649 = MVE_VRSHL_qrs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1648 = MVE_VRSHL_by_vecu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1647 = MVE_VRSHL_by_vecu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1646 = MVE_VRSHL_by_vecu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1645 = MVE_VRSHL_by_vecs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1644 = MVE_VRSHL_by_vecs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1643 = MVE_VRSHL_by_vecs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1642 = MVE_VRMULHu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1641 = MVE_VRMULHu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1640 = MVE_VRMULHu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1639 = MVE_VRMULHs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1638 = MVE_VRMULHs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1637 = MVE_VRMULHs16
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1636 = MVE_VRMLSLDAVHxs32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1635 = MVE_VRMLSLDAVHs32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1634 = MVE_VRMLSLDAVHaxs32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1633 = MVE_VRMLSLDAVHas32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1632 = MVE_VRMLALDAVHxs32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1631 = MVE_VRMLALDAVHu32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1630 = MVE_VRMLALDAVHs32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1629 = MVE_VRMLALDAVHaxs32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1628 = MVE_VRMLALDAVHau32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1627 = MVE_VRMLALDAVHas32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1626 = MVE_VRINTf32Z
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1625 = MVE_VRINTf32X
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1624 = MVE_VRINTf32P
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1623 = MVE_VRINTf32N
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1622 = MVE_VRINTf32M
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1621 = MVE_VRINTf32A
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1620 = MVE_VRINTf16Z
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1619 = MVE_VRINTf16X
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1618 = MVE_VRINTf16P
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1617 = MVE_VRINTf16N
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1616 = MVE_VRINTf16M
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1615 = MVE_VRINTf16A
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1614 = MVE_VRHADDu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1613 = MVE_VRHADDu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1612 = MVE_VRHADDu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1611 = MVE_VRHADDs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1610 = MVE_VRHADDs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1609 = MVE_VRHADDs16
  { 6, &ARMDescs.OperandInfo[1434] },  // Inst #1608 = MVE_VREV64_8
  { 6, &ARMDescs.OperandInfo[1434] },  // Inst #1607 = MVE_VREV64_32
  { 6, &ARMDescs.OperandInfo[1434] },  // Inst #1606 = MVE_VREV64_16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1605 = MVE_VREV32_8
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1604 = MVE_VREV32_16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1603 = MVE_VREV16_8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1602 = MVE_VQSUBu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1601 = MVE_VQSUBu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1600 = MVE_VQSUBu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1599 = MVE_VQSUBs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1598 = MVE_VQSUBs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1597 = MVE_VQSUBs16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1596 = MVE_VQSUB_qr_u8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1595 = MVE_VQSUB_qr_u32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1594 = MVE_VQSUB_qr_u16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1593 = MVE_VQSUB_qr_s8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1592 = MVE_VQSUB_qr_s32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1591 = MVE_VQSUB_qr_s16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1590 = MVE_VQSHRUNs32th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1589 = MVE_VQSHRUNs32bh
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1588 = MVE_VQSHRUNs16th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1587 = MVE_VQSHRUNs16bh
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1586 = MVE_VQSHRNthu32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1585 = MVE_VQSHRNthu16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1584 = MVE_VQSHRNths32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1583 = MVE_VQSHRNths16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1582 = MVE_VQSHRNbhu32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1581 = MVE_VQSHRNbhu16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1580 = MVE_VQSHRNbhs32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1579 = MVE_VQSHRNbhs16
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1578 = MVE_VQSHLimmu8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1577 = MVE_VQSHLimmu32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1576 = MVE_VQSHLimmu16
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1575 = MVE_VQSHLimms8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1574 = MVE_VQSHLimms32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1573 = MVE_VQSHLimms16
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1572 = MVE_VQSHL_qru8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1571 = MVE_VQSHL_qru32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1570 = MVE_VQSHL_qru16
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1569 = MVE_VQSHL_qrs8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1568 = MVE_VQSHL_qrs32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1567 = MVE_VQSHL_qrs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1566 = MVE_VQSHL_by_vecu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1565 = MVE_VQSHL_by_vecu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1564 = MVE_VQSHL_by_vecu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1563 = MVE_VQSHL_by_vecs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1562 = MVE_VQSHL_by_vecs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1561 = MVE_VQSHL_by_vecs16
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1560 = MVE_VQSHLU_imms8
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1559 = MVE_VQSHLU_imms32
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1558 = MVE_VQSHLU_imms16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1557 = MVE_VQRSHRUNs32th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1556 = MVE_VQRSHRUNs32bh
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1555 = MVE_VQRSHRUNs16th
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1554 = MVE_VQRSHRUNs16bh
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1553 = MVE_VQRSHRNthu32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1552 = MVE_VQRSHRNthu16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1551 = MVE_VQRSHRNths32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1550 = MVE_VQRSHRNths16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1549 = MVE_VQRSHRNbhu32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1548 = MVE_VQRSHRNbhu16
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1547 = MVE_VQRSHRNbhs32
  { 7, &ARMDescs.OperandInfo[1427] },  // Inst #1546 = MVE_VQRSHRNbhs16
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1545 = MVE_VQRSHL_qru8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1544 = MVE_VQRSHL_qru32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1543 = MVE_VQRSHL_qru16
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1542 = MVE_VQRSHL_qrs8
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1541 = MVE_VQRSHL_qrs32
  { 6, &ARMDescs.OperandInfo[1421] },  // Inst #1540 = MVE_VQRSHL_qrs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1539 = MVE_VQRSHL_by_vecu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1538 = MVE_VQRSHL_by_vecu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1537 = MVE_VQRSHL_by_vecu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1536 = MVE_VQRSHL_by_vecs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1535 = MVE_VQRSHL_by_vecs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1534 = MVE_VQRSHL_by_vecs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1533 = MVE_VQRDMULHi8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1532 = MVE_VQRDMULHi32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1531 = MVE_VQRDMULHi16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1530 = MVE_VQRDMULH_qr_s8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1529 = MVE_VQRDMULH_qr_s32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1528 = MVE_VQRDMULH_qr_s16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1527 = MVE_VQRDMLSDHs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1526 = MVE_VQRDMLSDHs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1525 = MVE_VQRDMLSDHs16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1524 = MVE_VQRDMLSDHXs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1523 = MVE_VQRDMLSDHXs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1522 = MVE_VQRDMLSDHXs16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1521 = MVE_VQRDMLASH_qrs8
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1520 = MVE_VQRDMLASH_qrs32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1519 = MVE_VQRDMLASH_qrs16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1518 = MVE_VQRDMLAH_qrs8
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1517 = MVE_VQRDMLAH_qrs32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1516 = MVE_VQRDMLAH_qrs16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1515 = MVE_VQRDMLADHs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1514 = MVE_VQRDMLADHs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1513 = MVE_VQRDMLADHs16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1512 = MVE_VQRDMLADHXs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1511 = MVE_VQRDMLADHXs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1510 = MVE_VQRDMLADHXs16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1509 = MVE_VQNEGs8
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1508 = MVE_VQNEGs32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1507 = MVE_VQNEGs16
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1506 = MVE_VQMOVUNs32th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1505 = MVE_VQMOVUNs32bh
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1504 = MVE_VQMOVUNs16th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1503 = MVE_VQMOVUNs16bh
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1502 = MVE_VQMOVNu32th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1501 = MVE_VQMOVNu32bh
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1500 = MVE_VQMOVNu16th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1499 = MVE_VQMOVNu16bh
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1498 = MVE_VQMOVNs32th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1497 = MVE_VQMOVNs32bh
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1496 = MVE_VQMOVNs16th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1495 = MVE_VQMOVNs16bh
  { 7, &ARMDescs.OperandInfo[1381] },  // Inst #1494 = MVE_VQDMULLs32th
  { 7, &ARMDescs.OperandInfo[1381] },  // Inst #1493 = MVE_VQDMULLs32bh
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1492 = MVE_VQDMULLs16th
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1491 = MVE_VQDMULLs16bh
  { 7, &ARMDescs.OperandInfo[1414] },  // Inst #1490 = MVE_VQDMULL_qr_s32th
  { 7, &ARMDescs.OperandInfo[1414] },  // Inst #1489 = MVE_VQDMULL_qr_s32bh
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1488 = MVE_VQDMULL_qr_s16th
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1487 = MVE_VQDMULL_qr_s16bh
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1486 = MVE_VQDMULHi8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1485 = MVE_VQDMULHi32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1484 = MVE_VQDMULHi16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1483 = MVE_VQDMULH_qr_s8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1482 = MVE_VQDMULH_qr_s32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1481 = MVE_VQDMULH_qr_s16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1480 = MVE_VQDMLSDHs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1479 = MVE_VQDMLSDHs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1478 = MVE_VQDMLSDHs16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1477 = MVE_VQDMLSDHXs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1476 = MVE_VQDMLSDHXs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1475 = MVE_VQDMLSDHXs16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1474 = MVE_VQDMLASH_qrs8
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1473 = MVE_VQDMLASH_qrs32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1472 = MVE_VQDMLASH_qrs16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1471 = MVE_VQDMLAH_qrs8
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1470 = MVE_VQDMLAH_qrs32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1469 = MVE_VQDMLAH_qrs16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1468 = MVE_VQDMLADHs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1467 = MVE_VQDMLADHs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1466 = MVE_VQDMLADHs16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1465 = MVE_VQDMLADHXs8
  { 7, &ARMDescs.OperandInfo[1407] },  // Inst #1464 = MVE_VQDMLADHXs32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1463 = MVE_VQDMLADHXs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1462 = MVE_VQADDu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1461 = MVE_VQADDu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1460 = MVE_VQADDu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1459 = MVE_VQADDs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1458 = MVE_VQADDs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1457 = MVE_VQADDs16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1456 = MVE_VQADD_qr_u8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1455 = MVE_VQADD_qr_u32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1454 = MVE_VQADD_qr_u16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1453 = MVE_VQADD_qr_s8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1452 = MVE_VQADD_qr_s32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1451 = MVE_VQADD_qr_s16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1450 = MVE_VQABSs8
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1449 = MVE_VQABSs32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1448 = MVE_VQABSs16
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1447 = MVE_VPTv8u16r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1446 = MVE_VPTv8u16
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1445 = MVE_VPTv8s16r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1444 = MVE_VPTv8s16
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1443 = MVE_VPTv8i16r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1442 = MVE_VPTv8i16
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1441 = MVE_VPTv8f16r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1440 = MVE_VPTv8f16
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1439 = MVE_VPTv4u32r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1438 = MVE_VPTv4u32
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1437 = MVE_VPTv4s32r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1436 = MVE_VPTv4s32
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1435 = MVE_VPTv4i32r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1434 = MVE_VPTv4i32
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1433 = MVE_VPTv4f32r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1432 = MVE_VPTv4f32
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1431 = MVE_VPTv16u8r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1430 = MVE_VPTv16u8
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1429 = MVE_VPTv16s8r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1428 = MVE_VPTv16s8
  { 4, &ARMDescs.OperandInfo[1403] },  // Inst #1427 = MVE_VPTv16i8r
  { 4, &ARMDescs.OperandInfo[1399] },  // Inst #1426 = MVE_VPTv16i8
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #1425 = MVE_VPST
  { 6, &ARMDescs.OperandInfo[1393] },  // Inst #1424 = MVE_VPSEL
  { 5, &ARMDescs.OperandInfo[1388] },  // Inst #1423 = MVE_VPNOT
  { 6, &ARMDescs.OperandInfo[1156] },  // Inst #1422 = MVE_VORRimmi32
  { 6, &ARMDescs.OperandInfo[1156] },  // Inst #1421 = MVE_VORRimmi16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1420 = MVE_VORR
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1419 = MVE_VORN
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1418 = MVE_VNEGs8
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1417 = MVE_VNEGs32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1416 = MVE_VNEGs16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1415 = MVE_VNEGf32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1414 = MVE_VNEGf16
  { 6, &ARMDescs.OperandInfo[1375] },  // Inst #1413 = MVE_VMVNimmi32
  { 6, &ARMDescs.OperandInfo[1375] },  // Inst #1412 = MVE_VMVNimmi16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1411 = MVE_VMVN
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1410 = MVE_VMULi8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1409 = MVE_VMULi32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1408 = MVE_VMULi16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1407 = MVE_VMULf32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1406 = MVE_VMULf16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1405 = MVE_VMUL_qr_i8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1404 = MVE_VMUL_qr_i32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1403 = MVE_VMUL_qr_i16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1402 = MVE_VMUL_qr_f32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1401 = MVE_VMUL_qr_f16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1400 = MVE_VMULLTu8
  { 7, &ARMDescs.OperandInfo[1381] },  // Inst #1399 = MVE_VMULLTu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1398 = MVE_VMULLTu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1397 = MVE_VMULLTs8
  { 7, &ARMDescs.OperandInfo[1381] },  // Inst #1396 = MVE_VMULLTs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1395 = MVE_VMULLTs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1394 = MVE_VMULLTp8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1393 = MVE_VMULLTp16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1392 = MVE_VMULLBu8
  { 7, &ARMDescs.OperandInfo[1381] },  // Inst #1391 = MVE_VMULLBu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1390 = MVE_VMULLBu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1389 = MVE_VMULLBs8
  { 7, &ARMDescs.OperandInfo[1381] },  // Inst #1388 = MVE_VMULLBs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1387 = MVE_VMULLBs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1386 = MVE_VMULLBp8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1385 = MVE_VMULLBp16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1384 = MVE_VMULHu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1383 = MVE_VMULHu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1382 = MVE_VMULHu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1381 = MVE_VMULHs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1380 = MVE_VMULHs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1379 = MVE_VMULHs16
  { 6, &ARMDescs.OperandInfo[1375] },  // Inst #1378 = MVE_VMOVimmi8
  { 6, &ARMDescs.OperandInfo[1375] },  // Inst #1377 = MVE_VMOVimmi64
  { 6, &ARMDescs.OperandInfo[1375] },  // Inst #1376 = MVE_VMOVimmi32
  { 6, &ARMDescs.OperandInfo[1375] },  // Inst #1375 = MVE_VMOVimmi16
  { 6, &ARMDescs.OperandInfo[1375] },  // Inst #1374 = MVE_VMOVimmf32
  { 6, &ARMDescs.OperandInfo[1369] },  // Inst #1373 = MVE_VMOV_to_lane_8
  { 6, &ARMDescs.OperandInfo[1369] },  // Inst #1372 = MVE_VMOV_to_lane_32
  { 6, &ARMDescs.OperandInfo[1369] },  // Inst #1371 = MVE_VMOV_to_lane_16
  { 7, &ARMDescs.OperandInfo[1362] },  // Inst #1370 = MVE_VMOV_rr_q
  { 8, &ARMDescs.OperandInfo[1354] },  // Inst #1369 = MVE_VMOV_q_rr
  { 5, &ARMDescs.OperandInfo[1349] },  // Inst #1368 = MVE_VMOV_from_lane_u8
  { 5, &ARMDescs.OperandInfo[1349] },  // Inst #1367 = MVE_VMOV_from_lane_u16
  { 5, &ARMDescs.OperandInfo[1349] },  // Inst #1366 = MVE_VMOV_from_lane_s8
  { 5, &ARMDescs.OperandInfo[1349] },  // Inst #1365 = MVE_VMOV_from_lane_s16
  { 5, &ARMDescs.OperandInfo[1349] },  // Inst #1364 = MVE_VMOV_from_lane_32
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1363 = MVE_VMOVNi32th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1362 = MVE_VMOVNi32bh
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1361 = MVE_VMOVNi16th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1360 = MVE_VMOVNi16bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1359 = MVE_VMOVLu8th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1358 = MVE_VMOVLu8bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1357 = MVE_VMOVLu16th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1356 = MVE_VMOVLu16bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1355 = MVE_VMOVLs8th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1354 = MVE_VMOVLs8bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1353 = MVE_VMOVLs16th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1352 = MVE_VMOVLs16bh
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1351 = MVE_VMLSLDAVxs32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1350 = MVE_VMLSLDAVxs16
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1349 = MVE_VMLSLDAVs32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1348 = MVE_VMLSLDAVs16
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1347 = MVE_VMLSLDAVaxs32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1346 = MVE_VMLSLDAVaxs16
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1345 = MVE_VMLSLDAVas32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1344 = MVE_VMLSLDAVas16
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1343 = MVE_VMLSDAVxs8
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1342 = MVE_VMLSDAVxs32
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1341 = MVE_VMLSDAVxs16
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1340 = MVE_VMLSDAVs8
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1339 = MVE_VMLSDAVs32
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1338 = MVE_VMLSDAVs16
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1337 = MVE_VMLSDAVaxs8
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1336 = MVE_VMLSDAVaxs32
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1335 = MVE_VMLSDAVaxs16
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1334 = MVE_VMLSDAVas8
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1333 = MVE_VMLSDAVas32
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1332 = MVE_VMLSDAVas16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1331 = MVE_VMLA_qr_i8
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1330 = MVE_VMLA_qr_i32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1329 = MVE_VMLA_qr_i16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1328 = MVE_VMLAS_qr_i8
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1327 = MVE_VMLAS_qr_i32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1326 = MVE_VMLAS_qr_i16
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1325 = MVE_VMLALDAVxs32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1324 = MVE_VMLALDAVxs16
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1323 = MVE_VMLALDAVu32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1322 = MVE_VMLALDAVu16
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1321 = MVE_VMLALDAVs32
  { 7, &ARMDescs.OperandInfo[1342] },  // Inst #1320 = MVE_VMLALDAVs16
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1319 = MVE_VMLALDAVaxs32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1318 = MVE_VMLALDAVaxs16
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1317 = MVE_VMLALDAVau32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1316 = MVE_VMLALDAVau16
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1315 = MVE_VMLALDAVas32
  { 9, &ARMDescs.OperandInfo[1333] },  // Inst #1314 = MVE_VMLALDAVas16
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1313 = MVE_VMLADAVxs8
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1312 = MVE_VMLADAVxs32
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1311 = MVE_VMLADAVxs16
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1310 = MVE_VMLADAVu8
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1309 = MVE_VMLADAVu32
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1308 = MVE_VMLADAVu16
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1307 = MVE_VMLADAVs8
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1306 = MVE_VMLADAVs32
  { 6, &ARMDescs.OperandInfo[1327] },  // Inst #1305 = MVE_VMLADAVs16
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1304 = MVE_VMLADAVaxs8
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1303 = MVE_VMLADAVaxs32
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1302 = MVE_VMLADAVaxs16
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1301 = MVE_VMLADAVau8
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1300 = MVE_VMLADAVau32
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1299 = MVE_VMLADAVau16
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1298 = MVE_VMLADAVas8
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1297 = MVE_VMLADAVas32
  { 7, &ARMDescs.OperandInfo[1320] },  // Inst #1296 = MVE_VMLADAVas16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1295 = MVE_VMINu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1294 = MVE_VMINu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1293 = MVE_VMINu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1292 = MVE_VMINs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1291 = MVE_VMINs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1290 = MVE_VMINs16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1289 = MVE_VMINVu8
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1288 = MVE_VMINVu32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1287 = MVE_VMINVu16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1286 = MVE_VMINVs8
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1285 = MVE_VMINVs32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1284 = MVE_VMINVs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1283 = MVE_VMINNMf32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1282 = MVE_VMINNMf16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1281 = MVE_VMINNMVf32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1280 = MVE_VMINNMVf16
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1279 = MVE_VMINNMAf32
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1278 = MVE_VMINNMAf16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1277 = MVE_VMINNMAVf32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1276 = MVE_VMINNMAVf16
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1275 = MVE_VMINAs8
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1274 = MVE_VMINAs32
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1273 = MVE_VMINAs16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1272 = MVE_VMINAVs8
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1271 = MVE_VMINAVs32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1270 = MVE_VMINAVs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1269 = MVE_VMAXu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1268 = MVE_VMAXu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1267 = MVE_VMAXu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1266 = MVE_VMAXs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1265 = MVE_VMAXs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1264 = MVE_VMAXs16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1263 = MVE_VMAXVu8
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1262 = MVE_VMAXVu32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1261 = MVE_VMAXVu16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1260 = MVE_VMAXVs8
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1259 = MVE_VMAXVs32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1258 = MVE_VMAXVs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1257 = MVE_VMAXNMf32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1256 = MVE_VMAXNMf16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1255 = MVE_VMAXNMVf32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1254 = MVE_VMAXNMVf16
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1253 = MVE_VMAXNMAf32
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1252 = MVE_VMAXNMAf16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1251 = MVE_VMAXNMAVf32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1250 = MVE_VMAXNMAVf16
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1249 = MVE_VMAXAs8
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1248 = MVE_VMAXAs32
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1247 = MVE_VMAXAs16
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1246 = MVE_VMAXAVs8
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1245 = MVE_VMAXAVs32
  { 6, &ARMDescs.OperandInfo[1314] },  // Inst #1244 = MVE_VMAXAVs16
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1243 = MVE_VLDRWU32_rq_u
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1242 = MVE_VLDRWU32_rq
  { 7, &ARMDescs.OperandInfo[1307] },  // Inst #1241 = MVE_VLDRWU32_qi_pre
  { 6, &ARMDescs.OperandInfo[1301] },  // Inst #1240 = MVE_VLDRWU32_qi
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1239 = MVE_VLDRWU32_pre
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1238 = MVE_VLDRWU32_post
  { 6, &ARMDescs.OperandInfo[1288] },  // Inst #1237 = MVE_VLDRWU32
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1236 = MVE_VLDRHU32_rq_u
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1235 = MVE_VLDRHU32_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1234 = MVE_VLDRHU32_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1233 = MVE_VLDRHU32_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1232 = MVE_VLDRHU32
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1231 = MVE_VLDRHU16_rq_u
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1230 = MVE_VLDRHU16_rq
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1229 = MVE_VLDRHU16_pre
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1228 = MVE_VLDRHU16_post
  { 6, &ARMDescs.OperandInfo[1288] },  // Inst #1227 = MVE_VLDRHU16
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1226 = MVE_VLDRHS32_rq_u
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1225 = MVE_VLDRHS32_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1224 = MVE_VLDRHS32_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1223 = MVE_VLDRHS32_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1222 = MVE_VLDRHS32
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1221 = MVE_VLDRDU64_rq_u
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1220 = MVE_VLDRDU64_rq
  { 7, &ARMDescs.OperandInfo[1307] },  // Inst #1219 = MVE_VLDRDU64_qi_pre
  { 6, &ARMDescs.OperandInfo[1301] },  // Inst #1218 = MVE_VLDRDU64_qi
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1217 = MVE_VLDRBU8_rq
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1216 = MVE_VLDRBU8_pre
  { 7, &ARMDescs.OperandInfo[1294] },  // Inst #1215 = MVE_VLDRBU8_post
  { 6, &ARMDescs.OperandInfo[1288] },  // Inst #1214 = MVE_VLDRBU8
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1213 = MVE_VLDRBU32_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1212 = MVE_VLDRBU32_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1211 = MVE_VLDRBU32_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1210 = MVE_VLDRBU32
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1209 = MVE_VLDRBU16_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1208 = MVE_VLDRBU16_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1207 = MVE_VLDRBU16_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1206 = MVE_VLDRBU16
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1205 = MVE_VLDRBS32_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1204 = MVE_VLDRBS32_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1203 = MVE_VLDRBS32_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1202 = MVE_VLDRBS32
  { 6, &ARMDescs.OperandInfo[1282] },  // Inst #1201 = MVE_VLDRBS16_rq
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1200 = MVE_VLDRBS16_pre
  { 7, &ARMDescs.OperandInfo[1275] },  // Inst #1199 = MVE_VLDRBS16_post
  { 6, &ARMDescs.OperandInfo[1269] },  // Inst #1198 = MVE_VLDRBS16
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1197 = MVE_VLD43_8_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1196 = MVE_VLD43_8
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1195 = MVE_VLD43_32_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1194 = MVE_VLD43_32
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1193 = MVE_VLD43_16_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1192 = MVE_VLD43_16
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1191 = MVE_VLD42_8_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1190 = MVE_VLD42_8
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1189 = MVE_VLD42_32_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1188 = MVE_VLD42_32
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1187 = MVE_VLD42_16_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1186 = MVE_VLD42_16
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1185 = MVE_VLD41_8_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1184 = MVE_VLD41_8
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1183 = MVE_VLD41_32_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1182 = MVE_VLD41_32
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1181 = MVE_VLD41_16_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1180 = MVE_VLD41_16
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1179 = MVE_VLD40_8_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1178 = MVE_VLD40_8
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1177 = MVE_VLD40_32_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1176 = MVE_VLD40_32
  { 4, &ARMDescs.OperandInfo[1265] },  // Inst #1175 = MVE_VLD40_16_wb
  { 3, &ARMDescs.OperandInfo[1262] },  // Inst #1174 = MVE_VLD40_16
  { 4, &ARMDescs.OperandInfo[1258] },  // Inst #1173 = MVE_VLD21_8_wb
  { 3, &ARMDescs.OperandInfo[1255] },  // Inst #1172 = MVE_VLD21_8
  { 4, &ARMDescs.OperandInfo[1258] },  // Inst #1171 = MVE_VLD21_32_wb
  { 3, &ARMDescs.OperandInfo[1255] },  // Inst #1170 = MVE_VLD21_32
  { 4, &ARMDescs.OperandInfo[1258] },  // Inst #1169 = MVE_VLD21_16_wb
  { 3, &ARMDescs.OperandInfo[1255] },  // Inst #1168 = MVE_VLD21_16
  { 4, &ARMDescs.OperandInfo[1258] },  // Inst #1167 = MVE_VLD20_8_wb
  { 3, &ARMDescs.OperandInfo[1255] },  // Inst #1166 = MVE_VLD20_8
  { 4, &ARMDescs.OperandInfo[1258] },  // Inst #1165 = MVE_VLD20_32_wb
  { 3, &ARMDescs.OperandInfo[1255] },  // Inst #1164 = MVE_VLD20_32
  { 4, &ARMDescs.OperandInfo[1258] },  // Inst #1163 = MVE_VLD20_16_wb
  { 3, &ARMDescs.OperandInfo[1255] },  // Inst #1162 = MVE_VLD20_16
  { 9, &ARMDescs.OperandInfo[1232] },  // Inst #1161 = MVE_VIWDUPu8
  { 9, &ARMDescs.OperandInfo[1232] },  // Inst #1160 = MVE_VIWDUPu32
  { 9, &ARMDescs.OperandInfo[1232] },  // Inst #1159 = MVE_VIWDUPu16
  { 8, &ARMDescs.OperandInfo[1218] },  // Inst #1158 = MVE_VIDUPu8
  { 8, &ARMDescs.OperandInfo[1218] },  // Inst #1157 = MVE_VIDUPu32
  { 8, &ARMDescs.OperandInfo[1218] },  // Inst #1156 = MVE_VIDUPu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1155 = MVE_VHSUBu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1154 = MVE_VHSUBu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1153 = MVE_VHSUBu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1152 = MVE_VHSUBs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1151 = MVE_VHSUBs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1150 = MVE_VHSUBs16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1149 = MVE_VHSUB_qr_u8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1148 = MVE_VHSUB_qr_u32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1147 = MVE_VHSUB_qr_u16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1146 = MVE_VHSUB_qr_s8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1145 = MVE_VHSUB_qr_s32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1144 = MVE_VHSUB_qr_s16
  { 8, &ARMDescs.OperandInfo[1162] },  // Inst #1143 = MVE_VHCADDs8
  { 8, &ARMDescs.OperandInfo[1170] },  // Inst #1142 = MVE_VHCADDs32
  { 8, &ARMDescs.OperandInfo[1162] },  // Inst #1141 = MVE_VHCADDs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1140 = MVE_VHADDu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1139 = MVE_VHADDu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1138 = MVE_VHADDu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1137 = MVE_VHADDs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1136 = MVE_VHADDs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1135 = MVE_VHADDs16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1134 = MVE_VHADD_qr_u8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1133 = MVE_VHADD_qr_u32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1132 = MVE_VHADD_qr_u16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1131 = MVE_VHADD_qr_s8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1130 = MVE_VHADD_qr_s32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1129 = MVE_VHADD_qr_s16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1128 = MVE_VFMSf32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1127 = MVE_VFMSf16
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1126 = MVE_VFMAf32
  { 7, &ARMDescs.OperandInfo[1248] },  // Inst #1125 = MVE_VFMAf16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1124 = MVE_VFMA_qr_f32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1123 = MVE_VFMA_qr_f16
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1122 = MVE_VFMA_qr_Sf32
  { 7, &ARMDescs.OperandInfo[1241] },  // Inst #1121 = MVE_VFMA_qr_Sf16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1120 = MVE_VEOR
  { 9, &ARMDescs.OperandInfo[1232] },  // Inst #1119 = MVE_VDWDUPu8
  { 9, &ARMDescs.OperandInfo[1232] },  // Inst #1118 = MVE_VDWDUPu32
  { 9, &ARMDescs.OperandInfo[1232] },  // Inst #1117 = MVE_VDWDUPu16
  { 6, &ARMDescs.OperandInfo[1226] },  // Inst #1116 = MVE_VDUP8
  { 6, &ARMDescs.OperandInfo[1226] },  // Inst #1115 = MVE_VDUP32
  { 6, &ARMDescs.OperandInfo[1226] },  // Inst #1114 = MVE_VDUP16
  { 8, &ARMDescs.OperandInfo[1218] },  // Inst #1113 = MVE_VDDUPu8
  { 8, &ARMDescs.OperandInfo[1218] },  // Inst #1112 = MVE_VDDUPu32
  { 8, &ARMDescs.OperandInfo[1218] },  // Inst #1111 = MVE_VDDUPu16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1110 = MVE_VCVTu32f32z
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1109 = MVE_VCVTu32f32p
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1108 = MVE_VCVTu32f32n
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1107 = MVE_VCVTu32f32m
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1106 = MVE_VCVTu32f32a
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1105 = MVE_VCVTu32f32_fix
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1104 = MVE_VCVTu16f16z
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1103 = MVE_VCVTu16f16p
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1102 = MVE_VCVTu16f16n
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1101 = MVE_VCVTu16f16m
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1100 = MVE_VCVTu16f16a
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1099 = MVE_VCVTu16f16_fix
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1098 = MVE_VCVTs32f32z
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1097 = MVE_VCVTs32f32p
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1096 = MVE_VCVTs32f32n
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1095 = MVE_VCVTs32f32m
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1094 = MVE_VCVTs32f32a
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1093 = MVE_VCVTs32f32_fix
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1092 = MVE_VCVTs16f16z
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1091 = MVE_VCVTs16f16p
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1090 = MVE_VCVTs16f16n
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1089 = MVE_VCVTs16f16m
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1088 = MVE_VCVTs16f16a
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1087 = MVE_VCVTs16f16_fix
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1086 = MVE_VCVTf32u32n
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1085 = MVE_VCVTf32u32_fix
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1084 = MVE_VCVTf32s32n
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1083 = MVE_VCVTf32s32_fix
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1082 = MVE_VCVTf32f16th
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1081 = MVE_VCVTf32f16bh
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1080 = MVE_VCVTf16u16n
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1079 = MVE_VCVTf16u16_fix
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1078 = MVE_VCVTf16s16n
  { 7, &ARMDescs.OperandInfo[1211] },  // Inst #1077 = MVE_VCVTf16s16_fix
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1076 = MVE_VCVTf16f32th
  { 6, &ARMDescs.OperandInfo[1205] },  // Inst #1075 = MVE_VCVTf16f32bh
  { 5, &ARMDescs.OperandInfo[1200] },  // Inst #1074 = MVE_VCTP8
  { 5, &ARMDescs.OperandInfo[1200] },  // Inst #1073 = MVE_VCTP64
  { 5, &ARMDescs.OperandInfo[1200] },  // Inst #1072 = MVE_VCTP32
  { 5, &ARMDescs.OperandInfo[1200] },  // Inst #1071 = MVE_VCTP16
  { 8, &ARMDescs.OperandInfo[1170] },  // Inst #1070 = MVE_VCMULf32
  { 8, &ARMDescs.OperandInfo[1162] },  // Inst #1069 = MVE_VCMULf16
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1068 = MVE_VCMPu8r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1067 = MVE_VCMPu8
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1066 = MVE_VCMPu32r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1065 = MVE_VCMPu32
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1064 = MVE_VCMPu16r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1063 = MVE_VCMPu16
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1062 = MVE_VCMPs8r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1061 = MVE_VCMPs8
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1060 = MVE_VCMPs32r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1059 = MVE_VCMPs32
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1058 = MVE_VCMPs16r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1057 = MVE_VCMPs16
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1056 = MVE_VCMPi8r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1055 = MVE_VCMPi8
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1054 = MVE_VCMPi32r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1053 = MVE_VCMPi32
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1052 = MVE_VCMPi16r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1051 = MVE_VCMPi16
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1050 = MVE_VCMPf32r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1049 = MVE_VCMPf32
  { 7, &ARMDescs.OperandInfo[1193] },  // Inst #1048 = MVE_VCMPf16r
  { 7, &ARMDescs.OperandInfo[1186] },  // Inst #1047 = MVE_VCMPf16
  { 8, &ARMDescs.OperandInfo[1178] },  // Inst #1046 = MVE_VCMLAf32
  { 8, &ARMDescs.OperandInfo[1178] },  // Inst #1045 = MVE_VCMLAf16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1044 = MVE_VCLZs8
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1043 = MVE_VCLZs32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1042 = MVE_VCLZs16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1041 = MVE_VCLSs8
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1040 = MVE_VCLSs32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #1039 = MVE_VCLSs16
  { 8, &ARMDescs.OperandInfo[1162] },  // Inst #1038 = MVE_VCADDi8
  { 8, &ARMDescs.OperandInfo[1170] },  // Inst #1037 = MVE_VCADDi32
  { 8, &ARMDescs.OperandInfo[1162] },  // Inst #1036 = MVE_VCADDi16
  { 8, &ARMDescs.OperandInfo[1170] },  // Inst #1035 = MVE_VCADDf32
  { 8, &ARMDescs.OperandInfo[1162] },  // Inst #1034 = MVE_VCADDf16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1033 = MVE_VBRSR8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1032 = MVE_VBRSR32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1031 = MVE_VBRSR16
  { 6, &ARMDescs.OperandInfo[1156] },  // Inst #1030 = MVE_VBICimmi32
  { 6, &ARMDescs.OperandInfo[1156] },  // Inst #1029 = MVE_VBICimmi16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1028 = MVE_VBIC
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1027 = MVE_VAND
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1026 = MVE_VADDi8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1025 = MVE_VADDi32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1024 = MVE_VADDi16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1023 = MVE_VADDf32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #1022 = MVE_VADDf16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1021 = MVE_VADD_qr_i8
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1020 = MVE_VADD_qr_i32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1019 = MVE_VADD_qr_i16
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1018 = MVE_VADD_qr_f32
  { 7, &ARMDescs.OperandInfo[1149] },  // Inst #1017 = MVE_VADD_qr_f16
  { 5, &ARMDescs.OperandInfo[1144] },  // Inst #1016 = MVE_VADDVu8no_acc
  { 6, &ARMDescs.OperandInfo[1138] },  // Inst #1015 = MVE_VADDVu8acc
  { 5, &ARMDescs.OperandInfo[1144] },  // Inst #1014 = MVE_VADDVu32no_acc
  { 6, &ARMDescs.OperandInfo[1138] },  // Inst #1013 = MVE_VADDVu32acc
  { 5, &ARMDescs.OperandInfo[1144] },  // Inst #1012 = MVE_VADDVu16no_acc
  { 6, &ARMDescs.OperandInfo[1138] },  // Inst #1011 = MVE_VADDVu16acc
  { 5, &ARMDescs.OperandInfo[1144] },  // Inst #1010 = MVE_VADDVs8no_acc
  { 6, &ARMDescs.OperandInfo[1138] },  // Inst #1009 = MVE_VADDVs8acc
  { 5, &ARMDescs.OperandInfo[1144] },  // Inst #1008 = MVE_VADDVs32no_acc
  { 6, &ARMDescs.OperandInfo[1138] },  // Inst #1007 = MVE_VADDVs32acc
  { 5, &ARMDescs.OperandInfo[1144] },  // Inst #1006 = MVE_VADDVs16no_acc
  { 6, &ARMDescs.OperandInfo[1138] },  // Inst #1005 = MVE_VADDVs16acc
  { 6, &ARMDescs.OperandInfo[1132] },  // Inst #1004 = MVE_VADDLVu32no_acc
  { 8, &ARMDescs.OperandInfo[1124] },  // Inst #1003 = MVE_VADDLVu32acc
  { 6, &ARMDescs.OperandInfo[1132] },  // Inst #1002 = MVE_VADDLVs32no_acc
  { 8, &ARMDescs.OperandInfo[1124] },  // Inst #1001 = MVE_VADDLVs32acc
  { 8, &ARMDescs.OperandInfo[1116] },  // Inst #1000 = MVE_VADCI
  { 9, &ARMDescs.OperandInfo[1107] },  // Inst #999 = MVE_VADC
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #998 = MVE_VABSs8
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #997 = MVE_VABSs32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #996 = MVE_VABSs16
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #995 = MVE_VABSf32
  { 6, &ARMDescs.OperandInfo[1101] },  // Inst #994 = MVE_VABSf16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #993 = MVE_VABDu8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #992 = MVE_VABDu32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #991 = MVE_VABDu16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #990 = MVE_VABDs8
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #989 = MVE_VABDs32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #988 = MVE_VABDs16
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #987 = MVE_VABDf32
  { 7, &ARMDescs.OperandInfo[1094] },  // Inst #986 = MVE_VABDf16
  { 7, &ARMDescs.OperandInfo[1087] },  // Inst #985 = MVE_VABAVu8
  { 7, &ARMDescs.OperandInfo[1087] },  // Inst #984 = MVE_VABAVu32
  { 7, &ARMDescs.OperandInfo[1087] },  // Inst #983 = MVE_VABAVu16
  { 7, &ARMDescs.OperandInfo[1087] },  // Inst #982 = MVE_VABAVs8
  { 7, &ARMDescs.OperandInfo[1087] },  // Inst #981 = MVE_VABAVs32
  { 7, &ARMDescs.OperandInfo[1087] },  // Inst #980 = MVE_VABAVs16
  { 7, &ARMDescs.OperandInfo[1060] },  // Inst #979 = MVE_URSHRL
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #978 = MVE_URSHR
  { 7, &ARMDescs.OperandInfo[1060] },  // Inst #977 = MVE_UQSHLL
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #976 = MVE_UQSHL
  { 8, &ARMDescs.OperandInfo[1079] },  // Inst #975 = MVE_UQRSHLL
  { 5, &ARMDescs.OperandInfo[1074] },  // Inst #974 = MVE_UQRSHL
  { 7, &ARMDescs.OperandInfo[1060] },  // Inst #973 = MVE_SRSHRL
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #972 = MVE_SRSHR
  { 7, &ARMDescs.OperandInfo[1060] },  // Inst #971 = MVE_SQSHLL
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #970 = MVE_SQSHL
  { 8, &ARMDescs.OperandInfo[1079] },  // Inst #969 = MVE_SQRSHRL
  { 5, &ARMDescs.OperandInfo[1074] },  // Inst #968 = MVE_SQRSHR
  { 7, &ARMDescs.OperandInfo[1060] },  // Inst #967 = MVE_LSRL
  { 7, &ARMDescs.OperandInfo[1067] },  // Inst #966 = MVE_LSLLr
  { 7, &ARMDescs.OperandInfo[1060] },  // Inst #965 = MVE_LSLLi
  { 3, &ARMDescs.OperandInfo[441] },  // Inst #964 = MVE_LETP
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #963 = MVE_LCTP
  { 2, &ARMDescs.OperandInfo[420] },  // Inst #962 = MVE_DLSTP_8
  { 2, &ARMDescs.OperandInfo[420] },  // Inst #961 = MVE_DLSTP_64
  { 2, &ARMDescs.OperandInfo[420] },  // Inst #960 = MVE_DLSTP_32
  { 2, &ARMDescs.OperandInfo[420] },  // Inst #959 = MVE_DLSTP_16
  { 7, &ARMDescs.OperandInfo[1067] },  // Inst #958 = MVE_ASRLr
  { 7, &ARMDescs.OperandInfo[1060] },  // Inst #957 = MVE_ASRLi
  { 6, &ARMDescs.OperandInfo[175] },  // Inst #956 = MUL
  { 4, &ARMDescs.OperandInfo[1056] },  // Inst #955 = MSRi
  { 4, &ARMDescs.OperandInfo[1052] },  // Inst #954 = MSRbanked
  { 4, &ARMDescs.OperandInfo[1048] },  // Inst #953 = MSR
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #952 = MRSsys
  { 4, &ARMDescs.OperandInfo[425] },  // Inst #951 = MRSbanked
  { 3, &ARMDescs.OperandInfo[1045] },  // Inst #950 = MRS
  { 5, &ARMDescs.OperandInfo[1040] },  // Inst #949 = MRRC2
  { 7, &ARMDescs.OperandInfo[1033] },  // Inst #948 = MRRC
  { 6, &ARMDescs.OperandInfo[1027] },  // Inst #947 = MRC2
  { 8, &ARMDescs.OperandInfo[1019] },  // Inst #946 = MRC
  { 7, &ARMDescs.OperandInfo[1012] },  // Inst #945 = MOVsr
  { 6, &ARMDescs.OperandInfo[1006] },  // Inst #944 = MOVsi
  { 5, &ARMDescs.OperandInfo[1001] },  // Inst #943 = MOVr_TC
  { 5, &ARMDescs.OperandInfo[314] },  // Inst #942 = MOVr
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #941 = MOVi16
  { 5, &ARMDescs.OperandInfo[996] },  // Inst #940 = MOVi
  { 5, &ARMDescs.OperandInfo[991] },  // Inst #939 = MOVTi16
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #938 = MOVPCLR
  { 6, &ARMDescs.OperandInfo[985] },  // Inst #937 = MLS
  { 7, &ARMDescs.OperandInfo[978] },  // Inst #936 = MLA
  { 5, &ARMDescs.OperandInfo[973] },  // Inst #935 = MCRR2
  { 7, &ARMDescs.OperandInfo[966] },  // Inst #934 = MCRR
  { 6, &ARMDescs.OperandInfo[960] },  // Inst #933 = MCR2
  { 8, &ARMDescs.OperandInfo[952] },  // Inst #932 = MCR
  { 6, &ARMDescs.OperandInfo[946] },  // Inst #931 = LDRrs
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #930 = LDRi12
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #929 = LDRcp
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #928 = LDR_PRE_REG
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #927 = LDR_PRE_IMM
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #926 = LDR_POST_REG
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #925 = LDR_POST_IMM
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #924 = LDRT_POST_REG
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #923 = LDRT_POST_IMM
  { 7, &ARMDescs.OperandInfo[939] },  // Inst #922 = LDRSH_PRE
  { 7, &ARMDescs.OperandInfo[939] },  // Inst #921 = LDRSH_POST
  { 7, &ARMDescs.OperandInfo[932] },  // Inst #920 = LDRSHTr
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #919 = LDRSHTi
  { 6, &ARMDescs.OperandInfo[926] },  // Inst #918 = LDRSH
  { 7, &ARMDescs.OperandInfo[939] },  // Inst #917 = LDRSB_PRE
  { 7, &ARMDescs.OperandInfo[939] },  // Inst #916 = LDRSB_POST
  { 7, &ARMDescs.OperandInfo[932] },  // Inst #915 = LDRSBTr
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #914 = LDRSBTi
  { 6, &ARMDescs.OperandInfo[926] },  // Inst #913 = LDRSB
  { 7, &ARMDescs.OperandInfo[939] },  // Inst #912 = LDRH_PRE
  { 7, &ARMDescs.OperandInfo[939] },  // Inst #911 = LDRH_POST
  { 7, &ARMDescs.OperandInfo[932] },  // Inst #910 = LDRHTr
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #909 = LDRHTi
  { 6, &ARMDescs.OperandInfo[926] },  // Inst #908 = LDRH
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #907 = LDREXH
  { 4, &ARMDescs.OperandInfo[863] },  // Inst #906 = LDREXD
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #905 = LDREXB
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #904 = LDREX
  { 8, &ARMDescs.OperandInfo[918] },  // Inst #903 = LDRD_PRE
  { 8, &ARMDescs.OperandInfo[918] },  // Inst #902 = LDRD_POST
  { 7, &ARMDescs.OperandInfo[911] },  // Inst #901 = LDRD
  { 6, &ARMDescs.OperandInfo[905] },  // Inst #900 = LDRBrs
  { 5, &ARMDescs.OperandInfo[900] },  // Inst #899 = LDRBi12
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #898 = LDRB_PRE_REG
  { 6, &ARMDescs.OperandInfo[894] },  // Inst #897 = LDRB_PRE_IMM
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #896 = LDRB_POST_REG
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #895 = LDRB_POST_IMM
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #894 = LDRBT_POST_REG
  { 7, &ARMDescs.OperandInfo[887] },  // Inst #893 = LDRBT_POST_IMM
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #892 = LDMIB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #891 = LDMIB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #890 = LDMIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #889 = LDMIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #888 = LDMDB_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #887 = LDMDB
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #886 = LDMDA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #885 = LDMDA
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #884 = LDC_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #883 = LDC_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #882 = LDC_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #881 = LDC_OFFSET
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #880 = LDCL_PRE
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #879 = LDCL_POST
  { 6, &ARMDescs.OperandInfo[881] },  // Inst #878 = LDCL_OPTION
  { 6, &ARMDescs.OperandInfo[875] },  // Inst #877 = LDCL_OFFSET
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #876 = LDC2_PRE
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #875 = LDC2_POST
  { 4, &ARMDescs.OperandInfo[871] },  // Inst #874 = LDC2_OPTION
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #873 = LDC2_OFFSET
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #872 = LDC2L_PRE
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #871 = LDC2L_POST
  { 4, &ARMDescs.OperandInfo[871] },  // Inst #870 = LDC2L_OPTION
  { 4, &ARMDescs.OperandInfo[867] },  // Inst #869 = LDC2L_OFFSET
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #868 = LDAH
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #867 = LDAEXH
  { 4, &ARMDescs.OperandInfo[863] },  // Inst #866 = LDAEXD
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #865 = LDAEXB
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #864 = LDAEX
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #863 = LDAB
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #862 = LDA
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #861 = ISB
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #860 = HVC
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #859 = HLT
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #858 = HINT
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #857 = FSTMXIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #856 = FSTMXIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #855 = FSTMXDB_UPD
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #854 = FMSTAT
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #853 = FLDMXIA_UPD
  { 4, &ARMDescs.OperandInfo[859] },  // Inst #852 = FLDMXIA
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #851 = FLDMXDB_UPD
  { 4, &ARMDescs.OperandInfo[855] },  // Inst #850 = FCONSTS
  { 4, &ARMDescs.OperandInfo[851] },  // Inst #849 = FCONSTH
  { 4, &ARMDescs.OperandInfo[847] },  // Inst #848 = FCONSTD
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #847 = ERET
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #846 = EORrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #845 = EORrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #844 = EORrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #843 = EORri
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #842 = DSB
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #841 = DMB
  { 3, &ARMDescs.OperandInfo[844] },  // Inst #840 = DBG
  { 3, &ARMDescs.OperandInfo[841] },  // Inst #839 = CRC32W
  { 3, &ARMDescs.OperandInfo[841] },  // Inst #838 = CRC32H
  { 3, &ARMDescs.OperandInfo[841] },  // Inst #837 = CRC32CW
  { 3, &ARMDescs.OperandInfo[841] },  // Inst #836 = CRC32CH
  { 3, &ARMDescs.OperandInfo[841] },  // Inst #835 = CRC32CB
  { 3, &ARMDescs.OperandInfo[841] },  // Inst #834 = CRC32B
  { 3, &ARMDescs.OperandInfo[838] },  // Inst #833 = CPS3p
  { 2, &ARMDescs.OperandInfo[13] },  // Inst #832 = CPS2p
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #831 = CPS1p
  { 6, &ARMDescs.OperandInfo[832] },  // Inst #830 = CMPrsr
  { 5, &ARMDescs.OperandInfo[827] },  // Inst #829 = CMPrsi
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #828 = CMPrr
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #827 = CMPri
  { 6, &ARMDescs.OperandInfo[832] },  // Inst #826 = CMNzrsr
  { 5, &ARMDescs.OperandInfo[827] },  // Inst #825 = CMNzrsi
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #824 = CMNzrr
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #823 = CMNri
  { 4, &ARMDescs.OperandInfo[823] },  // Inst #822 = CLZ
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #821 = CLREX
  { 6, &ARMDescs.OperandInfo[817] },  // Inst #820 = CDP2
  { 8, &ARMDescs.OperandInfo[809] },  // Inst #819 = CDP
  { 9, &ARMDescs.OperandInfo[800] },  // Inst #818 = CDE_VCX3_vec
  { 5, &ARMDescs.OperandInfo[795] },  // Inst #817 = CDE_VCX3_fpsp
  { 5, &ARMDescs.OperandInfo[790] },  // Inst #816 = CDE_VCX3_fpdp
  { 9, &ARMDescs.OperandInfo[781] },  // Inst #815 = CDE_VCX3A_vec
  { 6, &ARMDescs.OperandInfo[775] },  // Inst #814 = CDE_VCX3A_fpsp
  { 6, &ARMDescs.OperandInfo[769] },  // Inst #813 = CDE_VCX3A_fpdp
  { 8, &ARMDescs.OperandInfo[761] },  // Inst #812 = CDE_VCX2_vec
  { 4, &ARMDescs.OperandInfo[757] },  // Inst #811 = CDE_VCX2_fpsp
  { 4, &ARMDescs.OperandInfo[753] },  // Inst #810 = CDE_VCX2_fpdp
  { 8, &ARMDescs.OperandInfo[745] },  // Inst #809 = CDE_VCX2A_vec
  { 5, &ARMDescs.OperandInfo[740] },  // Inst #808 = CDE_VCX2A_fpsp
  { 5, &ARMDescs.OperandInfo[735] },  // Inst #807 = CDE_VCX2A_fpdp
  { 7, &ARMDescs.OperandInfo[728] },  // Inst #806 = CDE_VCX1_vec
  { 3, &ARMDescs.OperandInfo[725] },  // Inst #805 = CDE_VCX1_fpsp
  { 3, &ARMDescs.OperandInfo[722] },  // Inst #804 = CDE_VCX1_fpdp
  { 7, &ARMDescs.OperandInfo[715] },  // Inst #803 = CDE_VCX1A_vec
  { 4, &ARMDescs.OperandInfo[711] },  // Inst #802 = CDE_VCX1A_fpsp
  { 4, &ARMDescs.OperandInfo[707] },  // Inst #801 = CDE_VCX1A_fpdp
  { 8, &ARMDescs.OperandInfo[699] },  // Inst #800 = CDE_CX3DA
  { 5, &ARMDescs.OperandInfo[694] },  // Inst #799 = CDE_CX3D
  { 8, &ARMDescs.OperandInfo[686] },  // Inst #798 = CDE_CX3A
  { 5, &ARMDescs.OperandInfo[681] },  // Inst #797 = CDE_CX3
  { 7, &ARMDescs.OperandInfo[674] },  // Inst #796 = CDE_CX2DA
  { 4, &ARMDescs.OperandInfo[670] },  // Inst #795 = CDE_CX2D
  { 7, &ARMDescs.OperandInfo[663] },  // Inst #794 = CDE_CX2A
  { 4, &ARMDescs.OperandInfo[659] },  // Inst #793 = CDE_CX2
  { 6, &ARMDescs.OperandInfo[653] },  // Inst #792 = CDE_CX1DA
  { 3, &ARMDescs.OperandInfo[650] },  // Inst #791 = CDE_CX1D
  { 6, &ARMDescs.OperandInfo[644] },  // Inst #790 = CDE_CX1A
  { 3, &ARMDescs.OperandInfo[641] },  // Inst #789 = CDE_CX1
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #788 = Bcc
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #787 = BX_pred
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #786 = BX_RET
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #785 = BXJ
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #784 = BX
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #783 = BL_pred
  { 1, &ARMDescs.OperandInfo[181] },  // Inst #782 = BLXi
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #781 = BLX_pred
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #780 = BLX
  { 1, &ARMDescs.OperandInfo[181] },  // Inst #779 = BL
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #778 = BKPT
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #777 = BICrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #776 = BICrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #775 = BICrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #774 = BICri
  { 6, &ARMDescs.OperandInfo[635] },  // Inst #773 = BFI
  { 5, &ARMDescs.OperandInfo[255] },  // Inst #772 = BFC
  { 5, &ARMDescs.OperandInfo[394] },  // Inst #771 = BF16_VCVTT
  { 5, &ARMDescs.OperandInfo[394] },  // Inst #770 = BF16_VCVTB
  { 4, &ARMDescs.OperandInfo[631] },  // Inst #769 = BF16_VCVT
  { 4, &ARMDescs.OperandInfo[627] },  // Inst #768 = BF16VDOTS_VDOTQ
  { 4, &ARMDescs.OperandInfo[623] },  // Inst #767 = BF16VDOTS_VDOTD
  { 5, &ARMDescs.OperandInfo[618] },  // Inst #766 = BF16VDOTI_VDOTQ
  { 5, &ARMDescs.OperandInfo[613] },  // Inst #765 = BF16VDOTI_VDOTD
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #764 = ANDrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #763 = ANDrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #762 = ANDrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #761 = ANDri
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #760 = AESMC
  { 2, &ARMDescs.OperandInfo[611] },  // Inst #759 = AESIMC
  { 3, &ARMDescs.OperandInfo[608] },  // Inst #758 = AESE
  { 3, &ARMDescs.OperandInfo[608] },  // Inst #757 = AESD
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #756 = ADR
  { 8, &ARMDescs.OperandInfo[600] },  // Inst #755 = ADDrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #754 = ADDrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #753 = ADDrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #752 = ADDri
  { 8, &ARMDescs.OperandInfo[592] },  // Inst #751 = ADCrsr
  { 7, &ARMDescs.OperandInfo[585] },  // Inst #750 = ADCrsi
  { 6, &ARMDescs.OperandInfo[579] },  // Inst #749 = ADCrr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #748 = ADCri
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #747 = tTPsoft
  { 4, &ARMDescs.OperandInfo[575] },  // Inst #746 = tTBH_JT
  { 4, &ARMDescs.OperandInfo[575] },  // Inst #745 = tTBB_JT
  { 1, &ARMDescs.OperandInfo[355] },  // Inst #744 = tTAILJMPr
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #743 = tTAILJMPdND
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #742 = tTAILJMPd
  { 3, &ARMDescs.OperandInfo[504] },  // Inst #741 = tSUBSrr
  { 3, &ARMDescs.OperandInfo[507] },  // Inst #740 = tSUBSi8
  { 3, &ARMDescs.OperandInfo[507] },  // Inst #739 = tSUBSi3
  { 3, &ARMDescs.OperandInfo[504] },  // Inst #738 = tSBCS
  { 2, &ARMDescs.OperandInfo[573] },  // Inst #737 = tRSBS
  { 3, &ARMDescs.OperandInfo[570] },  // Inst #736 = tPOP_RET
  { 2, &ARMDescs.OperandInfo[429] },  // Inst #735 = tMOVi32imm
  { 5, &ARMDescs.OperandInfo[565] },  // Inst #734 = tMOVCCr_pseudo
  { 3, &ARMDescs.OperandInfo[507] },  // Inst #733 = tLSLSri
  { 4, &ARMDescs.OperandInfo[561] },  // Inst #732 = tLEApcrelJT
  { 4, &ARMDescs.OperandInfo[561] },  // Inst #731 = tLEApcrel
  { 3, &ARMDescs.OperandInfo[558] },  // Inst #730 = tLDRpci_pic
  { 5, &ARMDescs.OperandInfo[553] },  // Inst #729 = tLDR_postidx
  { 2, &ARMDescs.OperandInfo[524] },  // Inst #728 = tLDRLIT_ga_pcrel
  { 2, &ARMDescs.OperandInfo[524] },  // Inst #727 = tLDRLIT_ga_abs
  { 4, &ARMDescs.OperandInfo[549] },  // Inst #726 = tLDRConstPool
  { 5, &ARMDescs.OperandInfo[544] },  // Inst #725 = tLDMIA_UPD
  { 5, &ARMDescs.OperandInfo[534] },  // Inst #724 = tCMP_SWAP_8
  { 5, &ARMDescs.OperandInfo[539] },  // Inst #723 = tCMP_SWAP_32
  { 5, &ARMDescs.OperandInfo[534] },  // Inst #722 = tCMP_SWAP_16
  { 3, &ARMDescs.OperandInfo[531] },  // Inst #721 = tBfar
  { 3, &ARMDescs.OperandInfo[528] },  // Inst #720 = tBX_RET_vararg
  { 2, &ARMDescs.OperandInfo[526] },  // Inst #719 = tBX_RET
  { 1, &ARMDescs.OperandInfo[195] },  // Inst #718 = tBX_CALL
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #717 = tBXNS_RET
  { 2, &ARMDescs.OperandInfo[524] },  // Inst #716 = tBR_JTr
  { 3, &ARMDescs.OperandInfo[521] },  // Inst #715 = tBRIND
  { 4, &ARMDescs.OperandInfo[517] },  // Inst #714 = tBL_PUSHLR
  { 3, &ARMDescs.OperandInfo[514] },  // Inst #713 = tBLXr_noip
  { 1, &ARMDescs.OperandInfo[513] },  // Inst #712 = tBLXNS_CALL
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #711 = tADJCALLSTACKUP
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #710 = tADJCALLSTACKDOWN
  { 3, &ARMDescs.OperandInfo[510] },  // Inst #709 = tADDframe
  { 3, &ARMDescs.OperandInfo[504] },  // Inst #708 = tADDSrr
  { 3, &ARMDescs.OperandInfo[507] },  // Inst #707 = tADDSi8
  { 3, &ARMDescs.OperandInfo[507] },  // Inst #706 = tADDSi3
  { 3, &ARMDescs.OperandInfo[504] },  // Inst #705 = tADCS
  { 4, &ARMDescs.OperandInfo[500] },  // Inst #704 = t2WhileLoopStartTP
  { 3, &ARMDescs.OperandInfo[497] },  // Inst #703 = t2WhileLoopStartLR
  { 2, &ARMDescs.OperandInfo[193] },  // Inst #702 = t2WhileLoopStart
  { 2, &ARMDescs.OperandInfo[420] },  // Inst #701 = t2WhileLoopSetup
  { 4, &ARMDescs.OperandInfo[218] },  // Inst #700 = t2TBH_JT
  { 4, &ARMDescs.OperandInfo[218] },  // Inst #699 = t2TBB_JT
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #698 = t2SpeculationBarrierSBEndBB
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #697 = t2SpeculationBarrierISBDSBEndBB
  { 6, &ARMDescs.OperandInfo[411] },  // Inst #696 = t2SUBSrs
  { 5, &ARMDescs.OperandInfo[406] },  // Inst #695 = t2SUBSrr
  { 5, &ARMDescs.OperandInfo[401] },  // Inst #694 = t2SUBSri
  { 6, &ARMDescs.OperandInfo[491] },  // Inst #693 = t2STR_preidx
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #692 = t2STR_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #691 = t2STR_POST_imm
  { 6, &ARMDescs.OperandInfo[491] },  // Inst #690 = t2STRH_preidx
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #689 = t2STRH_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #688 = t2STRH_POST_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #687 = t2STRH_OFFSET_imm
  { 6, &ARMDescs.OperandInfo[491] },  // Inst #686 = t2STRB_preidx
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #685 = t2STRB_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #684 = t2STRB_POST_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #683 = t2STRB_OFFSET_imm
  { 6, &ARMDescs.OperandInfo[485] },  // Inst #682 = t2RSBSrs
  { 5, &ARMDescs.OperandInfo[480] },  // Inst #681 = t2RSBSri
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #680 = t2MVNCCi
  { 6, &ARMDescs.OperandInfo[470] },  // Inst #679 = t2MOVsr
  { 5, &ARMDescs.OperandInfo[465] },  // Inst #678 = t2MOVsi
  { 2, &ARMDescs.OperandInfo[429] },  // Inst #677 = t2MOVi32imm
  { 3, &ARMDescs.OperandInfo[431] },  // Inst #676 = t2MOVi16_ga_pcrel
  { 2, &ARMDescs.OperandInfo[429] },  // Inst #675 = t2MOV_ga_pcrel
  { 4, &ARMDescs.OperandInfo[476] },  // Inst #674 = t2MOVTi16_ga_pcrel
  { 6, &ARMDescs.OperandInfo[470] },  // Inst #673 = t2MOVSsr
  { 5, &ARMDescs.OperandInfo[465] },  // Inst #672 = t2MOVSsi
  { 6, &ARMDescs.OperandInfo[444] },  // Inst #671 = t2MOVCCror
  { 5, &ARMDescs.OperandInfo[460] },  // Inst #670 = t2MOVCCr
  { 6, &ARMDescs.OperandInfo[444] },  // Inst #669 = t2MOVCClsr
  { 6, &ARMDescs.OperandInfo[444] },  // Inst #668 = t2MOVCClsl
  { 5, &ARMDescs.OperandInfo[455] },  // Inst #667 = t2MOVCCi32imm
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #666 = t2MOVCCi16
  { 5, &ARMDescs.OperandInfo[450] },  // Inst #665 = t2MOVCCi
  { 6, &ARMDescs.OperandInfo[444] },  // Inst #664 = t2MOVCCasr
  { 3, &ARMDescs.OperandInfo[441] },  // Inst #663 = t2LoopEndDec
  { 2, &ARMDescs.OperandInfo[193] },  // Inst #662 = t2LoopEnd
  { 3, &ARMDescs.OperandInfo[438] },  // Inst #661 = t2LoopDec
  { 4, &ARMDescs.OperandInfo[434] },  // Inst #660 = t2LEApcrelJT
  { 4, &ARMDescs.OperandInfo[434] },  // Inst #659 = t2LEApcrel
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #658 = t2LDRpcrel
  { 3, &ARMDescs.OperandInfo[431] },  // Inst #657 = t2LDRpci_pic
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #656 = t2LDR_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #655 = t2LDR_POST_imm
  { 4, &ARMDescs.OperandInfo[425] },  // Inst #654 = t2LDRSHpcrel
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #653 = t2LDRSH_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #652 = t2LDRSH_POST_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #651 = t2LDRSH_OFFSET_imm
  { 4, &ARMDescs.OperandInfo[425] },  // Inst #650 = t2LDRSBpcrel
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #649 = t2LDRSB_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #648 = t2LDRSB_POST_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #647 = t2LDRSB_OFFSET_imm
  { 2, &ARMDescs.OperandInfo[429] },  // Inst #646 = t2LDRLIT_ga_pcrel
  { 4, &ARMDescs.OperandInfo[425] },  // Inst #645 = t2LDRHpcrel
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #644 = t2LDRH_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #643 = t2LDRH_POST_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #642 = t2LDRH_OFFSET_imm
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #641 = t2LDRConstPool
  { 4, &ARMDescs.OperandInfo[425] },  // Inst #640 = t2LDRBpcrel
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #639 = t2LDRB_PRE_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #638 = t2LDRB_POST_imm
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #637 = t2LDRB_OFFSET_imm
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #636 = t2LDMIA_RET
  { 3, &ARMDescs.OperandInfo[422] },  // Inst #635 = t2DoLoopStartTP
  { 2, &ARMDescs.OperandInfo[420] },  // Inst #634 = t2DoLoopStart
  { 3, &ARMDescs.OperandInfo[417] },  // Inst #633 = t2CALL_BTI
  { 3, &ARMDescs.OperandInfo[196] },  // Inst #632 = t2BR_JT
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #631 = t2BF_LabelPseudo
  { 6, &ARMDescs.OperandInfo[411] },  // Inst #630 = t2ADDSrs
  { 5, &ARMDescs.OperandInfo[406] },  // Inst #629 = t2ADDSrr
  { 5, &ARMDescs.OperandInfo[401] },  // Inst #628 = t2ADDSri
  { 2, &ARMDescs.OperandInfo[399] },  // Inst #627 = t2ABS
  { 1, &ARMDescs.OperandInfo[195] },  // Inst #626 = WIN__DBZCHK
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #625 = WIN__CHKSTK
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #624 = VST4qWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #623 = VST4qWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #622 = VST4qWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #621 = VST4qWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #620 = VST4qWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #619 = VST4qWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #618 = VST4qAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #617 = VST4qAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #616 = VST4qAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #615 = VST4dWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #614 = VST4dWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #613 = VST4dWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #612 = VST4dWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #611 = VST4dWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #610 = VST4dWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #609 = VST4dAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #608 = VST4dAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #607 = VST4dAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #606 = VST4LNqWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #605 = VST4LNqWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #604 = VST4LNqWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #603 = VST4LNqWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #602 = VST4LNqAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #601 = VST4LNqAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #600 = VST4LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #599 = VST4LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #598 = VST4LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #597 = VST4LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #596 = VST4LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #595 = VST4LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #594 = VST4LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #593 = VST4LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #592 = VST4LNdAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #591 = VST3qWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #590 = VST3qWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #589 = VST3qWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #588 = VST3qWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #587 = VST3qWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #586 = VST3qWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #585 = VST3qAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #584 = VST3qAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #583 = VST3qAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #582 = VST3dWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #581 = VST3dWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #580 = VST3dWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #579 = VST3dWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #578 = VST3dWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #577 = VST3dWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #576 = VST3dAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #575 = VST3dAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #574 = VST3dAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #573 = VST3LNqWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #572 = VST3LNqWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #571 = VST3LNqWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #570 = VST3LNqWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #569 = VST3LNqAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #568 = VST3LNqAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #567 = VST3LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #566 = VST3LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #565 = VST3LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #564 = VST3LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #563 = VST3LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #562 = VST3LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #561 = VST3LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #560 = VST3LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #559 = VST3LNdAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #558 = VST2LNqWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #557 = VST2LNqWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #556 = VST2LNqWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #555 = VST2LNqWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #554 = VST2LNqAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #553 = VST2LNqAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #552 = VST2LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #551 = VST2LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #550 = VST2LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #549 = VST2LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #548 = VST2LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #547 = VST2LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #546 = VST2LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #545 = VST2LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #544 = VST2LNdAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #543 = VST1LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #542 = VST1LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #541 = VST1LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #540 = VST1LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #539 = VST1LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #538 = VST1LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #537 = VST1LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #536 = VST1LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #535 = VST1LNdAsm_16
  { 5, &ARMDescs.OperandInfo[394] },  // Inst #534 = VMOVScc
  { 1, &ARMDescs.OperandInfo[393] },  // Inst #533 = VMOVQ0
  { 5, &ARMDescs.OperandInfo[388] },  // Inst #532 = VMOVHcc
  { 5, &ARMDescs.OperandInfo[383] },  // Inst #531 = VMOVDcc
  { 1, &ARMDescs.OperandInfo[382] },  // Inst #530 = VMOVD0
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #529 = VLD4qWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #528 = VLD4qWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #527 = VLD4qWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #526 = VLD4qWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #525 = VLD4qWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #524 = VLD4qWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #523 = VLD4qAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #522 = VLD4qAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #521 = VLD4qAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #520 = VLD4dWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #519 = VLD4dWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #518 = VLD4dWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #517 = VLD4dWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #516 = VLD4dWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #515 = VLD4dWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #514 = VLD4dAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #513 = VLD4dAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #512 = VLD4dAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #511 = VLD4LNqWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #510 = VLD4LNqWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #509 = VLD4LNqWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #508 = VLD4LNqWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #507 = VLD4LNqAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #506 = VLD4LNqAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #505 = VLD4LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #504 = VLD4LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #503 = VLD4LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #502 = VLD4LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #501 = VLD4LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #500 = VLD4LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #499 = VLD4LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #498 = VLD4LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #497 = VLD4LNdAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #496 = VLD4DUPqWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #495 = VLD4DUPqWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #494 = VLD4DUPqWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #493 = VLD4DUPqWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #492 = VLD4DUPqWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #491 = VLD4DUPqWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #490 = VLD4DUPqAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #489 = VLD4DUPqAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #488 = VLD4DUPqAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #487 = VLD4DUPdWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #486 = VLD4DUPdWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #485 = VLD4DUPdWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #484 = VLD4DUPdWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #483 = VLD4DUPdWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #482 = VLD4DUPdWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #481 = VLD4DUPdAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #480 = VLD4DUPdAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #479 = VLD4DUPdAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #478 = VLD3qWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #477 = VLD3qWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #476 = VLD3qWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #475 = VLD3qWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #474 = VLD3qWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #473 = VLD3qWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #472 = VLD3qAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #471 = VLD3qAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #470 = VLD3qAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #469 = VLD3dWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #468 = VLD3dWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #467 = VLD3dWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #466 = VLD3dWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #465 = VLD3dWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #464 = VLD3dWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #463 = VLD3dAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #462 = VLD3dAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #461 = VLD3dAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #460 = VLD3LNqWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #459 = VLD3LNqWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #458 = VLD3LNqWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #457 = VLD3LNqWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #456 = VLD3LNqAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #455 = VLD3LNqAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #454 = VLD3LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #453 = VLD3LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #452 = VLD3LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #451 = VLD3LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #450 = VLD3LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #449 = VLD3LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #448 = VLD3LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #447 = VLD3LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #446 = VLD3LNdAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #445 = VLD3DUPqWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #444 = VLD3DUPqWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #443 = VLD3DUPqWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #442 = VLD3DUPqWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #441 = VLD3DUPqWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #440 = VLD3DUPqWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #439 = VLD3DUPqAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #438 = VLD3DUPqAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #437 = VLD3DUPqAsm_16
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #436 = VLD3DUPdWB_register_Asm_8
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #435 = VLD3DUPdWB_register_Asm_32
  { 6, &ARMDescs.OperandInfo[376] },  // Inst #434 = VLD3DUPdWB_register_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #433 = VLD3DUPdWB_fixed_Asm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #432 = VLD3DUPdWB_fixed_Asm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #431 = VLD3DUPdWB_fixed_Asm_16
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #430 = VLD3DUPdAsm_8
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #429 = VLD3DUPdAsm_32
  { 5, &ARMDescs.OperandInfo[371] },  // Inst #428 = VLD3DUPdAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #427 = VLD2LNqWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #426 = VLD2LNqWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #425 = VLD2LNqWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #424 = VLD2LNqWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #423 = VLD2LNqAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #422 = VLD2LNqAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #421 = VLD2LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #420 = VLD2LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #419 = VLD2LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #418 = VLD2LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #417 = VLD2LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #416 = VLD2LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #415 = VLD2LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #414 = VLD2LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #413 = VLD2LNdAsm_16
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #412 = VLD1LNdWB_register_Asm_8
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #411 = VLD1LNdWB_register_Asm_32
  { 7, &ARMDescs.OperandInfo[364] },  // Inst #410 = VLD1LNdWB_register_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #409 = VLD1LNdWB_fixed_Asm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #408 = VLD1LNdWB_fixed_Asm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #407 = VLD1LNdWB_fixed_Asm_16
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #406 = VLD1LNdAsm_8
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #405 = VLD1LNdAsm_32
  { 6, &ARMDescs.OperandInfo[358] },  // Inst #404 = VLD1LNdAsm_16
  { 7, &ARMDescs.OperandInfo[328] },  // Inst #403 = UMULLv5
  { 9, &ARMDescs.OperandInfo[319] },  // Inst #402 = UMLALv5
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #401 = TPsoft
  { 2, &ARMDescs.OperandInfo[356] },  // Inst #400 = TCRETURNri
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #399 = TCRETURNdi
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #398 = TAILJMPr4
  { 1, &ARMDescs.OperandInfo[355] },  // Inst #397 = TAILJMPr
  { 1, &ARMDescs.OperandInfo[181] },  // Inst #396 = TAILJMPd
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #395 = SpeculationBarrierSBEndBB
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #394 = SpeculationBarrierISBDSBEndBB
  { 7, &ARMDescs.OperandInfo[158] },  // Inst #393 = SUBSrsr
  { 6, &ARMDescs.OperandInfo[152] },  // Inst #392 = SUBSrsi
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #391 = SUBSrr
  { 5, &ARMDescs.OperandInfo[142] },  // Inst #390 = SUBSri
  { 3, &ARMDescs.OperandInfo[352] },  // Inst #389 = SUBS_PC_LR
  { 7, &ARMDescs.OperandInfo[338] },  // Inst #388 = STRr_preidx
  { 7, &ARMDescs.OperandInfo[338] },  // Inst #387 = STRi_preidx
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #386 = STRT_POST
  { 7, &ARMDescs.OperandInfo[345] },  // Inst #385 = STRH_preidx
  { 7, &ARMDescs.OperandInfo[338] },  // Inst #384 = STRBr_preidx
  { 7, &ARMDescs.OperandInfo[338] },  // Inst #383 = STRBi_preidx
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #382 = STRBT_POST
  { 4, &ARMDescs.OperandInfo[239] },  // Inst #381 = STOREDUAL
  { 3, &ARMDescs.OperandInfo[335] },  // Inst #380 = SPACE
  { 7, &ARMDescs.OperandInfo[328] },  // Inst #379 = SMULLv5
  { 9, &ARMDescs.OperandInfo[319] },  // Inst #378 = SMLALv5
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #377 = SEH_StackAlloc
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #376 = SEH_SaveSP
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #375 = SEH_SaveRegs_Ret
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #374 = SEH_SaveRegs
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #373 = SEH_SaveLR
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #372 = SEH_SaveFRegs
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #371 = SEH_PrologEnd
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #370 = SEH_Nop_Ret
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #369 = SEH_Nop
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #368 = SEH_EpilogStart
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #367 = SEH_EpilogEnd
  { 7, &ARMDescs.OperandInfo[158] },  // Inst #366 = RSBSrsr
  { 6, &ARMDescs.OperandInfo[152] },  // Inst #365 = RSBSrsi
  { 5, &ARMDescs.OperandInfo[142] },  // Inst #364 = RSBSri
  { 5, &ARMDescs.OperandInfo[314] },  // Inst #363 = RRXi
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #362 = RRX
  { 6, &ARMDescs.OperandInfo[175] },  // Inst #361 = RORr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #360 = RORi
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #359 = PICSTRH
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #358 = PICSTRB
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #357 = PICSTR
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #356 = PICLDRSH
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #355 = PICLDRSB
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #354 = PICLDRH
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #353 = PICLDRB
  { 5, &ARMDescs.OperandInfo[309] },  // Inst #352 = PICLDR
  { 5, &ARMDescs.OperandInfo[142] },  // Inst #351 = PICADD
  { 5, &ARMDescs.OperandInfo[255] },  // Inst #350 = MVNCCi
  { 3, &ARMDescs.OperandInfo[306] },  // Inst #349 = MVE_MEMSETLOOPINST
  { 3, &ARMDescs.OperandInfo[303] },  // Inst #348 = MVE_MEMCPYLOOPINST
  { 6, &ARMDescs.OperandInfo[297] },  // Inst #347 = MULv5
  { 2, &ARMDescs.OperandInfo[295] },  // Inst #346 = MQQQQPRStore
  { 2, &ARMDescs.OperandInfo[295] },  // Inst #345 = MQQQQPRLoad
  { 2, &ARMDescs.OperandInfo[293] },  // Inst #344 = MQQPRStore
  { 2, &ARMDescs.OperandInfo[293] },  // Inst #343 = MQQPRLoad
  { 2, &ARMDescs.OperandInfo[291] },  // Inst #342 = MQPRCopy
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #341 = MOVsrl_glue
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #340 = MOVsra_glue
  { 2, &ARMDescs.OperandInfo[206] },  // Inst #339 = MOVi32imm
  { 3, &ARMDescs.OperandInfo[288] },  // Inst #338 = MOVi16_ga_pcrel
  { 2, &ARMDescs.OperandInfo[206] },  // Inst #337 = MOV_ga_pcrel_ldr
  { 2, &ARMDescs.OperandInfo[206] },  // Inst #336 = MOV_ga_pcrel
  { 4, &ARMDescs.OperandInfo[284] },  // Inst #335 = MOVTi16_ga_pcrel
  { 1, &ARMDescs.OperandInfo[283] },  // Inst #334 = MOVPCRX
  { 7, &ARMDescs.OperandInfo[276] },  // Inst #333 = MOVCCsr
  { 6, &ARMDescs.OperandInfo[270] },  // Inst #332 = MOVCCsi
  { 5, &ARMDescs.OperandInfo[265] },  // Inst #331 = MOVCCr
  { 5, &ARMDescs.OperandInfo[260] },  // Inst #330 = MOVCCi32imm
  { 5, &ARMDescs.OperandInfo[255] },  // Inst #329 = MOVCCi16
  { 5, &ARMDescs.OperandInfo[255] },  // Inst #328 = MOVCCi
  { 7, &ARMDescs.OperandInfo[248] },  // Inst #327 = MLAv5
  { 5, &ARMDescs.OperandInfo[243] },  // Inst #326 = MEMCPY
  { 6, &ARMDescs.OperandInfo[175] },  // Inst #325 = LSRr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #324 = LSRi
  { 6, &ARMDescs.OperandInfo[175] },  // Inst #323 = LSLr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #322 = LSLi
  { 4, &ARMDescs.OperandInfo[239] },  // Inst #321 = LOADDUAL
  { 4, &ARMDescs.OperandInfo[235] },  // Inst #320 = LEApcrelJT
  { 4, &ARMDescs.OperandInfo[235] },  // Inst #319 = LEApcrel
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #318 = LDRT_POST
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #317 = LDRSHTii
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #316 = LDRSBTii
  { 2, &ARMDescs.OperandInfo[206] },  // Inst #315 = LDRLIT_ga_pcrel_ldr
  { 2, &ARMDescs.OperandInfo[206] },  // Inst #314 = LDRLIT_ga_pcrel
  { 2, &ARMDescs.OperandInfo[206] },  // Inst #313 = LDRLIT_ga_abs
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #312 = LDRHTii
  { 4, &ARMDescs.OperandInfo[231] },  // Inst #311 = LDRConstPool
  { 4, &ARMDescs.OperandInfo[227] },  // Inst #310 = LDRBT_POST
  { 5, &ARMDescs.OperandInfo[222] },  // Inst #309 = LDMIA_RET
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #308 = JUMPTABLE_TBH
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #307 = JUMPTABLE_TBB
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #306 = JUMPTABLE_INSTS
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #305 = JUMPTABLE_ADDRS
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #304 = Int_eh_sjlj_setup_dispatch
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #303 = Int_eh_sjlj_setjmp_nofp
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #302 = Int_eh_sjlj_setjmp
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #301 = Int_eh_sjlj_longjmp
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #300 = Int_eh_sjlj_dispatchsetup
  { 2, &ARMDescs.OperandInfo[13] },  // Inst #299 = ITasm
  { 4, &ARMDescs.OperandInfo[218] },  // Inst #298 = COPY_STRUCT_BYVAL_I32
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #297 = CONSTPOOL_ENTRY
  { 5, &ARMDescs.OperandInfo[208] },  // Inst #296 = CMP_SWAP_8
  { 5, &ARMDescs.OperandInfo[213] },  // Inst #295 = CMP_SWAP_64
  { 5, &ARMDescs.OperandInfo[208] },  // Inst #294 = CMP_SWAP_32
  { 5, &ARMDescs.OperandInfo[208] },  // Inst #293 = CMP_SWAP_16
  { 1, &ARMDescs.OperandInfo[195] },  // Inst #292 = BX_CALL
  { 2, &ARMDescs.OperandInfo[206] },  // Inst #291 = BR_JTr
  { 4, &ARMDescs.OperandInfo[202] },  // Inst #290 = BR_JTm_rs
  { 3, &ARMDescs.OperandInfo[199] },  // Inst #289 = BR_JTm_i12
  { 3, &ARMDescs.OperandInfo[196] },  // Inst #288 = BR_JTadd
  { 1, &ARMDescs.OperandInfo[195] },  // Inst #287 = BMOVPCRX_CALL
  { 1, &ARMDescs.OperandInfo[181] },  // Inst #286 = BMOVPCB_CALL
  { 2, &ARMDescs.OperandInfo[193] },  // Inst #285 = BL_PUSHLR
  { 1, &ARMDescs.OperandInfo[192] },  // Inst #284 = BLX_pred_noip
  { 1, &ARMDescs.OperandInfo[192] },  // Inst #283 = BLX_noip
  { 6, &ARMDescs.OperandInfo[186] },  // Inst #282 = BCCi64
  { 4, &ARMDescs.OperandInfo[182] },  // Inst #281 = BCCZi64
  { 1, &ARMDescs.OperandInfo[181] },  // Inst #280 = B
  { 6, &ARMDescs.OperandInfo[175] },  // Inst #279 = ASRr
  { 6, &ARMDescs.OperandInfo[169] },  // Inst #278 = ASRi
  { 4, &ARMDescs.OperandInfo[165] },  // Inst #277 = ADJCALLSTACKUP
  { 4, &ARMDescs.OperandInfo[165] },  // Inst #276 = ADJCALLSTACKDOWN
  { 7, &ARMDescs.OperandInfo[158] },  // Inst #275 = ADDSrsr
  { 6, &ARMDescs.OperandInfo[152] },  // Inst #274 = ADDSrsi
  { 5, &ARMDescs.OperandInfo[147] },  // Inst #273 = ADDSrr
  { 5, &ARMDescs.OperandInfo[142] },  // Inst #272 = ADDSri
  { 2, &ARMDescs.OperandInfo[140] },  // Inst #271 = ABS
  { 4, &ARMDescs.OperandInfo[136] },  // Inst #270 = G_UBFX
  { 4, &ARMDescs.OperandInfo[136] },  // Inst #269 = G_SBFX
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #268 = G_VECREDUCE_UMIN
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #267 = G_VECREDUCE_UMAX
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #266 = G_VECREDUCE_SMIN
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #265 = G_VECREDUCE_SMAX
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #264 = G_VECREDUCE_XOR
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #263 = G_VECREDUCE_OR
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #262 = G_VECREDUCE_AND
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #261 = G_VECREDUCE_MUL
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #260 = G_VECREDUCE_ADD
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #259 = G_VECREDUCE_FMINIMUM
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #258 = G_VECREDUCE_FMAXIMUM
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #257 = G_VECREDUCE_FMIN
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #256 = G_VECREDUCE_FMAX
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #255 = G_VECREDUCE_FMUL
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #254 = G_VECREDUCE_FADD
  { 3, &ARMDescs.OperandInfo[123] },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
  { 3, &ARMDescs.OperandInfo[123] },  // Inst #252 = G_VECREDUCE_SEQ_FADD
  { 3, &ARMDescs.OperandInfo[53] },  // Inst #251 = G_BZERO
  { 4, &ARMDescs.OperandInfo[132] },  // Inst #250 = G_MEMSET
  { 4, &ARMDescs.OperandInfo[132] },  // Inst #249 = G_MEMMOVE
  { 3, &ARMDescs.OperandInfo[123] },  // Inst #248 = G_MEMCPY_INLINE
  { 4, &ARMDescs.OperandInfo[132] },  // Inst #247 = G_MEMCPY
  { 2, &ARMDescs.OperandInfo[130] },  // Inst #246 = G_WRITE_REGISTER
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #245 = G_READ_REGISTER
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #244 = G_STRICT_FLDEXP
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #243 = G_STRICT_FSQRT
  { 4, &ARMDescs.OperandInfo[46] },  // Inst #242 = G_STRICT_FMA
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #241 = G_STRICT_FREM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #240 = G_STRICT_FDIV
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #239 = G_STRICT_FMUL
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #238 = G_STRICT_FSUB
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #237 = G_STRICT_FADD
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #236 = G_STACKRESTORE
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #235 = G_STACKSAVE
  { 3, &ARMDescs.OperandInfo[64] },  // Inst #234 = G_DYN_STACKALLOC
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #233 = G_JUMP_TABLE
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #232 = G_BLOCK_ADDR
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #231 = G_ADDRSPACE_CAST
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #230 = G_FNEARBYINT
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #229 = G_FRINT
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #228 = G_FFLOOR
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #227 = G_FSQRT
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #226 = G_FSIN
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #225 = G_FCOS
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #224 = G_FCEIL
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #223 = G_BITREVERSE
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #222 = G_BSWAP
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #221 = G_CTPOP
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #220 = G_CTLZ_ZERO_UNDEF
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #219 = G_CTLZ
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #218 = G_CTTZ_ZERO_UNDEF
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #217 = G_CTTZ
  { 4, &ARMDescs.OperandInfo[126] },  // Inst #216 = G_SHUFFLE_VECTOR
  { 3, &ARMDescs.OperandInfo[123] },  // Inst #215 = G_EXTRACT_VECTOR_ELT
  { 4, &ARMDescs.OperandInfo[119] },  // Inst #214 = G_INSERT_VECTOR_ELT
  { 3, &ARMDescs.OperandInfo[116] },  // Inst #213 = G_BRJT
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #212 = G_BR
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #211 = G_LLROUND
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #210 = G_LROUND
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #209 = G_ABS
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #208 = G_UMAX
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #207 = G_UMIN
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #206 = G_SMAX
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #205 = G_SMIN
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #204 = G_PTRMASK
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #203 = G_PTR_ADD
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #202 = G_RESET_FPMODE
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #201 = G_SET_FPMODE
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #200 = G_GET_FPMODE
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #199 = G_RESET_FPENV
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #198 = G_SET_FPENV
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #197 = G_GET_FPENV
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #196 = G_FMAXIMUM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #195 = G_FMINIMUM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #194 = G_FMAXNUM_IEEE
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #193 = G_FMINNUM_IEEE
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #192 = G_FMAXNUM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #191 = G_FMINNUM
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #190 = G_FCANONICALIZE
  { 3, &ARMDescs.OperandInfo[93] },  // Inst #189 = G_IS_FPCLASS
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #188 = G_FCOPYSIGN
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #187 = G_FABS
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #186 = G_UITOFP
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #185 = G_SITOFP
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #184 = G_FPTOUI
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #183 = G_FPTOSI
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #182 = G_FPTRUNC
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #181 = G_FPEXT
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #180 = G_FNEG
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #179 = G_FFREXP
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #178 = G_FLDEXP
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #177 = G_FLOG10
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #176 = G_FLOG2
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #175 = G_FLOG
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #174 = G_FEXP10
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #173 = G_FEXP2
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #172 = G_FEXP
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #171 = G_FPOWI
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #170 = G_FPOW
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #169 = G_FREM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #168 = G_FDIV
  { 4, &ARMDescs.OperandInfo[46] },  // Inst #167 = G_FMAD
  { 4, &ARMDescs.OperandInfo[46] },  // Inst #166 = G_FMA
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #165 = G_FMUL
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #164 = G_FSUB
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #163 = G_FADD
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #162 = G_UDIVFIXSAT
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #161 = G_SDIVFIXSAT
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #160 = G_UDIVFIX
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #159 = G_SDIVFIX
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #158 = G_UMULFIXSAT
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #157 = G_SMULFIXSAT
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #156 = G_UMULFIX
  { 4, &ARMDescs.OperandInfo[112] },  // Inst #155 = G_SMULFIX
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #154 = G_SSHLSAT
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #153 = G_USHLSAT
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #152 = G_SSUBSAT
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #151 = G_USUBSAT
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #150 = G_SADDSAT
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #149 = G_UADDSAT
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #148 = G_SMULH
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #147 = G_UMULH
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #146 = G_SMULO
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #145 = G_UMULO
  { 5, &ARMDescs.OperandInfo[107] },  // Inst #144 = G_SSUBE
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #143 = G_SSUBO
  { 5, &ARMDescs.OperandInfo[107] },  // Inst #142 = G_SADDE
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #141 = G_SADDO
  { 5, &ARMDescs.OperandInfo[107] },  // Inst #140 = G_USUBE
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #139 = G_USUBO
  { 5, &ARMDescs.OperandInfo[107] },  // Inst #138 = G_UADDE
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #137 = G_UADDO
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #136 = G_SELECT
  { 4, &ARMDescs.OperandInfo[103] },  // Inst #135 = G_FCMP
  { 4, &ARMDescs.OperandInfo[103] },  // Inst #134 = G_ICMP
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #133 = G_ROTL
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #132 = G_ROTR
  { 4, &ARMDescs.OperandInfo[99] },  // Inst #131 = G_FSHR
  { 4, &ARMDescs.OperandInfo[99] },  // Inst #130 = G_FSHL
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #129 = G_ASHR
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #128 = G_LSHR
  { 3, &ARMDescs.OperandInfo[96] },  // Inst #127 = G_SHL
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #126 = G_ZEXT
  { 3, &ARMDescs.OperandInfo[40] },  // Inst #125 = G_SEXT_INREG
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #124 = G_SEXT
  { 3, &ARMDescs.OperandInfo[93] },  // Inst #123 = G_VAARG
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #122 = G_VASTART
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #121 = G_FCONSTANT
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #120 = G_CONSTANT
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #119 = G_TRUNC
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #118 = G_ANYEXT
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #116 = G_INTRINSIC_CONVERGENT
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #114 = G_INTRINSIC
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #113 = G_INVOKE_REGION_START
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #112 = G_BRINDIRECT
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #111 = G_BRCOND
  { 4, &ARMDescs.OperandInfo[89] },  // Inst #110 = G_PREFETCH
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #109 = G_FENCE
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #106 = G_ATOMICRMW_FMIN
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #105 = G_ATOMICRMW_FMAX
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #104 = G_ATOMICRMW_FSUB
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #103 = G_ATOMICRMW_FADD
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #102 = G_ATOMICRMW_UMIN
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #101 = G_ATOMICRMW_UMAX
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #100 = G_ATOMICRMW_MIN
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #99 = G_ATOMICRMW_MAX
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #98 = G_ATOMICRMW_XOR
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #97 = G_ATOMICRMW_OR
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #96 = G_ATOMICRMW_NAND
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #95 = G_ATOMICRMW_AND
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #94 = G_ATOMICRMW_SUB
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #93 = G_ATOMICRMW_ADD
  { 3, &ARMDescs.OperandInfo[86] },  // Inst #92 = G_ATOMICRMW_XCHG
  { 4, &ARMDescs.OperandInfo[82] },  // Inst #91 = G_ATOMIC_CMPXCHG
  { 5, &ARMDescs.OperandInfo[77] },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
  { 5, &ARMDescs.OperandInfo[72] },  // Inst #89 = G_INDEXED_STORE
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #88 = G_STORE
  { 5, &ARMDescs.OperandInfo[67] },  // Inst #87 = G_INDEXED_ZEXTLOAD
  { 5, &ARMDescs.OperandInfo[67] },  // Inst #86 = G_INDEXED_SEXTLOAD
  { 5, &ARMDescs.OperandInfo[67] },  // Inst #85 = G_INDEXED_LOAD
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #84 = G_ZEXTLOAD
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #83 = G_SEXTLOAD
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #82 = G_LOAD
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #81 = G_READCYCLECOUNTER
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #79 = G_INTRINSIC_LRINT
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #78 = G_INTRINSIC_ROUND
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #77 = G_INTRINSIC_TRUNC
  { 3, &ARMDescs.OperandInfo[64] },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
  { 2, &ARMDescs.OperandInfo[62] },  // Inst #74 = G_FREEZE
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #73 = G_BITCAST
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #72 = G_INTTOPTR
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #71 = G_PTRTOINT
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #70 = G_CONCAT_VECTORS
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #69 = G_BUILD_VECTOR_TRUNC
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #68 = G_BUILD_VECTOR
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #67 = G_MERGE_VALUES
  { 4, &ARMDescs.OperandInfo[58] },  // Inst #66 = G_INSERT
  { 2, &ARMDescs.OperandInfo[56] },  // Inst #65 = G_UNMERGE_VALUES
  { 3, &ARMDescs.OperandInfo[53] },  // Inst #64 = G_EXTRACT
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #63 = G_CONSTANT_POOL
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #62 = G_GLOBAL_VALUE
  { 2, &ARMDescs.OperandInfo[51] },  // Inst #61 = G_FRAME_INDEX
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #60 = G_PHI
  { 1, &ARMDescs.OperandInfo[50] },  // Inst #59 = G_IMPLICIT_DEF
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #58 = G_XOR
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #57 = G_OR
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #56 = G_AND
  { 4, &ARMDescs.OperandInfo[46] },  // Inst #55 = G_UDIVREM
  { 4, &ARMDescs.OperandInfo[46] },  // Inst #54 = G_SDIVREM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #53 = G_UREM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #52 = G_SREM
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #51 = G_UDIV
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #50 = G_SDIV
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #49 = G_MUL
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #48 = G_SUB
  { 3, &ARMDescs.OperandInfo[43] },  // Inst #47 = G_ADD
  { 3, &ARMDescs.OperandInfo[40] },  // Inst #46 = G_ASSERT_ALIGN
  { 3, &ARMDescs.OperandInfo[40] },  // Inst #45 = G_ASSERT_ZEXT
  { 3, &ARMDescs.OperandInfo[40] },  // Inst #44 = G_ASSERT_SEXT
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #42 = MEMBARRIER
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #41 = ICALL_BRANCH_FUNNEL
  { 3, &ARMDescs.OperandInfo[37] },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
  { 2, &ARMDescs.OperandInfo[35] },  // Inst #39 = PATCHABLE_EVENT_CALL
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #38 = PATCHABLE_TAIL_CALL
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #36 = PATCHABLE_RET
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #34 = PATCHABLE_OP
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #33 = FAULTING_OP
  { 2, &ARMDescs.OperandInfo[33] },  // Inst #32 = LOCAL_ESCAPE
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #31 = STATEPOINT
  { 3, &ARMDescs.OperandInfo[30] },  // Inst #30 = PREALLOCATED_ARG
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #29 = PREALLOCATED_SETUP
  { 1, &ARMDescs.OperandInfo[29] },  // Inst #28 = LOAD_STACK_GUARD
  { 6, &ARMDescs.OperandInfo[23] },  // Inst #27 = PATCHPOINT
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #26 = FENTRY_CALL
  { 2, &ARMDescs.OperandInfo[21] },  // Inst #25 = STACKMAP
  { 2, &ARMDescs.OperandInfo[19] },  // Inst #24 = ARITH_FENCE
  { 4, &ARMDescs.OperandInfo[15] },  // Inst #23 = PSEUDO_PROBE
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #22 = LIFETIME_END
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #21 = LIFETIME_START
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #20 = BUNDLE
  { 2, &ARMDescs.OperandInfo[13] },  // Inst #19 = COPY
  { 2, &ARMDescs.OperandInfo[13] },  // Inst #18 = REG_SEQUENCE
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #17 = DBG_LABEL
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #16 = DBG_PHI
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #15 = DBG_INSTR_REF
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #14 = DBG_VALUE_LIST
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #13 = DBG_VALUE
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #12 = COPY_TO_REGCLASS
  { 4, &ARMDescs.OperandInfo[9] },  // Inst #11 = SUBREG_TO_REG
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #10 = IMPLICIT_DEF
  { 4, &ARMDescs.OperandInfo[5] },  // Inst #9 = INSERT_SUBREG
  { 3, &ARMDescs.OperandInfo[2] },  // Inst #8 = EXTRACT_SUBREG
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #7 = KILL
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #6 = ANNOTATION_LABEL
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #5 = GC_LABEL
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #4 = EH_LABEL
  { 1, &ARMDescs.OperandInfo[1] },  // Inst #3 = CFI_INSTRUCTION
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #2 = INLINEASM_BR
  { 0, &ARMDescs.OperandInfo[1] },  // Inst #1 = INLINEASM
  { 1, &ARMDescs.OperandInfo[0] },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
    /* 56 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
    /* 58 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
    /* 62 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 64 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 67 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 72 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 82 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 86 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 89 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 93 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 96 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
    /* 99 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
    /* 103 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
    /* 107 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
    /* 116 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
    /* 119 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
    /* 123 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
    /* 126 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 130 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
    /* 132 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
    /* 136 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
    /* 140 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 142 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 147 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 152 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 158 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 165 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 169 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 175 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 181 */ { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 182 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 186 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 192 */ { ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 193 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 195 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 196 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 199 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 202 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 206 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 208 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 213 */ { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 218 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 222 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 227 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 231 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 235 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 239 */ { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 243 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 248 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 255 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 260 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 265 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 270 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 276 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 283 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 284 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 288 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 291 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 293 */ { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 295 */ { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 297 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 303 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 306 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 309 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 314 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 319 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 328 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 335 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 338 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 345 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 352 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 355 */ { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 356 */ { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 358 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 364 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 371 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 376 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 382 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 383 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 388 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 393 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 394 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 399 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 401 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 406 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 411 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 417 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 420 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 422 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 425 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 429 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 431 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 434 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 438 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 441 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 444 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 450 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 455 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 460 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 465 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 470 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 476 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 480 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 485 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 491 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 497 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 500 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 504 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 507 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 510 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 513 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 514 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 517 */ { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 521 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 524 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 526 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 528 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 531 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 534 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 539 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 544 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 549 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 553 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 558 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 561 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 565 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 570 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 573 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 575 */ { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
    /* 579 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 585 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 592 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 600 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 608 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 611 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 613 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 618 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 623 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 627 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 631 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 635 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 641 */ { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 644 */ { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 650 */ { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 653 */ { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 659 */ { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 663 */ { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 670 */ { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 674 */ { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 681 */ { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 686 */ { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 694 */ { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 699 */ { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 707 */ { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 711 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 715 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 722 */ { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 725 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 728 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 735 */ { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 740 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 745 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 753 */ { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 757 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 761 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 769 */ { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 775 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 781 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 790 */ { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 795 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 800 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 809 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 817 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 823 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 827 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 832 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 838 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 841 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 844 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 847 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 851 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 855 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 859 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 863 */ { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 867 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 871 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 875 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 881 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 887 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 894 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 900 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 905 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 911 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 918 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(2) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 926 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 932 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 939 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 946 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 952 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 960 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 966 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 973 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 978 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 985 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 991 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 996 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1001 */ { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1006 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1012 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1019 */ { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1027 */ { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1033 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1040 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1045 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1048 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1052 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1056 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1060 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1067 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1074 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1079 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1087 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1094 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1101 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1107 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1116 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1124 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1132 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1138 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1144 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1149 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1156 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1162 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1170 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1178 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1186 */ { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1193 */ { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1200 */ { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1205 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1211 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1218 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1226 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1232 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1241 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1248 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1255 */ { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 1258 */ { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) },
    /* 1262 */ { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 1265 */ { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) },
    /* 1269 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1275 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1282 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1288 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1294 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1301 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1307 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1314 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1320 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1327 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1333 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1342 */ { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1349 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1354 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1362 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1369 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1375 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1381 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1388 */ { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1393 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1399 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1403 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1407 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1414 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1421 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1427 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1434 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1440 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1448 */ { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 1450 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1453 */ { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 1455 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) },
    /* 1458 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1464 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1470 */ { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
    /* 1477 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1484 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1487 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1490 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1496 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 1498 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 },
    /* 1501 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1506 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1512 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1518 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1527 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1535 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1542 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1548 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1553 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1558 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1563 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1570 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1577 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1583 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1591 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1597 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1604 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1609 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1615 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1620 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1628 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1634 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1640 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1646 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1651 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1656 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1661 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1665 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1669 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1673 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1677 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1682 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1687 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1692 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1697 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1702 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1707 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1712 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1718 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1724 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1728 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1732 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1737 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1743 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1749 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1754 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1760 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1766 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1769 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1772 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1775 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1777 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1779 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1781 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1783 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1788 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1792 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1796 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1801 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1806 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1810 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1814 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1818 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1823 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1829 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1835 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1841 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1844 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1848 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1851 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 1855 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1861 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1864 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1867 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1872 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 1875 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1881 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1888 */ { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1893 */ { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1899 */ { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1906 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1913 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1922 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1929 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1938 */ { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1943 */ { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1949 */ { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1956 */ { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1962 */ { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1970 */ { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1975 */ { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1981 */ { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1988 */ { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 1995 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2004 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2015 */ { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2022 */ { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2031 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2038 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2047 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2058 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2071 */ { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2078 */ { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2087 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2095 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(4) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2105 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2118 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(4) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2133 */ { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2137 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2142 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2147 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2151 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2156 */ { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2161 */ { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2167 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2174 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2181 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2188 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2195 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2202 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2209 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2214 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2218 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2222 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2227 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2233 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2237 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2241 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2247 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2251 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2255 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2259 */ { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2263 */ { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2267 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2273 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2279 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2285 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2291 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2297 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2303 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2308 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2313 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2318 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2323 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 2325 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2331 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2337 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2343 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2348 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2353 */ { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2357 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2363 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2369 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2375 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2383 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2389 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2397 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2402 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2407 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2413 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2420 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2426 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2433 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2438 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2443 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2450 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2456 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2463 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2470 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2479 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2485 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2493 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2500 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2508 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2518 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2524 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2532 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2539 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2548 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2557 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2568 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2576 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2586 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2592 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2598 */ { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2604 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2609 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2614 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2620 */ { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2626 */ { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2630 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2636 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2642 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2649 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2655 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2660 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2666 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2673 */ { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2679 */ { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2684 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2688 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 2693 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2699 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2703 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2707 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 2711 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 2716 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2720 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2724 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2729 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 2733 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2737 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2742 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2747 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2751 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2757 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2764 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2770 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2775 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2779 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2785 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2792 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2798 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2803 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2808 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2815 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2819 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2824 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2829 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2835 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 2840 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2846 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2850 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2855 */ { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2858 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2864 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2872 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2878 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2883 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2888 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2894 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2900 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2906 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2913 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2919 */ { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2925 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2929 */ { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2933 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2939 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2945 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2951 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2956 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2961 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2967 */ { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2972 */ { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2977 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2981 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 2984 */ { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
    /* 2987 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
    /* 2989 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 2993 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
    /* 2997 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 3002 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 3007 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 3011 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 3016 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 3021 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 3027 */ { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
    /* 3032 */ { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
  }, {
    /* 0 */
    /* 0 */ ARM_CPSR,
    /* 1 */ ARM_SP, ARM_SP,
    /* 3 */ ARM_SP, ARM_LR,
    /* 5 */ ARM_R7, ARM_LR, ARM_SP,
    /* 8 */ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15,
    /* 39 */ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR,
    /* 54 */ ARM_SP,
    /* 55 */ ARM_SP, ARM_R0, ARM_R12, ARM_LR, ARM_CPSR,
    /* 60 */ ARM_R4, ARM_R4, ARM_SP,
    /* 63 */ ARM_CPSR, ARM_CPSR,
    /* 65 */ ARM_LR,
    /* 66 */ ARM_PC,
    /* 67 */ ARM_FPSCR_NZCV, ARM_CPSR,
    /* 69 */ ARM_VPR,
    /* 70 */ ARM_FPSCR_NZCV,
    /* 71 */ ARM_FPSCR,
    /* 72 */ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_VPR, ARM_FPSCR, ARM_FPSCR_NZCV,
    /* 83 */ ARM_R12, ARM_LR, ARM_SP,
    /* 86 */ ARM_ITSTATE,
    /* 87 */ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15,
    /* 114 */ ARM_LR, ARM_SP, ARM_R12,
    /* 117 */ ARM_R11, ARM_LR, ARM_SP,
    /* 120 */ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R12, ARM_CPSR,
  }
};

#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES

#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER

#endif // GET_AVAILABLE_OPCODE_CHECKER