/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

  Xtensa_OP_GROUP_Operand = 0,
  Xtensa_OP_GROUP_BranchTarget = 1,
  Xtensa_OP_GROUP_Imm8_AsmOperand = 2,
  Xtensa_OP_GROUP_Select_4_AsmOperand = 3,
  Xtensa_OP_GROUP_Select_2_AsmOperand = 4,
  Xtensa_OP_GROUP_Select_8_AsmOperand = 5,
  Xtensa_OP_GROUP_Offset_16_16_AsmOperand = 6,
  Xtensa_OP_GROUP_Offset_256_8_AsmOperand = 7,
  Xtensa_OP_GROUP_Offset_256_16_AsmOperand = 8,
  Xtensa_OP_GROUP_Offset_256_4_AsmOperand = 9,
  Xtensa_OP_GROUP_Select_16_AsmOperand = 10,
  Xtensa_OP_GROUP_Offset_128_2_AsmOperand = 11,
  Xtensa_OP_GROUP_Offset_128_1_AsmOperand = 12,
  Xtensa_OP_GROUP_Offset_64_16_AsmOperand = 13,
  Xtensa_OP_GROUP_MemOperand = 14,
  Xtensa_OP_GROUP_Imm1n_15_AsmOperand = 15,
  Xtensa_OP_GROUP_Imm8_sh8_AsmOperand = 16,
  Xtensa_OP_GROUP_Imm1_16_AsmOperand = 17,
  Xtensa_OP_GROUP_ImmOperand_minus16_14_2 = 18,
  Xtensa_OP_GROUP_ImmOperand_minus32_28_4 = 19,
  Xtensa_OP_GROUP_ImmOperand_minus64_56_8 = 20,
  Xtensa_OP_GROUP_ImmOperand_0_56_8 = 21,
  Xtensa_OP_GROUP_ImmOperand_minus16_47_1 = 22,
  Xtensa_OP_GROUP_ImmOperand_0_3_1 = 23,
  Xtensa_OP_GROUP_Uimm4_AsmOperand = 24,
  Xtensa_OP_GROUP_Imm7_22_AsmOperand = 25,
  Xtensa_OP_GROUP_Uimm5_AsmOperand = 26,
  Xtensa_OP_GROUP_ImmOperand_0_63_1 = 27,
  Xtensa_OP_GROUP_B4const_AsmOperand = 28,
  Xtensa_OP_GROUP_B4constu_AsmOperand = 29,
  Xtensa_OP_GROUP_CallOperand = 30,
  Xtensa_OP_GROUP_Select_256_AsmOperand = 31,
  Xtensa_OP_GROUP_Entry_Imm12_AsmOperand = 32,
  Xtensa_OP_GROUP_JumpTarget = 33,
  Xtensa_OP_GROUP_Imm64n_4n_AsmOperand = 34,
  Xtensa_OP_GROUP_L32RTarget = 35,
  Xtensa_OP_GROUP_LoopTarget = 36,
  Xtensa_OP_GROUP_Offset8m32_AsmOperand = 37,
  Xtensa_OP_GROUP_Imm12m_AsmOperand = 38,
  Xtensa_OP_GROUP_Imm32n_95_AsmOperand = 39,
  Xtensa_OP_GROUP_Imm8n_7_AsmOperand = 40,
  Xtensa_OP_GROUP_Shimm0_31_AsmOperand = 41,
  Xtensa_OP_GROUP_Imm12_AsmOperand = 42,
  Xtensa_OP_GROUP_Shimm1_31_AsmOperand = 43,