#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

enum {
  Sparc_NoRegister,
  Sparc_CANRESTORE = 1,
  Sparc_CANSAVE = 2,
  Sparc_CLEANWIN = 3,
  Sparc_CPQ = 4,
  Sparc_CPSR = 5,
  Sparc_CWP = 6,
  Sparc_FQ = 7,
  Sparc_FSR = 8,
  Sparc_GL = 9,
  Sparc_ICC = 10,
  Sparc_OTHERWIN = 11,
  Sparc_PIL = 12,
  Sparc_PSR = 13,
  Sparc_PSTATE = 14,
  Sparc_TBA = 15,
  Sparc_TBR = 16,
  Sparc_TICK = 17,
  Sparc_TL = 18,
  Sparc_TNPC = 19,
  Sparc_TPC = 20,
  Sparc_TSTATE = 21,
  Sparc_TT = 22,
  Sparc_VER = 23,
  Sparc_WIM = 24,
  Sparc_WSTATE = 25,
  Sparc_Y = 26,
  Sparc_ASR1 = 27,
  Sparc_ASR2 = 28,
  Sparc_ASR3 = 29,
  Sparc_ASR4 = 30,
  Sparc_ASR5 = 31,
  Sparc_ASR6 = 32,
  Sparc_ASR7 = 33,
  Sparc_ASR8 = 34,
  Sparc_ASR9 = 35,
  Sparc_ASR10 = 36,
  Sparc_ASR11 = 37,
  Sparc_ASR12 = 38,
  Sparc_ASR13 = 39,
  Sparc_ASR14 = 40,
  Sparc_ASR15 = 41,
  Sparc_ASR16 = 42,
  Sparc_ASR17 = 43,
  Sparc_ASR18 = 44,
  Sparc_ASR19 = 45,
  Sparc_ASR20 = 46,
  Sparc_ASR21 = 47,
  Sparc_ASR22 = 48,
  Sparc_ASR23 = 49,
  Sparc_ASR24 = 50,
  Sparc_ASR25 = 51,
  Sparc_ASR26 = 52,
  Sparc_ASR27 = 53,
  Sparc_ASR28 = 54,
  Sparc_ASR29 = 55,
  Sparc_ASR30 = 56,
  Sparc_ASR31 = 57,
  Sparc_C0 = 58,
  Sparc_C1 = 59,
  Sparc_C2 = 60,
  Sparc_C3 = 61,
  Sparc_C4 = 62,
  Sparc_C5 = 63,
  Sparc_C6 = 64,
  Sparc_C7 = 65,
  Sparc_C8 = 66,
  Sparc_C9 = 67,
  Sparc_C10 = 68,
  Sparc_C11 = 69,
  Sparc_C12 = 70,
  Sparc_C13 = 71,
  Sparc_C14 = 72,
  Sparc_C15 = 73,
  Sparc_C16 = 74,
  Sparc_C17 = 75,
  Sparc_C18 = 76,
  Sparc_C19 = 77,
  Sparc_C20 = 78,
  Sparc_C21 = 79,
  Sparc_C22 = 80,
  Sparc_C23 = 81,
  Sparc_C24 = 82,
  Sparc_C25 = 83,
  Sparc_C26 = 84,
  Sparc_C27 = 85,
  Sparc_C28 = 86,
  Sparc_C29 = 87,
  Sparc_C30 = 88,
  Sparc_C31 = 89,
  Sparc_D0 = 90,
  Sparc_D1 = 91,
  Sparc_D2 = 92,
  Sparc_D3 = 93,
  Sparc_D4 = 94,
  Sparc_D5 = 95,
  Sparc_D6 = 96,
  Sparc_D7 = 97,
  Sparc_D8 = 98,
  Sparc_D9 = 99,
  Sparc_D10 = 100,
  Sparc_D11 = 101,
  Sparc_D12 = 102,
  Sparc_D13 = 103,
  Sparc_D14 = 104,
  Sparc_D15 = 105,
  Sparc_D16 = 106,
  Sparc_D17 = 107,
  Sparc_D18 = 108,
  Sparc_D19 = 109,
  Sparc_D20 = 110,
  Sparc_D21 = 111,
  Sparc_D22 = 112,
  Sparc_D23 = 113,
  Sparc_D24 = 114,
  Sparc_D25 = 115,
  Sparc_D26 = 116,
  Sparc_D27 = 117,
  Sparc_D28 = 118,
  Sparc_D29 = 119,
  Sparc_D30 = 120,
  Sparc_D31 = 121,
  Sparc_F0 = 122,
  Sparc_F1 = 123,
  Sparc_F2 = 124,
  Sparc_F3 = 125,
  Sparc_F4 = 126,
  Sparc_F5 = 127,
  Sparc_F6 = 128,
  Sparc_F7 = 129,
  Sparc_F8 = 130,
  Sparc_F9 = 131,
  Sparc_F10 = 132,
  Sparc_F11 = 133,
  Sparc_F12 = 134,
  Sparc_F13 = 135,
  Sparc_F14 = 136,
  Sparc_F15 = 137,
  Sparc_F16 = 138,
  Sparc_F17 = 139,
  Sparc_F18 = 140,
  Sparc_F19 = 141,
  Sparc_F20 = 142,
  Sparc_F21 = 143,
  Sparc_F22 = 144,
  Sparc_F23 = 145,
  Sparc_F24 = 146,
  Sparc_F25 = 147,
  Sparc_F26 = 148,
  Sparc_F27 = 149,
  Sparc_F28 = 150,
  Sparc_F29 = 151,
  Sparc_F30 = 152,
  Sparc_F31 = 153,
  Sparc_FCC0 = 154,
  Sparc_FCC1 = 155,
  Sparc_FCC2 = 156,
  Sparc_FCC3 = 157,
  Sparc_G0 = 158,
  Sparc_G1 = 159,
  Sparc_G2 = 160,
  Sparc_G3 = 161,
  Sparc_G4 = 162,
  Sparc_G5 = 163,
  Sparc_G6 = 164,
  Sparc_G7 = 165,
  Sparc_I0 = 166,
  Sparc_I1 = 167,
  Sparc_I2 = 168,
  Sparc_I3 = 169,
  Sparc_I4 = 170,
  Sparc_I5 = 171,
  Sparc_I6 = 172,
  Sparc_I7 = 173,
  Sparc_L0 = 174,
  Sparc_L1 = 175,
  Sparc_L2 = 176,
  Sparc_L3 = 177,
  Sparc_L4 = 178,
  Sparc_L5 = 179,
  Sparc_L6 = 180,
  Sparc_L7 = 181,
  Sparc_O0 = 182,
  Sparc_O1 = 183,
  Sparc_O2 = 184,
  Sparc_O3 = 185,
  Sparc_O4 = 186,
  Sparc_O5 = 187,
  Sparc_O6 = 188,
  Sparc_O7 = 189,
  Sparc_Q0 = 190,
  Sparc_Q1 = 191,
  Sparc_Q2 = 192,
  Sparc_Q3 = 193,
  Sparc_Q4 = 194,
  Sparc_Q5 = 195,
  Sparc_Q6 = 196,
  Sparc_Q7 = 197,
  Sparc_Q8 = 198,
  Sparc_Q9 = 199,
  Sparc_Q10 = 200,
  Sparc_Q11 = 201,
  Sparc_Q12 = 202,
  Sparc_Q13 = 203,
  Sparc_Q14 = 204,
  Sparc_Q15 = 205,
  Sparc_C0_C1 = 206,
  Sparc_C2_C3 = 207,
  Sparc_C4_C5 = 208,
  Sparc_C6_C7 = 209,
  Sparc_C8_C9 = 210,
  Sparc_C10_C11 = 211,
  Sparc_C12_C13 = 212,
  Sparc_C14_C15 = 213,
  Sparc_C16_C17 = 214,
  Sparc_C18_C19 = 215,
  Sparc_C20_C21 = 216,
  Sparc_C22_C23 = 217,
  Sparc_C24_C25 = 218,
  Sparc_C26_C27 = 219,
  Sparc_C28_C29 = 220,
  Sparc_C30_C31 = 221,
  Sparc_G0_G1 = 222,
  Sparc_G2_G3 = 223,
  Sparc_G4_G5 = 224,
  Sparc_G6_G7 = 225,
  Sparc_I0_I1 = 226,
  Sparc_I2_I3 = 227,
  Sparc_I4_I5 = 228,
  Sparc_I6_I7 = 229,
  Sparc_L0_L1 = 230,
  Sparc_L2_L3 = 231,
  Sparc_L4_L5 = 232,
  Sparc_L6_L7 = 233,
  Sparc_O0_O1 = 234,
  Sparc_O2_O3 = 235,
  Sparc_O4_O5 = 236,
  Sparc_O6_O7 = 237,
  NUM_TARGET_REGS // 238
};

// Register classes

enum {
  Sparc_FCCRegsRegClassID = 0,
  Sparc_ASRRegsRegClassID = 1,
  Sparc_CoprocRegsRegClassID = 2,
  Sparc_FPRegsRegClassID = 3,
  Sparc_IntRegsRegClassID = 4,
  Sparc_GPRIncomingArgRegClassID = 5,
  Sparc_GPROutgoingArgRegClassID = 6,
  Sparc_DFPRegsRegClassID = 7,
  Sparc_I64RegsRegClassID = 8,
  Sparc_PRRegsRegClassID = 9,
  Sparc_CoprocPairRegClassID = 10,
  Sparc_IntPairRegClassID = 11,
  Sparc_LowDFPRegsRegClassID = 12,
  Sparc_I64Regs_and_GPRIncomingArgRegClassID = 13,
  Sparc_I64Regs_and_GPROutgoingArgRegClassID = 14,
  Sparc_IntPair_with_sub_even_in_GPRIncomingArgRegClassID = 15,
  Sparc_IntPair_with_sub_even_in_GPROutgoingArgRegClassID = 16,
  Sparc_PRRegs_and_ASRRegsRegClassID = 17,
  Sparc_QFPRegsRegClassID = 18,
  Sparc_LowQFPRegsRegClassID = 19,

};

// Register alternate name indices

enum {
  Sparc_NoRegAltName,	// 0
  Sparc_RegNamesStateReg,	// 1
  NUM_TARGET_REG_ALT_NAMES = 2
};

// Subregister indices

enum {
  Sparc_NoSubRegister,
  Sparc_sub_even,	// 1
  Sparc_sub_even64,	// 2
  Sparc_sub_odd,	// 3
  Sparc_sub_odd64,	// 4
  Sparc_sub_odd64_then_sub_even,	// 5
  Sparc_sub_odd64_then_sub_odd,	// 6
  Sparc_NUM_TARGET_SUBREGS
};
#endif // GET_REGINFO_ENUM

/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

static const MCPhysReg SparcRegDiffLists[] = {
  /* 0 */ -148, 1, 0,
  /* 3 */ -147, 1, 0,
  /* 6 */ -146, 1, 0,
  /* 9 */ -145, 1, 0,
  /* 12 */ -144, 1, 0,
  /* 15 */ -143, 1, 0,
  /* 18 */ -142, 1, 0,
  /* 21 */ -141, 1, 0,
  /* 24 */ -140, 1, 0,
  /* 27 */ -139, 1, 0,
  /* 30 */ -138, 1, 0,
  /* 33 */ -137, 1, 0,
  /* 36 */ -136, 1, 0,
  /* 39 */ -135, 1, 0,
  /* 42 */ -134, 1, 0,
  /* 45 */ -133, 1, 0,
  /* 48 */ -92, 1, 0,
  /* 51 */ -91, 1, 0,
  /* 54 */ -90, 1, 0,
  /* 57 */ -89, 1, 0,
  /* 60 */ -88, 1, 0,
  /* 63 */ -87, 1, 0,
  /* 66 */ -86, 1, 0,
  /* 69 */ -85, 1, 0,
  /* 72 */ -64, 1, 0,
  /* 75 */ -63, 1, 0,
  /* 78 */ -62, 1, 0,
  /* 81 */ -61, 1, 0,
  /* 84 */ -60, 1, 0,
  /* 87 */ -59, 1, 0,
  /* 90 */ -58, 1, 0,
  /* 93 */ -57, 1, 0,
  /* 96 */ -56, 1, 0,
  /* 99 */ -55, 1, 0,
  /* 102 */ -54, 1, 0,
  /* 105 */ -53, 1, 0,
  /* 108 */ -52, 1, 0,
  /* 111 */ -51, 1, 0,
  /* 114 */ -50, 1, 0,
  /* 117 */ -49, 1, 0,
  /* 120 */ 1, 1, 1, 0,
  /* 124 */ 32, 1, 0,
  /* 127 */ -100, 32, 1, -32, 33, 1, 0,
  /* 134 */ 34, 1, 0,
  /* 137 */ -99, 34, 1, -34, 35, 1, 0,
  /* 144 */ 36, 1, 0,
  /* 147 */ -98, 36, 1, -36, 37, 1, 0,
  /* 154 */ 38, 1, 0,
  /* 157 */ -97, 38, 1, -38, 39, 1, 0,
  /* 164 */ 40, 1, 0,
  /* 167 */ -96, 40, 1, -40, 41, 1, 0,
  /* 174 */ 42, 1, 0,
  /* 177 */ -95, 42, 1, -42, 43, 1, 0,
  /* 184 */ 44, 1, 0,
  /* 187 */ -94, 44, 1, -44, 45, 1, 0,
  /* 194 */ 46, 1, 0,
  /* 197 */ -93, 46, 1, -46, 47, 1, 0,
  /* 204 */ 48, 0,
  /* 206 */ 49, 0,
  /* 208 */ 50, 0,
  /* 210 */ 51, 0,
  /* 212 */ 52, 0,
  /* 214 */ 53, 0,
  /* 216 */ 54, 0,
  /* 218 */ 55, 0,
  /* 220 */ 56, 0,
  /* 222 */ 57, 0,
  /* 224 */ 58, 0,
  /* 226 */ 59, 0,
  /* 228 */ 60, 0,
  /* 230 */ 61, 0,
  /* 232 */ 62, 0,
  /* 234 */ 63, 0,
  /* 236 */ 64, 0,
  /* 238 */ 84, 0,
  /* 240 */ 85, 0,
  /* 242 */ 86, 0,
  /* 244 */ 87, 0,
  /* 246 */ 88, 0,
  /* 248 */ 89, 0,
  /* 250 */ 90, 0,
  /* 252 */ 91, 0,
  /* 254 */ -48, 92, 0,
  /* 257 */ -47, 92, 0,
  /* 260 */ -47, 93, 0,
  /* 263 */ -46, 93, 0,
  /* 266 */ -45, 93, 0,
  /* 269 */ -45, 94, 0,
  /* 272 */ -44, 94, 0,
  /* 275 */ -43, 94, 0,
  /* 278 */ -43, 95, 0,
  /* 281 */ -42, 95, 0,
  /* 284 */ -41, 95, 0,
  /* 287 */ -41, 96, 0,
  /* 290 */ -40, 96, 0,
  /* 293 */ -39, 96, 0,
  /* 296 */ -39, 97, 0,
  /* 299 */ -38, 97, 0,
  /* 302 */ -37, 97, 0,
  /* 305 */ -37, 98, 0,
  /* 308 */ -36, 98, 0,
  /* 311 */ -35, 98, 0,
  /* 314 */ -35, 99, 0,
  /* 317 */ -34, 99, 0,
  /* 320 */ -33, 99, 0,
  /* 323 */ -33, 100, 0,
  /* 326 */ -32, 100, 0,
  /* 329 */ 132, 0,
  /* 331 */ 133, 0,
  /* 333 */ 134, 0,
  /* 335 */ 135, 0,
  /* 337 */ 136, 0,
  /* 339 */ 137, 0,
  /* 341 */ 138, 0,
  /* 343 */ 139, 0,
  /* 345 */ 140, 0,
  /* 347 */ 141, 0,
  /* 349 */ 142, 0,
  /* 351 */ 143, 0,
  /* 353 */ 144, 0,
  /* 355 */ 145, 0,
  /* 357 */ 146, 0,
  /* 359 */ 147, 0,
  /* 361 */ 148, 0,
};

static const uint16_t SparcSubRegIdxLists[] = {
  /* 0 */ 1, 3, 0,
  /* 3 */ 2, 4, 0,
  /* 6 */ 2, 1, 3, 4, 5, 6, 0,
};

static const MCRegisterDesc SparcRegDesc[] = { // Descriptors
  { 3, 0, 0, 0, 0, 0 },
  { 819, 2, 2, 2, 8192, 11 },
  { 851, 2, 2, 2, 8193, 11 },
  { 878, 2, 2, 2, 8194, 11 },
  { 903, 2, 2, 2, 8195, 11 },
  { 919, 2, 2, 2, 8196, 11 },
  { 896, 2, 2, 2, 8197, 11 },
  { 900, 2, 2, 2, 8198, 11 },
  { 915, 2, 2, 2, 8199, 11 },
  { 864, 2, 2, 2, 8200, 11 },
  { 806, 2, 2, 2, 8201, 11 },
  { 887, 2, 2, 2, 8202, 11 },
  { 867, 2, 2, 2, 8203, 11 },
  { 920, 2, 2, 2, 8204, 11 },
  { 830, 2, 2, 2, 8205, 11 },
  { 802, 2, 2, 2, 8206, 11 },
  { 907, 2, 2, 2, 8207, 11 },
  { 859, 2, 2, 2, 8208, 11 },
  { 871, 2, 2, 2, 8209, 11 },
  { 810, 2, 2, 2, 8210, 11 },
  { 815, 2, 2, 2, 8211, 11 },
  { 837, 2, 2, 2, 8212, 11 },
  { 924, 2, 2, 2, 8213, 11 },
  { 911, 2, 2, 2, 8214, 11 },
  { 874, 2, 2, 2, 8215, 11 },
  { 844, 2, 2, 2, 8216, 11 },
  { 927, 2, 2, 2, 8217, 11 },
  { 198, 2, 2, 2, 8218, 11 },
  { 269, 2, 2, 2, 8219, 11 },
  { 366, 2, 2, 2, 8220, 11 },
  { 435, 2, 2, 2, 8221, 11 },
  { 527, 2, 2, 2, 8222, 11 },
  { 592, 2, 2, 2, 8223, 11 },
  { 680, 2, 2, 2, 8224, 11 },
  { 733, 2, 2, 2, 8225, 11 },
  { 797, 2, 2, 2, 8226, 11 },
  { 16, 2, 2, 2, 8227, 11 },
  { 104, 2, 2, 2, 8228, 11 },
  { 219, 2, 2, 2, 8229, 11 },
  { 294, 2, 2, 2, 8230, 11 },
  { 387, 2, 2, 2, 8231, 11 },
  { 460, 2, 2, 2, 8232, 11 },
  { 544, 2, 2, 2, 8233, 11 },
  { 613, 2, 2, 2, 8234, 11 },
  { 697, 2, 2, 2, 8235, 11 },
  { 754, 2, 2, 2, 8236, 11 },
  { 34, 2, 2, 2, 8237, 11 },
  { 126, 2, 2, 2, 8238, 11 },
  { 237, 2, 2, 2, 8239, 11 },
  { 316, 2, 2, 2, 8240, 11 },
  { 405, 2, 2, 2, 8241, 11 },
  { 482, 2, 2, 2, 8242, 11 },
  { 562, 2, 2, 2, 8243, 11 },
  { 635, 2, 2, 2, 8244, 11 },
  { 715, 2, 2, 2, 8245, 11 },
  { 776, 2, 2, 2, 8246, 11 },
  { 52, 2, 2, 2, 8247, 11 },
  { 148, 2, 2, 2, 8248, 11 },
  { 60, 2, 361, 2, 8249, 11 },
  { 156, 2, 359, 2, 8250, 11 },
  { 245, 2, 359, 2, 8251, 11 },
  { 324, 2, 357, 2, 8252, 11 },
  { 411, 2, 357, 2, 8253, 11 },
  { 491, 2, 355, 2, 8254, 11 },
  { 568, 2, 355, 2, 8255, 11 },
  { 644, 2, 353, 2, 8256, 11 },
  { 721, 2, 353, 2, 8257, 11 },
  { 785, 2, 351, 2, 8258, 11 },
  { 0, 2, 351, 2, 8259, 11 },
  { 88, 2, 349, 2, 8260, 11 },
  { 203, 2, 349, 2, 8261, 11 },
  { 278, 2, 347, 2, 8262, 11 },
  { 371, 2, 347, 2, 8263, 11 },
  { 444, 2, 345, 2, 8264, 11 },
  { 532, 2, 345, 2, 8265, 11 },
  { 601, 2, 343, 2, 8266, 11 },
  { 685, 2, 343, 2, 8267, 11 },
  { 742, 2, 341, 2, 8268, 11 },
  { 22, 2, 341, 2, 8269, 11 },
  { 114, 2, 339, 2, 8270, 11 },
  { 225, 2, 339, 2, 8271, 11 },
  { 304, 2, 337, 2, 8272, 11 },
  { 393, 2, 337, 2, 8273, 11 },
  { 470, 2, 335, 2, 8274, 11 },
  { 550, 2, 335, 2, 8275, 11 },
  { 623, 2, 333, 2, 8276, 11 },
  { 703, 2, 333, 2, 8277, 11 },
  { 764, 2, 331, 2, 8278, 11 },
  { 40, 2, 331, 2, 8279, 11 },
  { 136, 2, 329, 2, 8280, 11 },
  { 63, 124, 324, 0, 4185, 0 },
  { 165, 131, 315, 0, 4187, 0 },
  { 248, 134, 315, 0, 4189, 0 },
  { 333, 141, 306, 0, 4191, 0 },
  { 414, 144, 306, 0, 4193, 0 },
  { 494, 151, 297, 0, 4195, 0 },
  { 571, 154, 297, 0, 4197, 0 },
  { 647, 161, 288, 0, 4199, 0 },
  { 724, 164, 288, 0, 4201, 0 },
  { 788, 171, 279, 0, 4203, 0 },
  { 4, 174, 279, 0, 4205, 0 },
  { 92, 181, 270, 0, 4207, 0 },
  { 207, 184, 270, 0, 4209, 0 },
  { 282, 191, 261, 0, 4211, 0 },
  { 375, 194, 261, 0, 4213, 0 },
  { 448, 201, 255, 0, 4215, 0 },
  { 536, 2, 255, 2, 8313, 11 },
  { 605, 2, 252, 2, 8314, 11 },
  { 689, 2, 252, 2, 8315, 11 },
  { 746, 2, 250, 2, 8316, 11 },
  { 26, 2, 250, 2, 8317, 11 },
  { 118, 2, 248, 2, 8318, 11 },
  { 229, 2, 248, 2, 8319, 11 },
  { 308, 2, 246, 2, 8320, 11 },
  { 397, 2, 246, 2, 8321, 11 },
  { 474, 2, 244, 2, 8322, 11 },
  { 554, 2, 244, 2, 8323, 11 },
  { 627, 2, 242, 2, 8324, 11 },
  { 707, 2, 242, 2, 8325, 11 },
  { 768, 2, 240, 2, 8326, 11 },
  { 44, 2, 240, 2, 8327, 11 },
  { 140, 2, 238, 2, 8328, 11 },
  { 66, 2, 326, 2, 8281, 11 },
  { 168, 2, 323, 2, 8282, 11 },
  { 251, 2, 320, 2, 8283, 11 },
  { 336, 2, 317, 2, 8284, 11 },
  { 417, 2, 317, 2, 8285, 11 },
  { 497, 2, 314, 2, 8286, 11 },
  { 574, 2, 311, 2, 8287, 11 },
  { 650, 2, 308, 2, 8288, 11 },
  { 727, 2, 308, 2, 8289, 11 },
  { 791, 2, 305, 2, 8290, 11 },
  { 8, 2, 302, 2, 8291, 11 },
  { 96, 2, 299, 2, 8292, 11 },
  { 211, 2, 299, 2, 8293, 11 },
  { 286, 2, 296, 2, 8294, 11 },
  { 379, 2, 293, 2, 8295, 11 },
  { 452, 2, 290, 2, 8296, 11 },
  { 540, 2, 290, 2, 8297, 11 },
  { 609, 2, 287, 2, 8298, 11 },
  { 693, 2, 284, 2, 8299, 11 },
  { 750, 2, 281, 2, 8300, 11 },
  { 30, 2, 281, 2, 8301, 11 },
  { 122, 2, 278, 2, 8302, 11 },
  { 233, 2, 275, 2, 8303, 11 },
  { 312, 2, 272, 2, 8304, 11 },
  { 401, 2, 272, 2, 8305, 11 },
  { 478, 2, 269, 2, 8306, 11 },
  { 558, 2, 266, 2, 8307, 11 },
  { 631, 2, 263, 2, 8308, 11 },
  { 711, 2, 263, 2, 8309, 11 },
  { 772, 2, 260, 2, 8310, 11 },
  { 48, 2, 257, 2, 8311, 11 },
  { 144, 2, 254, 2, 8312, 11 },
  { 58, 2, 2, 2, 8329, 11 },
  { 154, 2, 2, 2, 8330, 11 },
  { 243, 2, 2, 2, 8331, 11 },
  { 322, 2, 2, 2, 8332, 11 },
  { 69, 2, 236, 2, 8333, 11 },
  { 174, 2, 234, 2, 8334, 11 },
  { 254, 2, 234, 2, 8335, 11 },
  { 342, 2, 232, 2, 8336, 11 },
  { 420, 2, 232, 2, 8337, 11 },
  { 503, 2, 230, 2, 8338, 11 },
  { 577, 2, 230, 2, 8339, 11 },
  { 656, 2, 228, 2, 8340, 11 },
  { 72, 2, 228, 2, 8341, 11 },
  { 180, 2, 226, 2, 8342, 11 },
  { 257, 2, 226, 2, 8343, 11 },
  { 348, 2, 224, 2, 8344, 11 },
  { 423, 2, 224, 2, 8345, 11 },
  { 509, 2, 222, 2, 8346, 11 },
  { 580, 2, 222, 2, 8347, 11 },
  { 662, 2, 220, 2, 8348, 11 },
  { 75, 2, 220, 2, 8349, 11 },
  { 186, 2, 218, 2, 8350, 11 },
  { 260, 2, 218, 2, 8351, 11 },
  { 354, 2, 216, 2, 8352, 11 },
  { 426, 2, 216, 2, 8353, 11 },
  { 515, 2, 214, 2, 8354, 11 },
  { 583, 2, 214, 2, 8355, 11 },
  { 668, 2, 212, 2, 8356, 11 },
  { 78, 2, 212, 2, 8357, 11 },
  { 192, 2, 210, 2, 8358, 11 },
  { 263, 2, 210, 2, 8359, 11 },
  { 360, 2, 208, 2, 8360, 11 },
  { 429, 2, 208, 2, 8361, 11 },
  { 521, 2, 206, 2, 8362, 11 },
  { 586, 2, 206, 2, 8363, 11 },
  { 674, 2, 204, 2, 8364, 11 },
  { 81, 127, 2, 6, 491609, 3 },
  { 195, 137, 2, 6, 491613, 3 },
  { 266, 147, 2, 6, 491617, 3 },
  { 363, 157, 2, 6, 491621, 3 },
  { 432, 167, 2, 6, 491625, 3 },
  { 524, 177, 2, 6, 491629, 3 },
  { 589, 187, 2, 6, 491633, 3 },
  { 677, 197, 2, 6, 491637, 3 },
  { 730, 48, 2, 3, 4217, 8 },
  { 794, 51, 2, 3, 4219, 8 },
  { 12, 54, 2, 3, 4221, 8 },
  { 100, 57, 2, 3, 4223, 8 },
  { 215, 60, 2, 3, 4225, 8 },
  { 290, 63, 2, 3, 4227, 8 },
  { 383, 66, 2, 3, 4229, 8 },
  { 456, 69, 2, 3, 4231, 8 },
  { 159, 0, 2, 0, 4153, 0 },
  { 327, 3, 2, 0, 4155, 0 },
  { 488, 6, 2, 0, 4157, 0 },
  { 641, 9, 2, 0, 4159, 0 },
  { 782, 12, 2, 0, 4161, 0 },
  { 84, 15, 2, 0, 4163, 0 },
  { 274, 18, 2, 0, 4165, 0 },
  { 440, 21, 2, 0, 4167, 0 },
  { 597, 24, 2, 0, 4169, 0 },
  { 738, 27, 2, 0, 4171, 0 },
  { 110, 30, 2, 0, 4173, 0 },
  { 300, 33, 2, 0, 4175, 0 },
  { 466, 36, 2, 0, 4177, 0 },
  { 619, 39, 2, 0, 4179, 0 },
  { 760, 42, 2, 0, 4181, 0 },
  { 132, 45, 2, 0, 4183, 0 },
  { 171, 72, 2, 0, 4237, 0 },
  { 339, 75, 2, 0, 4239, 0 },
  { 500, 78, 2, 0, 4241, 0 },
  { 653, 81, 2, 0, 4243, 0 },
  { 177, 84, 2, 0, 4245, 0 },
  { 345, 87, 2, 0, 4247, 0 },
  { 506, 90, 2, 0, 4249, 0 },
  { 659, 93, 2, 0, 4251, 0 },
  { 183, 96, 2, 0, 4253, 0 },
  { 351, 99, 2, 0, 4255, 0 },
  { 512, 102, 2, 0, 4257, 0 },
  { 665, 105, 2, 0, 4259, 0 },
  { 189, 108, 2, 0, 4261, 0 },
  { 357, 111, 2, 0, 4263, 0 },
  { 518, 114, 2, 0, 4265, 0 },
  { 671, 117, 2, 0, 4267, 0 },
};

  // FCCRegs Register Class...
  static const MCPhysReg FCCRegs[] = {
    Sparc_FCC0, Sparc_FCC1, Sparc_FCC2, Sparc_FCC3, 
  };

  // FCCRegs Bit set.
  static const uint8_t FCCRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // ASRRegs Register Class...
  static const MCPhysReg ASRRegs[] = {
    Sparc_Y, Sparc_TICK, Sparc_ASR1, Sparc_ASR2, Sparc_ASR3, Sparc_ASR4, Sparc_ASR5, Sparc_ASR6, Sparc_ASR7, Sparc_ASR8, Sparc_ASR9, Sparc_ASR10, Sparc_ASR11, Sparc_ASR12, Sparc_ASR13, Sparc_ASR14, Sparc_ASR15, Sparc_ASR16, Sparc_ASR17, Sparc_ASR18, Sparc_ASR19, Sparc_ASR20, Sparc_ASR21, Sparc_ASR22, Sparc_ASR23, Sparc_ASR24, Sparc_ASR25, Sparc_ASR26, Sparc_ASR27, Sparc_ASR28, Sparc_ASR29, Sparc_ASR30, Sparc_ASR31, 
  };

  // ASRRegs Bit set.
  static const uint8_t ASRRegsBits[] = {
    0x00, 0x00, 0x02, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // CoprocRegs Register Class...
  static const MCPhysReg CoprocRegs[] = {
    Sparc_C0, Sparc_C1, Sparc_C2, Sparc_C3, Sparc_C4, Sparc_C5, Sparc_C6, Sparc_C7, Sparc_C8, Sparc_C9, Sparc_C10, Sparc_C11, Sparc_C12, Sparc_C13, Sparc_C14, Sparc_C15, Sparc_C16, Sparc_C17, Sparc_C18, Sparc_C19, Sparc_C20, Sparc_C21, Sparc_C22, Sparc_C23, Sparc_C24, Sparc_C25, Sparc_C26, Sparc_C27, Sparc_C28, Sparc_C29, Sparc_C30, Sparc_C31, 
  };

  // CoprocRegs Bit set.
  static const uint8_t CoprocRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // FPRegs Register Class...
  static const MCPhysReg FPRegs[] = {
    Sparc_F0, Sparc_F1, Sparc_F2, Sparc_F3, Sparc_F4, Sparc_F5, Sparc_F6, Sparc_F7, Sparc_F8, Sparc_F9, Sparc_F10, Sparc_F11, Sparc_F12, Sparc_F13, Sparc_F14, Sparc_F15, Sparc_F16, Sparc_F17, Sparc_F18, Sparc_F19, Sparc_F20, Sparc_F21, Sparc_F22, Sparc_F23, Sparc_F24, Sparc_F25, Sparc_F26, Sparc_F27, Sparc_F28, Sparc_F29, Sparc_F30, Sparc_F31, 
  };

  // FPRegs Bit set.
  static const uint8_t FPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // IntRegs Register Class...
  static const MCPhysReg IntRegs[] = {
    Sparc_I0, Sparc_I1, Sparc_I2, Sparc_I3, Sparc_I4, Sparc_I5, Sparc_I6, Sparc_I7, Sparc_G0, Sparc_G1, Sparc_G2, Sparc_G3, Sparc_G4, Sparc_G5, Sparc_G6, Sparc_G7, Sparc_L0, Sparc_L1, Sparc_L2, Sparc_L3, Sparc_L4, Sparc_L5, Sparc_L6, Sparc_L7, Sparc_O0, Sparc_O1, Sparc_O2, Sparc_O3, Sparc_O4, Sparc_O5, Sparc_O6, Sparc_O7, 
  };

  // IntRegs Bit set.
  static const uint8_t IntRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // GPRIncomingArg Register Class...
  static const MCPhysReg GPRIncomingArg[] = {
    Sparc_I0, Sparc_I1, Sparc_I2, Sparc_I3, Sparc_I4, Sparc_I5, 
  };

  // GPRIncomingArg Bit set.
  static const uint8_t GPRIncomingArgBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // GPROutgoingArg Register Class...
  static const MCPhysReg GPROutgoingArg[] = {
    Sparc_O0, Sparc_O1, Sparc_O2, Sparc_O3, Sparc_O4, Sparc_O5, 
  };

  // GPROutgoingArg Bit set.
  static const uint8_t GPROutgoingArgBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // DFPRegs Register Class...
  static const MCPhysReg DFPRegs[] = {
    Sparc_D0, Sparc_D1, Sparc_D2, Sparc_D3, Sparc_D4, Sparc_D5, Sparc_D6, Sparc_D7, Sparc_D8, Sparc_D9, Sparc_D10, Sparc_D11, Sparc_D12, Sparc_D13, Sparc_D14, Sparc_D15, Sparc_D16, Sparc_D17, Sparc_D18, Sparc_D19, Sparc_D20, Sparc_D21, Sparc_D22, Sparc_D23, Sparc_D24, Sparc_D25, Sparc_D26, Sparc_D27, Sparc_D28, Sparc_D29, Sparc_D30, Sparc_D31, 
  };

  // DFPRegs Bit set.
  static const uint8_t DFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // I64Regs Register Class...
  static const MCPhysReg I64Regs[] = {
    Sparc_I0, Sparc_I1, Sparc_I2, Sparc_I3, Sparc_I4, Sparc_I5, Sparc_I6, Sparc_I7, Sparc_G0, Sparc_G1, Sparc_G2, Sparc_G3, Sparc_G4, Sparc_G5, Sparc_G6, Sparc_G7, Sparc_L0, Sparc_L1, Sparc_L2, Sparc_L3, Sparc_L4, Sparc_L5, Sparc_L6, Sparc_L7, Sparc_O0, Sparc_O1, Sparc_O2, Sparc_O3, Sparc_O4, Sparc_O5, Sparc_O6, Sparc_O7, 
  };

  // I64Regs Bit set.
  static const uint8_t I64RegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // PRRegs Register Class...
  static const MCPhysReg PRRegs[] = {
    Sparc_TPC, Sparc_TNPC, Sparc_TSTATE, Sparc_TT, Sparc_TICK, Sparc_TBA, Sparc_PSTATE, Sparc_TL, Sparc_PIL, Sparc_CWP, Sparc_CANSAVE, Sparc_CANRESTORE, Sparc_CLEANWIN, Sparc_OTHERWIN, Sparc_WSTATE, Sparc_GL, Sparc_VER, 
  };

  // PRRegs Bit set.
  static const uint8_t PRRegsBits[] = {
    0x4e, 0xda, 0xfe, 0x02, 
  };

  // CoprocPair Register Class...
  static const MCPhysReg CoprocPair[] = {
    Sparc_C0_C1, Sparc_C2_C3, Sparc_C4_C5, Sparc_C6_C7, Sparc_C8_C9, Sparc_C10_C11, Sparc_C12_C13, Sparc_C14_C15, Sparc_C16_C17, Sparc_C18_C19, Sparc_C20_C21, Sparc_C22_C23, Sparc_C24_C25, Sparc_C26_C27, Sparc_C28_C29, Sparc_C30_C31, 
  };

  // CoprocPair Bit set.
  static const uint8_t CoprocPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // IntPair Register Class...
  static const MCPhysReg IntPair[] = {
    Sparc_I0_I1, Sparc_I2_I3, Sparc_I4_I5, Sparc_I6_I7, Sparc_G0_G1, Sparc_G2_G3, Sparc_G4_G5, Sparc_G6_G7, Sparc_L0_L1, Sparc_L2_L3, Sparc_L4_L5, Sparc_L6_L7, Sparc_O0_O1, Sparc_O2_O3, Sparc_O4_O5, Sparc_O6_O7, 
  };

  // IntPair Bit set.
  static const uint8_t IntPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // LowDFPRegs Register Class...
  static const MCPhysReg LowDFPRegs[] = {
    Sparc_D0, Sparc_D1, Sparc_D2, Sparc_D3, Sparc_D4, Sparc_D5, Sparc_D6, Sparc_D7, Sparc_D8, Sparc_D9, Sparc_D10, Sparc_D11, Sparc_D12, Sparc_D13, Sparc_D14, Sparc_D15, 
  };

  // LowDFPRegs Bit set.
  static const uint8_t LowDFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
  };

  // I64Regs_and_GPRIncomingArg Register Class...
  static const MCPhysReg I64Regs_and_GPRIncomingArg[] = {
    Sparc_I0, Sparc_I1, Sparc_I2, Sparc_I3, Sparc_I4, Sparc_I5, 
  };

  // I64Regs_and_GPRIncomingArg Bit set.
  static const uint8_t I64Regs_and_GPRIncomingArgBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // I64Regs_and_GPROutgoingArg Register Class...
  static const MCPhysReg I64Regs_and_GPROutgoingArg[] = {
    Sparc_O0, Sparc_O1, Sparc_O2, Sparc_O3, Sparc_O4, Sparc_O5, 
  };

  // I64Regs_and_GPROutgoingArg Bit set.
  static const uint8_t I64Regs_and_GPROutgoingArgBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // IntPair_with_sub_even_in_GPRIncomingArg Register Class...
  static const MCPhysReg IntPair_with_sub_even_in_GPRIncomingArg[] = {
    Sparc_I0_I1, Sparc_I2_I3, Sparc_I4_I5, 
  };

  // IntPair_with_sub_even_in_GPRIncomingArg Bit set.
  static const uint8_t IntPair_with_sub_even_in_GPRIncomingArgBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
  };

  // IntPair_with_sub_even_in_GPROutgoingArg Register Class...
  static const MCPhysReg IntPair_with_sub_even_in_GPROutgoingArg[] = {
    Sparc_O0_O1, Sparc_O2_O3, Sparc_O4_O5, 
  };

  // IntPair_with_sub_even_in_GPROutgoingArg Bit set.
  static const uint8_t IntPair_with_sub_even_in_GPROutgoingArgBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
  };

  // PRRegs_and_ASRRegs Register Class...
  static const MCPhysReg PRRegs_and_ASRRegs[] = {
    Sparc_TICK, 
  };

  // PRRegs_and_ASRRegs Bit set.
  static const uint8_t PRRegs_and_ASRRegsBits[] = {
    0x00, 0x00, 0x02, 
  };

  // QFPRegs Register Class...
  static const MCPhysReg QFPRegs[] = {
    Sparc_Q0, Sparc_Q1, Sparc_Q2, Sparc_Q3, Sparc_Q4, Sparc_Q5, Sparc_Q6, Sparc_Q7, Sparc_Q8, Sparc_Q9, Sparc_Q10, Sparc_Q11, Sparc_Q12, Sparc_Q13, Sparc_Q14, Sparc_Q15, 
  };

  // QFPRegs Bit set.
  static const uint8_t QFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // LowQFPRegs Register Class...
  static const MCPhysReg LowQFPRegs[] = {
    Sparc_Q0, Sparc_Q1, Sparc_Q2, Sparc_Q3, Sparc_Q4, Sparc_Q5, Sparc_Q6, Sparc_Q7, 
  };

  // LowQFPRegs Bit set.
  static const uint8_t LowQFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

static const MCRegisterClass SparcMCRegisterClasses[] = {
  { FCCRegs, FCCRegsBits, sizeof(FCCRegsBits) },
  { ASRRegs, ASRRegsBits, sizeof(ASRRegsBits) },
  { CoprocRegs, CoprocRegsBits, sizeof(CoprocRegsBits) },
  { FPRegs, FPRegsBits, sizeof(FPRegsBits) },
  { IntRegs, IntRegsBits, sizeof(IntRegsBits) },
  { GPRIncomingArg, GPRIncomingArgBits, sizeof(GPRIncomingArgBits) },
  { GPROutgoingArg, GPROutgoingArgBits, sizeof(GPROutgoingArgBits) },
  { DFPRegs, DFPRegsBits, sizeof(DFPRegsBits) },
  { I64Regs, I64RegsBits, sizeof(I64RegsBits) },
  { PRRegs, PRRegsBits, sizeof(PRRegsBits) },
  { CoprocPair, CoprocPairBits, sizeof(CoprocPairBits) },
  { IntPair, IntPairBits, sizeof(IntPairBits) },
  { LowDFPRegs, LowDFPRegsBits, sizeof(LowDFPRegsBits) },
  { I64Regs_and_GPRIncomingArg, I64Regs_and_GPRIncomingArgBits, sizeof(I64Regs_and_GPRIncomingArgBits) },
  { I64Regs_and_GPROutgoingArg, I64Regs_and_GPROutgoingArgBits, sizeof(I64Regs_and_GPROutgoingArgBits) },
  { IntPair_with_sub_even_in_GPRIncomingArg, IntPair_with_sub_even_in_GPRIncomingArgBits, sizeof(IntPair_with_sub_even_in_GPRIncomingArgBits) },
  { IntPair_with_sub_even_in_GPROutgoingArg, IntPair_with_sub_even_in_GPROutgoingArgBits, sizeof(IntPair_with_sub_even_in_GPROutgoingArgBits) },
  { PRRegs_and_ASRRegs, PRRegs_and_ASRRegsBits, sizeof(PRRegs_and_ASRRegsBits) },
  { QFPRegs, QFPRegsBits, sizeof(QFPRegsBits) },
  { LowQFPRegs, LowQFPRegsBits, sizeof(LowQFPRegsBits) },
};

static const uint16_t SparcRegEncodingTable[] = {
  0,
  11,
  10,
  12,
  0,
  0,
  9,
  0,
  0,
  16,
  0,
  13,
  8,
  0,
  6,
  5,
  0,
  4,
  7,
  1,
  0,
  2,
  3,
  31,
  0,
  14,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  1,
  3,
  5,
  7,
  9,
  11,
  13,
  15,
  17,
  19,
  21,
  23,
  25,
  27,
  29,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  0,
  4,
  8,
  12,
  16,
  20,
  24,
  28,
  1,
  5,
  9,
  13,
  17,
  21,
  25,
  29,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  0,
  2,
  4,
  6,
  24,
  26,
  28,
  30,
  16,
  18,
  20,
  22,
  8,
  10,
  12,
  14,
};
#endif // GET_REGINFO_MC_DESC