test_cases:
  -
    input:
      bytes: [ 0x04, 0x11, 0x00, 0x00, 0x04, 0x11, 0x00, 0x02, 0x04, 0x11, 0x00, 0x04, 0x04, 0x11, 0x00, 0x01, 0x04, 0x11, 0x00, 0x03, 0x04, 0x11, 0x00, 0x05, 0x04, 0x11, 0x80, 0x00, 0x04, 0x11, 0x80, 0x02, 0x04, 0x11, 0x80, 0x04, 0x2d, 0x0a, 0x40, 0x00, 0xca, 0x22, 0x81, 0x01 ]
      arch: "arc"
      options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ld %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ld.aw %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ld.ab %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ldh %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ldh.aw %r0, [%r1,4]" 
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ldh.ab %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ldb %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ldb.aw %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "ldb.ab %r0, [%r1,4]"
        details:
          arc:
            operands:
              -
                type: ARC_OP_REG
                reg: "%r0"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 4
                access: CS_AC_READ
      -
        asm_text: "breq %r2, %r1, 80"
        details:
          arc:
            operands:
              -
                type: ARC_OP_IMM
                imm: 0
                access: CS_AC_READ
              -
                type: ARC_OP_REG
                reg: "%r2"
                access: CS_AC_READ
              -
                type: ARC_OP_REG
                reg: "%r1"
                access: CS_AC_READ
              -
                type: ARC_OP_IMM
                imm: 0x50
                access: CS_AC_READ
          regs_read: [ "%r2", "%r1" ]
          groups: [ jump, branch_relative ]
      -
        asm_text: "mov.eq %r2, %r6"
        details:
          arc:
            operands:
              -
                type: ARC_OP_IMM
                imm: 1
                access: CS_AC_READ
              -
                type: ARC_OP_REG
                reg: "%r2"
                access: CS_AC_WRITE
              -
                type: ARC_OP_REG
                reg: "%r6"
                access: CS_AC_READ
          regs_read: [ "status32", "%r6" ]
          regs_write: [ "%r2" ]     