test_cases:
  - input:
      bytes: [ 0x60, 0x51, 0x60, 0x1a, 0x23 ]
      arch: "CS_ARCH_XTENSA"
      options: [ CS_OPT_DETAIL ]
    expected:
      insns:
        - asm_text: "abs a5, a6"
          details:
            xtensa:
              format: XTENSA_INSN_FORM_RRR
              operands:
                - type: XTENSA_OP_REG
                  reg: a5
                  access: CS_AC_WRITE
                - type: XTENSA_OP_REG
                  reg: a6
                  access: CS_AC_READ
        - asm_text: "add.n a2, a3, a1"
          details:
            xtensa:
              format: XTENSA_INSN_FORM_RRRN
              operands:
                - type: XTENSA_OP_REG
                  reg: a2
                  access: CS_AC_WRITE
                - type: XTENSA_OP_REG
                  reg: a3
                  access: CS_AC_READ
                - type: XTENSA_OP_REG
                  reg: a1
                  access: CS_AC_READ
  - input:
      bytes: [ 0x18, 0x23 ]
      arch: "CS_ARCH_XTENSA"
      options: [ CS_OPT_DETAIL ]
    expected:
      insns:
        - asm_text: "l32i.n a1, a3, 8"
          details:
            xtensa:
              format: XTENSA_INSN_FORM_RRRN
              operands:
                - type: XTENSA_OP_REG
                  reg: a1
                  access: CS_AC_WRITE
                - type: XTENSA_OP_MEM
                  mem_base: a3
                  mem_disp: 8
                  access: CS_AC_READ
  - input:
      bytes: [ 0x12, 0xaf, 0xff ]
      arch: "CS_ARCH_XTENSA"
      options: [ CS_OPT_DETAIL ]
    expected:
      insns:
        - asm_text: "movi a1, -1"
          details:
            xtensa:
              format: XTENSA_INSN_FORM_RRI8
              operands:
                - type: XTENSA_OP_REG
                  reg: a1
                  access: CS_AC_WRITE
                - type: XTENSA_OP_IMM
                  imm: -1
                  access: CS_AC_READ
