test_cases:
  -
    input:
      bytes: [ 0x0b, 0xe5, 0xc5, 0x60 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.flrd fa0, a1, a2, 0"

  -
    input:
      bytes: [ 0x0b, 0xe5, 0xc5, 0x66 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.flrd fa0, a1, a2, 3"

  -
    input:
      bytes: [ 0x0b, 0xe5, 0xc5, 0x40 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.flrw fa0, a1, a2, 0"

  -
    input:
      bytes: [ 0x0b, 0xe5, 0xc5, 0x46 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.flrw fa0, a1, a2, 3"

  -
    input:
      bytes: [ 0x0b, 0xf5, 0xc5, 0x60 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.fsrd fa0, a1, a2, 0"

  -
    input:
      bytes: [ 0x0b, 0xf5, 0xc5, 0x66 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.fsrd fa0, a1, a2, 3"

  -
    input:
      bytes: [ 0x0b, 0xf5, 0xc5, 0x40 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.fsrw fa0, a1, a2, 0"

  -
    input:
      bytes: [ 0x0b, 0xf5, 0xc5, 0x46 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_D", "CS_MODE_RISCV_XTHEADFMEMIDX" ]
    expected:
      insns:
        -
          asm_text: "th.fsrw fa0, a1, a2, 3"
