test_cases:
  -
    input:
      bytes: [ 0x9b, 0x12, 0x03, 0x08 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_ZBA" ]
    expected:
      insns:
        -
          asm_text: "slli.uw t0, t1, 0"

  -
    input:
      bytes: [ 0xbb, 0x02, 0x73, 0x08 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_ZBA" ]
    expected:
      insns:
        -
          asm_text: "add.uw t0, t1, t2"

  -
    input:
      bytes: [ 0xbb, 0x22, 0x73, 0x20 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_ZBA" ]
    expected:
      insns:
        -
          asm_text: "sh1add.uw t0, t1, t2"

  -
    input:
      bytes: [ 0xbb, 0x42, 0x73, 0x20 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_ZBA" ]
    expected:
      insns:
        -
          asm_text: "sh2add.uw t0, t1, t2"

  -
    input:
      bytes: [ 0xbb, 0x62, 0x73, 0x20 ]
      arch: "CS_ARCH_RISCV"
      options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_ZBA" ]
    expected:
      insns:
        -
          asm_text: "sh3add.uw t0, t1, t2"
