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Squashed 'external/capstone/' content from commit e46f64fa

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git-subtree-dir: external/capstone
git-subtree-split: e46f64fadb351e9ecd05264fab26f2772feb0994
This commit is contained in:
iris
2026-05-11 11:55:07 +02:00
commit 802798ce3c
3968 changed files with 2967598 additions and 0 deletions
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arch/AArch64/AArch64AddressingModes.h
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arch/AArch64/AArch64BaseInfo.c
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file provides basic encoding and assembly information for AArch64.
//
//===----------------------------------------------------------------------===//
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "AArch64BaseInfo.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define GET_AT_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_AT_IMPL
#define GET_DBNXS_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_DBNXS_IMPL
#define GET_DB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_DB_IMPL
#define GET_DC_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_DC_IMPL
#define GET_IC_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_IC_IMPL
#define GET_ISB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_ISB_IMPL
#define GET_TSB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_TSB_IMPL
#define GET_PRCTX_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PRCTX_IMPL
#define GET_PRFM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PRFM_IMPL
#define GET_SVEPRFM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVEPRFM_IMPL
#define GET_RPRFM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_RPRFM_IMPL
// namespace AArch64RPRFM
// namespace llvm
#define GET_SVEPREDPAT_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVEPREDPAT_IMPL
#define GET_SVEVECLENSPECIFIER_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVEVECLENSPECIFIER_IMPL
// namespace AArch64SVEVecLenSpecifier
// namespace llvm
#define GET_EXACTFPIMM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_EXACTFPIMM_IMPL
#define GET_PSTATEIMM0_15_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PSTATEIMM0_15_IMPL
#define GET_PSTATEIMM0_1_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PSTATEIMM0_1_IMPL
#define GET_PSB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PSB_IMPL
#define GET_BTI_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_BTI_IMPL
#define SysReg AArch64SysReg_SysReg
#define GET_SYSREG_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SYSREG_IMPL
#undef SysReg
// return a string representing the number X
// NOTE: result must be big enough to contain the data
static void utostr(uint64_t X, bool isNeg, char *result)
{
char Buffer[22];
char *BufPtr = Buffer + 21;
Buffer[21] = '\0';
if (X == 0)
*--BufPtr = '0'; // Handle special case...
while (X) {
*--BufPtr = X % 10 + '0';
X /= 10;
}
if (isNeg)
*--BufPtr = '-'; // Add negative sign...
// suppose that result is big enough
strncpy(result, BufPtr, sizeof(Buffer));
}
// NOTE: result must be big enough to contain the result
void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
{
CS_ASSERT_RET(Bits < 0x10000);
char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32];
int dummy;
uint32_t Op0 = (Bits >> 14) & 0x3;
uint32_t Op1 = (Bits >> 11) & 0x7;
uint32_t CRn = (Bits >> 7) & 0xf;
uint32_t CRm = (Bits >> 3) & 0xf;
uint32_t Op2 = Bits & 0x7;
utostr(Op0, false, Op0Str);
utostr(Op1, false, Op1Str);
utostr(Op2, false, Op2Str);
utostr(CRn, false, CRnStr);
utostr(CRm, false, CRmStr);
dummy = cs_snprintf(result, AARCH64_GRS_LEN, "s%s_%s_c%s_c%s_%s",
Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
(void)dummy;
}
#define GET_TLBITable_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_TLBITable_IMPL
#define GET_SVCR_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVCR_IMPL
arch/AArch64/AArch64BaseInfo.h
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the AArch64 target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
// FIXME: Is it easiest to fix this layering violation by moving the .inc
// #includes from AArch64MCTargetDesc.h to here?
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../MCInstPrinter.h"
#include "../../utils.h"
#include "capstone/aarch64.h"
#define GET_SUBTARGETINFO_ENUM
#include "AArch64GenSubtargetInfo.inc"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "AArch64GenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "AArch64GenInstrInfo.inc"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
static inline unsigned getWRegFromXReg(unsigned Reg)
{
switch (Reg) {
case AArch64_X0:
return AArch64_W0;
case AArch64_X1:
return AArch64_W1;
case AArch64_X2:
return AArch64_W2;
case AArch64_X3:
return AArch64_W3;
case AArch64_X4:
return AArch64_W4;
case AArch64_X5:
return AArch64_W5;
case AArch64_X6:
return AArch64_W6;
case AArch64_X7:
return AArch64_W7;
case AArch64_X8:
return AArch64_W8;
case AArch64_X9:
return AArch64_W9;
case AArch64_X10:
return AArch64_W10;
case AArch64_X11:
return AArch64_W11;
case AArch64_X12:
return AArch64_W12;
case AArch64_X13:
return AArch64_W13;
case AArch64_X14:
return AArch64_W14;
case AArch64_X15:
return AArch64_W15;
case AArch64_X16:
return AArch64_W16;
case AArch64_X17:
return AArch64_W17;
case AArch64_X18:
return AArch64_W18;
case AArch64_X19:
return AArch64_W19;
case AArch64_X20:
return AArch64_W20;
case AArch64_X21:
return AArch64_W21;
case AArch64_X22:
return AArch64_W22;
case AArch64_X23:
return AArch64_W23;
case AArch64_X24:
return AArch64_W24;
case AArch64_X25:
return AArch64_W25;
case AArch64_X26:
return AArch64_W26;
case AArch64_X27:
return AArch64_W27;
case AArch64_X28:
return AArch64_W28;
case AArch64_FP:
return AArch64_W29;
case AArch64_LR:
return AArch64_W30;
case AArch64_SP:
return AArch64_WSP;
case AArch64_XZR:
return AArch64_WZR;
}
// For anything else, return it unchanged.
return Reg;
}
static inline unsigned getXRegFromWReg(unsigned Reg)
{
switch (Reg) {
case AArch64_W0:
return AArch64_X0;
case AArch64_W1:
return AArch64_X1;
case AArch64_W2:
return AArch64_X2;
case AArch64_W3:
return AArch64_X3;
case AArch64_W4:
return AArch64_X4;
case AArch64_W5:
return AArch64_X5;
case AArch64_W6:
return AArch64_X6;
case AArch64_W7:
return AArch64_X7;
case AArch64_W8:
return AArch64_X8;
case AArch64_W9:
return AArch64_X9;
case AArch64_W10:
return AArch64_X10;
case AArch64_W11:
return AArch64_X11;
case AArch64_W12:
return AArch64_X12;
case AArch64_W13:
return AArch64_X13;
case AArch64_W14:
return AArch64_X14;
case AArch64_W15:
return AArch64_X15;
case AArch64_W16:
return AArch64_X16;
case AArch64_W17:
return AArch64_X17;
case AArch64_W18:
return AArch64_X18;
case AArch64_W19:
return AArch64_X19;
case AArch64_W20:
return AArch64_X20;
case AArch64_W21:
return AArch64_X21;
case AArch64_W22:
return AArch64_X22;
case AArch64_W23:
return AArch64_X23;
case AArch64_W24:
return AArch64_X24;
case AArch64_W25:
return AArch64_X25;
case AArch64_W26:
return AArch64_X26;
case AArch64_W27:
return AArch64_X27;
case AArch64_W28:
return AArch64_X28;
case AArch64_W29:
return AArch64_FP;
case AArch64_W30:
return AArch64_LR;
case AArch64_WSP:
return AArch64_SP;
case AArch64_WZR:
return AArch64_XZR;
}
// For anything else, return it unchanged.
return Reg;
}
static inline unsigned getXRegFromXRegTuple(unsigned RegTuple)
{
switch (RegTuple) {
case AArch64_X0_X1_X2_X3_X4_X5_X6_X7:
return AArch64_X0;
case AArch64_X2_X3_X4_X5_X6_X7_X8_X9:
return AArch64_X2;
case AArch64_X4_X5_X6_X7_X8_X9_X10_X11:
return AArch64_X4;
case AArch64_X6_X7_X8_X9_X10_X11_X12_X13:
return AArch64_X6;
case AArch64_X8_X9_X10_X11_X12_X13_X14_X15:
return AArch64_X8;
case AArch64_X10_X11_X12_X13_X14_X15_X16_X17:
return AArch64_X10;
case AArch64_X12_X13_X14_X15_X16_X17_X18_X19:
return AArch64_X12;
case AArch64_X14_X15_X16_X17_X18_X19_X20_X21:
return AArch64_X14;
case AArch64_X16_X17_X18_X19_X20_X21_X22_X23:
return AArch64_X16;
case AArch64_X18_X19_X20_X21_X22_X23_X24_X25:
return AArch64_X18;
case AArch64_X20_X21_X22_X23_X24_X25_X26_X27:
return AArch64_X20;
case AArch64_X22_X23_X24_X25_X26_X27_X28_FP:
return AArch64_X22;
}
// For anything else, return it unchanged.
return RegTuple;
}
static inline unsigned getBRegFromDReg(unsigned Reg)
{
switch (Reg) {
case AArch64_D0:
return AArch64_B0;
case AArch64_D1:
return AArch64_B1;
case AArch64_D2:
return AArch64_B2;
case AArch64_D3:
return AArch64_B3;
case AArch64_D4:
return AArch64_B4;
case AArch64_D5:
return AArch64_B5;
case AArch64_D6:
return AArch64_B6;
case AArch64_D7:
return AArch64_B7;
case AArch64_D8:
return AArch64_B8;
case AArch64_D9:
return AArch64_B9;
case AArch64_D10:
return AArch64_B10;
case AArch64_D11:
return AArch64_B11;
case AArch64_D12:
return AArch64_B12;
case AArch64_D13:
return AArch64_B13;
case AArch64_D14:
return AArch64_B14;
case AArch64_D15:
return AArch64_B15;
case AArch64_D16:
return AArch64_B16;
case AArch64_D17:
return AArch64_B17;
case AArch64_D18:
return AArch64_B18;
case AArch64_D19:
return AArch64_B19;
case AArch64_D20:
return AArch64_B20;
case AArch64_D21:
return AArch64_B21;
case AArch64_D22:
return AArch64_B22;
case AArch64_D23:
return AArch64_B23;
case AArch64_D24:
return AArch64_B24;
case AArch64_D25:
return AArch64_B25;
case AArch64_D26:
return AArch64_B26;
case AArch64_D27:
return AArch64_B27;
case AArch64_D28:
return AArch64_B28;
case AArch64_D29:
return AArch64_B29;
case AArch64_D30:
return AArch64_B30;
case AArch64_D31:
return AArch64_B31;
}
// For anything else, return it unchanged.
return Reg;
}
static inline unsigned getDRegFromBReg(unsigned Reg)
{
switch (Reg) {
case AArch64_B0:
return AArch64_D0;
case AArch64_B1:
return AArch64_D1;
case AArch64_B2:
return AArch64_D2;
case AArch64_B3:
return AArch64_D3;
case AArch64_B4:
return AArch64_D4;
case AArch64_B5:
return AArch64_D5;
case AArch64_B6:
return AArch64_D6;
case AArch64_B7:
return AArch64_D7;
case AArch64_B8:
return AArch64_D8;
case AArch64_B9:
return AArch64_D9;
case AArch64_B10:
return AArch64_D10;
case AArch64_B11:
return AArch64_D11;
case AArch64_B12:
return AArch64_D12;
case AArch64_B13:
return AArch64_D13;
case AArch64_B14:
return AArch64_D14;
case AArch64_B15:
return AArch64_D15;
case AArch64_B16:
return AArch64_D16;
case AArch64_B17:
return AArch64_D17;
case AArch64_B18:
return AArch64_D18;
case AArch64_B19:
return AArch64_D19;
case AArch64_B20:
return AArch64_D20;
case AArch64_B21:
return AArch64_D21;
case AArch64_B22:
return AArch64_D22;
case AArch64_B23:
return AArch64_D23;
case AArch64_B24:
return AArch64_D24;
case AArch64_B25:
return AArch64_D25;
case AArch64_B26:
return AArch64_D26;
case AArch64_B27:
return AArch64_D27;
case AArch64_B28:
return AArch64_D28;
case AArch64_B29:
return AArch64_D29;
case AArch64_B30:
return AArch64_D30;
case AArch64_B31:
return AArch64_D31;
}
// For anything else, return it unchanged.
return Reg;
}
static inline bool atomicBarrierDroppedOnZero(unsigned Opcode)
{
switch (Opcode) {
case AArch64_LDADDAB:
case AArch64_LDADDAH:
case AArch64_LDADDAW:
case AArch64_LDADDAX:
case AArch64_LDADDALB:
case AArch64_LDADDALH:
case AArch64_LDADDALW:
case AArch64_LDADDALX:
case AArch64_LDCLRAB:
case AArch64_LDCLRAH:
case AArch64_LDCLRAW:
case AArch64_LDCLRAX:
case AArch64_LDCLRALB:
case AArch64_LDCLRALH:
case AArch64_LDCLRALW:
case AArch64_LDCLRALX:
case AArch64_LDEORAB:
case AArch64_LDEORAH:
case AArch64_LDEORAW:
case AArch64_LDEORAX:
case AArch64_LDEORALB:
case AArch64_LDEORALH:
case AArch64_LDEORALW:
case AArch64_LDEORALX:
case AArch64_LDSETAB:
case AArch64_LDSETAH:
case AArch64_LDSETAW:
case AArch64_LDSETAX:
case AArch64_LDSETALB:
case AArch64_LDSETALH:
case AArch64_LDSETALW:
case AArch64_LDSETALX:
case AArch64_LDSMAXAB:
case AArch64_LDSMAXAH:
case AArch64_LDSMAXAW:
case AArch64_LDSMAXAX:
case AArch64_LDSMAXALB:
case AArch64_LDSMAXALH:
case AArch64_LDSMAXALW:
case AArch64_LDSMAXALX:
case AArch64_LDSMINAB:
case AArch64_LDSMINAH:
case AArch64_LDSMINAW:
case AArch64_LDSMINAX:
case AArch64_LDSMINALB:
case AArch64_LDSMINALH:
case AArch64_LDSMINALW:
case AArch64_LDSMINALX:
case AArch64_LDUMAXAB:
case AArch64_LDUMAXAH:
case AArch64_LDUMAXAW:
case AArch64_LDUMAXAX:
case AArch64_LDUMAXALB:
case AArch64_LDUMAXALH:
case AArch64_LDUMAXALW:
case AArch64_LDUMAXALX:
case AArch64_LDUMINAB:
case AArch64_LDUMINAH:
case AArch64_LDUMINAW:
case AArch64_LDUMINAX:
case AArch64_LDUMINALB:
case AArch64_LDUMINALH:
case AArch64_LDUMINALW:
case AArch64_LDUMINALX:
case AArch64_SWPAB:
case AArch64_SWPAH:
case AArch64_SWPAW:
case AArch64_SWPAX:
case AArch64_SWPALB:
case AArch64_SWPALH:
case AArch64_SWPALW:
case AArch64_SWPALX:
return true;
}
return false;
}
// MOVE-NOTICE: AArch64CC_CondCode : moved to aarch64.h
// MOVE-NOTICE: AArch64CC_getCondCodeName : moved to aarch64.h
// MOVE-NOTICE: AArch64CC_getInvertedCondCode : moved to aarch64.h
// MOVE-NOTICE: AArch64CC_getNZCVToSatisfyCondCode : moved to aarch64.h
typedef struct SysAlias {
const char *Name;
aarch64_sysop_alias SysAlias;
uint16_t Encoding;
aarch64_insn_group FeaturesRequired[3];
} SysAlias;
typedef struct SysAliasReg {
const char *Name;
aarch64_sysop_reg SysReg;
uint16_t Encoding;
bool NeedsReg;
aarch64_insn_group FeaturesRequired[3];
} SysAliasReg;
typedef struct SysAliasImm {
const char *Name;
aarch64_sysop_imm SysImm;
uint16_t ImmValue;
uint16_t Encoding;
aarch64_insn_group FeaturesRequired[3];
} SysAliasImm;
// CS namespace begin: AArch64SVCR
#define AArch64SVCR_SVCR SysAlias
#define GET_SVCR_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVCR
// CS namespace begin: AArch64AT
#define AArch64AT_AT SysAlias
#define GET_AT_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64AT
// CS namespace begin: AArch64DB
#define AArch64DB_DB SysAlias
#define GET_DB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64DB
// CS namespace begin: AArch64DBnXS
#define AArch64DBnXS_DBnXS SysAliasImm
#define GET_DBNXS_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64DBnXS
// CS namespace begin: AArch64DC
#define AArch64DC_DC SysAlias
#define GET_DC_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64DC
// CS namespace begin: AArch64IC
#define AArch64IC_IC SysAliasReg
#define GET_IC_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64IC
// CS namespace begin: AArch64ISB
#define AArch64ISB_ISB SysAlias
#define GET_ISB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64ISB
// CS namespace begin: AArch64TSB
#define AArch64TSB_TSB SysAlias
#define GET_TSB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64TSB
// CS namespace begin: AArch64PRFM
#define AArch64PRFM_PRFM SysAlias
#define GET_PRFM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PRFM
// CS namespace begin: AArch64SVEPRFM
#define AArch64SVEPRFM_SVEPRFM SysAlias
#define GET_SVEPRFM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVEPRFM
// CS namespace begin: AArch64RPRFM
#define AArch64RPRFM_RPRFM SysAlias
#define GET_RPRFM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64RPRFM
// CS namespace begin: AArch64SVEPredPattern
typedef struct SVEPREDPAT {
const char *Name;
aarch64_sysop_alias SysAlias;
uint16_t Encoding;
} AArch64SVEPredPattern_SVEPREDPAT;
#define GET_SVEPREDPAT_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVEPredPattern
// CS namespace begin: AArch64SVEVecLenSpecifier
typedef struct SVEVECLENSPECIFIER {
const char *Name;
aarch64_sysop_alias SysAlias;
uint16_t Encoding;
} AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER;
#define GET_SVEVECLENSPECIFIER_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64SVEVecLenSpecifier
// namespace AArch64SVEVecLenSpecifier
/// Return the number of active elements for VL1 to VL256 predicate pattern,
/// zero for all other patterns.
static inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
{
switch (Pattern) {
default:
return 0;
case AARCH64_SVEPREDPAT_VL1:
case AARCH64_SVEPREDPAT_VL2:
case AARCH64_SVEPREDPAT_VL3:
case AARCH64_SVEPREDPAT_VL4:
case AARCH64_SVEPREDPAT_VL5:
case AARCH64_SVEPREDPAT_VL6:
case AARCH64_SVEPREDPAT_VL7:
case AARCH64_SVEPREDPAT_VL8:
return Pattern;
case AARCH64_SVEPREDPAT_VL16:
return 16;
case AARCH64_SVEPREDPAT_VL32:
return 32;
case AARCH64_SVEPREDPAT_VL64:
return 64;
case AARCH64_SVEPREDPAT_VL128:
return 128;
case AARCH64_SVEPREDPAT_VL256:
return 256;
}
}
/// Return specific VL predicate pattern based on the number of elements.
static inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts)
{
switch (MinNumElts) {
default:
return 0;
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
return MinNumElts;
case 16:
return AARCH64_SVEPREDPAT_VL16;
case 32:
return AARCH64_SVEPREDPAT_VL32;
case 64:
return AARCH64_SVEPREDPAT_VL64;
case 128:
return AARCH64_SVEPREDPAT_VL128;
case 256:
return AARCH64_SVEPREDPAT_VL256;
}
}
// CS namespace begin: AArch64ExactFPImm
typedef struct ExactFPImm {
const char *Name;
aarch64_sysop_imm SysImm;
int Enum;
const char *Repr;
} AArch64ExactFPImm_ExactFPImm;
enum {
AArch64ExactFPImm_half = 1,
AArch64ExactFPImm_one = 2,
AArch64ExactFPImm_two = 3,
AArch64ExactFPImm_zero = 0,
};
#define GET_EXACTFPIMM_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64ExactFPImm
// CS namespace begin: AArch64PState
#define AArch64PState_PStateImm0_15 SysAlias
#define GET_PSTATEIMM0_15_DECL
#include "AArch64GenSystemOperands.inc"
#define AArch64PState_PStateImm0_1 SysAlias
#define GET_PSTATEIMM0_1_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PState
// CS namespace begin: AArch64PSBHint
#define AArch64PSBHint_PSB SysAlias
#define GET_PSB_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PSBHint
// CS namespace begin: AArch64BTIHint
#define AArch64BTIHint_BTI SysAlias
#define GET_BTI_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64BTIHint
// CS namespace begin: AArch64SE
typedef enum ShiftExtSpecifiers {
AArch64SE_Invalid = -1,
AArch64SE_LSL,
AArch64SE_MSL,
AArch64SE_LSR,
AArch64SE_ASR,
AArch64SE_ROR,
AArch64SE_UXTB,
AArch64SE_UXTH,
AArch64SE_UXTW,
AArch64SE_UXTX,
AArch64SE_SXTB,
AArch64SE_SXTH,
AArch64SE_SXTW,
AArch64SE_SXTX
} AArch64SE_ShiftExtSpecifiers;
// CS namespace end: AArch64SE
// CS namespace begin: AArch64Layout
// MOVE_NOTICE: AArch64Layout_VectorLayout - move to aarch64.h
// MOVE_NOTICE: AArch64VectorLayoutToString - move to aarch64.h
// MOVE_NOTICE: AArch64StringToVectorLayout - move to aarch64.h
// CS namespace end: AArch64Layout
// CS namespace begin: AArch64SysReg
typedef struct SysReg {
const char *Name;
aarch64_sysop_reg SysReg;
const char *AltName;
aarch64_sysop_reg AliasReg;
unsigned Encoding;
bool Readable;
bool Writeable;
aarch64_insn_group FeaturesRequired[3];
} AArch64SysReg_SysReg;
#define GET_SYSREG_DECL
#include "AArch64GenSystemOperands.inc"
const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name);
const AArch64SysReg_SysReg *
AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
#define AARCH64_GRS_LEN 128
void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
// CS namespace end: AArch64SysReg
// CS namespace begin: AArch64TLBI
#define AArch64TLBI_TLBI SysAliasReg
#define GET_TLBITable_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64TLBI
// CS namespace begin: AArch64PRCTX
#define AArch64PRCTX_PRCTX SysAliasReg
#define GET_PRCTX_DECL
#include "AArch64GenSystemOperands.inc"
// CS namespace end: AArch64PRCTX
// CS namespace begin: AArch64II
/// Target Operand Flag enum.
typedef enum TOF {
//===------------------------------------------------------------------===//
// AArch64 Specific MachineOperand flags.
AArch64II_MO_NO_FLAG,
AArch64II_MO_FRAGMENT = 0x7,
/// MO_PAGE - A symbol operand with this flag represents the pc-relative
/// offset of the 4K page containing the symbol. This is used with the
/// ADRP instruction.
AArch64II_MO_PAGE = 1,
/// MO_PAGEOFF - A symbol operand with this flag represents the offset of
/// that symbol within a 4K page. This offset is added to the page address
/// to produce the complete address.
AArch64II_MO_PAGEOFF = 2,
/// MO_G3 - A symbol operand with this flag (granule 3) represents the high
/// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
AArch64II_MO_G3 = 3,
/// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
/// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
AArch64II_MO_G2 = 4,
/// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
/// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
AArch64II_MO_G1 = 5,
/// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
AArch64II_MO_G0 = 6,
/// MO_HI12 - This flag indicates that a symbol operand represents the bits
/// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
/// by-12-bits instruction.
AArch64II_MO_HI12 = 7,
/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
/// reference is actually to the ".refptr.FOO" symbol. This is used for
/// stub symbols on windows.
AArch64II_MO_COFFSTUB = 0x8,
/// MO_GOT - This flag indicates that a symbol operand represents the
/// address of the GOT entry for the symbol, rather than the address of
/// the symbol itself.
AArch64II_MO_GOT = 0x10,
/// MO_NC - Indicates whether the linker is expected to check the symbol
/// reference for overflow. For example in an ADRP/ADD pair of relocations
/// the ADRP usually does check, but not the ADD.
AArch64II_MO_NC = 0x20,
/// MO_TLS - Indicates that the operand being accessed is some kind of
/// thread-local symbol. On Darwin, only one type of thread-local access
/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
/// referee will affect interpretation.
AArch64II_MO_TLS = 0x40,
/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
/// to the symbol is for an import stub. This is used for DLL import
/// storage class indication on Windows.
AArch64II_MO_DLLIMPORT = 0x80,
/// MO_S - Indicates that the bits of the symbol operand represented by
/// MO_G0 etc are signed.
AArch64II_MO_S = 0x100,
/// MO_PREL - Indicates that the bits of the symbol operand represented by
/// MO_G0 etc are PC relative.
AArch64II_MO_PREL = 0x200,
/// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
/// in bits 56-63.
/// On a FrameIndex operand, indicates that the underlying memory is tagged
/// with an unknown tag value (MTE); this needs to be lowered either to an
/// SP-relative load or store instruction (which do not check tags), or to
/// an LDG instruction to obtain the tag value.
AArch64II_MO_TAGGED = 0x400,
/// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
/// of a symbol, not the original. For dllimport symbols, this means it
/// uses "__imp_aux". For other symbols, this means it uses the mangled
/// ("#" prefix for C) name.
AArch64II_MO_ARM64EC_CALLMANGLE = 0x800,
} AArch64II_TOF;
// CS namespace end: AArch64II
// end namespace AArch64II
//===----------------------------------------------------------------------===//
// v8.3a Pointer Authentication
//
// CS namespace begin: AArch64PACKey
typedef enum ID {
AArch64PACKey_IA = 0,
AArch64PACKey_IB = 1,
AArch64PACKey_DA = 2,
AArch64PACKey_DB = 3,
AArch64PACKey_LAST = AArch64PACKey_DB,
AArch64PACKey_INVALID,
} AArch64PACKey_ID;
// CS namespace end: AArch64PACKey
// namespace AArch64PACKey
/// Return 2-letter identifier string for numeric key ID.
static inline const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
{
switch (KeyID) {
default:
break;
case AArch64PACKey_IA:
return "ia";
case AArch64PACKey_IB:
return "ib";
case AArch64PACKey_DA:
return "da";
case AArch64PACKey_DB:
return "db";
}
return NULL;
}
/// Return numeric key ID for 2-letter identifier string.
static inline AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name)
{
if (strcmp(Name, "ia") == 0)
return AArch64PACKey_IA;
if (strcmp(Name, "ib") == 0)
return AArch64PACKey_IB;
if (strcmp(Name, "da") == 0)
return AArch64PACKey_DA;
if (strcmp(Name, "db") == 0)
return AArch64PACKey_DB;
CS_ASSERT_RET_VAL(0 && "Invalid PAC key", AArch64PACKey_INVALID);
return AArch64PACKey_LAST;
}
// CS namespace begin: AArch64
// The number of bits in a SVE register is architecturally defined
// to be a multiple of this value. If <M x t> has this number of bits,
// a <n x M x t> vector can be stored in a SVE register without any
// redundant bits. If <M x t> has this number of bits divided by P,
// a <n x M x t> vector is stored in a SVE register by placing index i
// in index i*P of a <n x (M*P) x t> vector. The other elements of the
// <n x (M*P) x t> vector (such as index 1) are undefined.
static const unsigned SVEBitsPerBlock = 128;
static const unsigned SVEMaxBitsPerVector = 2048;
// CS namespace end: AArch64
// end namespace AArch64
// end namespace llvm
#endif
arch/AArch64/AArch64Disassembler.c
+2217
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arch/AArch64/AArch64DisassemblerExtension.c
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#include "AArch64DisassemblerExtension.h"
#include "AArch64BaseInfo.h"
bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature)
{
if (feature == AArch64_FeatureAMX || feature == AArch64_FeatureMUL53 ||
feature == AArch64_FeatureAppleSys) {
return mode & CS_MODE_APPLE_PROPRIETARY;
}
// we support everything
return true;
}
/// Tests a NULL terminated array of features if they are enabled.
bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features)
{
int i = 0;
while (features[i]) {
if (!AArch64_getFeatureBits(mode, features[i]))
return false;
++i;
}
return true;
}
arch/AArch64/AArch64DisassemblerExtension.h
+19
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@@ -0,0 +1,19 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#ifndef CS_AARCH64_DISASSEMBLER_EXTENSION_H
#define CS_AARCH64_DISASSEMBLER_EXTENSION_H
#include "../../MCDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "../../cs_priv.h"
#include "AArch64AddressingModes.h"
#include "capstone/aarch64.h"
#include "capstone/capstone.h"
bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features);
#endif // CS_AARCH64_DISASSEMBLER_EXTENSION_H
arch/AArch64/AArch64GenAsmWriter.inc
+34894
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arch/AArch64/AArch64GenCSAliasMnemMap.inc
+375
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@@ -0,0 +1,375 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ AARCH64_INS_ALIAS_ADDPT, "addpt" },
{ AARCH64_INS_ALIAS_GCSB, "gcsb" },
{ AARCH64_INS_ALIAS_GCSPOPM, "gcspopm" },
{ AARCH64_INS_ALIAS_LDAPUR, "ldapur" },
{ AARCH64_INS_ALIAS_STLLRB, "stllrb" },
{ AARCH64_INS_ALIAS_STLLRH, "stllrh" },
{ AARCH64_INS_ALIAS_STLLR, "stllr" },
{ AARCH64_INS_ALIAS_STLRB, "stlrb" },
{ AARCH64_INS_ALIAS_STLRH, "stlrh" },
{ AARCH64_INS_ALIAS_STLR, "stlr" },
{ AARCH64_INS_ALIAS_STLUR, "stlur" },
{ AARCH64_INS_ALIAS_SUBPT, "subpt" },
{ AARCH64_INS_ALIAS_LDRAA, "ldraa" },
{ AARCH64_INS_ALIAS_ADD, "add" },
{ AARCH64_INS_ALIAS_CMN, "cmn" },
{ AARCH64_INS_ALIAS_ADDS, "adds" },
{ AARCH64_INS_ALIAS_AND, "and" },
{ AARCH64_INS_ALIAS_ANDS, "ands" },
{ AARCH64_INS_ALIAS_LDR, "ldr" },
{ AARCH64_INS_ALIAS_STR, "str" },
{ AARCH64_INS_ALIAS_LDRB, "ldrb" },
{ AARCH64_INS_ALIAS_STRB, "strb" },
{ AARCH64_INS_ALIAS_LDRH, "ldrh" },
{ AARCH64_INS_ALIAS_STRH, "strh" },
{ AARCH64_INS_ALIAS_PRFM, "prfm" },
{ AARCH64_INS_ALIAS_LDAPURB, "ldapurb" },
{ AARCH64_INS_ALIAS_STLURB, "stlurb" },
{ AARCH64_INS_ALIAS_LDUR, "ldur" },
{ AARCH64_INS_ALIAS_STUR, "stur" },
{ AARCH64_INS_ALIAS_PRFUM, "prfum" },
{ AARCH64_INS_ALIAS_LDTR, "ldtr" },
{ AARCH64_INS_ALIAS_STTR, "sttr" },
{ AARCH64_INS_ALIAS_LDP, "ldp" },
{ AARCH64_INS_ALIAS_STGP, "stgp" },
{ AARCH64_INS_ALIAS_LDNP, "ldnp" },
{ AARCH64_INS_ALIAS_STNP, "stnp" },
{ AARCH64_INS_ALIAS_STG, "stg" },
{ AARCH64_INS_ALIAS_MOV, "mov" },
{ AARCH64_INS_ALIAS_LD1, "ld1" },
{ AARCH64_INS_ALIAS_LD1R, "ld1r" },
{ AARCH64_INS_ALIAS_STADDLB, "staddlb" },
{ AARCH64_INS_ALIAS_STADDLH, "staddlh" },
{ AARCH64_INS_ALIAS_STADDL, "staddl" },
{ AARCH64_INS_ALIAS_STADDB, "staddb" },
{ AARCH64_INS_ALIAS_STADDH, "staddh" },
{ AARCH64_INS_ALIAS_STADD, "stadd" },
{ AARCH64_INS_ALIAS_PTRUE, "ptrue" },
{ AARCH64_INS_ALIAS_PTRUES, "ptrues" },
{ AARCH64_INS_ALIAS_CNTB, "cntb" },
{ AARCH64_INS_ALIAS_SQINCH, "sqinch" },
{ AARCH64_INS_ALIAS_INCB, "incb" },
{ AARCH64_INS_ALIAS_SQINCB, "sqincb" },
{ AARCH64_INS_ALIAS_UQINCB, "uqincb" },
{ AARCH64_INS_ALIAS_ORR, "orr" },
{ AARCH64_INS_ALIAS_DUPM, "dupm" },
{ AARCH64_INS_ALIAS_FMOV, "fmov" },
{ AARCH64_INS_ALIAS_EOR3, "eor3" },
{ AARCH64_INS_ALIAS_ST1B, "st1b" },
{ AARCH64_INS_ALIAS_ST2B, "st2b" },
{ AARCH64_INS_ALIAS_ST2Q, "st2q" },
{ AARCH64_INS_ALIAS_STNT1B, "stnt1b" },
{ AARCH64_INS_ALIAS_LD1B, "ld1b" },
{ AARCH64_INS_ALIAS_LDNT1B, "ldnt1b" },
{ AARCH64_INS_ALIAS_LD1RQB, "ld1rqb" },
{ AARCH64_INS_ALIAS_LD1RB, "ld1rb" },
{ AARCH64_INS_ALIAS_LDFF1B, "ldff1b" },
{ AARCH64_INS_ALIAS_LDNF1B, "ldnf1b" },
{ AARCH64_INS_ALIAS_LD2B, "ld2b" },
{ AARCH64_INS_ALIAS_LD1SB, "ld1sb" },
{ AARCH64_INS_ALIAS_PRFB, "prfb" },
{ AARCH64_INS_ALIAS_LDNT1SB, "ldnt1sb" },
{ AARCH64_INS_ALIAS_LD1ROB, "ld1rob" },
{ AARCH64_INS_ALIAS_LD1Q, "ld1q" },
{ AARCH64_INS_ALIAS_ST1Q, "st1q" },
{ AARCH64_INS_ALIAS_LD1W, "ld1w" },
{ AARCH64_INS_ALIAS_PMOV, "pmov" },
{ AARCH64_INS_ALIAS_SMSTART, "smstart" },
{ AARCH64_INS_ALIAS_SMSTOP, "smstop" },
{ AARCH64_INS_ALIAS_ZERO, "zero" },
{ AARCH64_INS_ALIAS_MOVT, "movt" },
{ AARCH64_INS_ALIAS_NOP, "nop" },
{ AARCH64_INS_ALIAS_YIELD, "yield" },
{ AARCH64_INS_ALIAS_WFE, "wfe" },
{ AARCH64_INS_ALIAS_WFI, "wfi" },
{ AARCH64_INS_ALIAS_SEV, "sev" },
{ AARCH64_INS_ALIAS_SEVL, "sevl" },
{ AARCH64_INS_ALIAS_DGH, "dgh" },
{ AARCH64_INS_ALIAS_ESB, "esb" },
{ AARCH64_INS_ALIAS_CSDB, "csdb" },
{ AARCH64_INS_ALIAS_BTI, "bti" },
{ AARCH64_INS_ALIAS_PSB, "psb" },
{ AARCH64_INS_ALIAS_CHKFEAT, "chkfeat" },
{ AARCH64_INS_ALIAS_PACIAZ, "paciaz" },
{ AARCH64_INS_ALIAS_PACIBZ, "pacibz" },
{ AARCH64_INS_ALIAS_AUTIAZ, "autiaz" },
{ AARCH64_INS_ALIAS_AUTIBZ, "autibz" },
{ AARCH64_INS_ALIAS_PACIASP, "paciasp" },
{ AARCH64_INS_ALIAS_PACIBSP, "pacibsp" },
{ AARCH64_INS_ALIAS_AUTIASP, "autiasp" },
{ AARCH64_INS_ALIAS_AUTIBSP, "autibsp" },
{ AARCH64_INS_ALIAS_PACIA1716, "pacia1716" },
{ AARCH64_INS_ALIAS_PACIB1716, "pacib1716" },
{ AARCH64_INS_ALIAS_AUTIA1716, "autia1716" },
{ AARCH64_INS_ALIAS_AUTIB1716, "autib1716" },
{ AARCH64_INS_ALIAS_XPACLRI, "xpaclri" },
{ AARCH64_INS_ALIAS_LDRAB, "ldrab" },
{ AARCH64_INS_ALIAS_PACM, "pacm" },
{ AARCH64_INS_ALIAS_CLREX, "clrex" },
{ AARCH64_INS_ALIAS_ISB, "isb" },
{ AARCH64_INS_ALIAS_SSBB, "ssbb" },
{ AARCH64_INS_ALIAS_PSSBB, "pssbb" },
{ AARCH64_INS_ALIAS_DFB, "dfb" },
{ AARCH64_INS_ALIAS_SYS, "sys" },
{ AARCH64_INS_ALIAS_MOVN, "movn" },
{ AARCH64_INS_ALIAS_MOVZ, "movz" },
{ AARCH64_INS_ALIAS_NGC, "ngc" },
{ AARCH64_INS_ALIAS_NGCS, "ngcs" },
{ AARCH64_INS_ALIAS_SUB, "sub" },
{ AARCH64_INS_ALIAS_CMP, "cmp" },
{ AARCH64_INS_ALIAS_SUBS, "subs" },
{ AARCH64_INS_ALIAS_NEG, "neg" },
{ AARCH64_INS_ALIAS_NEGS, "negs" },
{ AARCH64_INS_ALIAS_MUL, "mul" },
{ AARCH64_INS_ALIAS_MNEG, "mneg" },
{ AARCH64_INS_ALIAS_SMULL, "smull" },
{ AARCH64_INS_ALIAS_SMNEGL, "smnegl" },
{ AARCH64_INS_ALIAS_UMULL, "umull" },
{ AARCH64_INS_ALIAS_UMNEGL, "umnegl" },
{ AARCH64_INS_ALIAS_STCLRLB, "stclrlb" },
{ AARCH64_INS_ALIAS_STCLRLH, "stclrlh" },
{ AARCH64_INS_ALIAS_STCLRL, "stclrl" },
{ AARCH64_INS_ALIAS_STCLRB, "stclrb" },
{ AARCH64_INS_ALIAS_STCLRH, "stclrh" },
{ AARCH64_INS_ALIAS_STCLR, "stclr" },
{ AARCH64_INS_ALIAS_STEORLB, "steorlb" },
{ AARCH64_INS_ALIAS_STEORLH, "steorlh" },
{ AARCH64_INS_ALIAS_STEORL, "steorl" },
{ AARCH64_INS_ALIAS_STEORB, "steorb" },
{ AARCH64_INS_ALIAS_STEORH, "steorh" },
{ AARCH64_INS_ALIAS_STEOR, "steor" },
{ AARCH64_INS_ALIAS_STSETLB, "stsetlb" },
{ AARCH64_INS_ALIAS_STSETLH, "stsetlh" },
{ AARCH64_INS_ALIAS_STSETL, "stsetl" },
{ AARCH64_INS_ALIAS_STSETB, "stsetb" },
{ AARCH64_INS_ALIAS_STSETH, "stseth" },
{ AARCH64_INS_ALIAS_STSET, "stset" },
{ AARCH64_INS_ALIAS_STSMAXLB, "stsmaxlb" },
{ AARCH64_INS_ALIAS_STSMAXLH, "stsmaxlh" },
{ AARCH64_INS_ALIAS_STSMAXL, "stsmaxl" },
{ AARCH64_INS_ALIAS_STSMAXB, "stsmaxb" },
{ AARCH64_INS_ALIAS_STSMAXH, "stsmaxh" },
{ AARCH64_INS_ALIAS_STSMAX, "stsmax" },
{ AARCH64_INS_ALIAS_STSMINLB, "stsminlb" },
{ AARCH64_INS_ALIAS_STSMINLH, "stsminlh" },
{ AARCH64_INS_ALIAS_STSMINL, "stsminl" },
{ AARCH64_INS_ALIAS_STSMINB, "stsminb" },
{ AARCH64_INS_ALIAS_STSMINH, "stsminh" },
{ AARCH64_INS_ALIAS_STSMIN, "stsmin" },
{ AARCH64_INS_ALIAS_STUMAXLB, "stumaxlb" },
{ AARCH64_INS_ALIAS_STUMAXLH, "stumaxlh" },
{ AARCH64_INS_ALIAS_STUMAXL, "stumaxl" },
{ AARCH64_INS_ALIAS_STUMAXB, "stumaxb" },
{ AARCH64_INS_ALIAS_STUMAXH, "stumaxh" },
{ AARCH64_INS_ALIAS_STUMAX, "stumax" },
{ AARCH64_INS_ALIAS_STUMINLB, "stuminlb" },
{ AARCH64_INS_ALIAS_STUMINLH, "stuminlh" },
{ AARCH64_INS_ALIAS_STUMINL, "stuminl" },
{ AARCH64_INS_ALIAS_STUMINB, "stuminb" },
{ AARCH64_INS_ALIAS_STUMINH, "stuminh" },
{ AARCH64_INS_ALIAS_STUMIN, "stumin" },
{ AARCH64_INS_ALIAS_IRG, "irg" },
{ AARCH64_INS_ALIAS_LDG, "ldg" },
{ AARCH64_INS_ALIAS_STZG, "stzg" },
{ AARCH64_INS_ALIAS_ST2G, "st2g" },
{ AARCH64_INS_ALIAS_STZ2G, "stz2g" },
{ AARCH64_INS_ALIAS_BICS, "bics" },
{ AARCH64_INS_ALIAS_BIC, "bic" },
{ AARCH64_INS_ALIAS_EON, "eon" },
{ AARCH64_INS_ALIAS_EOR, "eor" },
{ AARCH64_INS_ALIAS_ORN, "orn" },
{ AARCH64_INS_ALIAS_MVN, "mvn" },
{ AARCH64_INS_ALIAS_TST, "tst" },
{ AARCH64_INS_ALIAS_ROR, "ror" },
{ AARCH64_INS_ALIAS_ASR, "asr" },
{ AARCH64_INS_ALIAS_SXTB, "sxtb" },
{ AARCH64_INS_ALIAS_SXTH, "sxth" },
{ AARCH64_INS_ALIAS_SXTW, "sxtw" },
{ AARCH64_INS_ALIAS_LSR, "lsr" },
{ AARCH64_INS_ALIAS_UXTB, "uxtb" },
{ AARCH64_INS_ALIAS_UXTH, "uxth" },
{ AARCH64_INS_ALIAS_UXTW, "uxtw" },
{ AARCH64_INS_ALIAS_CSET, "cset" },
{ AARCH64_INS_ALIAS_CSETM, "csetm" },
{ AARCH64_INS_ALIAS_CINC, "cinc" },
{ AARCH64_INS_ALIAS_CINV, "cinv" },
{ AARCH64_INS_ALIAS_CNEG, "cneg" },
{ AARCH64_INS_ALIAS_RET, "ret" },
{ AARCH64_INS_ALIAS_DCPS1, "dcps1" },
{ AARCH64_INS_ALIAS_DCPS2, "dcps2" },
{ AARCH64_INS_ALIAS_DCPS3, "dcps3" },
{ AARCH64_INS_ALIAS_LDPSW, "ldpsw" },
{ AARCH64_INS_ALIAS_LDRSH, "ldrsh" },
{ AARCH64_INS_ALIAS_LDRSB, "ldrsb" },
{ AARCH64_INS_ALIAS_LDRSW, "ldrsw" },
{ AARCH64_INS_ALIAS_LDURH, "ldurh" },
{ AARCH64_INS_ALIAS_LDURB, "ldurb" },
{ AARCH64_INS_ALIAS_LDURSH, "ldursh" },
{ AARCH64_INS_ALIAS_LDURSB, "ldursb" },
{ AARCH64_INS_ALIAS_LDURSW, "ldursw" },
{ AARCH64_INS_ALIAS_LDTRH, "ldtrh" },
{ AARCH64_INS_ALIAS_LDTRB, "ldtrb" },
{ AARCH64_INS_ALIAS_LDTRSH, "ldtrsh" },
{ AARCH64_INS_ALIAS_LDTRSB, "ldtrsb" },
{ AARCH64_INS_ALIAS_LDTRSW, "ldtrsw" },
{ AARCH64_INS_ALIAS_STP, "stp" },
{ AARCH64_INS_ALIAS_STURH, "sturh" },
{ AARCH64_INS_ALIAS_STURB, "sturb" },
{ AARCH64_INS_ALIAS_STLURH, "stlurh" },
{ AARCH64_INS_ALIAS_LDAPURSB, "ldapursb" },
{ AARCH64_INS_ALIAS_LDAPURH, "ldapurh" },
{ AARCH64_INS_ALIAS_LDAPURSH, "ldapursh" },
{ AARCH64_INS_ALIAS_LDAPURSW, "ldapursw" },
{ AARCH64_INS_ALIAS_STTRH, "sttrh" },
{ AARCH64_INS_ALIAS_STTRB, "sttrb" },
{ AARCH64_INS_ALIAS_BIC_4H, "bic_4h" },
{ AARCH64_INS_ALIAS_BIC_8H, "bic_8h" },
{ AARCH64_INS_ALIAS_BIC_2S, "bic_2s" },
{ AARCH64_INS_ALIAS_BIC_4S, "bic_4s" },
{ AARCH64_INS_ALIAS_ORR_4H, "orr_4h" },
{ AARCH64_INS_ALIAS_ORR_8H, "orr_8h" },
{ AARCH64_INS_ALIAS_ORR_2S, "orr_2s" },
{ AARCH64_INS_ALIAS_ORR_4S, "orr_4s" },
{ AARCH64_INS_ALIAS_SXTL_8H, "sxtl_8h" },
{ AARCH64_INS_ALIAS_SXTL, "sxtl" },
{ AARCH64_INS_ALIAS_SXTL_4S, "sxtl_4s" },
{ AARCH64_INS_ALIAS_SXTL_2D, "sxtl_2d" },
{ AARCH64_INS_ALIAS_SXTL2_8H, "sxtl2_8h" },
{ AARCH64_INS_ALIAS_SXTL2, "sxtl2" },
{ AARCH64_INS_ALIAS_SXTL2_4S, "sxtl2_4s" },
{ AARCH64_INS_ALIAS_SXTL2_2D, "sxtl2_2d" },
{ AARCH64_INS_ALIAS_UXTL_8H, "uxtl_8h" },
{ AARCH64_INS_ALIAS_UXTL, "uxtl" },
{ AARCH64_INS_ALIAS_UXTL_4S, "uxtl_4s" },
{ AARCH64_INS_ALIAS_UXTL_2D, "uxtl_2d" },
{ AARCH64_INS_ALIAS_UXTL2_8H, "uxtl2_8h" },
{ AARCH64_INS_ALIAS_UXTL2, "uxtl2" },
{ AARCH64_INS_ALIAS_UXTL2_4S, "uxtl2_4s" },
{ AARCH64_INS_ALIAS_UXTL2_2D, "uxtl2_2d" },
{ AARCH64_INS_ALIAS_LD2, "ld2" },
{ AARCH64_INS_ALIAS_LD3, "ld3" },
{ AARCH64_INS_ALIAS_LD4, "ld4" },
{ AARCH64_INS_ALIAS_ST1, "st1" },
{ AARCH64_INS_ALIAS_ST2, "st2" },
{ AARCH64_INS_ALIAS_ST3, "st3" },
{ AARCH64_INS_ALIAS_ST4, "st4" },
{ AARCH64_INS_ALIAS_LD2R, "ld2r" },
{ AARCH64_INS_ALIAS_LD3R, "ld3r" },
{ AARCH64_INS_ALIAS_LD4R, "ld4r" },
{ AARCH64_INS_ALIAS_CLRBHB, "clrbhb" },
{ AARCH64_INS_ALIAS_STILP, "stilp" },
{ AARCH64_INS_ALIAS_STL1, "stl1" },
{ AARCH64_INS_ALIAS_SYSP, "sysp" },
{ AARCH64_INS_ALIAS_LD1SW, "ld1sw" },
{ AARCH64_INS_ALIAS_LD1H, "ld1h" },
{ AARCH64_INS_ALIAS_LD1SH, "ld1sh" },
{ AARCH64_INS_ALIAS_LD1D, "ld1d" },
{ AARCH64_INS_ALIAS_LD1RSW, "ld1rsw" },
{ AARCH64_INS_ALIAS_LD1RH, "ld1rh" },
{ AARCH64_INS_ALIAS_LD1RSH, "ld1rsh" },
{ AARCH64_INS_ALIAS_LD1RW, "ld1rw" },
{ AARCH64_INS_ALIAS_LD1RSB, "ld1rsb" },
{ AARCH64_INS_ALIAS_LD1RD, "ld1rd" },
{ AARCH64_INS_ALIAS_LD1RQH, "ld1rqh" },
{ AARCH64_INS_ALIAS_LD1RQW, "ld1rqw" },
{ AARCH64_INS_ALIAS_LD1RQD, "ld1rqd" },
{ AARCH64_INS_ALIAS_LDNF1SW, "ldnf1sw" },
{ AARCH64_INS_ALIAS_LDNF1H, "ldnf1h" },
{ AARCH64_INS_ALIAS_LDNF1SH, "ldnf1sh" },
{ AARCH64_INS_ALIAS_LDNF1W, "ldnf1w" },
{ AARCH64_INS_ALIAS_LDNF1SB, "ldnf1sb" },
{ AARCH64_INS_ALIAS_LDNF1D, "ldnf1d" },
{ AARCH64_INS_ALIAS_LDFF1SW, "ldff1sw" },
{ AARCH64_INS_ALIAS_LDFF1H, "ldff1h" },
{ AARCH64_INS_ALIAS_LDFF1SH, "ldff1sh" },
{ AARCH64_INS_ALIAS_LDFF1W, "ldff1w" },
{ AARCH64_INS_ALIAS_LDFF1SB, "ldff1sb" },
{ AARCH64_INS_ALIAS_LDFF1D, "ldff1d" },
{ AARCH64_INS_ALIAS_LD3B, "ld3b" },
{ AARCH64_INS_ALIAS_LD4B, "ld4b" },
{ AARCH64_INS_ALIAS_LD2H, "ld2h" },
{ AARCH64_INS_ALIAS_LD3H, "ld3h" },
{ AARCH64_INS_ALIAS_LD4H, "ld4h" },
{ AARCH64_INS_ALIAS_LD2W, "ld2w" },
{ AARCH64_INS_ALIAS_LD3W, "ld3w" },
{ AARCH64_INS_ALIAS_LD4W, "ld4w" },
{ AARCH64_INS_ALIAS_LD2D, "ld2d" },
{ AARCH64_INS_ALIAS_LD3D, "ld3d" },
{ AARCH64_INS_ALIAS_LD4D, "ld4d" },
{ AARCH64_INS_ALIAS_LD2Q, "ld2q" },
{ AARCH64_INS_ALIAS_LD3Q, "ld3q" },
{ AARCH64_INS_ALIAS_LD4Q, "ld4q" },
{ AARCH64_INS_ALIAS_LDNT1H, "ldnt1h" },
{ AARCH64_INS_ALIAS_LDNT1W, "ldnt1w" },
{ AARCH64_INS_ALIAS_LDNT1D, "ldnt1d" },
{ AARCH64_INS_ALIAS_ST1H, "st1h" },
{ AARCH64_INS_ALIAS_ST1W, "st1w" },
{ AARCH64_INS_ALIAS_ST1D, "st1d" },
{ AARCH64_INS_ALIAS_ST3B, "st3b" },
{ AARCH64_INS_ALIAS_ST4B, "st4b" },
{ AARCH64_INS_ALIAS_ST2H, "st2h" },
{ AARCH64_INS_ALIAS_ST3H, "st3h" },
{ AARCH64_INS_ALIAS_ST4H, "st4h" },
{ AARCH64_INS_ALIAS_ST2W, "st2w" },
{ AARCH64_INS_ALIAS_ST3W, "st3w" },
{ AARCH64_INS_ALIAS_ST4W, "st4w" },
{ AARCH64_INS_ALIAS_ST2D, "st2d" },
{ AARCH64_INS_ALIAS_ST3D, "st3d" },
{ AARCH64_INS_ALIAS_ST4D, "st4d" },
{ AARCH64_INS_ALIAS_ST3Q, "st3q" },
{ AARCH64_INS_ALIAS_ST4Q, "st4q" },
{ AARCH64_INS_ALIAS_STNT1H, "stnt1h" },
{ AARCH64_INS_ALIAS_STNT1W, "stnt1w" },
{ AARCH64_INS_ALIAS_STNT1D, "stnt1d" },
{ AARCH64_INS_ALIAS_PRFH, "prfh" },
{ AARCH64_INS_ALIAS_PRFW, "prfw" },
{ AARCH64_INS_ALIAS_PRFD, "prfd" },
{ AARCH64_INS_ALIAS_CNTH, "cnth" },
{ AARCH64_INS_ALIAS_CNTW, "cntw" },
{ AARCH64_INS_ALIAS_CNTD, "cntd" },
{ AARCH64_INS_ALIAS_DECB, "decb" },
{ AARCH64_INS_ALIAS_INCH, "inch" },
{ AARCH64_INS_ALIAS_DECH, "dech" },
{ AARCH64_INS_ALIAS_INCW, "incw" },
{ AARCH64_INS_ALIAS_DECW, "decw" },
{ AARCH64_INS_ALIAS_INCD, "incd" },
{ AARCH64_INS_ALIAS_DECD, "decd" },
{ AARCH64_INS_ALIAS_SQDECB, "sqdecb" },
{ AARCH64_INS_ALIAS_UQDECB, "uqdecb" },
{ AARCH64_INS_ALIAS_UQINCH, "uqinch" },
{ AARCH64_INS_ALIAS_SQDECH, "sqdech" },
{ AARCH64_INS_ALIAS_UQDECH, "uqdech" },
{ AARCH64_INS_ALIAS_SQINCW, "sqincw" },
{ AARCH64_INS_ALIAS_UQINCW, "uqincw" },
{ AARCH64_INS_ALIAS_SQDECW, "sqdecw" },
{ AARCH64_INS_ALIAS_UQDECW, "uqdecw" },
{ AARCH64_INS_ALIAS_SQINCD, "sqincd" },
{ AARCH64_INS_ALIAS_UQINCD, "uqincd" },
{ AARCH64_INS_ALIAS_SQDECD, "sqdecd" },
{ AARCH64_INS_ALIAS_UQDECD, "uqdecd" },
{ AARCH64_INS_ALIAS_MOVS, "movs" },
{ AARCH64_INS_ALIAS_NOT, "not" },
{ AARCH64_INS_ALIAS_NOTS, "nots" },
{ AARCH64_INS_ALIAS_LD1ROH, "ld1roh" },
{ AARCH64_INS_ALIAS_LD1ROW, "ld1row" },
{ AARCH64_INS_ALIAS_LD1ROD, "ld1rod" },
{ AARCH64_INS_ALIAS_BCAX, "bcax" },
{ AARCH64_INS_ALIAS_BSL, "bsl" },
{ AARCH64_INS_ALIAS_BSL1N, "bsl1n" },
{ AARCH64_INS_ALIAS_BSL2N, "bsl2n" },
{ AARCH64_INS_ALIAS_NBSL, "nbsl" },
{ AARCH64_INS_ALIAS_LDNT1SH, "ldnt1sh" },
{ AARCH64_INS_ALIAS_LDNT1SW, "ldnt1sw" },
arch/AArch64/AArch64GenCSFeatureName.inc
+139
View File
@@ -0,0 +1,139 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ AARCH64_FEATURE_HASV8_0A, "HasV8_0a" },
{ AARCH64_FEATURE_HASV8_1A, "HasV8_1a" },
{ AARCH64_FEATURE_HASV8_2A, "HasV8_2a" },
{ AARCH64_FEATURE_HASV8_3A, "HasV8_3a" },
{ AARCH64_FEATURE_HASV8_4A, "HasV8_4a" },
{ AARCH64_FEATURE_HASV8_5A, "HasV8_5a" },
{ AARCH64_FEATURE_HASV8_6A, "HasV8_6a" },
{ AARCH64_FEATURE_HASV8_7A, "HasV8_7a" },
{ AARCH64_FEATURE_HASV8_8A, "HasV8_8a" },
{ AARCH64_FEATURE_HASV8_9A, "HasV8_9a" },
{ AARCH64_FEATURE_HASV9_0A, "HasV9_0a" },
{ AARCH64_FEATURE_HASV9_1A, "HasV9_1a" },
{ AARCH64_FEATURE_HASV9_2A, "HasV9_2a" },
{ AARCH64_FEATURE_HASV9_3A, "HasV9_3a" },
{ AARCH64_FEATURE_HASV9_4A, "HasV9_4a" },
{ AARCH64_FEATURE_HASV8_0R, "HasV8_0r" },
{ AARCH64_FEATURE_HASEL2VMSA, "HasEL2VMSA" },
{ AARCH64_FEATURE_HASEL3, "HasEL3" },
{ AARCH64_FEATURE_HASVH, "HasVH" },
{ AARCH64_FEATURE_HASLOR, "HasLOR" },
{ AARCH64_FEATURE_HASPAUTH, "HasPAuth" },
{ AARCH64_FEATURE_HASPAUTHLR, "HasPAuthLR" },
{ AARCH64_FEATURE_HASJS, "HasJS" },
{ AARCH64_FEATURE_HASCCIDX, "HasCCIDX" },
{ AARCH64_FEATURE_HASCOMPLXNUM, "HasComplxNum" },
{ AARCH64_FEATURE_HASNV, "HasNV" },
{ AARCH64_FEATURE_HASMPAM, "HasMPAM" },
{ AARCH64_FEATURE_HASDIT, "HasDIT" },
{ AARCH64_FEATURE_HASTRACEV8_4, "HasTRACEV8_4" },
{ AARCH64_FEATURE_HASAM, "HasAM" },
{ AARCH64_FEATURE_HASSEL2, "HasSEL2" },
{ AARCH64_FEATURE_HASTLB_RMI, "HasTLB_RMI" },
{ AARCH64_FEATURE_HASFLAGM, "HasFlagM" },
{ AARCH64_FEATURE_HASRCPC_IMMO, "HasRCPC_IMMO" },
{ AARCH64_FEATURE_HASFPARMV8, "HasFPARMv8" },
{ AARCH64_FEATURE_HASNEON, "HasNEON" },
{ AARCH64_FEATURE_HASSM4, "HasSM4" },
{ AARCH64_FEATURE_HASSHA3, "HasSHA3" },
{ AARCH64_FEATURE_HASSHA2, "HasSHA2" },
{ AARCH64_FEATURE_HASAES, "HasAES" },
{ AARCH64_FEATURE_HASDOTPROD, "HasDotProd" },
{ AARCH64_FEATURE_HASCRC, "HasCRC" },
{ AARCH64_FEATURE_HASCSSC, "HasCSSC" },
{ AARCH64_FEATURE_HASLSE, "HasLSE" },
{ AARCH64_FEATURE_HASRAS, "HasRAS" },
{ AARCH64_FEATURE_HASRDM, "HasRDM" },
{ AARCH64_FEATURE_HASFULLFP16, "HasFullFP16" },
{ AARCH64_FEATURE_HASFP16FML, "HasFP16FML" },
{ AARCH64_FEATURE_HASSPE, "HasSPE" },
{ AARCH64_FEATURE_HASFUSEAES, "HasFuseAES" },
{ AARCH64_FEATURE_HASSVE, "HasSVE" },
{ AARCH64_FEATURE_HASSVE2, "HasSVE2" },
{ AARCH64_FEATURE_HASSVE2P1, "HasSVE2p1" },
{ AARCH64_FEATURE_HASSVE2AES, "HasSVE2AES" },
{ AARCH64_FEATURE_HASSVE2SM4, "HasSVE2SM4" },
{ AARCH64_FEATURE_HASSVE2SHA3, "HasSVE2SHA3" },
{ AARCH64_FEATURE_HASSVE2BITPERM, "HasSVE2BitPerm" },
{ AARCH64_FEATURE_HASB16B16, "HasB16B16" },
{ AARCH64_FEATURE_HASSME, "HasSME" },
{ AARCH64_FEATURE_HASSMEF64F64, "HasSMEF64F64" },
{ AARCH64_FEATURE_HASSMEF16F16, "HasSMEF16F16" },
{ AARCH64_FEATURE_HASSMEFA64, "HasSMEFA64" },
{ AARCH64_FEATURE_HASSMEI16I64, "HasSMEI16I64" },
{ AARCH64_FEATURE_HASSME2, "HasSME2" },
{ AARCH64_FEATURE_HASSME2P1, "HasSME2p1" },
{ AARCH64_FEATURE_HASFPMR, "HasFPMR" },
{ AARCH64_FEATURE_HASFP8, "HasFP8" },
{ AARCH64_FEATURE_HASFAMINMAX, "HasFAMINMAX" },
{ AARCH64_FEATURE_HASFP8FMA, "HasFP8FMA" },
{ AARCH64_FEATURE_HASSSVE_FP8FMA, "HasSSVE_FP8FMA" },
{ AARCH64_FEATURE_HASFP8DOT2, "HasFP8DOT2" },
{ AARCH64_FEATURE_HASSSVE_FP8DOT2, "HasSSVE_FP8DOT2" },
{ AARCH64_FEATURE_HASFP8DOT4, "HasFP8DOT4" },
{ AARCH64_FEATURE_HASSSVE_FP8DOT4, "HasSSVE_FP8DOT4" },
{ AARCH64_FEATURE_HASLUT, "HasLUT" },
{ AARCH64_FEATURE_HASSME_LUTV2, "HasSME_LUTv2" },
{ AARCH64_FEATURE_HASSMEF8F16, "HasSMEF8F16" },
{ AARCH64_FEATURE_HASSMEF8F32, "HasSMEF8F32" },
{ AARCH64_FEATURE_HASSVEORSME, "HasSVEorSME" },
{ AARCH64_FEATURE_HASSVE2ORSME, "HasSVE2orSME" },
{ AARCH64_FEATURE_HASSVE2ORSME2, "HasSVE2orSME2" },
{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME, "HasSVE2p1_or_HasSME" },
{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2, "HasSVE2p1_or_HasSME2" },
{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2P1, "HasSVE2p1_or_HasSME2p1" },
{ AARCH64_FEATURE_HASNEONORSME, "HasNEONorSME" },
{ AARCH64_FEATURE_HASRCPC, "HasRCPC" },
{ AARCH64_FEATURE_HASALTNZCV, "HasAltNZCV" },
{ AARCH64_FEATURE_HASFRINT3264, "HasFRInt3264" },
{ AARCH64_FEATURE_HASSB, "HasSB" },
{ AARCH64_FEATURE_HASPREDRES, "HasPredRes" },
{ AARCH64_FEATURE_HASCCDP, "HasCCDP" },
{ AARCH64_FEATURE_HASBTI, "HasBTI" },
{ AARCH64_FEATURE_HASMTE, "HasMTE" },
{ AARCH64_FEATURE_HASTME, "HasTME" },
{ AARCH64_FEATURE_HASETE, "HasETE" },
{ AARCH64_FEATURE_HASTRBE, "HasTRBE" },
{ AARCH64_FEATURE_HASBF16, "HasBF16" },
{ AARCH64_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
{ AARCH64_FEATURE_HASMATMULFP32, "HasMatMulFP32" },
{ AARCH64_FEATURE_HASMATMULFP64, "HasMatMulFP64" },
{ AARCH64_FEATURE_HASXS, "HasXS" },
{ AARCH64_FEATURE_HASWFXT, "HasWFxT" },
{ AARCH64_FEATURE_HASLS64, "HasLS64" },
{ AARCH64_FEATURE_HASBRBE, "HasBRBE" },
{ AARCH64_FEATURE_HASSPE_EEF, "HasSPE_EEF" },
{ AARCH64_FEATURE_HASHBC, "HasHBC" },
{ AARCH64_FEATURE_HASMOPS, "HasMOPS" },
{ AARCH64_FEATURE_HASCLRBHB, "HasCLRBHB" },
{ AARCH64_FEATURE_HASSPECRES2, "HasSPECRES2" },
{ AARCH64_FEATURE_HASITE, "HasITE" },
{ AARCH64_FEATURE_HASTHE, "HasTHE" },
{ AARCH64_FEATURE_HASRCPC3, "HasRCPC3" },
{ AARCH64_FEATURE_HASLSE128, "HasLSE128" },
{ AARCH64_FEATURE_HASD128, "HasD128" },
{ AARCH64_FEATURE_HASCHK, "HasCHK" },
{ AARCH64_FEATURE_HASGCS, "HasGCS" },
{ AARCH64_FEATURE_HASCPA, "HasCPA" },
{ AARCH64_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
{ AARCH64_FEATURE_HASAMX, "HasAMX" },
{ AARCH64_FEATURE_HASMUL53, "HasMUL53" },
{ AARCH64_FEATURE_HASAPPLESYS, "HasAppleSys" },
{ AARCH64_FEATURE_HASCCPP, "HasCCPP" },
{ AARCH64_FEATURE_HASPAN, "HasPAN" },
{ AARCH64_FEATURE_HASPSUAO, "HasPsUAO" },
{ AARCH64_FEATURE_HASPAN_RWV, "HasPAN_RWV" },
{ AARCH64_FEATURE_HASCONTEXTIDREL2, "HasCONTEXTIDREL2" },
arch/AArch64/AArch64GenCSMappingInsn.inc
+64676
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arch/AArch64/AArch64GenCSMappingInsnName.inc
+1435
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arch/AArch64/AArch64GenCSMappingInsnOp.inc
+55762
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arch/AArch64/AArch64GenCSOpGroup.inc
+181
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@@ -0,0 +1,181 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
AArch64_OP_GROUP_AMNoIndex = 0,
AArch64_OP_GROUP_AdrLabel = 1,
AArch64_OP_GROUP_AdrpLabel = 2,
AArch64_OP_GROUP_BTIHintOp = 3,
AArch64_OP_GROUP_ImplicitlyTypedVectorList = 4,
AArch64_OP_GROUP_InverseCondCode = 5,
AArch64_OP_GROUP_LogicalImm_int16_t = 6,
AArch64_OP_GROUP_LogicalImm_int8_t = 7,
AArch64_OP_GROUP_MatrixIndex_0 = 8,
AArch64_OP_GROUP_MatrixIndex_1 = 9,
AArch64_OP_GROUP_MatrixIndex_8 = 10,
AArch64_OP_GROUP_PSBHintOp = 11,
AArch64_OP_GROUP_PrefetchOp_1 = 12,
AArch64_OP_GROUP_SVELogicalImm_int16_t = 13,
AArch64_OP_GROUP_SVELogicalImm_int32_t = 14,
AArch64_OP_GROUP_SVELogicalImm_int64_t = 15,
AArch64_OP_GROUP_SVERegOp_0 = 16,
AArch64_OP_GROUP_VectorIndex_8 = 17,
AArch64_OP_GROUP_ZPRasFPR_128 = 18,
AArch64_OP_GROUP_Operand = 19,
AArch64_OP_GROUP_SVERegOp_b = 20,
AArch64_OP_GROUP_SVERegOp_d = 21,
AArch64_OP_GROUP_SVERegOp_h = 22,
AArch64_OP_GROUP_SVERegOp_s = 23,
AArch64_OP_GROUP_TypedVectorList_0_d = 24,
AArch64_OP_GROUP_TypedVectorList_0_s = 25,
AArch64_OP_GROUP_VRegOperand = 26,
AArch64_OP_GROUP_TypedVectorList_0_h = 27,
AArch64_OP_GROUP_VectorIndex_1 = 28,
AArch64_OP_GROUP_ImmRangeScale_2_1 = 29,
AArch64_OP_GROUP_AlignedLabel = 30,
AArch64_OP_GROUP_CondCode = 31,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 32,
AArch64_OP_GROUP_TypedVectorList_0_b = 33,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 34,
AArch64_OP_GROUP_ImmRangeScale_4_3 = 35,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 36,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 37,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 38,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 39,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 40,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 41,
AArch64_OP_GROUP_ImmScale_8 = 42,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 43,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 44,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 45,
AArch64_OP_GROUP_ImmScale_2 = 46,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 47,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 48,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 49,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 50,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 51,
AArch64_OP_GROUP_ImmScale_4 = 52,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 53,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 54,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 55,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 56,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 57,
AArch64_OP_GROUP_PredicateAsCounter_0 = 58,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 59,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 60,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 61,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 62,
AArch64_OP_GROUP_SVCROp = 63,
AArch64_OP_GROUP_ImmScale_16 = 64,
AArch64_OP_GROUP_MatrixTile = 65,
AArch64_OP_GROUP_Shifter = 66,
AArch64_OP_GROUP_AddSubImm = 67,
AArch64_OP_GROUP_ShiftedRegister = 68,
AArch64_OP_GROUP_ExtendedRegister = 69,
AArch64_OP_GROUP_ArithExtend = 70,
AArch64_OP_GROUP_Matrix_64 = 71,
AArch64_OP_GROUP_Matrix_32 = 72,
AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 73,
AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 74,
AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 75,
AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 76,
AArch64_OP_GROUP_AdrAdrpLabel = 77,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 78,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 79,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 80,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 81,
AArch64_OP_GROUP_LogicalImm_int32_t = 82,
AArch64_OP_GROUP_LogicalImm_int64_t = 83,
AArch64_OP_GROUP_ZPRasFPR_8 = 84,
AArch64_OP_GROUP_ZPRasFPR_64 = 85,
AArch64_OP_GROUP_ZPRasFPR_16 = 86,
AArch64_OP_GROUP_ZPRasFPR_32 = 87,
AArch64_OP_GROUP_Matrix_16 = 88,
AArch64_OP_GROUP_Imm = 89,
AArch64_OP_GROUP_ImmHex = 90,
AArch64_OP_GROUP_ComplexRotationOp_180_90 = 91,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 92,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 93,
AArch64_OP_GROUP_ComplexRotationOp_90_0 = 94,
AArch64_OP_GROUP_SVEPattern = 95,
AArch64_OP_GROUP_PredicateAsCounter_8 = 96,
AArch64_OP_GROUP_SVEVecLenSpecifier = 97,
AArch64_OP_GROUP_PredicateAsCounter_64 = 98,
AArch64_OP_GROUP_PredicateAsCounter_16 = 99,
AArch64_OP_GROUP_PredicateAsCounter_32 = 100,
AArch64_OP_GROUP_Imm8OptLsl_int8_t = 101,
AArch64_OP_GROUP_Imm8OptLsl_int64_t = 102,
AArch64_OP_GROUP_Imm8OptLsl_int16_t = 103,
AArch64_OP_GROUP_Imm8OptLsl_int32_t = 104,
AArch64_OP_GROUP_BarrierOption = 105,
AArch64_OP_GROUP_BarriernXSOption = 106,
AArch64_OP_GROUP_SVERegOp_q = 107,
AArch64_OP_GROUP_MatrixTileVector_0 = 108,
AArch64_OP_GROUP_MatrixTileVector_1 = 109,
AArch64_OP_GROUP_FPImmOperand = 110,
AArch64_OP_GROUP_TypedVectorList_0_q = 111,
AArch64_OP_GROUP_SImm_8 = 112,
AArch64_OP_GROUP_SImm_16 = 113,
AArch64_OP_GROUP_TypedVectorList_16_b = 114,
AArch64_OP_GROUP_PostIncOperand_64 = 115,
AArch64_OP_GROUP_TypedVectorList_1_d = 116,
AArch64_OP_GROUP_PostIncOperand_32 = 117,
AArch64_OP_GROUP_TypedVectorList_2_d = 118,
AArch64_OP_GROUP_TypedVectorList_2_s = 119,
AArch64_OP_GROUP_TypedVectorList_4_h = 120,
AArch64_OP_GROUP_TypedVectorList_4_s = 121,
AArch64_OP_GROUP_TypedVectorList_8_b = 122,
AArch64_OP_GROUP_TypedVectorList_8_h = 123,
AArch64_OP_GROUP_PostIncOperand_16 = 124,
AArch64_OP_GROUP_PostIncOperand_8 = 125,
AArch64_OP_GROUP_ImmScale_32 = 126,
AArch64_OP_GROUP_PostIncOperand_1 = 127,
AArch64_OP_GROUP_PostIncOperand_4 = 128,
AArch64_OP_GROUP_PostIncOperand_2 = 129,
AArch64_OP_GROUP_PostIncOperand_48 = 130,
AArch64_OP_GROUP_PostIncOperand_24 = 131,
AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 132,
AArch64_OP_GROUP_ImmScale_3 = 133,
AArch64_OP_GROUP_PostIncOperand_3 = 134,
AArch64_OP_GROUP_PostIncOperand_12 = 135,
AArch64_OP_GROUP_PostIncOperand_6 = 136,
AArch64_OP_GROUP_GPR64x8 = 137,
AArch64_OP_GROUP_MemExtend_w_8 = 138,
AArch64_OP_GROUP_MemExtend_x_8 = 139,
AArch64_OP_GROUP_UImm12Offset_1 = 140,
AArch64_OP_GROUP_MemExtend_w_64 = 141,
AArch64_OP_GROUP_MemExtend_x_64 = 142,
AArch64_OP_GROUP_UImm12Offset_8 = 143,
AArch64_OP_GROUP_MemExtend_w_16 = 144,
AArch64_OP_GROUP_MemExtend_x_16 = 145,
AArch64_OP_GROUP_UImm12Offset_2 = 146,
AArch64_OP_GROUP_MemExtend_w_128 = 147,
AArch64_OP_GROUP_MemExtend_x_128 = 148,
AArch64_OP_GROUP_UImm12Offset_16 = 149,
AArch64_OP_GROUP_MemExtend_w_32 = 150,
AArch64_OP_GROUP_MemExtend_x_32 = 151,
AArch64_OP_GROUP_UImm12Offset_4 = 152,
AArch64_OP_GROUP_Matrix_0 = 153,
AArch64_OP_GROUP_TypedVectorList_0_0 = 154,
AArch64_OP_GROUP_SIMDType10Operand = 155,
AArch64_OP_GROUP_MRSSystemRegister = 156,
AArch64_OP_GROUP_MSRSystemRegister = 157,
AArch64_OP_GROUP_SystemPStateField = 158,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 159,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 160,
AArch64_OP_GROUP_PrefetchOp_0 = 161,
AArch64_OP_GROUP_RPRFMOperand = 162,
AArch64_OP_GROUP_AppleSysBarrierOption = 163,
AArch64_OP_GROUP_GPR64as32 = 164,
AArch64_OP_GROUP_SysCROperand = 165,
AArch64_OP_GROUP_SyspXzrPair = 166,
AArch64_OP_GROUP_MatrixTileList = 167,
arch/AArch64/AArch64GenDisassemblerTables.inc
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arch/AArch64/AArch64GenInstrInfo.inc
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arch/AArch64/AArch64GenRegisterInfo.inc
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arch/AArch64/AArch64GenSubtargetInfo.inc
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
AArch64_FeatureAES = 0,
AArch64_FeatureALULSLFast = 1,
AArch64_FeatureAM = 2,
AArch64_FeatureAMVS = 3,
AArch64_FeatureAMX = 4,
AArch64_FeatureAddrLSLFast = 5,
AArch64_FeatureAggressiveFMA = 6,
AArch64_FeatureAll = 7,
AArch64_FeatureAltFPCmp = 8,
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 9,
AArch64_FeatureAppleA7SysReg = 10,
AArch64_FeatureAppleSys = 11,
AArch64_FeatureArithmeticBccFusion = 12,
AArch64_FeatureArithmeticCbzFusion = 13,
AArch64_FeatureAscendStoreAddress = 14,
AArch64_FeatureB16B16 = 15,
AArch64_FeatureBF16 = 16,
AArch64_FeatureBRBE = 17,
AArch64_FeatureBalanceFPOps = 18,
AArch64_FeatureBranchTargetId = 19,
AArch64_FeatureCCIDX = 20,
AArch64_FeatureCCPP = 21,
AArch64_FeatureCHK = 22,
AArch64_FeatureCLRBHB = 23,
AArch64_FeatureCONTEXTIDREL2 = 24,
AArch64_FeatureCPA = 25,
AArch64_FeatureCRC = 26,
AArch64_FeatureCSSC = 27,
AArch64_FeatureCacheDeepPersist = 28,
AArch64_FeatureCallSavedX8 = 29,
AArch64_FeatureCallSavedX9 = 30,
AArch64_FeatureCallSavedX10 = 31,
AArch64_FeatureCallSavedX11 = 32,
AArch64_FeatureCallSavedX12 = 33,
AArch64_FeatureCallSavedX13 = 34,
AArch64_FeatureCallSavedX14 = 35,
AArch64_FeatureCallSavedX15 = 36,
AArch64_FeatureCallSavedX18 = 37,
AArch64_FeatureCmpBccFusion = 38,
AArch64_FeatureComplxNum = 39,
AArch64_FeatureCrypto = 40,
AArch64_FeatureD128 = 41,
AArch64_FeatureDIT = 42,
AArch64_FeatureDisableLatencySchedHeuristic = 43,
AArch64_FeatureDisableLdp = 44,
AArch64_FeatureDisableStp = 45,
AArch64_FeatureDotProd = 46,
AArch64_FeatureEL2VMSA = 47,
AArch64_FeatureEL3 = 48,
AArch64_FeatureETE = 49,
AArch64_FeatureEnableSelectOptimize = 50,
AArch64_FeatureEnhancedCounterVirtualization = 51,
AArch64_FeatureExperimentalZeroingPseudos = 52,
AArch64_FeatureExynosCheapAsMoveHandling = 53,
AArch64_FeatureFAMINMAX = 54,
AArch64_FeatureFMV = 55,
AArch64_FeatureFP8 = 56,
AArch64_FeatureFP8DOT2 = 57,
AArch64_FeatureFP8DOT4 = 58,
AArch64_FeatureFP8FMA = 59,
AArch64_FeatureFP16FML = 60,
AArch64_FeatureFPARMv8 = 61,
AArch64_FeatureFPMR = 62,
AArch64_FeatureFRInt3264 = 63,
AArch64_FeatureFineGrainedTraps = 64,
AArch64_FeatureFixCortexA53_835769 = 65,
AArch64_FeatureFlagM = 66,
AArch64_FeatureForce32BitJumpTables = 67,
AArch64_FeatureFullFP16 = 68,
AArch64_FeatureFuseAES = 69,
AArch64_FeatureFuseAddSub2RegAndConstOne = 70,
AArch64_FeatureFuseAddress = 71,
AArch64_FeatureFuseAdrpAdd = 72,
AArch64_FeatureFuseArithmeticLogic = 73,
AArch64_FeatureFuseCCSelect = 74,
AArch64_FeatureFuseCryptoEOR = 75,
AArch64_FeatureFuseLiterals = 76,
AArch64_FeatureGCS = 77,
AArch64_FeatureHBC = 78,
AArch64_FeatureHCX = 79,
AArch64_FeatureHardenSlsBlr = 80,
AArch64_FeatureHardenSlsNoComdat = 81,
AArch64_FeatureHardenSlsRetBr = 82,
AArch64_FeatureITE = 83,
AArch64_FeatureJS = 84,
AArch64_FeatureLOR = 85,
AArch64_FeatureLS64 = 86,
AArch64_FeatureLSE = 87,
AArch64_FeatureLSE2 = 88,
AArch64_FeatureLSE128 = 89,
AArch64_FeatureLUT = 90,
AArch64_FeatureLdpAlignedOnly = 91,
AArch64_FeatureMEC = 92,
AArch64_FeatureMOPS = 93,
AArch64_FeatureMPAM = 94,
AArch64_FeatureMTE = 95,
AArch64_FeatureMUL53 = 96,
AArch64_FeatureMatMulFP32 = 97,
AArch64_FeatureMatMulFP64 = 98,
AArch64_FeatureMatMulInt8 = 99,
AArch64_FeatureNEON = 100,
AArch64_FeatureNMI = 101,
AArch64_FeatureNV = 102,
AArch64_FeatureNoBTIAtReturnTwice = 103,
AArch64_FeatureNoNegativeImmediates = 104,
AArch64_FeatureNoSVEFPLD1R = 105,
AArch64_FeatureNoZCZeroingFP = 106,
AArch64_FeatureOutlineAtomics = 107,
AArch64_FeaturePAN = 108,
AArch64_FeaturePAN_RWV = 109,
AArch64_FeaturePAuth = 110,
AArch64_FeaturePAuthLR = 111,
AArch64_FeaturePRFM_SLC = 112,
AArch64_FeaturePerfMon = 113,
AArch64_FeaturePostRAScheduler = 114,
AArch64_FeaturePredRes = 115,
AArch64_FeaturePredictableSelectIsExpensive = 116,
AArch64_FeaturePsUAO = 117,
AArch64_FeatureRAS = 118,
AArch64_FeatureRASv2 = 119,
AArch64_FeatureRCPC = 120,
AArch64_FeatureRCPC3 = 121,
AArch64_FeatureRCPC_IMMO = 122,
AArch64_FeatureRDM = 123,
AArch64_FeatureRME = 124,
AArch64_FeatureRandGen = 125,
AArch64_FeatureReserveX1 = 126,
AArch64_FeatureReserveX2 = 127,
AArch64_FeatureReserveX3 = 128,
AArch64_FeatureReserveX4 = 129,
AArch64_FeatureReserveX5 = 130,
AArch64_FeatureReserveX6 = 131,
AArch64_FeatureReserveX7 = 132,
AArch64_FeatureReserveX9 = 133,
AArch64_FeatureReserveX10 = 134,
AArch64_FeatureReserveX11 = 135,
AArch64_FeatureReserveX12 = 136,
AArch64_FeatureReserveX13 = 137,
AArch64_FeatureReserveX14 = 138,
AArch64_FeatureReserveX15 = 139,
AArch64_FeatureReserveX18 = 140,
AArch64_FeatureReserveX20 = 141,
AArch64_FeatureReserveX21 = 142,
AArch64_FeatureReserveX22 = 143,
AArch64_FeatureReserveX23 = 144,
AArch64_FeatureReserveX24 = 145,
AArch64_FeatureReserveX25 = 146,
AArch64_FeatureReserveX26 = 147,
AArch64_FeatureReserveX27 = 148,
AArch64_FeatureReserveX28 = 149,
AArch64_FeatureReserveX30 = 150,
AArch64_FeatureSB = 151,
AArch64_FeatureSEL2 = 152,
AArch64_FeatureSHA2 = 153,
AArch64_FeatureSHA3 = 154,
AArch64_FeatureSM4 = 155,
AArch64_FeatureSME = 156,
AArch64_FeatureSME2 = 157,
AArch64_FeatureSME2p1 = 158,
AArch64_FeatureSMEF8F16 = 159,
AArch64_FeatureSMEF8F32 = 160,
AArch64_FeatureSMEF16F16 = 161,
AArch64_FeatureSMEF64F64 = 162,
AArch64_FeatureSMEFA64 = 163,
AArch64_FeatureSMEI16I64 = 164,
AArch64_FeatureSME_LUTv2 = 165,
AArch64_FeatureSPE = 166,
AArch64_FeatureSPECRES2 = 167,
AArch64_FeatureSPE_EEF = 168,
AArch64_FeatureSSBS = 169,
AArch64_FeatureSSVE_FP8DOT2 = 170,
AArch64_FeatureSSVE_FP8DOT4 = 171,
AArch64_FeatureSSVE_FP8FMA = 172,
AArch64_FeatureSVE = 173,
AArch64_FeatureSVE2 = 174,
AArch64_FeatureSVE2AES = 175,
AArch64_FeatureSVE2BitPerm = 176,
AArch64_FeatureSVE2SHA3 = 177,
AArch64_FeatureSVE2SM4 = 178,
AArch64_FeatureSVE2p1 = 179,
AArch64_FeatureSlowMisaligned128Store = 180,
AArch64_FeatureSlowPaired128 = 181,
AArch64_FeatureSlowSTRQro = 182,
AArch64_FeatureSpecRestrict = 183,
AArch64_FeatureStorePairSuppress = 184,
AArch64_FeatureStpAlignedOnly = 185,
AArch64_FeatureStrictAlign = 186,
AArch64_FeatureTHE = 187,
AArch64_FeatureTLBIW = 188,
AArch64_FeatureTLB_RMI = 189,
AArch64_FeatureTME = 190,
AArch64_FeatureTRACEV8_4 = 191,
AArch64_FeatureTRBE = 192,
AArch64_FeatureTaggedGlobals = 193,
AArch64_FeatureUseEL1ForTP = 194,
AArch64_FeatureUseEL2ForTP = 195,
AArch64_FeatureUseEL3ForTP = 196,
AArch64_FeatureUseROEL0ForTP = 197,
AArch64_FeatureUseRSqrt = 198,
AArch64_FeatureUseScalarIncVL = 199,
AArch64_FeatureVH = 200,
AArch64_FeatureWFxT = 201,
AArch64_FeatureXS = 202,
AArch64_FeatureZCRegMove = 203,
AArch64_FeatureZCZeroing = 204,
AArch64_FeatureZCZeroingFPWorkaround = 205,
AArch64_FeatureZCZeroingGP = 206,
AArch64_HasV8_0aOps = 207,
AArch64_HasV8_0rOps = 208,
AArch64_HasV8_1aOps = 209,
AArch64_HasV8_2aOps = 210,
AArch64_HasV8_3aOps = 211,
AArch64_HasV8_4aOps = 212,
AArch64_HasV8_5aOps = 213,
AArch64_HasV8_6aOps = 214,
AArch64_HasV8_7aOps = 215,
AArch64_HasV8_8aOps = 216,
AArch64_HasV8_9aOps = 217,
AArch64_HasV9_0aOps = 218,
AArch64_HasV9_1aOps = 219,
AArch64_HasV9_2aOps = 220,
AArch64_HasV9_3aOps = 221,
AArch64_HasV9_4aOps = 222,
AArch64_HasV9_5aOps = 223,
AArch64_TuneA35 = 224,
AArch64_TuneA53 = 225,
AArch64_TuneA55 = 226,
AArch64_TuneA57 = 227,
AArch64_TuneA64FX = 228,
AArch64_TuneA65 = 229,
AArch64_TuneA72 = 230,
AArch64_TuneA73 = 231,
AArch64_TuneA75 = 232,
AArch64_TuneA76 = 233,
AArch64_TuneA77 = 234,
AArch64_TuneA78 = 235,
AArch64_TuneA78C = 236,
AArch64_TuneA510 = 237,
AArch64_TuneA520 = 238,
AArch64_TuneA710 = 239,
AArch64_TuneA715 = 240,
AArch64_TuneA720 = 241,
AArch64_TuneAmpere1 = 242,
AArch64_TuneAmpere1A = 243,
AArch64_TuneAmpere1B = 244,
AArch64_TuneAppleA7 = 245,
AArch64_TuneAppleA10 = 246,
AArch64_TuneAppleA11 = 247,
AArch64_TuneAppleA12 = 248,
AArch64_TuneAppleA13 = 249,
AArch64_TuneAppleA14 = 250,
AArch64_TuneAppleA15 = 251,
AArch64_TuneAppleA16 = 252,
AArch64_TuneAppleA17 = 253,
AArch64_TuneCarmel = 254,
AArch64_TuneExynosM3 = 255,
AArch64_TuneExynosM4 = 256,
AArch64_TuneFalkor = 257,
AArch64_TuneKryo = 258,
AArch64_TuneNeoverse512TVB = 259,
AArch64_TuneNeoverseE1 = 260,
AArch64_TuneNeoverseN1 = 261,
AArch64_TuneNeoverseN2 = 262,
AArch64_TuneNeoverseV1 = 263,
AArch64_TuneNeoverseV2 = 264,
AArch64_TuneR82 = 265,
AArch64_TuneSaphira = 266,
AArch64_TuneTSV110 = 267,
AArch64_TuneThunderX = 268,
AArch64_TuneThunderX2T99 = 269,
AArch64_TuneThunderX3T110 = 270,
AArch64_TuneThunderXT81 = 271,
AArch64_TuneThunderXT83 = 272,
AArch64_TuneThunderXT88 = 273,
AArch64_TuneX1 = 274,
AArch64_TuneX2 = 275,
AArch64_TuneX3 = 276,
AArch64_TuneX4 = 277,
AArch64_NumSubtargetFeatures = 278
};
#endif // GET_SUBTARGETINFO_ENUM
arch/AArch64/AArch64GenSystemOperands.inc
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arch/AArch64/AArch64GenSystemRegister.inc
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arch/AArch64/AArch64InstPrinter.c
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arch/AArch64/AArch64InstPrinter.h
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an AArch64 MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "AArch64Mapping.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInstPrinter.h"
#include "../../SStream.h"
#include "../../utils.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define CHAR(c) #c[0]
void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
void printRegName(SStream *OS, unsigned Reg);
void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
// Autogenerated by tblgen.
const char *getRegName(unsigned Reg);
bool printSysAlias(MCInst *MI, SStream *O);
bool printSyspAlias(MCInst *MI, SStream *O);
bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot);
// Operand printers
void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printImm(MCInst *MI, unsigned OpNo, SStream *O);
void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
#define DECLARE_printSImm(Size) \
void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O);
DECLARE_printSImm(16);
DECLARE_printSImm(8);
#define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O);
DECLARE_printImmSVE(int16_t);
DECLARE_printImmSVE(int8_t);
DECLARE_printImmSVE(int64_t);
DECLARE_printImmSVE(int32_t);
DECLARE_printImmSVE(uint16_t);
DECLARE_printImmSVE(uint8_t);
DECLARE_printImmSVE(uint64_t);
DECLARE_printImmSVE(uint32_t);
void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
#define DEFINE_printPostIncOperand(Amount) \
static inline void CONCAT(printPostIncOperand, Amount)( \
MCInst * MI, unsigned OpNo, SStream *O) \
{ \
AArch64_add_cs_detail_1( \
MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
OpNo, Amount); \
printPostIncOperand(MI, OpNo, Amount, O); \
}
DEFINE_printPostIncOperand(64);
DEFINE_printPostIncOperand(32);
DEFINE_printPostIncOperand(16);
DEFINE_printPostIncOperand(8);
DEFINE_printPostIncOperand(1);
DEFINE_printPostIncOperand(4);
DEFINE_printPostIncOperand(2);
DEFINE_printPostIncOperand(48);
DEFINE_printPostIncOperand(24);
DEFINE_printPostIncOperand(3);
DEFINE_printPostIncOperand(12);
DEFINE_printPostIncOperand(6);
void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printLogicalImm(T) \
void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printLogicalImm(int64_t);
DECLARE_printLogicalImm(int32_t);
DECLARE_printLogicalImm(int8_t);
DECLARE_printLogicalImm(int16_t);
void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
unsigned Width);
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
unsigned Width);
#define DEFINE_printMemExtend(SrcRegKind, Width) \
static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
MCInst * MI, unsigned OpNum, SStream *O) \
{ \
AArch64_add_cs_detail_2( \
MI, \
CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
Width), \
OpNum, CHAR(SrcRegKind), Width); \
printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
}
DEFINE_printMemExtend(w, 8);
DEFINE_printMemExtend(x, 8);
DEFINE_printMemExtend(w, 64);
DEFINE_printMemExtend(x, 64);
DEFINE_printMemExtend(w, 16);
DEFINE_printMemExtend(x, 16);
DEFINE_printMemExtend(w, 128);
DEFINE_printMemExtend(x, 128);
DEFINE_printMemExtend(w, 32);
DEFINE_printMemExtend(x, 32);
#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
Suffix) \
void CONCAT(printRegWithShiftExtend, \
CONCAT(SignedExtend, \
CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printRegWithShiftExtend(false, 8, x, d);
DECLARE_printRegWithShiftExtend(true, 8, w, d);
DECLARE_printRegWithShiftExtend(false, 8, w, d);
DECLARE_printRegWithShiftExtend(false, 8, x, 0);
DECLARE_printRegWithShiftExtend(true, 8, w, s);
DECLARE_printRegWithShiftExtend(false, 8, w, s);
DECLARE_printRegWithShiftExtend(false, 64, x, d);
DECLARE_printRegWithShiftExtend(true, 64, w, d);
DECLARE_printRegWithShiftExtend(false, 64, w, d);
DECLARE_printRegWithShiftExtend(false, 64, x, 0);
DECLARE_printRegWithShiftExtend(true, 64, w, s);
DECLARE_printRegWithShiftExtend(false, 64, w, s);
DECLARE_printRegWithShiftExtend(false, 16, x, d);
DECLARE_printRegWithShiftExtend(true, 16, w, d);
DECLARE_printRegWithShiftExtend(false, 16, w, d);
DECLARE_printRegWithShiftExtend(false, 16, x, 0);
DECLARE_printRegWithShiftExtend(true, 16, w, s);
DECLARE_printRegWithShiftExtend(false, 16, w, s);
DECLARE_printRegWithShiftExtend(false, 32, x, d);
DECLARE_printRegWithShiftExtend(true, 32, w, d);
DECLARE_printRegWithShiftExtend(false, 32, w, d);
DECLARE_printRegWithShiftExtend(false, 32, x, 0);
DECLARE_printRegWithShiftExtend(true, 32, w, s);
DECLARE_printRegWithShiftExtend(false, 32, w, s);
DECLARE_printRegWithShiftExtend(false, 8, x, s);
DECLARE_printRegWithShiftExtend(false, 16, x, s);
DECLARE_printRegWithShiftExtend(false, 32, x, s);
DECLARE_printRegWithShiftExtend(false, 64, x, s);
DECLARE_printRegWithShiftExtend(false, 128, x, 0);
void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
#define DEFINE_printUImm12Offset(Scale) \
static inline void CONCAT(printUImm12Offset, Scale)( \
MCInst * MI, unsigned OpNum, SStream *O) \
{ \
AArch64_add_cs_detail_1( \
MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
OpNum, Scale); \
printUImm12Offset(MI, OpNum, Scale, O); \
}
DEFINE_printUImm12Offset(1);
DEFINE_printUImm12Offset(8);
DEFINE_printUImm12Offset(2);
DEFINE_printUImm12Offset(16);
DEFINE_printUImm12Offset(4);
void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printImmScale(Scale) \
void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printImmScale(8);
DECLARE_printImmScale(2);
DECLARE_printImmScale(4);
DECLARE_printImmScale(16);
DECLARE_printImmScale(32);
DECLARE_printImmScale(3);
#define DECLARE_printImmRangeScale(Scale, Offset) \
void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printImmRangeScale(2, 1);
DECLARE_printImmRangeScale(4, 3);
#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
void CONCAT(printPrefetchOp, \
IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printPrefetchOp(true);
DECLARE_printPrefetchOp(false);
void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
const char *LayoutSuffix);
void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
/// (i.e. attached to the instruction rather than the registers).
/// Print a list of vector registers where the type suffix is implicit
void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printTypedVectorList(NumLanes, LaneKind) \
void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printTypedVectorList(0, b);
DECLARE_printTypedVectorList(0, d);
DECLARE_printTypedVectorList(0, h);
DECLARE_printTypedVectorList(0, s);
DECLARE_printTypedVectorList(0, q);
DECLARE_printTypedVectorList(16, b);
DECLARE_printTypedVectorList(1, d);
DECLARE_printTypedVectorList(2, d);
DECLARE_printTypedVectorList(2, s);
DECLARE_printTypedVectorList(4, h);
DECLARE_printTypedVectorList(4, s);
DECLARE_printTypedVectorList(8, b);
DECLARE_printTypedVectorList(8, h);
DECLARE_printTypedVectorList(0, 0);
#define DECLARE_printVectorIndex(Scale) \
void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printVectorIndex(1);
DECLARE_printVectorIndex(8);
void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
void printAppleSysBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printPredicateAsCounter(EltSize) \
void CONCAT(printPredicateAsCounter, \
EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printPredicateAsCounter(8);
DECLARE_printPredicateAsCounter(64);
DECLARE_printPredicateAsCounter(16);
DECLARE_printPredicateAsCounter(32);
DECLARE_printPredicateAsCounter(0);
#define DECLARE_printGPRSeqPairsClassOperand(size) \
void CONCAT(printGPRSeqPairsClassOperand, \
size)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printGPRSeqPairsClassOperand(32);
DECLARE_printGPRSeqPairsClassOperand(64);
#define DECLARE_printImm8OptLsl(T) \
void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printImm8OptLsl(int16_t);
DECLARE_printImm8OptLsl(int8_t);
DECLARE_printImm8OptLsl(int64_t);
DECLARE_printImm8OptLsl(int32_t);
DECLARE_printImm8OptLsl(uint16_t);
DECLARE_printImm8OptLsl(uint8_t);
DECLARE_printImm8OptLsl(uint64_t);
DECLARE_printImm8OptLsl(uint32_t);
#define DECLARE_printSVELogicalImm(T) \
void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printSVELogicalImm(int16_t);
DECLARE_printSVELogicalImm(int32_t);
DECLARE_printSVELogicalImm(int64_t);
void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printMatrixTileVector(IsVertical) \
void CONCAT(printMatrixTileVector, \
IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printMatrixTileVector(0);
DECLARE_printMatrixTileVector(1);
void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printMatrix(EltSize) \
void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printMatrix(64);
DECLARE_printMatrix(32);
DECLARE_printMatrix(16);
DECLARE_printMatrix(0);
void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printSVERegOp(char) \
void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printSVERegOp(b);
DECLARE_printSVERegOp(d);
DECLARE_printSVERegOp(h);
DECLARE_printSVERegOp(s);
DECLARE_printSVERegOp(0);
DECLARE_printSVERegOp(q);
void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printZPRasFPR(Width) \
void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printZPRasFPR(8);
DECLARE_printZPRasFPR(64);
DECLARE_printZPRasFPR(16);
DECLARE_printZPRasFPR(32);
DECLARE_printZPRasFPR(128);
#define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \
void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
#define DECLARE_printMatrixIndex(Scale) \
void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printMatrixIndex(8);
DECLARE_printMatrixIndex(0);
DECLARE_printMatrixIndex(1);
// end namespace llvm
#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
arch/AArch64/AArch64Linkage.h
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/* Capstone Disassembly Engine */
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
#ifndef CS_AARCH64_LINKAGE_H
#define CS_AARCH64_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
DecodeStatus AArch64_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI,
uint16_t *Size, uint64_t Address,
void *Info);
const char *AArch64_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
#endif // CS_AARCH64_LINKAGE_H
arch/AArch64/AArch64Mapping.c
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arch/AArch64/AArch64Mapping.h
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_AARCH64_MAP_H
#define CS_AARCH64_MAP_H
#include "capstone/capstone.h"
#include "../../MCInst.h"
#include "../../SStream.h"
typedef enum {
#include "AArch64GenCSOpGroup.inc"
} aarch64_op_group;
/// Components of an SME matrix.
/// Used when an sme operand is set to signal which part should be set.
typedef enum {
AARCH64_SME_MATRIX_TILE,
AARCH64_SME_MATRIX_TILE_LIST,
AARCH64_SME_MATRIX_SLICE_REG,
AARCH64_SME_MATRIX_SLICE_OFF,
AARCH64_SME_MATRIX_SLICE_OFF_RANGE,
} aarch64_sme_op_part;
// return name of register in friendly string
const char *AArch64_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info
void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *AArch64_insn_name(csh handle, unsigned int id);
const char *AArch64_group_name(csh handle, unsigned int id);
void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group,
unsigned OpNum);
void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group,
unsigned OpNum, uint64_t temp_arg_0);
void AArch64_add_cs_detail_2(MCInst *MI, aarch64_op_group op_group,
unsigned OpNum, uint64_t temp_arg_0,
uint64_t temp_arg_1);
void AArch64_add_cs_detail_4(MCInst *MI, aarch64_op_group op_group,
unsigned OpNum, uint64_t temp_arg_0,
uint64_t temp_arg_1, uint64_t temp_arg_2,
uint64_t temp_arg_3);
void AArch64_init_mri(MCRegisterInfo *MRI);
void AArch64_init_cs_detail(MCInst *MI);
void AArch64_set_instr_map_data(MCInst *MI);
bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
void AArch64_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg);
void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
aarch64_op_type ImmType, int64_t Imm);
void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
uint32_t FirstImm, uint32_t offset);
void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val);
void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val);
void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
bool DoShift, unsigned ExtWidth,
char SrcRegKind);
void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val);
void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op,
aarch64_op_type type);
void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
aarch64_sme_op_part part,
AArch64Layout_VectorLayout vas, uint64_t arg_0,
uint64_t arg_1);
void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum);
void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index,
aarch64_reg Reg, cs_ac_type access);
void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val,
cs_ac_type access);
void AArch64_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Imm);
void AArch64_insert_detail_op_sys(MCInst *MI, unsigned index,
aarch64_sysop sys_op, aarch64_op_type type);
void AArch64_insert_detail_op_sme(MCInst *MI, unsigned index,
aarch64_op_sme sme_op);
void AArch64_add_vas(MCInst *MI, const SStream *OS);
#endif
arch/AArch64/AArch64Module.c
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/* Capstone Disassembly Engine */
/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
#ifdef CAPSTONE_HAS_AARCH64
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "AArch64InstPrinter.h"
#include "AArch64Mapping.h"
#include "AArch64Module.h"
cs_err AArch64_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
if (!mri)
return CS_ERR_MEM;
AArch64_init_mri(mri);
ud->printer = AArch64_printer;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = AArch64_getInstruction;
ud->reg_name = AArch64_reg_name;
ud->insn_id = AArch64_get_insn_id;
ud->insn_name = AArch64_insn_name;
ud->group_name = AArch64_group_name;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = AArch64_reg_access;
#endif
return CS_ERR_OK;
}
cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX)
handle->syntax |= (int)value;
if (type == CS_OPT_MODE) {
handle->mode |= (cs_mode)value;
}
return CS_ERR_OK;
}
#endif
arch/AArch64/AArch64Module.h
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/* Capstone Disassembly Engine */
/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
#ifndef CS_AARCH64_MODULE_H
#define CS_AARCH64_MODULE_H
#include "../../utils.h"
cs_err AArch64_global_init(cs_struct *ud);
cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif
arch/ARC/ARCDisassembler.c
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file is part of the ARC Disassembler.
///
//===----------------------------------------------------------------------===//
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInst.h"
#include "../../SStream.h"
#include "../../MCDisassembler.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MathExtras.h"
#include "../../utils.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "arc-disassembler"
/// A disassembler class for ARC.
static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size,
const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, SStream *CStream);
// end anonymous namespace
static bool readInstruction32(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint32_t *Insn)
{
*Size = 4;
// Read 2 16-bit values, but swap hi/lo parts.
*Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) |
(Bytes[3] << 8);
return true;
}
static bool readInstruction64(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint64_t *Insn)
{
*Size = 8;
*Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |
((uint64_t)Bytes[4] << 48) | ((uint64_t)Bytes[5] << 56) |
((uint64_t)Bytes[6] << 32) | ((uint64_t)Bytes[7] << 40);
return true;
}
static bool readInstruction48(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint64_t *Insn)
{
*Size = 6;
*Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) |
((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24);
return true;
}
static bool readInstruction16(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint32_t *Insn)
{
*Size = 2;
*Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
return true;
}
#define DECLARE_DecodeSignedOperand(B) \
static DecodeStatus CONCAT(DecodeSignedOperand, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder);
DECLARE_DecodeSignedOperand(11);
DECLARE_DecodeSignedOperand(9);
DECLARE_DecodeSignedOperand(10);
DECLARE_DecodeSignedOperand(12);
#define DECLARE_DecodeFromCyclicRange(B) \
static DecodeStatus CONCAT(DecodeFromCyclicRange, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder);
DECLARE_DecodeFromCyclicRange(3);
#define DECLARE_DecodeBranchTargetS(B) \
static DecodeStatus CONCAT(DecodeBranchTargetS, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder);
DECLARE_DecodeBranchTargetS(8);
DECLARE_DecodeBranchTargetS(10);
DECLARE_DecodeBranchTargetS(7);
DECLARE_DecodeBranchTargetS(13);
DECLARE_DecodeBranchTargetS(21);
DECLARE_DecodeBranchTargetS(25);
DECLARE_DecodeBranchTargetS(9);
static DecodeStatus DecodeMEMrs9(MCInst *, unsigned, uint64_t, const void *);
static DecodeStatus DecodeLdLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeStLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeLdRLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeSOPwithRS12(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeSOPwithRU6(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeCCRU6Instruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t, uint64_t,
const void *);
#define GET_REGINFO_ENUM
#include "ARCGenRegisterInfo.inc"
static const uint16_t GPR32DecoderTable[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6,
ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13,
ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20,
ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP,
ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK
};
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo >= 32) {
;
return MCDisassembler_Fail;
}
unsigned Reg = GPR32DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeGBR32ShortRegister(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
// Enumerates registers from ranges [r0-r3],[r12-r15].
if (RegNo > 3)
RegNo += 8; // 4 for r12, etc...
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
}
#include "ARCGenDisassemblerTables.inc"
static unsigned decodeCField(unsigned Insn)
{
return fieldFromInstruction_4(Insn, 6, 6);
}
static unsigned decodeBField(unsigned Insn)
{
return (fieldFromInstruction_4(Insn, 12, 3) << 3) |
fieldFromInstruction_4(Insn, 24, 3);
}
static unsigned decodeAField(unsigned Insn)
{
return fieldFromInstruction_4(Insn, 0, 6);
}
static DecodeStatus DecodeMEMrs9(MCInst *Inst, unsigned Insn, uint64_t Address,
const void *Decoder)
{
// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
unsigned S9 = Insn & 0x1ff;
unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
if (DecodeGPR32RegisterClass(Inst, R, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
MCOperand_CreateImm0(Inst, (SignExtend32((S9), 9)));
return MCDisassembler_Success;
}
static void DecodeSymbolicOperandOff(MCInst *Inst, uint64_t Address,
uint64_t Offset, const void *Decoder)
{
uint64_t NextAddress = Address + Offset;
MCOperand_CreateImm0(Inst, (NextAddress));
}
#define DEFINE_DecodeBranchTargetS(B) \
static DecodeStatus CONCAT(DecodeBranchTargetS, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
DecodeSymbolicOperandOff(Inst, Address, \
SignExtend32((InsnS), B), Decoder); \
return MCDisassembler_Success; \
}
DEFINE_DecodeBranchTargetS(8);
DEFINE_DecodeBranchTargetS(10);
DEFINE_DecodeBranchTargetS(7);
DEFINE_DecodeBranchTargetS(13);
DEFINE_DecodeBranchTargetS(21);
DEFINE_DecodeBranchTargetS(25);
DEFINE_DecodeBranchTargetS(9);
#define DEFINE_DecodeSignedOperand(B) \
static DecodeStatus CONCAT(DecodeSignedOperand, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
MCOperand_CreateImm0( \
Inst, SignExtend32(maskTrailingOnes32(B) & InsnS, B)); \
return MCDisassembler_Success; \
}
DEFINE_DecodeSignedOperand(11);
DEFINE_DecodeSignedOperand(9);
DEFINE_DecodeSignedOperand(10);
DEFINE_DecodeSignedOperand(12);
#define DEFINE_DecodeFromCyclicRange(B) \
static DecodeStatus CONCAT(DecodeFromCyclicRange, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
const unsigned max = (1u << B) - 1; \
MCOperand_CreateImm0(Inst, (InsnS < max ? (int)(InsnS) : -1)); \
return MCDisassembler_Success; \
}
DEFINE_DecodeFromCyclicRange(3);
static DecodeStatus DecodeStLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned SrcC, DstB, LImm;
DstB = decodeBField(Insn);
if (DstB != 62) {
return MCDisassembler_Fail;
}
SrcC = decodeCField(Insn);
if (DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
LImm = (Insn >> 32);
MCOperand_CreateImm0(Inst, (LImm));
MCOperand_CreateImm0(Inst, (0));
return MCDisassembler_Success;
}
static DecodeStatus DecodeLdLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstA, SrcB, LImm;
;
SrcB = decodeBField(Insn);
if (SrcB != 62) {
;
return MCDisassembler_Fail;
}
DstA = decodeAField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
LImm = (Insn >> 32);
MCOperand_CreateImm0(Inst, (LImm));
MCOperand_CreateImm0(Inst, (0));
return MCDisassembler_Success;
}
static DecodeStatus DecodeLdRLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstA, SrcB;
;
DstA = decodeAField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
SrcB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
if (decodeCField(Insn) != 62) {
;
return MCDisassembler_Fail;
}
MCOperand_CreateImm0(Inst, ((uint32_t)(Insn >> 32)));
return MCDisassembler_Success;
}
static DecodeStatus DecodeRegisterOrImm(MCInst *Inst, uint64_t Address,
const void *Decoder, uint64_t RegNum,
uint64_t Value)
{
if (30 == RegNum) {
MCOperand_CreateImm0(Inst, (Value));
return MCDisassembler_Success;
}
return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
}
static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
;
uint64_t H = fieldFromInstruction_8(Insn, 5, 3) |
(fieldFromInstruction_8(Insn, 0, 2) << 3);
uint64_t G = fieldFromInstruction_8(Insn, 8, 3) |
(fieldFromInstruction_8(Insn, 3, 2) << 3);
if (MCDisassembler_Success !=
DecodeRegisterOrImm(Inst, Address, Decoder, G, 0))
return MCDisassembler_Fail;
return DecodeRegisterOrImm(Inst, Address, Decoder, H, Insn >> 16u);
}
static DecodeStatus DecodeCCRU6Instruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstB;
;
DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t U6Field = fieldFromInstruction_8(Insn, 6, 6);
MCOperand_CreateImm0(Inst, (U6Field));
uint64_t CCField = fieldFromInstruction_8(Insn, 0, 4);
MCOperand_CreateImm0(Inst, (CCField));
return MCDisassembler_Success;
}
static DecodeStatus DecodeSOPwithRU6(MCInst *Inst, uint64_t Insn,
uint64_t Address, const void *Decoder)
{
unsigned DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t U6 = fieldFromInstruction_8(Insn, 6, 6);
MCOperand_CreateImm0(Inst, (U6));
return MCDisassembler_Success;
}
static DecodeStatus DecodeSOPwithRS12(MCInst *Inst, uint64_t Insn,
uint64_t Address, const void *Decoder)
{
unsigned DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) ==
MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t Lower = fieldFromInstruction_8(Insn, 6, 6);
uint64_t Upper = fieldFromInstruction_8(Insn, 0, 5);
uint64_t Sign = fieldFromInstruction_8(Insn, 5, 1) ? -1 : 1;
uint64_t Result = Sign * ((Upper << 6) + Lower);
MCOperand_CreateImm0(Inst, (Result));
return MCDisassembler_Success;
}
static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size,
const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, SStream *cStream)
{
DecodeStatus Result;
if (BytesLen < 2) {
*Size = 0;
return MCDisassembler_Fail;
}
uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;
// 0x00 -> 0x07 are 32-bit instructions.
// 0x08 -> 0x1F are 16-bit instructions.
if (DecodeByte < 0x08) {
// 32-bit instruction.
if (BytesLen < 4) {
// Did we decode garbage?
*Size = 0;
return MCDisassembler_Fail;
}
if (BytesLen >= 8) {
// Attempt to decode 64-bit instruction.
uint64_t Insn64;
if (!readInstruction64(Bytes, BytesLen, Address, Size,
&Insn64))
return MCDisassembler_Fail;
Result = decodeInstruction_8(DecoderTable64, Instr,
Insn64, Address, NULL);
if (MCDisassembler_Success == Result) {
;
return Result;
};
}
uint32_t Insn32;
if (!readInstruction32(Bytes, BytesLen, Address, Size,
&Insn32)) {
return MCDisassembler_Fail;
}
// Calling the auto-generated decoder function.
return decodeInstruction_4(DecoderTable32, Instr, Insn32,
Address, NULL);
} else {
if (BytesLen >= 6) {
// Attempt to treat as instr. with limm data.
uint64_t Insn48;
if (!readInstruction48(Bytes, BytesLen, Address, Size,
&Insn48))
return MCDisassembler_Fail;
Result = decodeInstruction_8(DecoderTable48, Instr,
Insn48, Address, NULL);
if (MCDisassembler_Success == Result) {
;
return Result;
};
}
uint32_t Insn16;
if (!readInstruction16(Bytes, BytesLen, Address, Size, &Insn16))
return MCDisassembler_Fail;
// Calling the auto-generated decoder function.
return decodeInstruction_2(DecoderTable16, Instr, Insn16,
Address, NULL);
}
}
DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, SStream *CS)
{
return getInstruction(MI, Size, Bytes, BytesLen, Address, CS);
}
#endif
arch/ARC/ARCGenAsmWriter.inc
+1324
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arch/ARC/ARCGenCSInsnEnum.inc
+204
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@@ -0,0 +1,204 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_INS_INVALID,
ARC_INS_h,
ARC_INS_PBR,
ARC_INS_ERROR_FLS,
ARC_INS_ERROR_FFS,
ARC_INS_PLDFI,
ARC_INS_STB_FAR,
ARC_INS_STH_FAR,
ARC_INS_ST_FAR,
ARC_INS_ADC,
ARC_INS_ADC_F,
ARC_INS_ADD_S,
ARC_INS_ADD,
ARC_INS_ADD_F,
ARC_INS_AND,
ARC_INS_AND_F,
ARC_INS_ASL_S,
ARC_INS_ASL,
ARC_INS_ASL_F,
ARC_INS_ASR_S,
ARC_INS_ASR,
ARC_INS_ASR_F,
ARC_INS_BCLR_S,
ARC_INS_BEQ_S,
ARC_INS_BGE_S,
ARC_INS_BGT_S,
ARC_INS_BHI_S,
ARC_INS_BHS_S,
ARC_INS_BL,
ARC_INS_BLE_S,
ARC_INS_BLO_S,
ARC_INS_BLS_S,
ARC_INS_BLT_S,
ARC_INS_BL_S,
ARC_INS_BMSK_S,
ARC_INS_BNE_S,
ARC_INS_B,
ARC_INS_BREQ_S,
ARC_INS_BRNE_S,
ARC_INS_BR,
ARC_INS_BSET_S,
ARC_INS_BTST_S,
ARC_INS_B_S,
ARC_INS_CMP_S,
ARC_INS_CMP,
ARC_INS_LD_S,
ARC_INS_MOV_S,
ARC_INS_EI_S,
ARC_INS_ENTER_S,
ARC_INS_FFS_F,
ARC_INS_FFS,
ARC_INS_FLS_F,
ARC_INS_FLS,
ARC_INS_ABS_S,
ARC_INS_ADD1_S,
ARC_INS_ADD2_S,
ARC_INS_ADD3_S,
ARC_INS_AND_S,
ARC_INS_BIC_S,
ARC_INS_BRK_S,
ARC_INS_EXTB_S,
ARC_INS_EXTH_S,
ARC_INS_JEQ_S,
ARC_INS_JL_S,
ARC_INS_JL_S_D,
ARC_INS_JNE_S,
ARC_INS_J_S,
ARC_INS_J_S_D,
ARC_INS_LSR_S,
ARC_INS_MPYUW_S,
ARC_INS_MPYW_S,
ARC_INS_MPY_S,
ARC_INS_NEG_S,
ARC_INS_NOP_S,
ARC_INS_NOT_S,
ARC_INS_OR_S,
ARC_INS_SEXB_S,
ARC_INS_SEXH_S,
ARC_INS_SUB_S,
ARC_INS_SUB_S_NE,
ARC_INS_SWI_S,
ARC_INS_TRAP_S,
ARC_INS_TST_S,
ARC_INS_UNIMP_S,
ARC_INS_XOR_S,
ARC_INS_LDB_S,
ARC_INS_LDH_S,
ARC_INS_J,
ARC_INS_JL,
ARC_INS_JLI_S,
ARC_INS_LDB_AB,
ARC_INS_LDB_AW,
ARC_INS_LDB_DI_AB,
ARC_INS_LDB_DI_AW,
ARC_INS_LDB_DI,
ARC_INS_LDB_X_AB,
ARC_INS_LDB_X_AW,
ARC_INS_LDB_X_DI_AB,
ARC_INS_LDB_X_DI_AW,
ARC_INS_LDB_X_DI,
ARC_INS_LDB_X,
ARC_INS_LDB,
ARC_INS_LDH_AB,
ARC_INS_LDH_AW,
ARC_INS_LDH_DI_AB,
ARC_INS_LDH_DI_AW,
ARC_INS_LDH_DI,
ARC_INS_LDH_S_X,
ARC_INS_LDH_X_AB,
ARC_INS_LDH_X_AW,
ARC_INS_LDH_X_DI_AB,
ARC_INS_LDH_X_DI_AW,
ARC_INS_LDH_X_DI,
ARC_INS_LDH_X,
ARC_INS_LDH,
ARC_INS_LDI_S,
ARC_INS_LD_AB,
ARC_INS_LD_AW,
ARC_INS_LD_DI_AB,
ARC_INS_LD_DI_AW,
ARC_INS_LD_DI,
ARC_INS_LD_S_AS,
ARC_INS_LD,
ARC_INS_LEAVE_S,
ARC_INS_LR,
ARC_INS_LSR,
ARC_INS_LSR_F,
ARC_INS_MAX,
ARC_INS_MAX_F,
ARC_INS_MIN,
ARC_INS_MIN_F,
ARC_INS_MOV_S_NE,
ARC_INS_MOV,
ARC_INS_MOV_F,
ARC_INS_MPYMU,
ARC_INS_MPYMU_F,
ARC_INS_MPYM,
ARC_INS_MPYM_F,
ARC_INS_MPY,
ARC_INS_MPY_F,
ARC_INS_NORMH_F,
ARC_INS_NORMH,
ARC_INS_NORM_F,
ARC_INS_NORM,
ARC_INS_OR,
ARC_INS_OR_F,
ARC_INS_POP_S,
ARC_INS_PUSH_S,
ARC_INS_ROR,
ARC_INS_ROR_F,
ARC_INS_RSUB,
ARC_INS_RSUB_F,
ARC_INS_SBC,
ARC_INS_SBC_F,
ARC_INS_SETEQ,
ARC_INS_SETEQ_F,
ARC_INS_SEXB_F,
ARC_INS_SEXB,
ARC_INS_SEXH_F,
ARC_INS_SEXH,
ARC_INS_STB_S,
ARC_INS_ST_S,
ARC_INS_STB_AB,
ARC_INS_STB_AW,
ARC_INS_STB_DI_AB,
ARC_INS_STB_DI_AW,
ARC_INS_STB_DI,
ARC_INS_STB,
ARC_INS_STH_AB,
ARC_INS_STH_AW,
ARC_INS_STH_DI_AB,
ARC_INS_STH_DI_AW,
ARC_INS_STH_DI,
ARC_INS_STH_S,
ARC_INS_STH,
ARC_INS_ST_AB,
ARC_INS_ST_AW,
ARC_INS_ST_DI_AB,
ARC_INS_ST_DI_AW,
ARC_INS_ST_DI,
ARC_INS_ST,
ARC_INS_SUB1,
ARC_INS_SUB1_F,
ARC_INS_SUB2,
ARC_INS_SUB2_F,
ARC_INS_SUB3,
ARC_INS_SUB3_F,
ARC_INS_SUB,
ARC_INS_SUB_F,
ARC_INS_XOR,
ARC_INS_XOR_F,
arch/ARC/ARCGenCSMappingInsn.inc
+5494
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arch/ARC/ARCGenCSMappingInsnName.inc
+204
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@@ -0,0 +1,204 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
"invalid", // ARC_INS_INVALID
"h", // ARC_INS_h
"pbr", // ARC_INS_PBR
"error_fls", // ARC_INS_ERROR_FLS
"error_ffs", // ARC_INS_ERROR_FFS
"pldfi", // ARC_INS_PLDFI
"STB_FAR", // ARC_INS_STB_FAR
"STH_FAR", // ARC_INS_STH_FAR
"ST_FAR", // ARC_INS_ST_FAR
"adc", // ARC_INS_ADC
"adc_f", // ARC_INS_ADC_F
"add_s", // ARC_INS_ADD_S
"add", // ARC_INS_ADD
"add_f", // ARC_INS_ADD_F
"and", // ARC_INS_AND
"and_f", // ARC_INS_AND_F
"asl_s", // ARC_INS_ASL_S
"asl", // ARC_INS_ASL
"asl_f", // ARC_INS_ASL_F
"asr_s", // ARC_INS_ASR_S
"asr", // ARC_INS_ASR
"asr_f", // ARC_INS_ASR_F
"bclr_s", // ARC_INS_BCLR_S
"beq_s", // ARC_INS_BEQ_S
"bge_s", // ARC_INS_BGE_S
"bgt_s", // ARC_INS_BGT_S
"bhi_s", // ARC_INS_BHI_S
"bhs_s", // ARC_INS_BHS_S
"bl", // ARC_INS_BL
"ble_s", // ARC_INS_BLE_S
"blo_s", // ARC_INS_BLO_S
"bls_s", // ARC_INS_BLS_S
"blt_s", // ARC_INS_BLT_S
"bl_s", // ARC_INS_BL_S
"bmsk_s", // ARC_INS_BMSK_S
"bne_s", // ARC_INS_BNE_S
"b", // ARC_INS_B
"breq_s", // ARC_INS_BREQ_S
"brne_s", // ARC_INS_BRNE_S
"br", // ARC_INS_BR
"bset_s", // ARC_INS_BSET_S
"btst_s", // ARC_INS_BTST_S
"b_s", // ARC_INS_B_S
"cmp_s", // ARC_INS_CMP_S
"cmp", // ARC_INS_CMP
"ld_s", // ARC_INS_LD_S
"mov_s", // ARC_INS_MOV_S
"ei_s", // ARC_INS_EI_S
"enter_s", // ARC_INS_ENTER_S
"ffs_f", // ARC_INS_FFS_F
"ffs", // ARC_INS_FFS
"fls_f", // ARC_INS_FLS_F
"fls", // ARC_INS_FLS
"abs_s", // ARC_INS_ABS_S
"add1_s", // ARC_INS_ADD1_S
"add2_s", // ARC_INS_ADD2_S
"add3_s", // ARC_INS_ADD3_S
"and_s", // ARC_INS_AND_S
"bic_s", // ARC_INS_BIC_S
"brk_s", // ARC_INS_BRK_S
"extb_s", // ARC_INS_EXTB_S
"exth_s", // ARC_INS_EXTH_S
"jeq_s", // ARC_INS_JEQ_S
"jl_s", // ARC_INS_JL_S
"jl_s_d", // ARC_INS_JL_S_D
"jne_s", // ARC_INS_JNE_S
"j_s", // ARC_INS_J_S
"j_s_d", // ARC_INS_J_S_D
"lsr_s", // ARC_INS_LSR_S
"mpyuw_s", // ARC_INS_MPYUW_S
"mpyw_s", // ARC_INS_MPYW_S
"mpy_s", // ARC_INS_MPY_S
"neg_s", // ARC_INS_NEG_S
"nop_s", // ARC_INS_NOP_S
"not_s", // ARC_INS_NOT_S
"or_s", // ARC_INS_OR_S
"sexb_s", // ARC_INS_SEXB_S
"sexh_s", // ARC_INS_SEXH_S
"sub_s", // ARC_INS_SUB_S
"sub_s_ne", // ARC_INS_SUB_S_NE
"swi_s", // ARC_INS_SWI_S
"trap_s", // ARC_INS_TRAP_S
"tst_s", // ARC_INS_TST_S
"unimp_s", // ARC_INS_UNIMP_S
"xor_s", // ARC_INS_XOR_S
"ldb_s", // ARC_INS_LDB_S
"ldh_s", // ARC_INS_LDH_S
"j", // ARC_INS_J
"jl", // ARC_INS_JL
"jli_s", // ARC_INS_JLI_S
"ldb_ab", // ARC_INS_LDB_AB
"ldb_aw", // ARC_INS_LDB_AW
"ldb_di_ab", // ARC_INS_LDB_DI_AB
"ldb_di_aw", // ARC_INS_LDB_DI_AW
"ldb_di", // ARC_INS_LDB_DI
"ldb_x_ab", // ARC_INS_LDB_X_AB
"ldb_x_aw", // ARC_INS_LDB_X_AW
"ldb_x_di_ab", // ARC_INS_LDB_X_DI_AB
"ldb_x_di_aw", // ARC_INS_LDB_X_DI_AW
"ldb_x_di", // ARC_INS_LDB_X_DI
"ldb_x", // ARC_INS_LDB_X
"ldb", // ARC_INS_LDB
"ldh_ab", // ARC_INS_LDH_AB
"ldh_aw", // ARC_INS_LDH_AW
"ldh_di_ab", // ARC_INS_LDH_DI_AB
"ldh_di_aw", // ARC_INS_LDH_DI_AW
"ldh_di", // ARC_INS_LDH_DI
"ldh_s_x", // ARC_INS_LDH_S_X
"ldh_x_ab", // ARC_INS_LDH_X_AB
"ldh_x_aw", // ARC_INS_LDH_X_AW
"ldh_x_di_ab", // ARC_INS_LDH_X_DI_AB
"ldh_x_di_aw", // ARC_INS_LDH_X_DI_AW
"ldh_x_di", // ARC_INS_LDH_X_DI
"ldh_x", // ARC_INS_LDH_X
"ldh", // ARC_INS_LDH
"ldi_s", // ARC_INS_LDI_S
"ld_ab", // ARC_INS_LD_AB
"ld_aw", // ARC_INS_LD_AW
"ld_di_ab", // ARC_INS_LD_DI_AB
"ld_di_aw", // ARC_INS_LD_DI_AW
"ld_di", // ARC_INS_LD_DI
"ld_s_as", // ARC_INS_LD_S_AS
"ld", // ARC_INS_LD
"leave_s", // ARC_INS_LEAVE_S
"lr", // ARC_INS_LR
"lsr", // ARC_INS_LSR
"lsr_f", // ARC_INS_LSR_F
"max", // ARC_INS_MAX
"max_f", // ARC_INS_MAX_F
"min", // ARC_INS_MIN
"min_f", // ARC_INS_MIN_F
"mov_s_ne", // ARC_INS_MOV_S_NE
"mov", // ARC_INS_MOV
"mov_f", // ARC_INS_MOV_F
"mpymu", // ARC_INS_MPYMU
"mpymu_f", // ARC_INS_MPYMU_F
"mpym", // ARC_INS_MPYM
"mpym_f", // ARC_INS_MPYM_F
"mpy", // ARC_INS_MPY
"mpy_f", // ARC_INS_MPY_F
"normh_f", // ARC_INS_NORMH_F
"normh", // ARC_INS_NORMH
"norm_f", // ARC_INS_NORM_F
"norm", // ARC_INS_NORM
"or", // ARC_INS_OR
"or_f", // ARC_INS_OR_F
"pop_s", // ARC_INS_POP_S
"push_s", // ARC_INS_PUSH_S
"ror", // ARC_INS_ROR
"ror_f", // ARC_INS_ROR_F
"rsub", // ARC_INS_RSUB
"rsub_f", // ARC_INS_RSUB_F
"sbc", // ARC_INS_SBC
"sbc_f", // ARC_INS_SBC_F
"seteq", // ARC_INS_SETEQ
"seteq_f", // ARC_INS_SETEQ_F
"sexb_f", // ARC_INS_SEXB_F
"sexb", // ARC_INS_SEXB
"sexh_f", // ARC_INS_SEXH_F
"sexh", // ARC_INS_SEXH
"stb_s", // ARC_INS_STB_S
"st_s", // ARC_INS_ST_S
"stb_ab", // ARC_INS_STB_AB
"stb_aw", // ARC_INS_STB_AW
"stb_di_ab", // ARC_INS_STB_DI_AB
"stb_di_aw", // ARC_INS_STB_DI_AW
"stb_di", // ARC_INS_STB_DI
"stb", // ARC_INS_STB
"sth_ab", // ARC_INS_STH_AB
"sth_aw", // ARC_INS_STH_AW
"sth_di_ab", // ARC_INS_STH_DI_AB
"sth_di_aw", // ARC_INS_STH_DI_AW
"sth_di", // ARC_INS_STH_DI
"sth_s", // ARC_INS_STH_S
"sth", // ARC_INS_STH
"st_ab", // ARC_INS_ST_AB
"st_aw", // ARC_INS_ST_AW
"st_di_ab", // ARC_INS_ST_DI_AB
"st_di_aw", // ARC_INS_ST_DI_AW
"st_di", // ARC_INS_ST_DI
"st", // ARC_INS_ST
"sub1", // ARC_INS_SUB1
"sub1_f", // ARC_INS_SUB1_F
"sub2", // ARC_INS_SUB2
"sub2_f", // ARC_INS_SUB2_F
"sub3", // ARC_INS_SUB3
"sub3_f", // ARC_INS_SUB3_F
"sub", // ARC_INS_SUB
"sub_f", // ARC_INS_SUB_F
"xor", // ARC_INS_XOR
"xor_f", // ARC_INS_XOR_F
arch/ARC/ARCGenCSMappingInsnOp.inc
+3850
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arch/ARC/ARCGenCSOpGroup.inc
+19
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_OP_GROUP_Operand = 0,
ARC_OP_GROUP_PredicateOperand = 1,
ARC_OP_GROUP_MemOperandRI = 2,
ARC_OP_GROUP_BRCCPredicateOperand = 3,
ARC_OP_GROUP_CCOperand = 4,
ARC_OP_GROUP_U6 = 5,
arch/ARC/ARCGenCSRegEnum.inc
+80
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@@ -0,0 +1,80 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_REG_INVALID = 0,
ARC_REG_BLINK = 1,
ARC_REG_FP = 2,
ARC_REG_GP = 3,
ARC_REG_ILINK = 4,
ARC_REG_SP = 5,
ARC_REG_R0 = 6,
ARC_REG_R1 = 7,
ARC_REG_R2 = 8,
ARC_REG_R3 = 9,
ARC_REG_R4 = 10,
ARC_REG_R5 = 11,
ARC_REG_R6 = 12,
ARC_REG_R7 = 13,
ARC_REG_R8 = 14,
ARC_REG_R9 = 15,
ARC_REG_R10 = 16,
ARC_REG_R11 = 17,
ARC_REG_R12 = 18,
ARC_REG_R13 = 19,
ARC_REG_R14 = 20,
ARC_REG_R15 = 21,
ARC_REG_R16 = 22,
ARC_REG_R17 = 23,
ARC_REG_R18 = 24,
ARC_REG_R19 = 25,
ARC_REG_R20 = 26,
ARC_REG_R21 = 27,
ARC_REG_R22 = 28,
ARC_REG_R23 = 29,
ARC_REG_R24 = 30,
ARC_REG_R25 = 31,
ARC_REG_R30 = 32,
ARC_REG_R32 = 33,
ARC_REG_R33 = 34,
ARC_REG_R34 = 35,
ARC_REG_R35 = 36,
ARC_REG_R36 = 37,
ARC_REG_R37 = 38,
ARC_REG_R38 = 39,
ARC_REG_R39 = 40,
ARC_REG_R40 = 41,
ARC_REG_R41 = 42,
ARC_REG_R42 = 43,
ARC_REG_R43 = 44,
ARC_REG_R44 = 45,
ARC_REG_R45 = 46,
ARC_REG_R46 = 47,
ARC_REG_R47 = 48,
ARC_REG_R48 = 49,
ARC_REG_R49 = 50,
ARC_REG_R50 = 51,
ARC_REG_R51 = 52,
ARC_REG_R52 = 53,
ARC_REG_R53 = 54,
ARC_REG_R54 = 55,
ARC_REG_R55 = 56,
ARC_REG_R56 = 57,
ARC_REG_R57 = 58,
ARC_REG_R58 = 59,
ARC_REG_R59 = 60,
ARC_REG_R60 = 61,
ARC_REG_R61 = 62,
ARC_REG_R62 = 63,
ARC_REG_R63 = 64,
ARC_REG_STATUS32 = 65,
ARC_REG_ENDING, // 66
arch/ARC/ARCGenDisassemblerTables.inc
+1803
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File diff suppressed because it is too large Load Diff
arch/ARC/ARCGenInstrInfo.inc
+1616
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arch/ARC/ARCGenRegisterInfo.inc
+296
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#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
ARC_NoRegister,
ARC_BLINK = 1,
ARC_FP = 2,
ARC_GP = 3,
ARC_ILINK = 4,
ARC_SP = 5,
ARC_R0 = 6,
ARC_R1 = 7,
ARC_R2 = 8,
ARC_R3 = 9,
ARC_R4 = 10,
ARC_R5 = 11,
ARC_R6 = 12,
ARC_R7 = 13,
ARC_R8 = 14,
ARC_R9 = 15,
ARC_R10 = 16,
ARC_R11 = 17,
ARC_R12 = 18,
ARC_R13 = 19,
ARC_R14 = 20,
ARC_R15 = 21,
ARC_R16 = 22,
ARC_R17 = 23,
ARC_R18 = 24,
ARC_R19 = 25,
ARC_R20 = 26,
ARC_R21 = 27,
ARC_R22 = 28,
ARC_R23 = 29,
ARC_R24 = 30,
ARC_R25 = 31,
ARC_R30 = 32,
ARC_R32 = 33,
ARC_R33 = 34,
ARC_R34 = 35,
ARC_R35 = 36,
ARC_R36 = 37,
ARC_R37 = 38,
ARC_R38 = 39,
ARC_R39 = 40,
ARC_R40 = 41,
ARC_R41 = 42,
ARC_R42 = 43,
ARC_R43 = 44,
ARC_R44 = 45,
ARC_R45 = 46,
ARC_R46 = 47,
ARC_R47 = 48,
ARC_R48 = 49,
ARC_R49 = 50,
ARC_R50 = 51,
ARC_R51 = 52,
ARC_R52 = 53,
ARC_R53 = 54,
ARC_R54 = 55,
ARC_R55 = 56,
ARC_R56 = 57,
ARC_R57 = 58,
ARC_R58 = 59,
ARC_R59 = 60,
ARC_R60 = 61,
ARC_R61 = 62,
ARC_R62 = 63,
ARC_R63 = 64,
ARC_STATUS32 = 65,
NUM_TARGET_REGS // 66
};
// Register classes
enum {
ARC_SREGRegClassID = 0,
ARC_GPR_SRegClassID = 1,
ARC_GPR32RegClassID = 2,
ARC_GPR32_and_GPR_SRegClassID = 3,
};
#endif // GET_REGINFO_ENUM
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg ARCRegDiffLists[] = {
/* 0 */ 0,
};
static const uint16_t ARCSubRegIdxLists[] = {
/* 0 */ 0,
};
static const MCRegisterDesc ARCRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 235, 0, 0, 0, 0, 0 },
{ 247, 0, 0, 0, 1, 0 },
{ 250, 0, 0, 0, 2, 0 },
{ 241, 0, 0, 0, 3, 0 },
{ 253, 0, 0, 0, 4, 0 },
{ 24, 0, 0, 0, 5, 0 },
{ 47, 0, 0, 0, 6, 0 },
{ 83, 0, 0, 0, 7, 0 },
{ 110, 0, 0, 0, 8, 0 },
{ 133, 0, 0, 0, 9, 0 },
{ 156, 0, 0, 0, 10, 0 },
{ 175, 0, 0, 0, 11, 0 },
{ 194, 0, 0, 0, 12, 0 },
{ 213, 0, 0, 0, 13, 0 },
{ 232, 0, 0, 0, 14, 0 },
{ 0, 0, 0, 0, 15, 0 },
{ 27, 0, 0, 0, 16, 0 },
{ 50, 0, 0, 0, 17, 0 },
{ 86, 0, 0, 0, 18, 0 },
{ 113, 0, 0, 0, 19, 0 },
{ 136, 0, 0, 0, 20, 0 },
{ 159, 0, 0, 0, 21, 0 },
{ 178, 0, 0, 0, 22, 0 },
{ 197, 0, 0, 0, 23, 0 },
{ 216, 0, 0, 0, 24, 0 },
{ 4, 0, 0, 0, 25, 0 },
{ 31, 0, 0, 0, 26, 0 },
{ 54, 0, 0, 0, 27, 0 },
{ 90, 0, 0, 0, 28, 0 },
{ 117, 0, 0, 0, 29, 0 },
{ 140, 0, 0, 0, 30, 0 },
{ 8, 0, 0, 0, 31, 0 },
{ 58, 0, 0, 0, 32, 0 },
{ 94, 0, 0, 0, 33, 0 },
{ 121, 0, 0, 0, 34, 0 },
{ 144, 0, 0, 0, 35, 0 },
{ 163, 0, 0, 0, 36, 0 },
{ 182, 0, 0, 0, 37, 0 },
{ 201, 0, 0, 0, 38, 0 },
{ 220, 0, 0, 0, 39, 0 },
{ 12, 0, 0, 0, 40, 0 },
{ 35, 0, 0, 0, 41, 0 },
{ 71, 0, 0, 0, 42, 0 },
{ 98, 0, 0, 0, 43, 0 },
{ 125, 0, 0, 0, 44, 0 },
{ 148, 0, 0, 0, 45, 0 },
{ 167, 0, 0, 0, 46, 0 },
{ 186, 0, 0, 0, 47, 0 },
{ 205, 0, 0, 0, 48, 0 },
{ 224, 0, 0, 0, 49, 0 },
{ 16, 0, 0, 0, 50, 0 },
{ 39, 0, 0, 0, 51, 0 },
{ 75, 0, 0, 0, 52, 0 },
{ 102, 0, 0, 0, 53, 0 },
{ 129, 0, 0, 0, 54, 0 },
{ 152, 0, 0, 0, 55, 0 },
{ 171, 0, 0, 0, 56, 0 },
{ 190, 0, 0, 0, 57, 0 },
{ 209, 0, 0, 0, 58, 0 },
{ 228, 0, 0, 0, 59, 0 },
{ 20, 0, 0, 0, 60, 0 },
{ 43, 0, 0, 0, 61, 0 },
{ 79, 0, 0, 0, 62, 0 },
{ 106, 0, 0, 0, 63, 0 },
{ 62, 0, 0, 0, 64, 0 },
};
// SREG Register Class...
static const MCPhysReg SREG[] = {
ARC_STATUS32,
};
// SREG Bit set.
static const uint8_t SREGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
};
// GPR_S Register Class...
static const MCPhysReg GPR_S[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
};
// GPR_S Bit set.
static const uint8_t GPR_SBits[] = {
0xc0, 0x03, 0x3c,
};
// GPR32 Register Class...
static const MCPhysReg GPR32[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6, ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13, ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20, ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP, ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK, ARC_R32, ARC_R33, ARC_R34, ARC_R35, ARC_R36, ARC_R37, ARC_R38, ARC_R39, ARC_R40, ARC_R41, ARC_R42, ARC_R43, ARC_R44, ARC_R45, ARC_R46, ARC_R47, ARC_R48, ARC_R49, ARC_R50, ARC_R51, ARC_R52, ARC_R53, ARC_R54, ARC_R55, ARC_R56, ARC_R57, ARC_R58, ARC_R59, ARC_R60, ARC_R61, ARC_R62, ARC_R63,
};
// GPR32 Bit set.
static const uint8_t GPR32Bits[] = {
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
};
// GPR32_and_GPR_S Register Class...
static const MCPhysReg GPR32_and_GPR_S[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
};
// GPR32_and_GPR_S Bit set.
static const uint8_t GPR32_and_GPR_SBits[] = {
0xc0, 0x03, 0x3c,
};
static const MCRegisterClass ARCMCRegisterClasses[] = {
{ SREG, SREGBits, sizeof(SREGBits) },
{ GPR_S, GPR_SBits, sizeof(GPR_SBits) },
{ GPR32, GPR32Bits, sizeof(GPR32Bits) },
{ GPR32_and_GPR_S, GPR32_and_GPR_SBits, sizeof(GPR32_and_GPR_SBits) },
};
static const uint16_t ARCRegEncodingTable[] = {
0,
31,
27,
26,
29,
28,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
30,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
10,
};
#endif // GET_REGINFO_MC_DESC
arch/ARC/ARCGenSubtargetInfo.inc
+24
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@@ -0,0 +1,24 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
ARC_FeatureNORM = 0,
ARC_NumSubtargetFeatures = 1
};
#endif // GET_SUBTARGETINFO_ENUM
arch/ARC/ARCInfo.h
+72
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@@ -0,0 +1,72 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInfo.h - Additional ARC Info --------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the ARC target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
#define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
// Enums corresponding to ARC condition codes
// CS namespace begin: ARCCC
typedef enum ARCCondCode {
ARCCC_AL = 0x0,
ARCCC_EQ = 0x1,
ARCCC_NE = 0x2,
ARCCC_P = 0x3,
ARCCC_N = 0x4,
ARCCC_LO = 0x5,
ARCCC_HS = 0x6,
ARCCC_VS = 0x7,
ARCCC_VC = 0x8,
ARCCC_GT = 0x9,
ARCCC_GE = 0xa,
ARCCC_LT = 0xb,
ARCCC_LE = 0xc,
ARCCC_HI = 0xd,
ARCCC_LS = 0xe,
ARCCC_PNZ = 0xf,
ARCCC_Z = 0x11, // Low 4-bits = EQ
ARCCC_NZ = 0x12 // Low 4-bits = NE
} ARCCC_CondCode;
typedef enum BRCondCode {
ARCCC_BREQ = 0x0,
ARCCC_BRNE = 0x1,
ARCCC_BRLT = 0x2,
ARCCC_BRGE = 0x3,
ARCCC_BRLO = 0x4,
ARCCC_BRHS = 0x5
} ARCCC_BRCondCode;
// CS namespace end: ARCCC
// end namespace ARCCC
// end namespace llvm
#endif
arch/ARC/ARCInstPrinter.c
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInstPrinter.cpp - ARC MCInst to assembly syntax -------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARC MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../SStream.h"
#include "../../MCInst.h"
#include "../../MCInstPrinter.h"
#include "ARCInfo.h"
#include "ARCInstPrinter.h"
#include "ARCLinkage.h"
#include "ARCMapping.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "asm-printer"
#include "ARCGenAsmWriter.inc"
static const char *ARCBRCondCodeToString(ARCCC_BRCondCode BRCC)
{
switch (BRCC) {
case ARCCC_BREQ:
return "eq";
case ARCCC_BRNE:
return "ne";
case ARCCC_BRLT:
return "lt";
case ARCCC_BRGE:
return "ge";
case ARCCC_BRLO:
return "lo";
case ARCCC_BRHS:
return "hs";
}
// CS_ASSERT(0 && "Unknown condition code passed");
return "";
}
static const char *ARCCondCodeToString(ARCCC_CondCode CC)
{
switch (CC) {
case ARCCC_EQ:
return "eq";
case ARCCC_NE:
return "ne";
case ARCCC_P:
return "p";
case ARCCC_N:
return "n";
case ARCCC_HS:
return "hs";
case ARCCC_LO:
return "lo";
case ARCCC_GT:
return "gt";
case ARCCC_GE:
return "ge";
case ARCCC_VS:
return "vs";
case ARCCC_VC:
return "vc";
case ARCCC_LT:
return "lt";
case ARCCC_LE:
return "le";
case ARCCC_HI:
return "hi";
case ARCCC_LS:
return "ls";
case ARCCC_PNZ:
return "pnz";
case ARCCC_AL:
return "al";
case ARCCC_NZ:
return "nz";
case ARCCC_Z:
return "z";
}
// CS_ASSERT(0 && "Unknown condition code passed");
return "";
}
static void printRegName(SStream *OS, MCRegister Reg)
{
SStream_concat0(OS, getRegisterName(Reg));
}
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
printInstruction(MI, Address, O);
}
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
ARC_add_cs_detail_0(MI, ARC_OP_GROUP_Operand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
} else if (MCOperand_isImm(Op)) {
SStream_concat(O, "%" PRId64, MCOperand_getImm(Op));
} else if (MCOperand_isExpr(Op)) {
printExpr(O, MCOperand_getExpr(Op));
}
}
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O)
{
printOperand(MI, OpNum, O);
}
static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O)
{
ARC_add_cs_detail_0(MI, ARC_OP_GROUP_MemOperandRI, OpNum);
MCOperand *base = MCInst_getOperand(MI, (OpNum));
MCOperand *offset = MCInst_getOperand(MI, (OpNum + 1));
CS_ASSERT((MCOperand_isReg(base) && "Base should be register."));
CS_ASSERT((MCOperand_isImm(offset) && "Offset should be immediate."));
printRegName(O, MCOperand_getReg(base));
SStream_concat(O, "%s", ",");
printInt64(O, MCOperand_getImm(offset));
}
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
ARC_add_cs_detail_0(MI, ARC_OP_GROUP_PredicateOperand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
SStream_concat0(
O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(Op)));
}
static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
ARC_add_cs_detail_0(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
SStream_concat0(O, ARCBRCondCodeToString(
(ARCCC_BRCondCode)MCOperand_getImm(Op)));
}
static void printCCOperand(MCInst *MI, int OpNum, SStream *O)
{
ARC_add_cs_detail_0(MI, ARC_OP_GROUP_CCOperand, OpNum);
SStream_concat0(O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(
MCInst_getOperand(MI, (OpNum)))));
}
static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum,
SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
unsigned Value = MCOperand_getImm(MO);
unsigned Value2 = Value >> ShiftBy;
if (Value2 > 0x3F || (Value2 << ShiftBy != Value)) {
CS_ASSERT((false && "instruction has wrong format"));
}
}
printOperand(MI, OpNum, O);
}
static void printU6(MCInst *MI, int OpNum, SStream *O)
{
ARC_add_cs_detail_0(MI, ARC_OP_GROUP_U6, OpNum);
printU6ShiftedBy(0, MI, OpNum, O);
}
void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
printInst(MI, Address, Annot, O);
}
const char *ARC_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}
#endif
arch/ARC/ARCInstPrinter.h
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInstPrinter.h - Convert ARC MCInst to assembly syntax -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file contains the declaration of the ARCInstPrinter class,
/// which is used to print ARC MCInst to a .s file.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
#define LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../SStream.h"
#include "../../MCInst.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
// Autogenerated by tblgen.
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
static void printRegName(SStream *OS, MCRegister Reg);
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);
static void printCCOperand(MCInst *MI, int OpNum, SStream *O);
static void printU6(MCInst *MI, int OpNum, SStream *O);
static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O);
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum,
SStream *O);
;
// end namespace llvm
#endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
arch/ARC/ARCLinkage.h
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_LINKAGE_H
#define CS_ARC_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
const char *ARC_LLVM_getRegisterName(unsigned RegNo);
void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);
DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, SStream *CS);
#endif // CS_ARC_LINKAGE_H
arch/ARC/ARCMapping.c
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <capstone/capstone.h>
#include <capstone/arc.h>
#include "../../Mapping.h"
#include "../../MCDisassembler.h"
#include "../../cs_priv.h"
#include "../../cs_simple_types.h"
#include "ARCMapping.h"
#include "ARCLinkage.h"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "ARCGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "ARCGenInstrInfo.inc"
void ARC_init_mri(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(MRI, ARCRegDesc, sizeof(ARCRegDesc),
0, 0, ARCMCRegisterClasses,
ARR_SIZE(ARCMCRegisterClasses), 0, 0,
ARCRegDiffLists, 0, ARCSubRegIdxLists,
ARR_SIZE(ARCSubRegIdxLists), 0);
}
const char *ARC_reg_name(csh handle, unsigned int reg)
{
return ARC_LLVM_getRegisterName(reg);
}
void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// Not used by ARC. Information is set after disassembly.
}
static const char *const insn_name_maps[] = {
#include "ARCGenCSMappingInsnName.inc"
};
const char *ARC_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id < ARR_SIZE(insn_name_maps))
return insn_name_maps[id];
// not found
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
{ ARC_GRP_INVALID, NULL },
{ ARC_GRP_JUMP, "jump" },
{ ARC_GRP_CALL, "call" },
{ ARC_GRP_RET, "return" },
{ ARC_GRP_BRANCH_RELATIVE, "branch_relative" },
};
#endif
const char *ARC_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_arc *arc = &(insn->detail->arc);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read,
read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write,
write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < arc->op_count; i++) {
cs_arc_op *op = &(arc->operands[i]);
switch ((int)op->type) {
case ARC_OP_REG:
if ((op->access & CS_AC_READ) &&
!arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) &&
!arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
const insn_map arc_insns[] = {
#include "ARCGenCSMappingInsn.inc"
};
void ARC_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, arc_insns, ARR_SIZE(arc_insns));
map_implicit_reads(MI, arc_insns);
map_implicit_writes(MI, arc_insns);
map_groups(MI, arc_insns);
}
bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info)
{
uint64_t temp_size;
ARC_init_cs_detail(instr);
DecodeStatus Result = ARC_LLVM_getInstruction(instr, &temp_size, code,
code_len, address, info);
ARC_set_instr_map_data(instr);
*size = temp_size;
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
void ARC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
MI->MRI = MRI;
ARC_LLVM_printInst(MI, MI->address, "", O);
}
void ARC_setup_op(cs_arc_op *op)
{
memset(op, 0, sizeof(cs_arc_op));
op->type = ARC_OP_INVALID;
}
void ARC_init_cs_detail(MCInst *MI)
{
if (!detail_is_set(MI)) {
return;
}
unsigned int i;
memset(get_detail(MI), 0, offsetof(cs_detail, arc) + sizeof(cs_arc));
for (i = 0; i < ARR_SIZE(ARC_get_detail(MI)->operands); i++)
ARC_setup_op(&ARC_get_detail(MI)->operands[i]);
}
static const map_insn_ops insn_operands[] = {
#include "ARCGenCSMappingInsnOp.inc"
};
void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum, arc_op_type ImmType,
int64_t Imm)
{
if (!detail_is_set(MI))
return;
ARC_check_safe_inc(MI);
CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
CS_ASSERT(ImmType == ARC_OP_IMM);
ARC_get_detail_op(MI, 0)->type = ImmType;
ARC_get_detail_op(MI, 0)->imm = Imm;
ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
ARC_inc_op_count(MI);
}
void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg)
{
if (!detail_is_set(MI))
return;
ARC_check_safe_inc(MI);
CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
ARC_get_detail_op(MI, 0)->type = ARC_OP_REG;
ARC_get_detail_op(MI, 0)->reg = Reg;
ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
ARC_inc_op_count(MI);
}
void ARC_add_cs_detail_0(MCInst *MI, int op_group, size_t OpNum)
{
if (!detail_is_set(MI))
return;
cs_op_type op_type = map_get_op_type(MI, OpNum);
cs_op_type base_op_type = op_type;
cs_op_type offset_op_type;
// Fill cs_detail
switch (op_group) {
default:
printf("ERROR: Operand group %d not handled!\n", op_group);
CS_ASSERT_RET(0);
case ARC_OP_GROUP_Operand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else if (op_type == CS_OP_REG) {
ARC_set_detail_op_reg(MI, OpNum,
MCInst_getOpVal(MI, OpNum));
} else {
// Expression
ARC_set_detail_op_imm(
MI, OpNum, ARC_OP_IMM,
MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
}
break;
case ARC_OP_GROUP_PredicateOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_MemOperandRI:
if (base_op_type == CS_OP_REG) {
ARC_set_detail_op_reg(MI, OpNum,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
offset_op_type = map_get_op_type(MI, OpNum + 1);
if (offset_op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum + 1, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum + 1));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_BRCCPredicateOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_CCOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_U6:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
}
}
#endif
arch/ARC/ARCMapping.h
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_MAP_H
#define CS_ARC_MAP_H
#include "../../Mapping.h"
#include "../../include/capstone/capstone.h"
#include "../../utils.h"
typedef enum {
#include "ARCGenCSOpGroup.inc"
} arc_op_group;
void ARC_init_mri(MCRegisterInfo *MRI);
// return name of register in friendly string
const char *ARC_reg_name(csh handle, unsigned int reg);
void ARC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
// given internal insn id, return public instruction ID
void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *ARC_insn_name(csh handle, unsigned int id);
const char *ARC_group_name(csh handle, unsigned int id);
void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
// cs_detail related functions
void ARC_init_cs_detail(MCInst *MI);
void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum, arc_op_type ImmType,
int64_t Imm);
void ARC_add_cs_detail_0(MCInst *MI, int /* arc_op_group */ op_group,
size_t op_num);
#endif
arch/ARC/ARCModule.c
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifdef CAPSTONE_HAS_ARC
#include <capstone/capstone.h>
#include "ARCModule.h"
#include "../../MCRegisterInfo.h"
#include "../../cs_priv.h"
#include "ARCMapping.h"
cs_err ARC_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
if (!mri)
return CS_ERR_MEM;
ARC_init_mri(mri);
ud->printer = ARC_printer;
ud->printer_info = mri;
ud->reg_name = ARC_reg_name;
ud->insn_id = ARC_get_insn_id;
ud->insn_name = ARC_insn_name;
ud->group_name = ARC_group_name;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = ARC_reg_access;
#endif
ud->disasm = ARC_getInstruction;
return CS_ERR_OK;
}
cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value)
{
switch (type) {
case CS_OPT_MODE:
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
handle->syntax |= (int)value;
break;
default:
break;
}
return CS_ERR_OK;
}
#endif
arch/ARC/ARCModule.h
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_MODULE_H
#define CS_ARC_MODULE_H
#include "../../utils.h"
cs_err ARC_global_init(cs_struct *ud);
cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif
arch/ARM/ARMAddressingModes.h
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the ARM addressing mode implementation stuff.
//
//===----------------------------------------------------------------------===//
#ifndef CS_ARM_ADDRESSINGMODES_H
#define CS_ARM_ADDRESSINGMODES_H
#include "../../cs_priv.h"
#include <capstone/platform.h>
#include <assert.h>
#include "../../MathExtras.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
/// ARM_AM - ARM Addressing Mode Stuff
// CS namespace begin: ARM_AM
typedef enum ShiftOpc {
ARM_AM_no_shift = 0,
ARM_AM_asr,
ARM_AM_lsl,
ARM_AM_lsr,
ARM_AM_ror,
ARM_AM_rrx,
ARM_AM_uxtw
} ARM_AM_ShiftOpc;
typedef enum AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc;
static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
{
return Op == ARM_AM_sub ? "-" : "";
}
static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
{
switch (Op) {
default:
CS_ASSERT_RET_VAL(0 && "Unknown shift opc!", NULL);
case ARM_AM_asr:
return "asr";
case ARM_AM_lsl:
return "lsl";
case ARM_AM_lsr:
return "lsr";
case ARM_AM_ror:
return "ror";
case ARM_AM_rrx:
return "rrx";
case ARM_AM_uxtw:
return "uxtw";
}
}
static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
{
switch (Op) {
default:
CS_ASSERT_RET_VAL(0 && "Unknown shift opc!", 0);
case ARM_AM_asr:
return 2;
case ARM_AM_lsl:
return 0;
case ARM_AM_lsr:
return 1;
case ARM_AM_ror:
return 3;
}
}
typedef enum AMSubMode {
ARM_AM_bad_am_submode = 0,
ARM_AM_ia,
ARM_AM_ib,
ARM_AM_da,
ARM_AM_db
} ARM_AM_SubMode;
static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode)
{
switch (Mode) {
default:
CS_ASSERT_RET_VAL(0 && "Unknown addressing sub-mode!", NULL);
case ARM_AM_ia:
return "ia";
case ARM_AM_ib:
return "ib";
case ARM_AM_da:
return "da";
case ARM_AM_db:
return "db";
}
}
//===--------------------------------------------------------------------===//
// Addressing Mode #1: shift_operand with registers
//===--------------------------------------------------------------------===//
//
// This 'addressing mode' is used for arithmetic instructions. It can
// represent things like:
// reg
// reg [asr|lsl|lsr|ror|rrx] reg
// reg [asr|lsl|lsr|ror|rrx] imm
//
// This is stored three operands [rega, regb, opc]. The first is the base
// reg, the second is the shift amount (or reg0 if not present or imm). The
// third operand encodes the shift opcode and the imm if a reg isn't present.
static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt)
{
CS_ASSERT(Amt <= 32);
if (Amt == 32) {
return Val;
}
// NOLINTBEGIN(clang-analyzer-core.BitwiseShift)
return (Val >> Amt) | (Val << ((32 - Amt) & 31));
// NOLINTEND(clang-analyzer-core.BitwiseShift)
}
static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
{
return (Val << Amt) | (Val >> ((32 - Amt) & 31));
}
static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
{
return ShOp | (Imm << 3);
}
static inline unsigned ARM_AM_getSORegOffset(unsigned Op)
{
return Op >> 3;
}
static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
{
return (ARM_AM_ShiftOpc)(Op & 7);
}
/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
/// the 8-bit imm value.
static inline unsigned ARM_AM_getSOImmValImm(unsigned Imm)
{
return Imm & 0xFF;
}
/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
/// the rotate amount.
static inline unsigned ARM_AM_getSOImmValRot(unsigned Imm)
{
return (Imm >> 8) * 2;
}
/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
/// computing the rotate amount to use. If this immediate value cannot be
/// handled with a single shifter-op, determine a good rotate amount that will
/// take a maximal chunk of bits out of the immediate.
static inline unsigned ARM_AM_getSOImmValRotate(unsigned Imm)
{
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Imm & ~255U) == 0)
return 0;
// Use CTZ to compute the rotate amount.
unsigned TZ = CountTrailingZeros_32(Imm);
// Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
// not 9.
unsigned RotAmt = TZ & ~1;
// If we can handle this spread, return it.
if ((ARM_AM_rotr32(Imm, RotAmt) & ~255U) == 0)
return (32 - RotAmt) & 31; // HW rotates right, not left.
// For values like 0xF000000F, we should ignore the low 6 bits, then
// retry the hunt.
if (Imm & 63U) {
unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
unsigned RotAmt2 = TZ2 & ~1;
if ((ARM_AM_rotr32(Imm, RotAmt2) & ~255U) == 0)
return (32 - RotAmt2) &
31; // HW rotates right, not left.
}
// Otherwise, we have no way to cover this span of bits with a single
// shifter_op immediate. Return a chunk of bits that will be useful to
// handle.
return (32 - RotAmt) & 31; // HW rotates right, not left.
}
/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
/// into an shifter_operand immediate operand, return the 12-bit encoding for
/// it. If not, return -1.
static inline int ARM_AM_getSOImmVal(unsigned Arg)
{
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Arg & ~255U) == 0)
return Arg;
unsigned RotAmt = ARM_AM_getSOImmValRotate(Arg);
// If this cannot be handled with a single shifter_op, bail out.
if (ARM_AM_rotr32(~255U, RotAmt) & Arg)
return -1;
// Encode this correctly.
return ARM_AM_rotl32(Arg, RotAmt) | ((RotAmt >> 1) << 8);
}
/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
/// or'ing together two SOImmVal's.
static inline bool ARM_AM_isSOImmTwoPartVal(unsigned V)
{
// If this can be handled with a single shifter_op, bail out.
V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
if (V == 0)
return false;
// If this can be handled with two shifter_op's, accept.
V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
return V == 0;
}
/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
/// return the first chunk of it.
static inline unsigned ARM_AM_getSOImmTwoPartFirst(unsigned V)
{
return ARM_AM_rotr32(255U, ARM_AM_getSOImmValRotate(V)) & V;
}
/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
/// return the second chunk of it.
static inline unsigned ARM_AM_getSOImmTwoPartSecond(unsigned V)
{
// Mask out the first hunk.
V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
// Take what's left.
return V;
}
/// isSOImmTwoPartValNeg - Return true if the specified value can be obtained
/// by two SOImmVal, that -V = First + Second.
/// "R+V" can be optimized to (sub (sub R, First), Second).
/// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
static inline bool ARM_AM_isSOImmTwoPartValNeg(unsigned V)
{
unsigned First;
if (!ARM_AM_isSOImmTwoPartVal(-V))
return false;
// Return false if ~(-First) is not a SoImmval.
First = ARM_AM_getSOImmTwoPartFirst(-V);
First = ~(-First);
return !(ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(First)) & First);
}
/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
/// by a left shift. Returns the shift amount to use.
static inline unsigned ARM_AM_getThumbImmValShift(unsigned Imm)
{
// 8-bit (or less) immediates are trivially immediate operand with a shift
// of zero.
if ((Imm & ~255U) == 0)
return 0;
// Use CTZ to compute the shift amount.
return CountTrailingZeros_32(Imm);
}
/// isThumbImmShiftedVal - Return true if the specified value can be obtained
/// by left shifting a 8-bit immediate.
static inline bool ARM_AM_isThumbImmShiftedVal(unsigned V)
{
// If this can be handled with
V = (~255U << ARM_AM_getThumbImmValShift(V)) & V;
return V == 0;
}
/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
/// by a left shift. Returns the shift amount to use.
static inline unsigned ARM_AM_getThumbImm16ValShift(unsigned Imm)
{
// 16-bit (or less) immediates are trivially immediate operand with a shift
// of zero.
if ((Imm & ~65535U) == 0)
return 0;
// Use CTZ to compute the shift amount.
return CountTrailingZeros_32(Imm);
}
/// isThumbImm16ShiftedVal - Return true if the specified value can be
/// obtained by left shifting a 16-bit immediate.
static inline bool ARM_AM_isThumbImm16ShiftedVal(unsigned V)
{
// If this can be handled with
V = (~65535U << ARM_AM_getThumbImm16ValShift(V)) & V;
return V == 0;
}
/// getThumbImmNonShiftedVal - If V is a value that satisfies
/// isThumbImmShiftedVal, return the non-shiftd value.
static inline unsigned ARM_AM_getThumbImmNonShiftedVal(unsigned V)
{
return V >> ARM_AM_getThumbImmValShift(V);
}
/// getT2SOImmValSplat - Return the 12-bit encoded representation
/// if the specified value can be obtained by splatting the low 8 bits
/// into every other byte or every byte of a 32-bit value. i.e.,
/// 00000000 00000000 00000000 abcdefgh control = 0
/// 00000000 abcdefgh 00000000 abcdefgh control = 1
/// abcdefgh 00000000 abcdefgh 00000000 control = 2
/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
/// Return -1 if none of the above apply.
/// See ARM Reference Manual A6.3.2.
static inline int ARM_AM_getT2SOImmValSplatVal(unsigned V)
{
unsigned u, Vs, Imm;
// control = 0
if ((V & 0xffffff00) == 0)
return V;
// If the value is zeroes in the first byte, just shift those off
Vs = ((V & 0xff) == 0) ? V >> 8 : V;
// Any passing value only has 8 bits of payload, splatted across the word
Imm = Vs & 0xff;
// Likewise, any passing values have the payload splatted into the 3rd byte
u = Imm | (Imm << 16);
// control = 1 or 2
if (Vs == u)
return (((Vs == V) ? 1 : 2) << 8) | Imm;
// control = 3
if (Vs == (u | (u << 8)))
return (3 << 8) | Imm;
return -1;
}
/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
/// specified value is a rotated 8-bit value. Return -1 if no rotation
/// encoding is possible.
/// See ARM Reference Manual A6.3.2.
static inline int ARM_AM_getT2SOImmValRotateVal(unsigned V)
{
unsigned RotAmt = CountLeadingZeros_32(V);
if (RotAmt >= 24)
return -1;
// If 'Arg' can be handled with a single shifter_op return the value.
if ((ARM_AM_rotr32(0xff000000U, RotAmt) & V) == V)
return (ARM_AM_rotr32(V, 24 - RotAmt) & 0x7f) |
((RotAmt + 8) << 7);
return -1;
}
/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
/// encoding for it. If not, return -1.
/// See ARM Reference Manual A6.3.2.
static inline int ARM_AM_getT2SOImmVal(unsigned Arg)
{
// If 'Arg' is an 8-bit splat, then get the encoded value.
int Splat = ARM_AM_getT2SOImmValSplatVal(Arg);
if (Splat != -1)
return Splat;
// If 'Arg' can be handled with a single shifter_op return the value.
int Rot = ARM_AM_getT2SOImmValRotateVal(Arg);
if (Rot != -1)
return Rot;
return -1;
}
static inline unsigned ARM_AM_getT2SOImmValRotate(unsigned V)
{
if ((V & ~255U) == 0)
return 0;
// Use CTZ to compute the rotate amount.
unsigned RotAmt = CountTrailingZeros_32(V);
return (32 - RotAmt) & 31;
}
static inline bool ARM_AM_isT2SOImmTwoPartVal(unsigned Imm)
{
unsigned V = Imm;
// Passing values can be any combination of splat values and shifter
// values. If this can be handled with a single shifter or splat, bail
// out. Those should be handled directly, not with a two-part val.
if (ARM_AM_getT2SOImmValSplatVal(V) != -1)
return false;
V = ARM_AM_rotr32(~255U, ARM_AM_getT2SOImmValRotate(V)) & V;
if (V == 0)
return false;
// If this can be handled as an immediate, accept.
if (ARM_AM_getT2SOImmVal(V) != -1)
return true;
// Likewise, try masking out a splat value first.
V = Imm;
if (ARM_AM_getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
V &= ~0xff00ff00U;
else if (ARM_AM_getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
V &= ~0x00ff00ffU;
// If what's left can be handled as an immediate, accept.
if (ARM_AM_getT2SOImmVal(V) != -1)
return true;
// Otherwise, do not accept.
return false;
}
static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm)
{
CS_ASSERT(ARM_AM_isT2SOImmTwoPartVal(Imm) &&
"Immedate cannot be encoded as two part immediate!");
// Try a shifter operand as one part
unsigned V = ARM_AM_rotr32(~255, ARM_AM_getT2SOImmValRotate(Imm)) & Imm;
// If the rest is encodable as an immediate, then return it.
if (ARM_AM_getT2SOImmVal(V) != -1)
return V;
// Try masking out a splat value first.
if (ARM_AM_getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
return Imm & 0xff00ff00U;
// The other splat is all that's left as an option.
CS_ASSERT(ARM_AM_getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
return Imm & 0x00ff00ffU;
}
static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm)
{
// Mask out the first hunk
Imm ^= ARM_AM_getT2SOImmTwoPartFirst(Imm);
// Return what's left
CS_ASSERT(ARM_AM_getT2SOImmVal(Imm) != -1 &&
"Unable to encode second part of T2 two part SO immediate");
return Imm;
}
//===--------------------------------------------------------------------===//
// Addressing Mode #2
//===--------------------------------------------------------------------===//
//
// This is used for most simple load/store instructions.
//
// addrmode2 := reg +/- reg shop imm
// addrmode2 := reg +/- imm12
//
// The first operand is always a Reg. The second operand is a reg if in
// reg/reg form, otherwise it's reg#0. The third field encodes the operation
// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
// fourth operand 16-17 encodes the index mode.
//
// If this addressing mode is a frame index (before prolog/epilog insertion
// and code rewriting), this operand will have the form: FI#, reg0, <offs>
// with no shift amount for the frame offset.
//
static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12,
ARM_AM_ShiftOpc SO, unsigned IdxMode)
{
CS_ASSERT(Imm12 < (1 << 12) && "Imm too large!");
bool isSub = Opc == ARM_AM_sub;
return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16);
}
static inline unsigned ARM_AM_getAM2Offset(unsigned AM2Opc)
{
return AM2Opc & ((1 << 12) - 1);
}
static inline ARM_AM_AddrOpc ARM_AM_getAM2Op(unsigned AM2Opc)
{
return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
}
static inline ARM_AM_ShiftOpc ARM_AM_getAM2ShiftOpc(unsigned AM2Opc)
{
return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
}
static inline unsigned ARM_AM_getAM2IdxMode(unsigned AM2Opc)
{
return (AM2Opc >> 16);
}
//===--------------------------------------------------------------------===//
// Addressing Mode #3
//===--------------------------------------------------------------------===//
//
// This is used for sign-extending loads, and load/store-pair instructions.
//
// addrmode3 := reg +/- reg
// addrmode3 := reg +/- imm8
//
// The first operand is always a Reg. The second operand is a reg if in
// reg/reg form, otherwise it's reg#0. The third field encodes the operation
// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
// index mode.
/// getAM3Opc - This function encodes the addrmode3 opc field.
static inline unsigned ARM_AM_getAM3Opc(ARM_AM_AddrOpc Opc,
unsigned char Offset, unsigned IdxMode)
{
bool isSub = Opc == ARM_AM_sub;
return ((int)isSub << 8) | Offset | (IdxMode << 9);
}
static inline unsigned char ARM_AM_getAM3Offset(unsigned AM3Opc)
{
return AM3Opc & 0xFF;
}
static inline ARM_AM_AddrOpc ARM_AM_getAM3Op(unsigned AM3Opc)
{
return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
}
static inline unsigned ARM_AM_getAM3IdxMode(unsigned AM3Opc)
{
return (AM3Opc >> 9);
}
//===--------------------------------------------------------------------===//
// Addressing Mode #4
//===--------------------------------------------------------------------===//
//
// This is used for load / store multiple instructions.
//
// addrmode4 := reg, <mode>
//
// The four modes are:
// IA - Increment after
// IB - Increment before
// DA - Decrement after
// DB - Decrement before
// For VFP instructions, only the IA and DB modes are valid.
static inline ARM_AM_SubMode ARM_AM_getAM4SubMode(unsigned Mode)
{
return (ARM_AM_SubMode)(Mode & 0x7);
}
static inline unsigned ARM_AM_getAM4ModeImm(ARM_AM_SubMode SubMode)
{
return (int)SubMode;
}
//===--------------------------------------------------------------------===//
// Addressing Mode #5
//===--------------------------------------------------------------------===//
//
// This is used for coprocessor instructions, such as FP load/stores.
//
// addrmode5 := reg +/- imm8*4
//
// The first operand is always a Reg. The second operand encodes the
// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
/// getAM5Opc - This function encodes the addrmode5 opc field.
static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc,
unsigned char Offset)
{
bool isSub = Opc == ARM_AM_sub;
return ((int)isSub << 8) | Offset;
}
static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
{
return AM5Opc & 0xFF;
}
static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
{
return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
}
//===--------------------------------------------------------------------===//
// Addressing Mode #5 FP16
//===--------------------------------------------------------------------===//
//
// This is used for coprocessor instructions, such as 16-bit FP load/stores.
//
// addrmode5fp16 := reg +/- imm8*2
//
// The first operand is always a Reg. The second operand encodes the
// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
/// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
static inline unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc,
unsigned char Offset)
{
bool isSub = Opc == ARM_AM_sub;
return ((int)isSub << 8) | Offset;
}
static inline unsigned char ARM_AM_getAM5FP16Offset(unsigned AM5Opc)
{
return AM5Opc & 0xFF;
}
static inline ARM_AM_AddrOpc ARM_AM_getAM5FP16Op(unsigned AM5Opc)
{
return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
}
//===--------------------------------------------------------------------===//
// Addressing Mode #6
//===--------------------------------------------------------------------===//
//
// This is used for NEON load / store instructions.
//
// addrmode6 := reg with optional alignment
//
// This is stored in two operands [regaddr, align]. The first is the
// address register. The second operand is the value of the alignment
// specifier in bytes or zero if no explicit alignment.
// Valid alignments depend on the specific instruction.
//===--------------------------------------------------------------------===//
// NEON/MVE Modified Immediates
//===--------------------------------------------------------------------===//
//
// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
// vector operand, where a small immediate encoded in the instruction
// specifies a full NEON vector value. These modified immediates are
// represented here as encoded integers. The low 8 bits hold the immediate
// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
// the "Cmode" field of the instruction. The interfaces below treat the
// Op and Cmode values as a single 5-bit value.
static inline unsigned ARM_AM_createVMOVModImm(unsigned OpCmode, unsigned Val)
{
return (OpCmode << 8) | Val;
}
static inline unsigned ARM_AM_getVMOVModImmOpCmode(unsigned ModImm)
{
return (ModImm >> 8) & 0x1f;
}
static inline unsigned ARM_AM_getVMOVModImmVal(unsigned ModImm)
{
return ModImm & 0xff;
}
/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
/// element value and the element size in bits. (If the element size is
/// smaller than the vector, it is splatted into all the elements.)
static inline uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm,
unsigned *EltBits)
{
unsigned OpCmode = ARM_AM_getVMOVModImmOpCmode(ModImm);
unsigned Imm8 = ARM_AM_getVMOVModImmVal(ModImm);
uint64_t Val = 0;
if (OpCmode == 0xe) {
// 8-bit vector elements
Val = Imm8;
*EltBits = 8;
} else if ((OpCmode & 0xc) == 0x8) {
// 16-bit vector elements
unsigned ByteNum = (OpCmode & 0x6) >> 1;
Val = Imm8 << (8 * ByteNum);
*EltBits = 16;
} else if ((OpCmode & 0x8) == 0) {
// 32-bit vector elements, zero with one byte set
unsigned ByteNum = (OpCmode & 0x6) >> 1;
Val = Imm8 << (8 * ByteNum);
*EltBits = 32;
} else if ((OpCmode & 0xe) == 0xc) {
// 32-bit vector elements, one byte with low bits set
unsigned ByteNum = 1 + (OpCmode & 0x1);
Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
*EltBits = 32;
} else if (OpCmode == 0x1e) {
// 64-bit vector elements
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
if ((ModImm >> ByteNum) & 1)
Val |= (uint64_t)0xff << (8 * ByteNum);
}
*EltBits = 64;
} else {
CS_ASSERT_RET_VAL(0 && "Unsupported VMOV immediate", 0);
}
return Val;
}
// Generic validation for single-byte immediate (0X00, 00X0, etc).
static inline bool ARM_AM_isNEONBytesplat(unsigned Value, unsigned Size)
{
CS_ASSERT(Size >= 1 && Size <= 4 && "Invalid size");
unsigned count = 0;
for (unsigned i = 0; i < Size; ++i) {
if (Value & 0xff)
count++;
Value >>= 8;
}
return count == 1;
}
/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
static inline bool ARM_AM_isNEONi16splat(unsigned Value)
{
if (Value > 0xffff)
return false;
// i16 value with set bits only in one byte X0 or 0X.
return Value == 0 || ARM_AM_isNEONBytesplat(Value, 2);
}
// Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
static inline unsigned ARM_AM_encodeNEONi16splat(unsigned Value)
{
CS_ASSERT(ARM_AM_isNEONi16splat(Value) && "Invalid NEON splat value");
if (Value >= 0x100)
Value = (Value >> 8) | 0xa00;
else
Value |= 0x800;
return Value;
}
/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
static inline bool ARM_AM_isNEONi32splat(unsigned Value)
{
// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
return Value == 0 || ARM_AM_isNEONBytesplat(Value, 4);
}
/// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
static inline unsigned ARM_AM_encodeNEONi32splat(unsigned Value)
{
CS_ASSERT(ARM_AM_isNEONi32splat(Value) && "Invalid NEON splat value");
if (Value >= 0x100 && Value <= 0xff00)
Value = (Value >> 8) | 0x200;
else if (Value > 0xffff && Value <= 0xff0000)
Value = (Value >> 16) | 0x400;
else if (Value > 0xffffff)
Value = (Value >> 24) | 0x600;
return Value;
}
//===--------------------------------------------------------------------===//
// Floating-point Immediates
//
static inline float ARM_AM_getFPImmFloat(unsigned Imm)
{
// We expect an 8-bit binary encoding of a floating-point number here.
uint32_t Sign = (Imm >> 7) & 0x1;
uint32_t Exp = (Imm >> 4) & 0x7;
uint32_t Mantissa = Imm & 0xf;
// 8-bit FP IEEE Float Encoding
// abcd efgh aBbbbbbc defgh000 00000000 00000000
//
// where B = NOT(b);
uint32_t I = 0;
I |= Sign << 31;
I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
I |= (Exp & 0x3) << 23;
I |= Mantissa << 19;
return BitsToFloat(I);
}
#endif // CS_ARM_ADDRESSINGMODES_H
arch/ARM/ARMBaseInfo.c
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file provides basic encoding and assembly information for ARM.
//
//===----------------------------------------------------------------------===//
#include <capstone/platform.h>
#include "ARMBaseInfo.h"
#include "../../utils.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
// CS namespace begin: ARMSysReg
// lookup system register using 12-bit SYSm value.
// Note: the search is uniqued using M1 mask
const char *get_pred_mask(ARM_PredBlockMask pred_mask)
{
switch (pred_mask) {
default:
CS_ASSERT_RET_VAL(0 && "pred_mask not handled.", NULL);
case ARM_T:
return "T";
case ARM_TT:
return "TT";
case ARM_TE:
return "TE";
case ARM_TTT:
return "TTT";
case ARM_TTE:
return "TTE";
case ARM_TEE:
return "TEE";
case ARM_TET:
return "TET";
case ARM_TTTT:
return "TTTT";
case ARM_TTTE:
return "TTTE";
case ARM_TTEE:
return "TTEE";
case ARM_TTET:
return "TTET";
case ARM_TEEE:
return "TEEE";
case ARM_TEET:
return "TEET";
case ARM_TETT:
return "TETT";
case ARM_TETE:
return "TETE";
}
}
#define GET_MCLASSSYSREG_IMPL
#include "ARMGenSystemRegister.inc"
const ARMSysReg_MClassSysReg *
ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
{
return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm);
}
// returns APSR with _<bits> qualifier.
// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
const ARMSysReg_MClassSysReg *
ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
{
return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) |
(SYSm & 0xFF));
}
// lookup system registers using 8-bit SYSm value
const ARMSysReg_MClassSysReg *
ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
{
return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) |
(SYSm & 0xFF));
}
arch/ARM/ARMBaseInfo.h
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//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the ARM target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
#ifndef CS_ARM_BASEINFO_H
#define CS_ARM_BASEINFO_H
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "../../MCInstPrinter.h"
#include "../../cs_priv.h"
#include "capstone/arm.h"
#define GET_INSTRINFO_ENUM
#include "ARMGenInstrInfo.inc"
// System Registers
typedef struct MClassSysReg {
const char *Name;
arm_sysop_reg sysreg;
uint16_t M1Encoding12;
uint16_t M2M3Encoding8;
uint16_t Encoding;
int FeaturesRequired[2];
} ARMSysReg_MClassSysReg;
// return true if FeaturesRequired are all present in ActiveFeatures
static inline bool hasRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
int ActiveFeatures)
{
return (TheReg->FeaturesRequired[0] == ActiveFeatures ||
TheReg->FeaturesRequired[1] == ActiveFeatures);
}
// returns true if TestFeatures are all present in FeaturesRequired
static inline bool
MClassSysReg_isInRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
int TestFeatures)
{
return (TheReg->FeaturesRequired[0] == TestFeatures ||
TheReg->FeaturesRequired[1] == TestFeatures);
}
#define GET_SUBTARGETINFO_ENUM
#include "ARMGenSubtargetInfo.inc"
// lookup system register using 12-bit SYSm value.
// Note: the search is uniqued using M1 mask
const ARMSysReg_MClassSysReg *
ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
// returns APSR with _<bits> qualifier.
// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
const ARMSysReg_MClassSysReg *
ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
// lookup system registers using 8-bit SYSm value
const ARMSysReg_MClassSysReg *
ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
// end namespace ARMSysReg
// Banked Registers
typedef struct BankedReg {
const char *Name;
arm_sysop_reg sysreg;
uint16_t Encoding;
} ARMBankedReg_BankedReg;
#define GET_BANKEDREG_DECL
#define GET_MCLASSSYSREG_DECL
#include "ARMGenSystemRegister.inc"
typedef enum IMod { ARM_PROC_IE = 2, ARM_PROC_ID = 3 } ARM_PROC_IMod;
typedef enum IFlags {
ARM_PROC_F = 1,
ARM_PROC_I = 2,
ARM_PROC_A = 4
} ARM_PROC_IFlags;
inline static const char *ARM_PROC_IFlagsToString(unsigned val)
{
switch (val) {
default:
// llvm_unreachable("Unknown iflags operand");
case ARM_PROC_F:
return "f";
case ARM_PROC_I:
return "i";
case ARM_PROC_A:
return "a";
}
}
inline static const char *ARM_PROC_IModToString(unsigned val)
{
switch (val) {
default:
CS_ASSERT_RET_VAL("Unknown imod operand", NULL);
case ARM_PROC_IE:
return "ie";
case ARM_PROC_ID:
return "id";
}
}
inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
{
switch (val) {
default:
CS_ASSERT_RET_VAL("Unknown memory operation", NULL);
case ARM_MB_SY:
return "sy";
case ARM_MB_ST:
return "st";
case ARM_MB_LD:
return HasV8 ? "ld" : "#0xd";
case ARM_MB_RESERVED_12:
return "#0xc";
case ARM_MB_ISH:
return "ish";
case ARM_MB_ISHST:
return "ishst";
case ARM_MB_ISHLD:
return HasV8 ? "ishld" : "#0x9";
case ARM_MB_RESERVED_8:
return "#0x8";
case ARM_MB_NSH:
return "nsh";
case ARM_MB_NSHST:
return "nshst";
case ARM_MB_NSHLD:
return HasV8 ? "nshld" : "#0x5";
case ARM_MB_RESERVED_4:
return "#0x4";
case ARM_MB_OSH:
return "osh";
case ARM_MB_OSHST:
return "oshst";
case ARM_MB_OSHLD:
return HasV8 ? "oshld" : "#0x1";
case ARM_MB_RESERVED_0:
return "#0x0";
}
}
typedef enum TraceSyncBOpt { ARM_TSB_CSYNC = 0 } ARM_TSB_TraceSyncBOpt;
inline static const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
{
switch (val) {
default:
CS_ASSERT_RET_VAL(
"Unknown trace synchronization barrier operation",
NULL);
case ARM_TSB_CSYNC:
return "csync";
}
}
typedef enum InstSyncBOpt {
ARM_ISB_RESERVED_0 = 0,
ARM_ISB_RESERVED_1 = 1,
ARM_ISB_RESERVED_2 = 2,
ARM_ISB_RESERVED_3 = 3,
ARM_ISB_RESERVED_4 = 4,
ARM_ISB_RESERVED_5 = 5,
ARM_ISB_RESERVED_6 = 6,
ARM_ISB_RESERVED_7 = 7,
ARM_ISB_RESERVED_8 = 8,
ARM_ISB_RESERVED_9 = 9,
ARM_ISB_RESERVED_10 = 10,
ARM_ISB_RESERVED_11 = 11,
ARM_ISB_RESERVED_12 = 12,
ARM_ISB_RESERVED_13 = 13,
ARM_ISB_RESERVED_14 = 14,
ARM_ISB_SY = 15
} ARM_ISB_InstSyncBOpt;
inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
{
switch (val) {
default:
CS_ASSERT_RET_VAL("Unknown memory operation", NULL);
case ARM_ISB_RESERVED_0:
return "#0x0";
case ARM_ISB_RESERVED_1:
return "#0x1";
case ARM_ISB_RESERVED_2:
return "#0x2";
case ARM_ISB_RESERVED_3:
return "#0x3";
case ARM_ISB_RESERVED_4:
return "#0x4";
case ARM_ISB_RESERVED_5:
return "#0x5";
case ARM_ISB_RESERVED_6:
return "#0x6";
case ARM_ISB_RESERVED_7:
return "#0x7";
case ARM_ISB_RESERVED_8:
return "#0x8";
case ARM_ISB_RESERVED_9:
return "#0x9";
case ARM_ISB_RESERVED_10:
return "#0xa";
case ARM_ISB_RESERVED_11:
return "#0xb";
case ARM_ISB_RESERVED_12:
return "#0xc";
case ARM_ISB_RESERVED_13:
return "#0xd";
case ARM_ISB_RESERVED_14:
return "#0xe";
case ARM_ISB_SY:
return "sy";
}
}
#define GET_REGINFO_ENUM
#include "ARMGenRegisterInfo.inc"
/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
///
static inline bool isARMLowRegister(unsigned Reg)
{
switch (Reg) {
case ARM_R0:
case ARM_R1:
case ARM_R2:
case ARM_R3:
case ARM_R4:
case ARM_R5:
case ARM_R6:
case ARM_R7:
return true;
default:
return false;
}
}
/// ARMII - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
/// ARM Index Modes
typedef enum IndexMode {
ARMII_IndexModeNone = 0,
ARMII_IndexModePre = 1,
ARMII_IndexModePost = 2,
ARMII_IndexModeUpd = 3
} ARMII_IndexMode;
/// ARM Addressing Modes
typedef enum AddrMode {
ARMII_AddrModeNone = 0,
ARMII_AddrMode1 = 1,
ARMII_AddrMode2 = 2,
ARMII_AddrMode3 = 3,
ARMII_AddrMode4 = 4,
ARMII_AddrMode5 = 5,
ARMII_AddrMode6 = 6,
ARMII_AddrModeT1_1 = 7,
ARMII_AddrModeT1_2 = 8,
ARMII_AddrModeT1_4 = 9,
ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
ARMII_AddrModeT2_i12 = 11,
ARMII_AddrModeT2_i8 = 12, // +/- i8
ARMII_AddrModeT2_i8pos = 13, // + i8
ARMII_AddrModeT2_i8neg = 14, // - i8
ARMII_AddrModeT2_so = 15,
ARMII_AddrModeT2_pc = 16, // +/- i12 for pc relative data
ARMII_AddrModeT2_i8s4 = 17, // i8 * 4
ARMII_AddrMode_i12 = 18,
ARMII_AddrMode5FP16 = 19, // i8 * 2
ARMII_AddrModeT2_ldrex = 20, // i8 * 4, with unscaled offset in MCInst
ARMII_AddrModeT2_i7s4 = 21, // i7 * 4
ARMII_AddrModeT2_i7s2 = 22, // i7 * 2
ARMII_AddrModeT2_i7 = 23, // i7 * 1
} ARMII_AddrMode;
inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
{
switch (addrmode) {
case ARMII_AddrModeNone:
return "AddrModeNone";
case ARMII_AddrMode1:
return "AddrMode1";
case ARMII_AddrMode2:
return "AddrMode2";
case ARMII_AddrMode3:
return "AddrMode3";
case ARMII_AddrMode4:
return "AddrMode4";
case ARMII_AddrMode5:
return "AddrMode5";
case ARMII_AddrMode5FP16:
return "AddrMode5FP16";
case ARMII_AddrMode6:
return "AddrMode6";
case ARMII_AddrModeT1_1:
return "AddrModeT1_1";
case ARMII_AddrModeT1_2:
return "AddrModeT1_2";
case ARMII_AddrModeT1_4:
return "AddrModeT1_4";
case ARMII_AddrModeT1_s:
return "AddrModeT1_s";
case ARMII_AddrModeT2_i12:
return "AddrModeT2_i12";
case ARMII_AddrModeT2_i8:
return "AddrModeT2_i8";
case ARMII_AddrModeT2_i8pos:
return "AddrModeT2_i8pos";
case ARMII_AddrModeT2_i8neg:
return "AddrModeT2_i8neg";
case ARMII_AddrModeT2_so:
return "AddrModeT2_so";
case ARMII_AddrModeT2_pc:
return "AddrModeT2_pc";
case ARMII_AddrModeT2_i8s4:
return "AddrModeT2_i8s4";
case ARMII_AddrMode_i12:
return "AddrMode_i12";
case ARMII_AddrModeT2_ldrex:
return "AddrModeT2_ldrex";
case ARMII_AddrModeT2_i7s4:
return "AddrModeT2_i7s4";
case ARMII_AddrModeT2_i7s2:
return "AddrModeT2_i7s2";
case ARMII_AddrModeT2_i7:
return "AddrModeT2_i7";
}
}
/// Target Operand Flag enum.
typedef enum TOF {
//===------------------------------------------------------------------===//
// ARM Specific MachineOperand flags.
ARMII_MO_NO_FLAG = 0,
/// MO_LO16 - On a symbol operand, this represents a relocation containing
/// lower 16 bit of the address. Used only via movw instruction.
ARMII_MO_LO16 = 0x1,
/// MO_HI16 - On a symbol operand, this represents a relocation containing
/// higher 16 bit of the address. Used only via movt instruction.
ARMII_MO_HI16 = 0x2,
/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
/// just that part of the flag set.
ARMII_MO_OPTION_MASK = 0x3,
/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
/// reference is actually to the ".refptr.FOO" symbol. This is used for
/// stub symbols on windows.
ARMII_MO_COFFSTUB = 0x4,
/// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
ARMII_MO_GOT = 0x8,
/// MO_SBREL - On a symbol operand, this represents a static base relative
/// relocation. Used in movw and movt instructions.
ARMII_MO_SBREL = 0x10,
/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
/// to the symbol is for an import stub. This is used for DLL import
/// storage class indication on Windows.
ARMII_MO_DLLIMPORT = 0x20,
/// MO_SECREL - On a symbol operand this indicates that the immediate is
/// the offset from beginning of section.
///
/// This is the TLS offset for the COFF/Windows TLS mechanism.
ARMII_MO_SECREL = 0x40,
/// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
/// represents a symbol which, if indirect, will get special Darwin mangling
/// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
/// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
/// example).
ARMII_MO_NONLAZY = 0x80,
// It's undefined behaviour if an enum overflows the range between its
// smallest and largest values, but since these are |ed together, it can
// happen. Put a sentinel in (values of this enum are stored as "unsigned
// char").
ARMII_MO_UNUSED_MAXIMUM = 0xff
} ARMII_TOF;
enum {
//===------------------------------------------------------------------===//
// Instruction Flags.
//===------------------------------------------------------------------===//
// This four-bit field describes the addressing mode used.
ARMII_AddrModeMask =
0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
// and store ops only. Generic "updating" flag is used for ld/st multiple.
// The index mode enums are declared in ARMBaseInfo.h
ARMII_IndexModeShift = 5,
ARMII_IndexModeMask = 3 << ARMII_IndexModeShift,
//===------------------------------------------------------------------===//
// Instruction encoding formats.
//
ARMII_FormShift = 7,
ARMII_FormMask = 0x3f << ARMII_FormShift,
// Pseudo instructions
ARMII_Pseudo = 0 << ARMII_FormShift,
// Multiply instructions
ARMII_MulFrm = 1 << ARMII_FormShift,
// Branch instructions
ARMII_BrFrm = 2 << ARMII_FormShift,
ARMII_BrMiscFrm = 3 << ARMII_FormShift,
// Data Processing instructions
ARMII_DPFrm = 4 << ARMII_FormShift,
ARMII_DPSoRegFrm = 5 << ARMII_FormShift,
// Load and Store
ARMII_LdFrm = 6 << ARMII_FormShift,
ARMII_StFrm = 7 << ARMII_FormShift,
ARMII_LdMiscFrm = 8 << ARMII_FormShift,
ARMII_StMiscFrm = 9 << ARMII_FormShift,
ARMII_LdStMulFrm = 10 << ARMII_FormShift,
ARMII_LdStExFrm = 11 << ARMII_FormShift,
// Miscellaneous arithmetic instructions
ARMII_ArithMiscFrm = 12 << ARMII_FormShift,
ARMII_SatFrm = 13 << ARMII_FormShift,
// Extend instructions
ARMII_ExtFrm = 14 << ARMII_FormShift,
// VFP formats
ARMII_VFPUnaryFrm = 15 << ARMII_FormShift,
ARMII_VFPBinaryFrm = 16 << ARMII_FormShift,
ARMII_VFPConv1Frm = 17 << ARMII_FormShift,
ARMII_VFPConv2Frm = 18 << ARMII_FormShift,
ARMII_VFPConv3Frm = 19 << ARMII_FormShift,
ARMII_VFPConv4Frm = 20 << ARMII_FormShift,
ARMII_VFPConv5Frm = 21 << ARMII_FormShift,
ARMII_VFPLdStFrm = 22 << ARMII_FormShift,
ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
ARMII_VFPMiscFrm = 24 << ARMII_FormShift,
// Thumb format
ARMII_ThumbFrm = 25 << ARMII_FormShift,
// Miscelleaneous format
ARMII_MiscFrm = 26 << ARMII_FormShift,
// NEON formats
ARMII_NGetLnFrm = 27 << ARMII_FormShift,
ARMII_NSetLnFrm = 28 << ARMII_FormShift,
ARMII_NDupFrm = 29 << ARMII_FormShift,
ARMII_NLdStFrm = 30 << ARMII_FormShift,
ARMII_N1RegModImmFrm = 31 << ARMII_FormShift,
ARMII_N2RegFrm = 32 << ARMII_FormShift,
ARMII_NVCVTFrm = 33 << ARMII_FormShift,
ARMII_NVDupLnFrm = 34 << ARMII_FormShift,
ARMII_N2RegVShLFrm = 35 << ARMII_FormShift,
ARMII_N2RegVShRFrm = 36 << ARMII_FormShift,
ARMII_N3RegFrm = 37 << ARMII_FormShift,
ARMII_N3RegVShFrm = 38 << ARMII_FormShift,
ARMII_NVExtFrm = 39 << ARMII_FormShift,
ARMII_NVMulSLFrm = 40 << ARMII_FormShift,
ARMII_NVTBLFrm = 41 << ARMII_FormShift,
ARMII_N3RegCplxFrm = 43 << ARMII_FormShift,
//===------------------------------------------------------------------===//
// Misc flags.
// UnaryDP - Indicates this is a unary data processing instruction, i.e.
// it doesn't have a Rn operand.
ARMII_UnaryDP = 1 << 13,
// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
// a 16-bit Thumb instruction if certain conditions are met.
ARMII_Xform16Bit = 1 << 14,
// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
// instruction. Used by the parser to determine whether to require the 'S'
// suffix on the mnemonic (when not in an IT block) or preclude it (when
// in an IT block).
ARMII_ThumbArithFlagSetting = 1 << 19,
// Whether an instruction can be included in an MVE tail-predicated loop,
// though extra validity checks may need to be performed too.
ARMII_ValidForTailPredication = 1 << 20,
// Whether an instruction writes to the top/bottom half of a vector element
// and leaves the other half untouched.
ARMII_RetainsPreviousHalfElement = 1 << 21,
// Whether the instruction produces a scalar result from vector operands.
ARMII_HorizontalReduction = 1 << 22,
// Whether this instruction produces a vector result that is larger than
// its input, typically reading from the top/bottom halves of the input(s).
ARMII_DoubleWidthResult = 1 << 23,
// The vector element size for MVE instructions. 00 = i8, 01 = i16, 10 = i32
// and 11 = i64. This is the largest type if multiple are present, so a
// MVE_VMOVLs8bh is ize 01=i16, as it extends from a i8 to a i16. There are
// some caveats so cannot be used blindly, such as exchanging VMLADAVA's and
// complex instructions, which may use different input lanes.
ARMII_VecSizeShift = 24,
ARMII_VecSize = 3 << ARMII_VecSizeShift,
//===------------------------------------------------------------------===//
// Code domain.
ARMII_DomainShift = 15,
ARMII_DomainMask = 15 << ARMII_DomainShift,
ARMII_DomainGeneral = 0 << ARMII_DomainShift,
ARMII_DomainVFP = 1 << ARMII_DomainShift,
ARMII_DomainNEON = 2 << ARMII_DomainShift,
ARMII_DomainNEONA8 = 4 << ARMII_DomainShift,
ARMII_DomainMVE = 8 << ARMII_DomainShift,
//===------------------------------------------------------------------===//
// Field shifts - such shifts are used to set field while generating
// machine instructions.
//
// FIXME: This list will need adjusting/fixing as the MC code emitter
// takes shape and the ARMCodeEmitter.cpp bits go away.
ARMII_ShiftTypeShift = 4,
ARMII_M_BitShift = 5,
ARMII_ShiftImmShift = 5,
ARMII_ShiftShift = 7,
ARMII_N_BitShift = 7,
ARMII_ImmHiShift = 8,
ARMII_SoRotImmShift = 8,
ARMII_RegRsShift = 8,
ARMII_ExtRotImmShift = 10,
ARMII_RegRdLoShift = 12,
ARMII_RegRdShift = 12,
ARMII_RegRdHiShift = 16,
ARMII_RegRnShift = 16,
ARMII_S_BitShift = 20,
ARMII_W_BitShift = 21,
ARMII_AM3_I_BitShift = 22,
ARMII_D_BitShift = 22,
ARMII_U_BitShift = 23,
ARMII_P_BitShift = 24,
ARMII_I_BitShift = 25,
ARMII_CondShift = 28
};
const char *get_pred_mask(ARM_PredBlockMask pred_mask);
#endif // CS_ARM_BASEINFO_H
arch/ARM/ARMDisassembler.c
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arch/ARM/ARMDisassemblerExtension.c
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#include "ARMDisassemblerExtension.h"
#include "ARMBaseInfo.h"
bool ITBlock_push_back(ARM_ITBlock *it, char v)
{
if (it->size >= sizeof(it->ITStates)) {
// TODO: consider warning user.
it->size = 0;
}
it->ITStates[it->size] = v;
it->size++;
return true;
}
// Returns true if the current instruction is in an IT block
bool ITBlock_instrInITBlock(ARM_ITBlock *it)
{
return (it->size > 0);
}
// Returns true if current instruction is the last instruction in an IT block
bool ITBlock_instrLastInITBlock(ARM_ITBlock *it)
{
return (it->size == 1);
}
// Returns the condition code for instruction in IT block
unsigned ITBlock_getITCC(ARM_ITBlock *it)
{
unsigned CC = ARMCC_AL;
if (ITBlock_instrInITBlock(it))
CC = it->ITStates[it->size - 1];
return CC;
}
// Advances the IT block state to the next T or E
void ITBlock_advanceITState(ARM_ITBlock *it)
{
it->size--;
}
// Called when decoding an IT instruction. Sets the IT state for the following
// instructions that for the IT block. Firstcond and Mask correspond to the
// fields in the IT instruction encoding.
void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask)
{
// (3 - the number of trailing zeros) is the number of then / else.
unsigned NumTZ = CountTrailingZeros_8(Mask);
unsigned char CCBits = (unsigned char)(Firstcond & 0xf);
CS_ASSERT_RET(NumTZ <= 3 && "Invalid IT mask!");
// push condition codes onto the stack the correct order for the pops
for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
unsigned Else = (Mask >> Pos) & 1;
ITBlock_push_back(it, CCBits ^ Else);
}
ITBlock_push_back(it, CCBits);
}
bool VPTBlock_push_back(ARM_VPTBlock *it, char v)
{
if (it->size >= sizeof(it->VPTStates)) {
// TODO: consider warning user.
it->size = 0;
}
it->VPTStates[it->size] = v;
it->size++;
return true;
}
bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT)
{
return VPT->size > 0;
}
unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT)
{
unsigned Pred = ARMVCC_None;
if (VPTBlock_instrInVPTBlock(VPT))
Pred = VPT->VPTStates[VPT->size - 1];
return Pred;
}
void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT)
{
VPT->size--;
}
void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask)
{
// (3 - the number of trailing zeros) is the number of then / else.
unsigned NumTZ = CountTrailingZeros_8(Mask);
CS_ASSERT_RET(NumTZ <= 3 && "Invalid VPT mask!");
// push predicates onto the stack the correct order for the pops
for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
bool T = ((Mask >> Pos) & 1) == 0;
if (T)
VPTBlock_push_back(VPT, ARMVCC_Then);
else
VPTBlock_push_back(VPT, ARMVCC_Else);
}
VPTBlock_push_back(VPT, ARMVCC_Then);
}
// Imported from ARMBaseInstrInfo.h
//
/// isValidCoprocessorNumber - decide whether an explicit coprocessor
/// number is legal in generic instructions like CDP. The answer can
/// vary with the subtarget.
bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num)
{
// In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
// coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
// useful for code which is shared with older architectures which do not
// know the new VFP/NEON mnemonics.
// Armv8-A disallows everything *other* than 111x (CP14 and CP15).
if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) &&
(Num & 0xE) != 0xE)
return false;
// Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
// which clash with MVE.
if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) &&
((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
return false;
return true;
}
// Imported from ARMMCTargetDesc.h
bool ARM_isVpred(arm_op_type op)
{
return op == ARM_OP_VPRED_R || op == ARM_OP_VPRED_N;
}
// Imported from ARMBaseInstrInfo.h
//
// This table shows the VPT instruction variants, i.e. the different
// mask field encodings, see also B5.6. Predication/conditional execution in
// the ArmARM.
bool isVPTOpcode(int Opc)
{
return Opc == ARM_MVE_VPTv16i8 || Opc == ARM_MVE_VPTv16u8 ||
Opc == ARM_MVE_VPTv16s8 || Opc == ARM_MVE_VPTv8i16 ||
Opc == ARM_MVE_VPTv8u16 || Opc == ARM_MVE_VPTv8s16 ||
Opc == ARM_MVE_VPTv4i32 || Opc == ARM_MVE_VPTv4u32 ||
Opc == ARM_MVE_VPTv4s32 || Opc == ARM_MVE_VPTv4f32 ||
Opc == ARM_MVE_VPTv8f16 || Opc == ARM_MVE_VPTv16i8r ||
Opc == ARM_MVE_VPTv16u8r || Opc == ARM_MVE_VPTv16s8r ||
Opc == ARM_MVE_VPTv8i16r || Opc == ARM_MVE_VPTv8u16r ||
Opc == ARM_MVE_VPTv8s16r || Opc == ARM_MVE_VPTv4i32r ||
Opc == ARM_MVE_VPTv4u32r || Opc == ARM_MVE_VPTv4s32r ||
Opc == ARM_MVE_VPTv4f32r || Opc == ARM_MVE_VPTv8f16r ||
Opc == ARM_MVE_VPST;
}
// Imported from ARMMCTargetDesc.cpp
bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI)
{
// Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
// to rely on feature bits.
if (Coproc >= 8)
return false;
return ARM_getFeatureBits(MI->csh->mode,
ARM_FeatureCoprocCDE0 + Coproc);
}
// Hacky: enable all features for disassembler
bool ARM_getFeatureBits(unsigned int mode, unsigned int feature)
{
if (feature == ARM_ModeThumb) {
if (mode & CS_MODE_THUMB)
return true;
return false;
}
if (feature == ARM_FeatureDFB)
return false;
if (feature == ARM_FeatureRAS)
return false;
if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0)
return false;
if ((feature == ARM_HasMVEIntegerOps || feature == ARM_HasMVEFloatOps ||
feature == ARM_FeatureMVEVectorCostFactor1 ||
feature == ARM_FeatureMVEVectorCostFactor2 ||
feature == ARM_FeatureMVEVectorCostFactor4) &&
(mode & CS_MODE_MCLASS) == 0)
return false;
if ((feature == ARM_HasV8Ops || feature == ARM_HasV8_1MMainlineOps ||
feature == ARM_HasV8_1aOps || feature == ARM_HasV8_2aOps ||
feature == ARM_HasV8_3aOps || feature == ARM_HasV8_4aOps ||
feature == ARM_HasV8_5aOps || feature == ARM_HasV8_6aOps ||
feature == ARM_HasV8_7aOps || feature == ARM_HasV8_8aOps ||
feature == ARM_HasV8_9aOps) &&
(mode & CS_MODE_V8) == 0)
return false;
if (feature >= ARM_FeatureCoprocCDE0 &&
feature <= ARM_FeatureCoprocCDE7)
// We currently have no way to detect CDE (Custom-Datapath-Extension)
// coprocessors.
return false;
// we support everything
return true;
}
arch/ARM/ARMDisassemblerExtension.h
+49
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@@ -0,0 +1,49 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#ifndef CS_ARM_DISASSEMBLER_EXTENSION_H
#define CS_ARM_DISASSEMBLER_EXTENSION_H
#include "../../MCDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "../../cs_priv.h"
#include "ARMAddressingModes.h"
#include "capstone/capstone.h"
unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset);
bool ITBlock_push_back(ARM_ITBlock *it, char v);
bool ITBlock_instrInITBlock(ARM_ITBlock *it);
bool ITBlock_instrLastInITBlock(ARM_ITBlock *it);
unsigned ITBlock_getITCC(ARM_ITBlock *it);
void ITBlock_advanceITState(ARM_ITBlock *it);
void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask);
bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num);
bool ARM_isVpred(arm_op_type op);
bool isVPTOpcode(int Opc);
bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI);
bool VPTBlock_push_back(ARM_VPTBlock *it, char v);
bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT);
unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT);
void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT);
void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask);
bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
#endif // CS_ARM_DISASSEMBLER_EXTENSION_H
arch/ARM/ARMFeatureEnum.inc
+22
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ARM_FEATURE_IsThumb = 128, ARM_FEATURE_IsARM, ARM_FEATURE_UseNegativeImmediates,
ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasAES,
ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, ARM_FEATURE_HasV7,
ARM_FEATURE_IsMClass, ARM_FEATURE_HasPACBTI, ARM_FEATURE_HasV8MBaseline,
ARM_FEATURE_HasLOB, ARM_FEATURE_HasV6T2, ARM_FEATURE_HasV5T,
ARM_FEATURE_IsNotMClass, ARM_FEATURE_Has8MSecExt, ARM_FEATURE_HasV4T,
ARM_FEATURE_PreV8, ARM_FEATURE_HasCLRBHB, ARM_FEATURE_HasV6K,
ARM_FEATURE_HasV7Clrex, ARM_FEATURE_HasCRC, ARM_FEATURE_HasCDE,
ARM_FEATURE_HasDFB, ARM_FEATURE_HasDB, ARM_FEATURE_HasVirtualization,
ARM_FEATURE_HasRAS, ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP,
ARM_FEATURE_HasVFP3, ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV6M,
ARM_FEATURE_HasV6, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV5TE,
ARM_FEATURE_HasDSP, ARM_FEATURE_HasMP, ARM_FEATURE_HasSB,
ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_HasDivideInARM,
ARM_FEATURE_HasV8_1a, ARM_FEATURE_HasSHA2, ARM_FEATURE_HasTrustZone,
ARM_FEATURE_UseNaClTrap, ARM_FEATURE_HasV8_4a, ARM_FEATURE_HasNEON,
ARM_FEATURE_HasFullFP16, ARM_FEATURE_HasMVEFloat, ARM_FEATURE_HasV8_3a,
ARM_FEATURE_HasFP16, ARM_FEATURE_HasBF16, ARM_FEATURE_HasFPARMv8,
ARM_FEATURE_HasVFP4, ARM_FEATURE_HasFP16FML, ARM_FEATURE_HasFPRegs16,
ARM_FEATURE_HasV8MMainline, ARM_FEATURE_HasFPRegs64,
ARM_FEATURE_HasFPRegsV8_1M, ARM_FEATURE_HasDotProd,
ARM_FEATURE_HasMatMulInt8,
arch/ARM/ARMGenAsmWriter.inc
+13428
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arch/ARM/ARMGenCSAliasMnemMap.inc
+48
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@@ -0,0 +1,48 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ ARM_INS_ALIAS_VMOV, "vmov" },
{ ARM_INS_ALIAS_NOP, "nop" },
{ ARM_INS_ALIAS_YIELD, "yield" },
{ ARM_INS_ALIAS_WFE, "wfe" },
{ ARM_INS_ALIAS_WFI, "wfi" },
{ ARM_INS_ALIAS_SEV, "sev" },
{ ARM_INS_ALIAS_SEVL, "sevl" },
{ ARM_INS_ALIAS_ESB, "esb" },
{ ARM_INS_ALIAS_CSDB, "csdb" },
{ ARM_INS_ALIAS_CLRBHB, "clrbhb" },
{ ARM_INS_ALIAS_PACBTI, "pacbti" },
{ ARM_INS_ALIAS_BTI, "bti" },
{ ARM_INS_ALIAS_PAC, "pac" },
{ ARM_INS_ALIAS_AUT, "aut" },
{ ARM_INS_ALIAS_SSBB, "ssbb" },
{ ARM_INS_ALIAS_PSSBB, "pssbb" },
{ ARM_INS_ALIAS_DFB, "dfb" },
{ ARM_INS_ALIAS_CSETM, "csetm" },
{ ARM_INS_ALIAS_CSET, "cset" },
{ ARM_INS_ALIAS_CINC, "cinc" },
{ ARM_INS_ALIAS_CINV, "cinv" },
{ ARM_INS_ALIAS_CNEG, "cneg" },
{ ARM_INS_ALIAS_VMLAV, "vmlav" },
{ ARM_INS_ALIAS_VMLAVA, "vmlava" },
{ ARM_INS_ALIAS_VRMLALVH, "vrmlalvh" },
{ ARM_INS_ALIAS_VRMLALVHA, "vrmlalvha" },
{ ARM_INS_ALIAS_VMLALV, "vmlalv" },
{ ARM_INS_ALIAS_VMLALVA, "vmlalva" },
{ ARM_INS_ALIAS_VBIC, "vbic" },
{ ARM_INS_ALIAS_VEOR, "veor" },
{ ARM_INS_ALIAS_VORN, "vorn" },
{ ARM_INS_ALIAS_VORR, "vorr" },
{ ARM_INS_ALIAS_VAND, "vand" },
{ ARM_INS_ALIAS_VPSEL, "vpsel" },
{ ARM_INS_ALIAS_ERET, "eret" },
arch/ARM/ARMGenCSFeatureName.inc
+80
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ ARM_FEATURE_HASV4T, "HasV4T" },
{ ARM_FEATURE_HASV5T, "HasV5T" },
{ ARM_FEATURE_HASV5TE, "HasV5TE" },
{ ARM_FEATURE_HASV6, "HasV6" },
{ ARM_FEATURE_HASV6M, "HasV6M" },
{ ARM_FEATURE_HASV8MBASELINE, "HasV8MBaseline" },
{ ARM_FEATURE_HASV8MMAINLINE, "HasV8MMainline" },
{ ARM_FEATURE_HASV8_1MMAINLINE, "HasV8_1MMainline" },
{ ARM_FEATURE_HASMVEINT, "HasMVEInt" },
{ ARM_FEATURE_HASMVEFLOAT, "HasMVEFloat" },
{ ARM_FEATURE_HASCDE, "HasCDE" },
{ ARM_FEATURE_HASFPREGS, "HasFPRegs" },
{ ARM_FEATURE_HASFPREGS16, "HasFPRegs16" },
{ ARM_FEATURE_HASNOFPREGS16, "HasNoFPRegs16" },
{ ARM_FEATURE_HASFPREGS64, "HasFPRegs64" },
{ ARM_FEATURE_HASFPREGSV8_1M, "HasFPRegsV8_1M" },
{ ARM_FEATURE_HASV6T2, "HasV6T2" },
{ ARM_FEATURE_HASV6K, "HasV6K" },
{ ARM_FEATURE_HASV7, "HasV7" },
{ ARM_FEATURE_HASV8, "HasV8" },
{ ARM_FEATURE_PREV8, "PreV8" },
{ ARM_FEATURE_HASV8_1A, "HasV8_1a" },
{ ARM_FEATURE_HASV8_2A, "HasV8_2a" },
{ ARM_FEATURE_HASV8_3A, "HasV8_3a" },
{ ARM_FEATURE_HASV8_4A, "HasV8_4a" },
{ ARM_FEATURE_HASV8_5A, "HasV8_5a" },
{ ARM_FEATURE_HASV8_6A, "HasV8_6a" },
{ ARM_FEATURE_HASV8_7A, "HasV8_7a" },
{ ARM_FEATURE_HASVFP2, "HasVFP2" },
{ ARM_FEATURE_HASVFP3, "HasVFP3" },
{ ARM_FEATURE_HASVFP4, "HasVFP4" },
{ ARM_FEATURE_HASDPVFP, "HasDPVFP" },
{ ARM_FEATURE_HASFPARMV8, "HasFPARMv8" },
{ ARM_FEATURE_HASNEON, "HasNEON" },
{ ARM_FEATURE_HASSHA2, "HasSHA2" },
{ ARM_FEATURE_HASAES, "HasAES" },
{ ARM_FEATURE_HASCRYPTO, "HasCrypto" },
{ ARM_FEATURE_HASDOTPROD, "HasDotProd" },
{ ARM_FEATURE_HASCRC, "HasCRC" },
{ ARM_FEATURE_HASRAS, "HasRAS" },
{ ARM_FEATURE_HASLOB, "HasLOB" },
{ ARM_FEATURE_HASPACBTI, "HasPACBTI" },
{ ARM_FEATURE_HASFP16, "HasFP16" },
{ ARM_FEATURE_HASFULLFP16, "HasFullFP16" },
{ ARM_FEATURE_HASFP16FML, "HasFP16FML" },
{ ARM_FEATURE_HASBF16, "HasBF16" },
{ ARM_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
{ ARM_FEATURE_HASDIVIDEINTHUMB, "HasDivideInThumb" },
{ ARM_FEATURE_HASDIVIDEINARM, "HasDivideInARM" },
{ ARM_FEATURE_HASDSP, "HasDSP" },
{ ARM_FEATURE_HASDB, "HasDB" },
{ ARM_FEATURE_HASDFB, "HasDFB" },
{ ARM_FEATURE_HASV7CLREX, "HasV7Clrex" },
{ ARM_FEATURE_HASACQUIRERELEASE, "HasAcquireRelease" },
{ ARM_FEATURE_HASMP, "HasMP" },
{ ARM_FEATURE_HASVIRTUALIZATION, "HasVirtualization" },
{ ARM_FEATURE_HASTRUSTZONE, "HasTrustZone" },
{ ARM_FEATURE_HAS8MSECEXT, "Has8MSecExt" },
{ ARM_FEATURE_ISTHUMB, "IsThumb" },
{ ARM_FEATURE_ISTHUMB2, "IsThumb2" },
{ ARM_FEATURE_ISMCLASS, "IsMClass" },
{ ARM_FEATURE_ISNOTMCLASS, "IsNotMClass" },
{ ARM_FEATURE_ISARM, "IsARM" },
{ ARM_FEATURE_USENACLTRAP, "UseNaClTrap" },
{ ARM_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
{ ARM_FEATURE_HASSB, "HasSB" },
{ ARM_FEATURE_HASCLRBHB, "HasCLRBHB" },
arch/ARM/ARMGenCSMappingInsn.inc
+34947
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arch/ARM/ARMGenCSMappingInsnName.inc
+650
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
"invalid", // ARM_INS_INVALID
"asr", // ARM_INS_ASR
"it", // ARM_INS_IT
"ldrbt", // ARM_INS_LDRBT
"ldr", // ARM_INS_LDR
"ldrht", // ARM_INS_LDRHT
"ldrsbt", // ARM_INS_LDRSBT
"ldrsht", // ARM_INS_LDRSHT
"ldrt", // ARM_INS_LDRT
"lsl", // ARM_INS_LSL
"lsr", // ARM_INS_LSR
"ror", // ARM_INS_ROR
"rrx", // ARM_INS_RRX
"strbt", // ARM_INS_STRBT
"strt", // ARM_INS_STRT
"vld1", // ARM_INS_VLD1
"vld2", // ARM_INS_VLD2
"vld3", // ARM_INS_VLD3
"vld4", // ARM_INS_VLD4
"vst1", // ARM_INS_VST1
"vst2", // ARM_INS_VST2
"vst3", // ARM_INS_VST3
"vst4", // ARM_INS_VST4
"ldrb", // ARM_INS_LDRB
"ldrh", // ARM_INS_LDRH
"ldrsb", // ARM_INS_LDRSB
"ldrsh", // ARM_INS_LDRSH
"movs", // ARM_INS_MOVS
"mov", // ARM_INS_MOV
"strb", // ARM_INS_STRB
"strh", // ARM_INS_STRH
"str", // ARM_INS_STR
"adc", // ARM_INS_ADC
"add", // ARM_INS_ADD
"adr", // ARM_INS_ADR
"aesd", // ARM_INS_AESD
"aese", // ARM_INS_AESE
"aesimc", // ARM_INS_AESIMC
"aesmc", // ARM_INS_AESMC
"and", // ARM_INS_AND
"vdot", // ARM_INS_VDOT
"vcvt", // ARM_INS_VCVT
"vcvtb", // ARM_INS_VCVTB
"vcvtt", // ARM_INS_VCVTT
"bfc", // ARM_INS_BFC
"bfi", // ARM_INS_BFI
"bic", // ARM_INS_BIC
"bkpt", // ARM_INS_BKPT
"bl", // ARM_INS_BL
"blx", // ARM_INS_BLX
"bx", // ARM_INS_BX
"bxj", // ARM_INS_BXJ
"b", // ARM_INS_B
"cx1", // ARM_INS_CX1
"cx1a", // ARM_INS_CX1A
"cx1d", // ARM_INS_CX1D
"cx1da", // ARM_INS_CX1DA
"cx2", // ARM_INS_CX2
"cx2a", // ARM_INS_CX2A
"cx2d", // ARM_INS_CX2D
"cx2da", // ARM_INS_CX2DA
"cx3", // ARM_INS_CX3
"cx3a", // ARM_INS_CX3A
"cx3d", // ARM_INS_CX3D
"cx3da", // ARM_INS_CX3DA
"vcx1a", // ARM_INS_VCX1A
"vcx1", // ARM_INS_VCX1
"vcx2a", // ARM_INS_VCX2A
"vcx2", // ARM_INS_VCX2
"vcx3a", // ARM_INS_VCX3A
"vcx3", // ARM_INS_VCX3
"cdp", // ARM_INS_CDP
"cdp2", // ARM_INS_CDP2
"clrex", // ARM_INS_CLREX
"clz", // ARM_INS_CLZ
"cmn", // ARM_INS_CMN
"cmp", // ARM_INS_CMP
"cps", // ARM_INS_CPS
"crc32b", // ARM_INS_CRC32B
"crc32cb", // ARM_INS_CRC32CB
"crc32ch", // ARM_INS_CRC32CH
"crc32cw", // ARM_INS_CRC32CW
"crc32h", // ARM_INS_CRC32H
"crc32w", // ARM_INS_CRC32W
"dbg", // ARM_INS_DBG
"dmb", // ARM_INS_DMB
"dsb", // ARM_INS_DSB
"eor", // ARM_INS_EOR
"eret", // ARM_INS_ERET
"vmov", // ARM_INS_VMOV
"fldmdbx", // ARM_INS_FLDMDBX
"fldmiax", // ARM_INS_FLDMIAX
"vmrs", // ARM_INS_VMRS
"fstmdbx", // ARM_INS_FSTMDBX
"fstmiax", // ARM_INS_FSTMIAX
"hint", // ARM_INS_HINT
"hlt", // ARM_INS_HLT
"hvc", // ARM_INS_HVC
"isb", // ARM_INS_ISB
"lda", // ARM_INS_LDA
"ldab", // ARM_INS_LDAB
"ldaex", // ARM_INS_LDAEX
"ldaexb", // ARM_INS_LDAEXB
"ldaexd", // ARM_INS_LDAEXD
"ldaexh", // ARM_INS_LDAEXH
"ldah", // ARM_INS_LDAH
"ldc2l", // ARM_INS_LDC2L
"ldc2", // ARM_INS_LDC2
"ldcl", // ARM_INS_LDCL
"ldc", // ARM_INS_LDC
"ldmda", // ARM_INS_LDMDA
"ldmdb", // ARM_INS_LDMDB
"ldm", // ARM_INS_LDM
"ldmib", // ARM_INS_LDMIB
"ldrd", // ARM_INS_LDRD
"ldrex", // ARM_INS_LDREX
"ldrexb", // ARM_INS_LDREXB
"ldrexd", // ARM_INS_LDREXD
"ldrexh", // ARM_INS_LDREXH
"mcr", // ARM_INS_MCR
"mcr2", // ARM_INS_MCR2
"mcrr", // ARM_INS_MCRR
"mcrr2", // ARM_INS_MCRR2
"mla", // ARM_INS_MLA
"mls", // ARM_INS_MLS
"movt", // ARM_INS_MOVT
"movw", // ARM_INS_MOVW
"mrc", // ARM_INS_MRC
"mrc2", // ARM_INS_MRC2
"mrrc", // ARM_INS_MRRC
"mrrc2", // ARM_INS_MRRC2
"mrs", // ARM_INS_MRS
"msr", // ARM_INS_MSR
"mul", // ARM_INS_MUL
"asrl", // ARM_INS_ASRL
"dlstp", // ARM_INS_DLSTP
"lctp", // ARM_INS_LCTP
"letp", // ARM_INS_LETP
"lsll", // ARM_INS_LSLL
"lsrl", // ARM_INS_LSRL
"sqrshr", // ARM_INS_SQRSHR
"sqrshrl", // ARM_INS_SQRSHRL
"sqshl", // ARM_INS_SQSHL
"sqshll", // ARM_INS_SQSHLL
"srshr", // ARM_INS_SRSHR
"srshrl", // ARM_INS_SRSHRL
"uqrshl", // ARM_INS_UQRSHL
"uqrshll", // ARM_INS_UQRSHLL
"uqshl", // ARM_INS_UQSHL
"uqshll", // ARM_INS_UQSHLL
"urshr", // ARM_INS_URSHR
"urshrl", // ARM_INS_URSHRL
"vabav", // ARM_INS_VABAV
"vabd", // ARM_INS_VABD
"vabs", // ARM_INS_VABS
"vadc", // ARM_INS_VADC
"vadci", // ARM_INS_VADCI
"vaddlva", // ARM_INS_VADDLVA
"vaddlv", // ARM_INS_VADDLV
"vaddva", // ARM_INS_VADDVA
"vaddv", // ARM_INS_VADDV
"vadd", // ARM_INS_VADD
"vand", // ARM_INS_VAND
"vbic", // ARM_INS_VBIC
"vbrsr", // ARM_INS_VBRSR
"vcadd", // ARM_INS_VCADD
"vcls", // ARM_INS_VCLS
"vclz", // ARM_INS_VCLZ
"vcmla", // ARM_INS_VCMLA
"vcmp", // ARM_INS_VCMP
"vcmul", // ARM_INS_VCMUL
"vctp", // ARM_INS_VCTP
"vcvta", // ARM_INS_VCVTA
"vcvtm", // ARM_INS_VCVTM
"vcvtn", // ARM_INS_VCVTN
"vcvtp", // ARM_INS_VCVTP
"vddup", // ARM_INS_VDDUP
"vdup", // ARM_INS_VDUP
"vdwdup", // ARM_INS_VDWDUP
"veor", // ARM_INS_VEOR
"vfmas", // ARM_INS_VFMAS
"vfma", // ARM_INS_VFMA
"vfms", // ARM_INS_VFMS
"vhadd", // ARM_INS_VHADD
"vhcadd", // ARM_INS_VHCADD
"vhsub", // ARM_INS_VHSUB
"vidup", // ARM_INS_VIDUP
"viwdup", // ARM_INS_VIWDUP
"vld20", // ARM_INS_VLD20
"vld21", // ARM_INS_VLD21
"vld40", // ARM_INS_VLD40
"vld41", // ARM_INS_VLD41
"vld42", // ARM_INS_VLD42
"vld43", // ARM_INS_VLD43
"vldrb", // ARM_INS_VLDRB
"vldrd", // ARM_INS_VLDRD
"vldrh", // ARM_INS_VLDRH
"vldrw", // ARM_INS_VLDRW
"vmaxav", // ARM_INS_VMAXAV
"vmaxa", // ARM_INS_VMAXA
"vmaxnmav", // ARM_INS_VMAXNMAV
"vmaxnma", // ARM_INS_VMAXNMA
"vmaxnmv", // ARM_INS_VMAXNMV
"vmaxnm", // ARM_INS_VMAXNM
"vmaxv", // ARM_INS_VMAXV
"vmax", // ARM_INS_VMAX
"vminav", // ARM_INS_VMINAV
"vmina", // ARM_INS_VMINA
"vminnmav", // ARM_INS_VMINNMAV
"vminnma", // ARM_INS_VMINNMA
"vminnmv", // ARM_INS_VMINNMV
"vminnm", // ARM_INS_VMINNM
"vminv", // ARM_INS_VMINV
"vmin", // ARM_INS_VMIN
"vmladava", // ARM_INS_VMLADAVA
"vmladavax", // ARM_INS_VMLADAVAX
"vmladav", // ARM_INS_VMLADAV
"vmladavx", // ARM_INS_VMLADAVX
"vmlaldava", // ARM_INS_VMLALDAVA
"vmlaldavax", // ARM_INS_VMLALDAVAX
"vmlaldav", // ARM_INS_VMLALDAV
"vmlaldavx", // ARM_INS_VMLALDAVX
"vmlas", // ARM_INS_VMLAS
"vmla", // ARM_INS_VMLA
"vmlsdava", // ARM_INS_VMLSDAVA
"vmlsdavax", // ARM_INS_VMLSDAVAX
"vmlsdav", // ARM_INS_VMLSDAV
"vmlsdavx", // ARM_INS_VMLSDAVX
"vmlsldava", // ARM_INS_VMLSLDAVA
"vmlsldavax", // ARM_INS_VMLSLDAVAX
"vmlsldav", // ARM_INS_VMLSLDAV
"vmlsldavx", // ARM_INS_VMLSLDAVX
"vmovlb", // ARM_INS_VMOVLB
"vmovlt", // ARM_INS_VMOVLT
"vmovnb", // ARM_INS_VMOVNB
"vmovnt", // ARM_INS_VMOVNT
"vmulh", // ARM_INS_VMULH
"vmullb", // ARM_INS_VMULLB
"vmullt", // ARM_INS_VMULLT
"vmul", // ARM_INS_VMUL
"vmvn", // ARM_INS_VMVN
"vneg", // ARM_INS_VNEG
"vorn", // ARM_INS_VORN
"vorr", // ARM_INS_VORR
"vpnot", // ARM_INS_VPNOT
"vpsel", // ARM_INS_VPSEL
"vpst", // ARM_INS_VPST
"vpt", // ARM_INS_VPT
"vqabs", // ARM_INS_VQABS
"vqadd", // ARM_INS_VQADD
"vqdmladhx", // ARM_INS_VQDMLADHX
"vqdmladh", // ARM_INS_VQDMLADH
"vqdmlah", // ARM_INS_VQDMLAH
"vqdmlash", // ARM_INS_VQDMLASH
"vqdmlsdhx", // ARM_INS_VQDMLSDHX
"vqdmlsdh", // ARM_INS_VQDMLSDH
"vqdmulh", // ARM_INS_VQDMULH
"vqdmullb", // ARM_INS_VQDMULLB
"vqdmullt", // ARM_INS_VQDMULLT
"vqmovnb", // ARM_INS_VQMOVNB
"vqmovnt", // ARM_INS_VQMOVNT
"vqmovunb", // ARM_INS_VQMOVUNB
"vqmovunt", // ARM_INS_VQMOVUNT
"vqneg", // ARM_INS_VQNEG
"vqrdmladhx", // ARM_INS_VQRDMLADHX
"vqrdmladh", // ARM_INS_VQRDMLADH
"vqrdmlah", // ARM_INS_VQRDMLAH
"vqrdmlash", // ARM_INS_VQRDMLASH
"vqrdmlsdhx", // ARM_INS_VQRDMLSDHX
"vqrdmlsdh", // ARM_INS_VQRDMLSDH
"vqrdmulh", // ARM_INS_VQRDMULH
"vqrshl", // ARM_INS_VQRSHL
"vqrshrnb", // ARM_INS_VQRSHRNB
"vqrshrnt", // ARM_INS_VQRSHRNT
"vqrshrunb", // ARM_INS_VQRSHRUNB
"vqrshrunt", // ARM_INS_VQRSHRUNT
"vqshlu", // ARM_INS_VQSHLU
"vqshl", // ARM_INS_VQSHL
"vqshrnb", // ARM_INS_VQSHRNB
"vqshrnt", // ARM_INS_VQSHRNT
"vqshrunb", // ARM_INS_VQSHRUNB
"vqshrunt", // ARM_INS_VQSHRUNT
"vqsub", // ARM_INS_VQSUB
"vrev16", // ARM_INS_VREV16
"vrev32", // ARM_INS_VREV32
"vrev64", // ARM_INS_VREV64
"vrhadd", // ARM_INS_VRHADD
"vrinta", // ARM_INS_VRINTA
"vrintm", // ARM_INS_VRINTM
"vrintn", // ARM_INS_VRINTN
"vrintp", // ARM_INS_VRINTP
"vrintx", // ARM_INS_VRINTX
"vrintz", // ARM_INS_VRINTZ
"vrmlaldavha", // ARM_INS_VRMLALDAVHA
"vrmlaldavhax", // ARM_INS_VRMLALDAVHAX
"vrmlaldavh", // ARM_INS_VRMLALDAVH
"vrmlaldavhx", // ARM_INS_VRMLALDAVHX
"vrmlsldavha", // ARM_INS_VRMLSLDAVHA
"vrmlsldavhax", // ARM_INS_VRMLSLDAVHAX
"vrmlsldavh", // ARM_INS_VRMLSLDAVH
"vrmlsldavhx", // ARM_INS_VRMLSLDAVHX
"vrmulh", // ARM_INS_VRMULH
"vrshl", // ARM_INS_VRSHL
"vrshrnb", // ARM_INS_VRSHRNB
"vrshrnt", // ARM_INS_VRSHRNT
"vrshr", // ARM_INS_VRSHR
"vsbc", // ARM_INS_VSBC
"vsbci", // ARM_INS_VSBCI
"vshlc", // ARM_INS_VSHLC
"vshllb", // ARM_INS_VSHLLB
"vshllt", // ARM_INS_VSHLLT
"vshl", // ARM_INS_VSHL
"vshrnb", // ARM_INS_VSHRNB
"vshrnt", // ARM_INS_VSHRNT
"vshr", // ARM_INS_VSHR
"vsli", // ARM_INS_VSLI
"vsri", // ARM_INS_VSRI
"vst20", // ARM_INS_VST20
"vst21", // ARM_INS_VST21
"vst40", // ARM_INS_VST40
"vst41", // ARM_INS_VST41
"vst42", // ARM_INS_VST42
"vst43", // ARM_INS_VST43
"vstrb", // ARM_INS_VSTRB
"vstrd", // ARM_INS_VSTRD
"vstrh", // ARM_INS_VSTRH
"vstrw", // ARM_INS_VSTRW
"vsub", // ARM_INS_VSUB
"wlstp", // ARM_INS_WLSTP
"mvn", // ARM_INS_MVN
"orr", // ARM_INS_ORR
"pkhbt", // ARM_INS_PKHBT
"pkhtb", // ARM_INS_PKHTB
"pldw", // ARM_INS_PLDW
"pld", // ARM_INS_PLD
"pli", // ARM_INS_PLI
"qadd", // ARM_INS_QADD
"qadd16", // ARM_INS_QADD16
"qadd8", // ARM_INS_QADD8
"qasx", // ARM_INS_QASX
"qdadd", // ARM_INS_QDADD
"qdsub", // ARM_INS_QDSUB
"qsax", // ARM_INS_QSAX
"qsub", // ARM_INS_QSUB
"qsub16", // ARM_INS_QSUB16
"qsub8", // ARM_INS_QSUB8
"rbit", // ARM_INS_RBIT
"rev", // ARM_INS_REV
"rev16", // ARM_INS_REV16
"revsh", // ARM_INS_REVSH
"rfeda", // ARM_INS_RFEDA
"rfedb", // ARM_INS_RFEDB
"rfeia", // ARM_INS_RFEIA
"rfeib", // ARM_INS_RFEIB
"rsb", // ARM_INS_RSB
"rsc", // ARM_INS_RSC
"sadd16", // ARM_INS_SADD16
"sadd8", // ARM_INS_SADD8
"sasx", // ARM_INS_SASX
"sb", // ARM_INS_SB
"sbc", // ARM_INS_SBC
"sbfx", // ARM_INS_SBFX
"sdiv", // ARM_INS_SDIV
"sel", // ARM_INS_SEL
"setend", // ARM_INS_SETEND
"setpan", // ARM_INS_SETPAN
"sha1c", // ARM_INS_SHA1C
"sha1h", // ARM_INS_SHA1H
"sha1m", // ARM_INS_SHA1M
"sha1p", // ARM_INS_SHA1P
"sha1su0", // ARM_INS_SHA1SU0
"sha1su1", // ARM_INS_SHA1SU1
"sha256h", // ARM_INS_SHA256H
"sha256h2", // ARM_INS_SHA256H2
"sha256su0", // ARM_INS_SHA256SU0
"sha256su1", // ARM_INS_SHA256SU1
"shadd16", // ARM_INS_SHADD16
"shadd8", // ARM_INS_SHADD8
"shasx", // ARM_INS_SHASX
"shsax", // ARM_INS_SHSAX
"shsub16", // ARM_INS_SHSUB16
"shsub8", // ARM_INS_SHSUB8
"smc", // ARM_INS_SMC
"smlabb", // ARM_INS_SMLABB
"smlabt", // ARM_INS_SMLABT
"smlad", // ARM_INS_SMLAD
"smladx", // ARM_INS_SMLADX
"smlal", // ARM_INS_SMLAL
"smlalbb", // ARM_INS_SMLALBB
"smlalbt", // ARM_INS_SMLALBT
"smlald", // ARM_INS_SMLALD
"smlaldx", // ARM_INS_SMLALDX
"smlaltb", // ARM_INS_SMLALTB
"smlaltt", // ARM_INS_SMLALTT
"smlatb", // ARM_INS_SMLATB
"smlatt", // ARM_INS_SMLATT
"smlawb", // ARM_INS_SMLAWB
"smlawt", // ARM_INS_SMLAWT
"smlsd", // ARM_INS_SMLSD
"smlsdx", // ARM_INS_SMLSDX
"smlsld", // ARM_INS_SMLSLD
"smlsldx", // ARM_INS_SMLSLDX
"smmla", // ARM_INS_SMMLA
"smmlar", // ARM_INS_SMMLAR
"smmls", // ARM_INS_SMMLS
"smmlsr", // ARM_INS_SMMLSR
"smmul", // ARM_INS_SMMUL
"smmulr", // ARM_INS_SMMULR
"smuad", // ARM_INS_SMUAD
"smuadx", // ARM_INS_SMUADX
"smulbb", // ARM_INS_SMULBB
"smulbt", // ARM_INS_SMULBT
"smull", // ARM_INS_SMULL
"smultb", // ARM_INS_SMULTB
"smultt", // ARM_INS_SMULTT
"smulwb", // ARM_INS_SMULWB
"smulwt", // ARM_INS_SMULWT
"smusd", // ARM_INS_SMUSD
"smusdx", // ARM_INS_SMUSDX
"srsda", // ARM_INS_SRSDA
"srsdb", // ARM_INS_SRSDB
"srsia", // ARM_INS_SRSIA
"srsib", // ARM_INS_SRSIB
"ssat", // ARM_INS_SSAT
"ssat16", // ARM_INS_SSAT16
"ssax", // ARM_INS_SSAX
"ssub16", // ARM_INS_SSUB16
"ssub8", // ARM_INS_SSUB8
"stc2l", // ARM_INS_STC2L
"stc2", // ARM_INS_STC2
"stcl", // ARM_INS_STCL
"stc", // ARM_INS_STC
"stl", // ARM_INS_STL
"stlb", // ARM_INS_STLB
"stlex", // ARM_INS_STLEX
"stlexb", // ARM_INS_STLEXB
"stlexd", // ARM_INS_STLEXD
"stlexh", // ARM_INS_STLEXH
"stlh", // ARM_INS_STLH
"stmda", // ARM_INS_STMDA
"stmdb", // ARM_INS_STMDB
"stm", // ARM_INS_STM
"stmib", // ARM_INS_STMIB
"strd", // ARM_INS_STRD
"strex", // ARM_INS_STREX
"strexb", // ARM_INS_STREXB
"strexd", // ARM_INS_STREXD
"strexh", // ARM_INS_STREXH
"strht", // ARM_INS_STRHT
"sub", // ARM_INS_SUB
"svc", // ARM_INS_SVC
"swp", // ARM_INS_SWP
"swpb", // ARM_INS_SWPB
"sxtab", // ARM_INS_SXTAB
"sxtab16", // ARM_INS_SXTAB16
"sxtah", // ARM_INS_SXTAH
"sxtb", // ARM_INS_SXTB
"sxtb16", // ARM_INS_SXTB16
"sxth", // ARM_INS_SXTH
"teq", // ARM_INS_TEQ
"trap", // ARM_INS_TRAP
"tsb", // ARM_INS_TSB
"tst", // ARM_INS_TST
"uadd16", // ARM_INS_UADD16
"uadd8", // ARM_INS_UADD8
"uasx", // ARM_INS_UASX
"ubfx", // ARM_INS_UBFX
"udf", // ARM_INS_UDF
"udiv", // ARM_INS_UDIV
"uhadd16", // ARM_INS_UHADD16
"uhadd8", // ARM_INS_UHADD8
"uhasx", // ARM_INS_UHASX
"uhsax", // ARM_INS_UHSAX
"uhsub16", // ARM_INS_UHSUB16
"uhsub8", // ARM_INS_UHSUB8
"umaal", // ARM_INS_UMAAL
"umlal", // ARM_INS_UMLAL
"umull", // ARM_INS_UMULL
"uqadd16", // ARM_INS_UQADD16
"uqadd8", // ARM_INS_UQADD8
"uqasx", // ARM_INS_UQASX
"uqsax", // ARM_INS_UQSAX
"uqsub16", // ARM_INS_UQSUB16
"uqsub8", // ARM_INS_UQSUB8
"usad8", // ARM_INS_USAD8
"usada8", // ARM_INS_USADA8
"usat", // ARM_INS_USAT
"usat16", // ARM_INS_USAT16
"usax", // ARM_INS_USAX
"usub16", // ARM_INS_USUB16
"usub8", // ARM_INS_USUB8
"uxtab", // ARM_INS_UXTAB
"uxtab16", // ARM_INS_UXTAB16
"uxtah", // ARM_INS_UXTAH
"uxtb", // ARM_INS_UXTB
"uxtb16", // ARM_INS_UXTB16
"uxth", // ARM_INS_UXTH
"vabal", // ARM_INS_VABAL
"vaba", // ARM_INS_VABA
"vabdl", // ARM_INS_VABDL
"vacge", // ARM_INS_VACGE
"vacgt", // ARM_INS_VACGT
"vaddhn", // ARM_INS_VADDHN
"vaddl", // ARM_INS_VADDL
"vaddw", // ARM_INS_VADDW
"vfmab", // ARM_INS_VFMAB
"vfmat", // ARM_INS_VFMAT
"vbif", // ARM_INS_VBIF
"vbit", // ARM_INS_VBIT
"vbsl", // ARM_INS_VBSL
"vceq", // ARM_INS_VCEQ
"vcge", // ARM_INS_VCGE
"vcgt", // ARM_INS_VCGT
"vcle", // ARM_INS_VCLE
"vclt", // ARM_INS_VCLT
"vcmpe", // ARM_INS_VCMPE
"vcnt", // ARM_INS_VCNT
"vdiv", // ARM_INS_VDIV
"vext", // ARM_INS_VEXT
"vfmal", // ARM_INS_VFMAL
"vfmsl", // ARM_INS_VFMSL
"vfnma", // ARM_INS_VFNMA
"vfnms", // ARM_INS_VFNMS
"vins", // ARM_INS_VINS
"vjcvt", // ARM_INS_VJCVT
"vldmdb", // ARM_INS_VLDMDB
"vldmia", // ARM_INS_VLDMIA
"vldr", // ARM_INS_VLDR
"vlldm", // ARM_INS_VLLDM
"vlstm", // ARM_INS_VLSTM
"vmlal", // ARM_INS_VMLAL
"vmls", // ARM_INS_VMLS
"vmlsl", // ARM_INS_VMLSL
"vmmla", // ARM_INS_VMMLA
"vmovx", // ARM_INS_VMOVX
"vmovl", // ARM_INS_VMOVL
"vmovn", // ARM_INS_VMOVN
"vmsr", // ARM_INS_VMSR
"vmull", // ARM_INS_VMULL
"vnmla", // ARM_INS_VNMLA
"vnmls", // ARM_INS_VNMLS
"vnmul", // ARM_INS_VNMUL
"vpadal", // ARM_INS_VPADAL
"vpaddl", // ARM_INS_VPADDL
"vpadd", // ARM_INS_VPADD
"vpmax", // ARM_INS_VPMAX
"vpmin", // ARM_INS_VPMIN
"vqdmlal", // ARM_INS_VQDMLAL
"vqdmlsl", // ARM_INS_VQDMLSL
"vqdmull", // ARM_INS_VQDMULL
"vqmovun", // ARM_INS_VQMOVUN
"vqmovn", // ARM_INS_VQMOVN
"vqrdmlsh", // ARM_INS_VQRDMLSH
"vqrshrn", // ARM_INS_VQRSHRN
"vqrshrun", // ARM_INS_VQRSHRUN
"vqshrn", // ARM_INS_VQSHRN
"vqshrun", // ARM_INS_VQSHRUN
"vraddhn", // ARM_INS_VRADDHN
"vrecpe", // ARM_INS_VRECPE
"vrecps", // ARM_INS_VRECPS
"vrintr", // ARM_INS_VRINTR
"vrshrn", // ARM_INS_VRSHRN
"vrsqrte", // ARM_INS_VRSQRTE
"vrsqrts", // ARM_INS_VRSQRTS
"vrsra", // ARM_INS_VRSRA
"vrsubhn", // ARM_INS_VRSUBHN
"vscclrm", // ARM_INS_VSCCLRM
"vsdot", // ARM_INS_VSDOT
"vseleq", // ARM_INS_VSELEQ
"vselge", // ARM_INS_VSELGE
"vselgt", // ARM_INS_VSELGT
"vselvs", // ARM_INS_VSELVS
"vshll", // ARM_INS_VSHLL
"vshrn", // ARM_INS_VSHRN
"vsmmla", // ARM_INS_VSMMLA
"vsqrt", // ARM_INS_VSQRT
"vsra", // ARM_INS_VSRA
"vstmdb", // ARM_INS_VSTMDB
"vstmia", // ARM_INS_VSTMIA
"vstr", // ARM_INS_VSTR
"vsubhn", // ARM_INS_VSUBHN
"vsubl", // ARM_INS_VSUBL
"vsubw", // ARM_INS_VSUBW
"vsudot", // ARM_INS_VSUDOT
"vswp", // ARM_INS_VSWP
"vtbl", // ARM_INS_VTBL
"vtbx", // ARM_INS_VTBX
"vcvtr", // ARM_INS_VCVTR
"vtrn", // ARM_INS_VTRN
"vtst", // ARM_INS_VTST
"vudot", // ARM_INS_VUDOT
"vummla", // ARM_INS_VUMMLA
"vusdot", // ARM_INS_VUSDOT
"vusmmla", // ARM_INS_VUSMMLA
"vuzp", // ARM_INS_VUZP
"vzip", // ARM_INS_VZIP
"addw", // ARM_INS_ADDW
"aut", // ARM_INS_AUT
"autg", // ARM_INS_AUTG
"bfl", // ARM_INS_BFL
"bflx", // ARM_INS_BFLX
"bf", // ARM_INS_BF
"bfcsel", // ARM_INS_BFCSEL
"bfx", // ARM_INS_BFX
"bti", // ARM_INS_BTI
"bxaut", // ARM_INS_BXAUT
"clrm", // ARM_INS_CLRM
"csel", // ARM_INS_CSEL
"csinc", // ARM_INS_CSINC
"csinv", // ARM_INS_CSINV
"csneg", // ARM_INS_CSNEG
"dcps1", // ARM_INS_DCPS1
"dcps2", // ARM_INS_DCPS2
"dcps3", // ARM_INS_DCPS3
"dls", // ARM_INS_DLS
"le", // ARM_INS_LE
"orn", // ARM_INS_ORN
"pac", // ARM_INS_PAC
"pacbti", // ARM_INS_PACBTI
"pacg", // ARM_INS_PACG
"sg", // ARM_INS_SG
"subs", // ARM_INS_SUBS
"subw", // ARM_INS_SUBW
"tbb", // ARM_INS_TBB
"tbh", // ARM_INS_TBH
"tt", // ARM_INS_TT
"tta", // ARM_INS_TTA
"ttat", // ARM_INS_TTAT
"ttt", // ARM_INS_TTT
"wls", // ARM_INS_WLS
"blxns", // ARM_INS_BLXNS
"bxns", // ARM_INS_BXNS
"cbnz", // ARM_INS_CBNZ
"cbz", // ARM_INS_CBZ
"pop", // ARM_INS_POP
"push", // ARM_INS_PUSH
"__brkdiv0", // ARM_INS___BRKDIV0
arch/ARM/ARMGenCSMappingInsnOp.inc
+37122
View File
File diff suppressed because it is too large Load Diff
arch/ARM/ARMGenCSOpGroup.inc
+115
View File
@@ -0,0 +1,115 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARM_OP_GROUP_LdStmModeOperand = 0,
ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 1,
ARM_OP_GROUP_RegImmShift = 2,
ARM_OP_GROUP_Operand = 3,
ARM_OP_GROUP_ModImmOperand = 4,
ARM_OP_GROUP_PredicateOperand = 5,
ARM_OP_GROUP_SORegImmOperand = 6,
ARM_OP_GROUP_SORegRegOperand = 7,
ARM_OP_GROUP_SBitModifierOperand = 8,
ARM_OP_GROUP_AddrModeImm12Operand_0 = 9,
ARM_OP_GROUP_AddrMode2Operand = 10,
ARM_OP_GROUP_CPInstOperand = 11,
ARM_OP_GROUP_MandatoryPredicateOperand = 12,
ARM_OP_GROUP_ThumbITMask = 13,
ARM_OP_GROUP_RegisterList = 14,
ARM_OP_GROUP_AddrMode7Operand = 15,
ARM_OP_GROUP_GPRPairOperand = 16,
ARM_OP_GROUP_AddrMode3Operand_0 = 17,
ARM_OP_GROUP_PCLabel = 18,
ARM_OP_GROUP_AddrModePCOperand = 19,
ARM_OP_GROUP_AddrMode2OffsetOperand = 20,
ARM_OP_GROUP_AddrMode3OffsetOperand = 21,
ARM_OP_GROUP_AddrMode6Operand = 22,
ARM_OP_GROUP_VectorListThreeAllLanes = 23,
ARM_OP_GROUP_VectorListThreeSpacedAllLanes = 24,
ARM_OP_GROUP_VectorListThree = 25,
ARM_OP_GROUP_VectorListThreeSpaced = 26,
ARM_OP_GROUP_VectorListFourAllLanes = 27,
ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28,
ARM_OP_GROUP_VectorListFour = 29,
ARM_OP_GROUP_VectorListFourSpaced = 30,
ARM_OP_GROUP_T2SOOperand = 31,
ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 32,
ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 33,
ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 34,
ARM_OP_GROUP_AdrLabelOperand_0 = 35,
ARM_OP_GROUP_VectorIndex = 36,
ARM_OP_GROUP_BitfieldInvMaskImmOperand = 37,
ARM_OP_GROUP_PImmediate = 38,
ARM_OP_GROUP_VPTPredicateOperand = 39,
ARM_OP_GROUP_CImmediate = 40,
ARM_OP_GROUP_CPSIMod = 41,
ARM_OP_GROUP_CPSIFlag = 42,
ARM_OP_GROUP_MemBOption = 43,
ARM_OP_GROUP_FPImmOperand = 44,
ARM_OP_GROUP_InstSyncBOption = 45,
ARM_OP_GROUP_AddrMode5Operand_0 = 46,
ARM_OP_GROUP_CoprocOptionImm = 47,
ARM_OP_GROUP_PostIdxImm8s4Operand = 48,
ARM_OP_GROUP_AddrMode5Operand_1 = 49,
ARM_OP_GROUP_AddrModeImm12Operand_1 = 50,
ARM_OP_GROUP_AddrMode3Operand_1 = 51,
ARM_OP_GROUP_PostIdxImm8Operand = 52,
ARM_OP_GROUP_PostIdxRegOperand = 53,
ARM_OP_GROUP_BankedRegOperand = 54,
ARM_OP_GROUP_MSRMaskOperand = 55,
ARM_OP_GROUP_MveSaturateOp = 56,
ARM_OP_GROUP_VMOVModImmOperand = 57,
ARM_OP_GROUP_ComplexRotationOp_180_90 = 58,
ARM_OP_GROUP_ComplexRotationOp_90_0 = 59,
ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 60,
ARM_OP_GROUP_MVEVectorList_2 = 61,
ARM_OP_GROUP_MVEVectorList_4 = 62,
ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63,
ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64,
ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65,
ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66,
ARM_OP_GROUP_VPTMask = 67,
ARM_OP_GROUP_PKHLSLShiftImm = 68,
ARM_OP_GROUP_PKHASRShiftImm = 69,
ARM_OP_GROUP_ImmPlusOneOperand = 70,
ARM_OP_GROUP_SetendOperand = 71,
ARM_OP_GROUP_ShiftImmOperand = 72,
ARM_OP_GROUP_RotImmOperand = 73,
ARM_OP_GROUP_TraceSyncBOption = 74,
ARM_OP_GROUP_VectorListOneAllLanes = 75,
ARM_OP_GROUP_VectorListTwoAllLanes = 76,
ARM_OP_GROUP_NoHashImmediate = 77,
ARM_OP_GROUP_AddrMode6OffsetOperand = 78,
ARM_OP_GROUP_VectorListOne = 79,
ARM_OP_GROUP_VectorListTwo = 80,
ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81,
ARM_OP_GROUP_VectorListTwoSpaced = 82,
ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83,
ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84,
ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85,
ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86,
ARM_OP_GROUP_FBits16 = 87,
ARM_OP_GROUP_FBits32 = 88,
ARM_OP_GROUP_ThumbSRImm = 89,
ARM_OP_GROUP_ThumbLdrLabelOperand = 90,
ARM_OP_GROUP_T2AddrModeSoRegOperand = 91,
ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92,
ARM_OP_GROUP_AddrModeTBB = 93,
ARM_OP_GROUP_AddrModeTBH = 94,
ARM_OP_GROUP_ThumbS4ImmOperand = 95,
ARM_OP_GROUP_AdrLabelOperand_2 = 96,
ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97,
ARM_OP_GROUP_ThumbAddrModeRROperand = 98,
ARM_OP_GROUP_ThumbAddrModeImm5S2Operand = 99,
ARM_OP_GROUP_ThumbAddrModeImm5S4Operand = 100,
ARM_OP_GROUP_ThumbAddrModeSPOperand = 101,
arch/ARM/ARMGenDisassemblerTables.inc
+22694
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arch/ARM/ARMGenInstrInfo.inc
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arch/ARM/ARMGenRegisterInfo.inc
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arch/ARM/ARMGenSubtargetInfo.inc
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
ARM_ARMv4 = 0,
ARM_ARMv4t = 1,
ARM_ARMv5t = 2,
ARM_ARMv5te = 3,
ARM_ARMv5tej = 4,
ARM_ARMv6 = 5,
ARM_ARMv6j = 6,
ARM_ARMv6k = 7,
ARM_ARMv6kz = 8,
ARM_ARMv6m = 9,
ARM_ARMv6sm = 10,
ARM_ARMv6t2 = 11,
ARM_ARMv7a = 12,
ARM_ARMv7em = 13,
ARM_ARMv7k = 14,
ARM_ARMv7m = 15,
ARM_ARMv7r = 16,
ARM_ARMv7s = 17,
ARM_ARMv7ve = 18,
ARM_ARMv8a = 19,
ARM_ARMv8mBaseline = 20,
ARM_ARMv8mMainline = 21,
ARM_ARMv8r = 22,
ARM_ARMv9a = 23,
ARM_ARMv81a = 24,
ARM_ARMv81mMainline = 25,
ARM_ARMv82a = 26,
ARM_ARMv83a = 27,
ARM_ARMv84a = 28,
ARM_ARMv85a = 29,
ARM_ARMv86a = 30,
ARM_ARMv87a = 31,
ARM_ARMv88a = 32,
ARM_ARMv89a = 33,
ARM_ARMv91a = 34,
ARM_ARMv92a = 35,
ARM_ARMv93a = 36,
ARM_ARMv94a = 37,
ARM_ARMv95a = 38,
ARM_Feature8MSecExt = 39,
ARM_FeatureAAPCSFrameChain = 40,
ARM_FeatureAAPCSFrameChainLeaf = 41,
ARM_FeatureAClass = 42,
ARM_FeatureAES = 43,
ARM_FeatureAcquireRelease = 44,
ARM_FeatureAtomics32 = 45,
ARM_FeatureAvoidMOVsShOp = 46,
ARM_FeatureAvoidPartialCPSR = 47,
ARM_FeatureBF16 = 48,
ARM_FeatureCLRBHB = 49,
ARM_FeatureCRC = 50,
ARM_FeatureCheapPredicableCPSR = 51,
ARM_FeatureCheckVLDnAlign = 52,
ARM_FeatureCoprocCDE0 = 53,
ARM_FeatureCoprocCDE1 = 54,
ARM_FeatureCoprocCDE2 = 55,
ARM_FeatureCoprocCDE3 = 56,
ARM_FeatureCoprocCDE4 = 57,
ARM_FeatureCoprocCDE5 = 58,
ARM_FeatureCoprocCDE6 = 59,
ARM_FeatureCoprocCDE7 = 60,
ARM_FeatureCrypto = 61,
ARM_FeatureD32 = 62,
ARM_FeatureDB = 63,
ARM_FeatureDFB = 64,
ARM_FeatureDSP = 65,
ARM_FeatureDontWidenVMOVS = 66,
ARM_FeatureDotProd = 67,
ARM_FeatureExecuteOnly = 68,
ARM_FeatureExpandMLx = 69,
ARM_FeatureFP16 = 70,
ARM_FeatureFP16FML = 71,
ARM_FeatureFP64 = 72,
ARM_FeatureFPAO = 73,
ARM_FeatureFPARMv8 = 74,
ARM_FeatureFPARMv8_D16 = 75,
ARM_FeatureFPARMv8_D16_SP = 76,
ARM_FeatureFPARMv8_SP = 77,
ARM_FeatureFPRegs = 78,
ARM_FeatureFPRegs16 = 79,
ARM_FeatureFPRegs64 = 80,
ARM_FeatureFixCMSE_CVE_2021_35465 = 81,
ARM_FeatureFixCortexA57AES1742098 = 82,
ARM_FeatureFullFP16 = 83,
ARM_FeatureFuseAES = 84,
ARM_FeatureFuseLiterals = 85,
ARM_FeatureHWDivARM = 86,
ARM_FeatureHWDivThumb = 87,
ARM_FeatureHardenSlsBlr = 88,
ARM_FeatureHardenSlsNoComdat = 89,
ARM_FeatureHardenSlsRetBr = 90,
ARM_FeatureHasNoBranchPredictor = 91,
ARM_FeatureHasRetAddrStack = 92,
ARM_FeatureHasSlowFPVFMx = 93,
ARM_FeatureHasSlowFPVMLx = 94,
ARM_FeatureHasVMLxHazards = 95,
ARM_FeatureLOB = 96,
ARM_FeatureLongCalls = 97,
ARM_FeatureMClass = 98,
ARM_FeatureMP = 99,
ARM_FeatureMVEVectorCostFactor1 = 100,
ARM_FeatureMVEVectorCostFactor2 = 101,
ARM_FeatureMVEVectorCostFactor4 = 102,
ARM_FeatureMatMulInt8 = 103,
ARM_FeatureMuxedUnits = 104,
ARM_FeatureNEON = 105,
ARM_FeatureNEONForFP = 106,
ARM_FeatureNEONForFPMovs = 107,
ARM_FeatureNaClTrap = 108,
ARM_FeatureNoARM = 109,
ARM_FeatureNoBTIAtReturnTwice = 110,
ARM_FeatureNoMovt = 111,
ARM_FeatureNoNegativeImmediates = 112,
ARM_FeatureNoPostRASched = 113,
ARM_FeatureNonpipelinedVFP = 114,
ARM_FeaturePACBTI = 115,
ARM_FeaturePerfMon = 116,
ARM_FeaturePref32BitThumb = 117,
ARM_FeaturePrefISHSTBarrier = 118,
ARM_FeaturePrefLoopAlign32 = 119,
ARM_FeaturePreferVMOVSR = 120,
ARM_FeatureProfUnpredicate = 121,
ARM_FeatureRAS = 122,
ARM_FeatureRClass = 123,
ARM_FeatureReadTpTPIDRPRW = 124,
ARM_FeatureReadTpTPIDRURO = 125,
ARM_FeatureReadTpTPIDRURW = 126,
ARM_FeatureReserveR9 = 127,
ARM_FeatureSB = 128,
ARM_FeatureSHA2 = 129,
ARM_FeatureSlowFPBrcc = 130,
ARM_FeatureSlowLoadDSubreg = 131,
ARM_FeatureSlowOddRegister = 132,
ARM_FeatureSlowVDUP32 = 133,
ARM_FeatureSlowVGETLNi32 = 134,
ARM_FeatureSplatVFPToNeon = 135,
ARM_FeatureStrictAlign = 136,
ARM_FeatureThumb2 = 137,
ARM_FeatureTrustZone = 138,
ARM_FeatureUseMIPipeliner = 139,
ARM_FeatureUseMISched = 140,
ARM_FeatureUseWideStrideVFP = 141,
ARM_FeatureV7Clrex = 142,
ARM_FeatureVFP2 = 143,
ARM_FeatureVFP2_SP = 144,
ARM_FeatureVFP3 = 145,
ARM_FeatureVFP3_D16 = 146,
ARM_FeatureVFP3_D16_SP = 147,
ARM_FeatureVFP3_SP = 148,
ARM_FeatureVFP4 = 149,
ARM_FeatureVFP4_D16 = 150,
ARM_FeatureVFP4_D16_SP = 151,
ARM_FeatureVFP4_SP = 152,
ARM_FeatureVMLxForwarding = 153,
ARM_FeatureVirtualization = 154,
ARM_FeatureZCZeroing = 155,
ARM_HasCDEOps = 156,
ARM_HasMVEFloatOps = 157,
ARM_HasMVEIntegerOps = 158,
ARM_HasV4TOps = 159,
ARM_HasV5TEOps = 160,
ARM_HasV5TOps = 161,
ARM_HasV6KOps = 162,
ARM_HasV6MOps = 163,
ARM_HasV6Ops = 164,
ARM_HasV6T2Ops = 165,
ARM_HasV7Ops = 166,
ARM_HasV8MBaselineOps = 167,
ARM_HasV8MMainlineOps = 168,
ARM_HasV8Ops = 169,
ARM_HasV8_1MMainlineOps = 170,
ARM_HasV8_1aOps = 171,
ARM_HasV8_2aOps = 172,
ARM_HasV8_3aOps = 173,
ARM_HasV8_4aOps = 174,
ARM_HasV8_5aOps = 175,
ARM_HasV8_6aOps = 176,
ARM_HasV8_7aOps = 177,
ARM_HasV8_8aOps = 178,
ARM_HasV8_9aOps = 179,
ARM_HasV9_0aOps = 180,
ARM_HasV9_1aOps = 181,
ARM_HasV9_2aOps = 182,
ARM_HasV9_3aOps = 183,
ARM_HasV9_4aOps = 184,
ARM_HasV9_5aOps = 185,
ARM_IWMMXT = 186,
ARM_IWMMXT2 = 187,
ARM_ModeBigEndianInstructions = 188,
ARM_ModeSoftFloat = 189,
ARM_ModeThumb = 190,
ARM_ProcA5 = 191,
ARM_ProcA7 = 192,
ARM_ProcA8 = 193,
ARM_ProcA9 = 194,
ARM_ProcA12 = 195,
ARM_ProcA15 = 196,
ARM_ProcA17 = 197,
ARM_ProcA32 = 198,
ARM_ProcA35 = 199,
ARM_ProcA53 = 200,
ARM_ProcA55 = 201,
ARM_ProcA57 = 202,
ARM_ProcA72 = 203,
ARM_ProcA73 = 204,
ARM_ProcA75 = 205,
ARM_ProcA76 = 206,
ARM_ProcA77 = 207,
ARM_ProcA78 = 208,
ARM_ProcA78C = 209,
ARM_ProcA710 = 210,
ARM_ProcExynos = 211,
ARM_ProcKrait = 212,
ARM_ProcKryo = 213,
ARM_ProcM3 = 214,
ARM_ProcM7 = 215,
ARM_ProcR4 = 216,
ARM_ProcR5 = 217,
ARM_ProcR7 = 218,
ARM_ProcR52 = 219,
ARM_ProcSwift = 220,
ARM_ProcV1 = 221,
ARM_ProcX1 = 222,
ARM_ProcX1C = 223,
ARM_XScale = 224,
ARM_NumSubtargetFeatures = 225
};
#endif // GET_SUBTARGETINFO_ENUM
arch/ARM/ARMGenSystemRegister.inc
+477
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_BANKEDREG_DECL
#endif
#ifdef GET_MCLASSSYSREG_DECL
#endif
#ifdef GET_BANKEDREG_DECL
const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name);
const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
#endif
#ifdef GET_MCLASSSYSREG_DECL
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name);
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8);
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
#endif
#ifdef GET_BANKEDREG_IMPL
static const ARMBankedReg_BankedReg BankedRegsList[] = {
{ "elr_hyp", { .raw_val = ARM_BANKEDREG_ELR_HYP }, 0x1E }, // 0
{ "lr_abt", { .raw_val = ARM_BANKEDREG_LR_ABT }, 0x14 }, // 1
{ "lr_fiq", { .raw_val = ARM_BANKEDREG_LR_FIQ }, 0xE }, // 2
{ "lr_irq", { .raw_val = ARM_BANKEDREG_LR_IRQ }, 0x10 }, // 3
{ "lr_mon", { .raw_val = ARM_BANKEDREG_LR_MON }, 0x1C }, // 4
{ "lr_svc", { .raw_val = ARM_BANKEDREG_LR_SVC }, 0x12 }, // 5
{ "lr_und", { .raw_val = ARM_BANKEDREG_LR_UND }, 0x16 }, // 6
{ "lr_usr", { .raw_val = ARM_BANKEDREG_LR_USR }, 0x6 }, // 7
{ "r10_fiq", { .raw_val = ARM_BANKEDREG_R10_FIQ }, 0xA }, // 8
{ "r10_usr", { .raw_val = ARM_BANKEDREG_R10_USR }, 0x2 }, // 9
{ "r11_fiq", { .raw_val = ARM_BANKEDREG_R11_FIQ }, 0xB }, // 10
{ "r11_usr", { .raw_val = ARM_BANKEDREG_R11_USR }, 0x3 }, // 11
{ "r12_fiq", { .raw_val = ARM_BANKEDREG_R12_FIQ }, 0xC }, // 12
{ "r12_usr", { .raw_val = ARM_BANKEDREG_R12_USR }, 0x4 }, // 13
{ "r8_fiq", { .raw_val = ARM_BANKEDREG_R8_FIQ }, 0x8 }, // 14
{ "r8_usr", { .raw_val = ARM_BANKEDREG_R8_USR }, 0x0 }, // 15
{ "r9_fiq", { .raw_val = ARM_BANKEDREG_R9_FIQ }, 0x9 }, // 16
{ "r9_usr", { .raw_val = ARM_BANKEDREG_R9_USR }, 0x1 }, // 17
{ "spsr_abt", { .raw_val = ARM_BANKEDREG_SPSR_ABT }, 0x34 }, // 18
{ "spsr_fiq", { .raw_val = ARM_BANKEDREG_SPSR_FIQ }, 0x2E }, // 19
{ "spsr_hyp", { .raw_val = ARM_BANKEDREG_SPSR_HYP }, 0x3E }, // 20
{ "spsr_irq", { .raw_val = ARM_BANKEDREG_SPSR_IRQ }, 0x30 }, // 21
{ "spsr_mon", { .raw_val = ARM_BANKEDREG_SPSR_MON }, 0x3C }, // 22
{ "spsr_svc", { .raw_val = ARM_BANKEDREG_SPSR_SVC }, 0x32 }, // 23
{ "spsr_und", { .raw_val = ARM_BANKEDREG_SPSR_UND }, 0x36 }, // 24
{ "sp_abt", { .raw_val = ARM_BANKEDREG_SP_ABT }, 0x15 }, // 25
{ "sp_fiq", { .raw_val = ARM_BANKEDREG_SP_FIQ }, 0xD }, // 26
{ "sp_hyp", { .raw_val = ARM_BANKEDREG_SP_HYP }, 0x1F }, // 27
{ "sp_irq", { .raw_val = ARM_BANKEDREG_SP_IRQ }, 0x11 }, // 28
{ "sp_mon", { .raw_val = ARM_BANKEDREG_SP_MON }, 0x1D }, // 29
{ "sp_svc", { .raw_val = ARM_BANKEDREG_SP_SVC }, 0x13 }, // 30
{ "sp_und", { .raw_val = ARM_BANKEDREG_SP_UND }, 0x17 }, // 31
{ "sp_usr", { .raw_val = ARM_BANKEDREG_SP_USR }, 0x5 }, // 32
};
const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name) {
static const struct IndexTypeStr Index[] = {
{ "ELR_HYP", 0 },
{ "LR_ABT", 1 },
{ "LR_FIQ", 2 },
{ "LR_IRQ", 3 },
{ "LR_MON", 4 },
{ "LR_SVC", 5 },
{ "LR_UND", 6 },
{ "LR_USR", 7 },
{ "R10_FIQ", 8 },
{ "R10_USR", 9 },
{ "R11_FIQ", 10 },
{ "R11_USR", 11 },
{ "R12_FIQ", 12 },
{ "R12_USR", 13 },
{ "R8_FIQ", 14 },
{ "R8_USR", 15 },
{ "R9_FIQ", 16 },
{ "R9_USR", 17 },
{ "SPSR_ABT", 18 },
{ "SPSR_FIQ", 19 },
{ "SPSR_HYP", 20 },
{ "SPSR_IRQ", 21 },
{ "SPSR_MON", 22 },
{ "SPSR_SVC", 23 },
{ "SPSR_UND", 24 },
{ "SP_ABT", 25 },
{ "SP_FIQ", 26 },
{ "SP_HYP", 27 },
{ "SP_IRQ", 28 },
{ "SP_MON", 29 },
{ "SP_SVC", 30 },
{ "SP_UND", 31 },
{ "SP_USR", 32 },
};
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
if (i == -1)
return NULL;
else
return &BankedRegsList[Index[i].index];
}
const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding) {
static const struct IndexType Index[] = {
{ 0x0, 15 },
{ 0x1, 17 },
{ 0x2, 9 },
{ 0x3, 11 },
{ 0x4, 13 },
{ 0x5, 32 },
{ 0x6, 7 },
{ 0x8, 14 },
{ 0x9, 16 },
{ 0xA, 8 },
{ 0xB, 10 },
{ 0xC, 12 },
{ 0xD, 26 },
{ 0xE, 2 },
{ 0x10, 3 },
{ 0x11, 28 },
{ 0x12, 5 },
{ 0x13, 30 },
{ 0x14, 1 },
{ 0x15, 25 },
{ 0x16, 6 },
{ 0x17, 31 },
{ 0x1C, 4 },
{ 0x1D, 29 },
{ 0x1E, 0 },
{ 0x1F, 27 },
{ 0x2E, 19 },
{ 0x30, 21 },
{ 0x32, 23 },
{ 0x34, 18 },
{ 0x36, 24 },
{ 0x3C, 22 },
{ 0x3E, 20 },
};
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
if (i == -1)
return NULL;
else
return &BankedRegsList[Index[i].index];
}
#endif
#ifdef GET_MCLASSSYSREG_IMPL
static const ARMSysReg_MClassSysReg MClassSysRegsList[] = {
{ "apsr", { .raw_val = ARM_MCLASSSYSREG_APSR }, 0x800, 0x100, 0x800, {0} }, // 0
{ "apsr_g", { .raw_val = ARM_MCLASSSYSREG_APSR_G }, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 1
{ "apsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_APSR_NZCVQ }, 0x1800, 0x200, 0x800, {0} }, // 2
{ "apsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_APSR_NZCVQG }, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 3
{ "basepri", { .raw_val = ARM_MCLASSSYSREG_BASEPRI }, 0x811, 0x111, 0x811, {ARM_HasV7Ops} }, // 4
{ "basepri_max", { .raw_val = ARM_MCLASSSYSREG_BASEPRI_MAX }, 0x812, 0x112, 0x812, {ARM_HasV7Ops} }, // 5
{ "basepri_ns", { .raw_val = ARM_MCLASSSYSREG_BASEPRI_NS }, 0x891, 0x191, 0x891, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 6
{ "control", { .raw_val = ARM_MCLASSSYSREG_CONTROL }, 0x814, 0x114, 0x814, {0} }, // 7
{ "control_ns", { .raw_val = ARM_MCLASSSYSREG_CONTROL_NS }, 0x894, 0x194, 0x894, {ARM_Feature8MSecExt} }, // 8
{ "eapsr", { .raw_val = ARM_MCLASSSYSREG_EAPSR }, 0x802, 0x102, 0x802, {0} }, // 9
{ "eapsr_g", { .raw_val = ARM_MCLASSSYSREG_EAPSR_G }, 0x402, 0x2, 0x402, {ARM_FeatureDSP} }, // 10
{ "eapsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_EAPSR_NZCVQ }, 0x1802, 0x202, 0x802, {0} }, // 11
{ "eapsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_EAPSR_NZCVQG }, 0xC02, 0x302, 0xC02, {ARM_FeatureDSP} }, // 12
{ "epsr", { .raw_val = ARM_MCLASSSYSREG_EPSR }, 0x806, 0x106, 0x806, {0} }, // 13
{ "faultmask", { .raw_val = ARM_MCLASSSYSREG_FAULTMASK }, 0x813, 0x113, 0x813, {ARM_HasV7Ops} }, // 14
{ "faultmask_ns", { .raw_val = ARM_MCLASSSYSREG_FAULTMASK_NS }, 0x893, 0x193, 0x893, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 15
{ "iapsr", { .raw_val = ARM_MCLASSSYSREG_IAPSR }, 0x801, 0x101, 0x801, {0} }, // 16
{ "iapsr_g", { .raw_val = ARM_MCLASSSYSREG_IAPSR_G }, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 17
{ "iapsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_IAPSR_NZCVQ }, 0x1801, 0x201, 0x801, {0} }, // 18
{ "iapsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_IAPSR_NZCVQG }, 0xC01, 0x301, 0xC01, {ARM_FeatureDSP} }, // 19
{ "iepsr", { .raw_val = ARM_MCLASSSYSREG_IEPSR }, 0x807, 0x107, 0x807, {0} }, // 20
{ "ipsr", { .raw_val = ARM_MCLASSSYSREG_IPSR }, 0x805, 0x105, 0x805, {0} }, // 21
{ "msp", { .raw_val = ARM_MCLASSSYSREG_MSP }, 0x808, 0x108, 0x808, {0} }, // 22
{ "msplim", { .raw_val = ARM_MCLASSSYSREG_MSPLIM }, 0x80A, 0x10A, 0x80A, {ARM_HasV8MBaselineOps} }, // 23
{ "msplim_ns", { .raw_val = ARM_MCLASSSYSREG_MSPLIM_NS }, 0x88A, 0x18A, 0x88A, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 24
{ "msp_ns", { .raw_val = ARM_MCLASSSYSREG_MSP_NS }, 0x888, 0x188, 0x888, {ARM_Feature8MSecExt} }, // 25
{ "pac_key_p_0", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_0 }, 0x820, 0x120, 0x820, {ARM_FeaturePACBTI} }, // 26
{ "pac_key_p_0_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_0_NS }, 0x8A0, 0x1A0, 0x8A0, {ARM_FeaturePACBTI} }, // 27
{ "pac_key_p_1", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_1 }, 0x821, 0x121, 0x821, {ARM_FeaturePACBTI} }, // 28
{ "pac_key_p_1_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_1_NS }, 0x8A1, 0x1A1, 0x8A1, {ARM_FeaturePACBTI} }, // 29
{ "pac_key_p_2", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_2 }, 0x822, 0x122, 0x822, {ARM_FeaturePACBTI} }, // 30
{ "pac_key_p_2_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_2_NS }, 0x8A2, 0x1A2, 0x8A2, {ARM_FeaturePACBTI} }, // 31
{ "pac_key_p_3", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_3 }, 0x823, 0x123, 0x823, {ARM_FeaturePACBTI} }, // 32
{ "pac_key_p_3_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_3_NS }, 0x8A3, 0x1A3, 0x8A3, {ARM_FeaturePACBTI} }, // 33
{ "pac_key_u_0", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_0 }, 0x824, 0x124, 0x824, {ARM_FeaturePACBTI} }, // 34
{ "pac_key_u_0_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_0_NS }, 0x8A4, 0x1A4, 0x8A4, {ARM_FeaturePACBTI} }, // 35
{ "pac_key_u_1", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_1 }, 0x825, 0x125, 0x825, {ARM_FeaturePACBTI} }, // 36
{ "pac_key_u_1_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_1_NS }, 0x8A5, 0x1A5, 0x8A5, {ARM_FeaturePACBTI} }, // 37
{ "pac_key_u_2", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_2 }, 0x826, 0x126, 0x826, {ARM_FeaturePACBTI} }, // 38
{ "pac_key_u_2_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_2_NS }, 0x8A6, 0x1A6, 0x8A6, {ARM_FeaturePACBTI} }, // 39
{ "pac_key_u_3", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_3 }, 0x827, 0x127, 0x827, {ARM_FeaturePACBTI} }, // 40
{ "pac_key_u_3_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_3_NS }, 0x8A7, 0x1A7, 0x8A7, {ARM_FeaturePACBTI} }, // 41
{ "primask", { .raw_val = ARM_MCLASSSYSREG_PRIMASK }, 0x810, 0x110, 0x810, {0} }, // 42
{ "primask_ns", { .raw_val = ARM_MCLASSSYSREG_PRIMASK_NS }, 0x890, 0x190, 0x890, {0} }, // 43
{ "psp", { .raw_val = ARM_MCLASSSYSREG_PSP }, 0x809, 0x109, 0x809, {0} }, // 44
{ "psplim", { .raw_val = ARM_MCLASSSYSREG_PSPLIM }, 0x80B, 0x10B, 0x80B, {ARM_HasV8MBaselineOps} }, // 45
{ "psplim_ns", { .raw_val = ARM_MCLASSSYSREG_PSPLIM_NS }, 0x88B, 0x18B, 0x88B, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 46
{ "psp_ns", { .raw_val = ARM_MCLASSSYSREG_PSP_NS }, 0x889, 0x189, 0x889, {ARM_Feature8MSecExt} }, // 47
{ "sp_ns", { .raw_val = ARM_MCLASSSYSREG_SP_NS }, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 48
{ "xpsr", { .raw_val = ARM_MCLASSSYSREG_XPSR }, 0x803, 0x103, 0x803, {0} }, // 49
{ "xpsr_g", { .raw_val = ARM_MCLASSSYSREG_XPSR_G }, 0x403, 0x3, 0x403, {ARM_FeatureDSP} }, // 50
{ "xpsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_XPSR_NZCVQ }, 0x1803, 0x203, 0x803, {0} }, // 51
{ "xpsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_XPSR_NZCVQG }, 0xC03, 0x303, 0xC03, {ARM_FeatureDSP} }, // 52
};
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name) {
static const struct IndexTypeStr Index[] = {
{ "APSR", 0 },
{ "APSR_G", 1 },
{ "APSR_NZCVQ", 2 },
{ "APSR_NZCVQG", 3 },
{ "BASEPRI", 4 },
{ "BASEPRI_MAX", 5 },
{ "BASEPRI_NS", 6 },
{ "CONTROL", 7 },
{ "CONTROL_NS", 8 },
{ "EAPSR", 9 },
{ "EAPSR_G", 10 },
{ "EAPSR_NZCVQ", 11 },
{ "EAPSR_NZCVQG", 12 },
{ "EPSR", 13 },
{ "FAULTMASK", 14 },
{ "FAULTMASK_NS", 15 },
{ "IAPSR", 16 },
{ "IAPSR_G", 17 },
{ "IAPSR_NZCVQ", 18 },
{ "IAPSR_NZCVQG", 19 },
{ "IEPSR", 20 },
{ "IPSR", 21 },
{ "MSP", 22 },
{ "MSPLIM", 23 },
{ "MSPLIM_NS", 24 },
{ "MSP_NS", 25 },
{ "PAC_KEY_P_0", 26 },
{ "PAC_KEY_P_0_NS", 27 },
{ "PAC_KEY_P_1", 28 },
{ "PAC_KEY_P_1_NS", 29 },
{ "PAC_KEY_P_2", 30 },
{ "PAC_KEY_P_2_NS", 31 },
{ "PAC_KEY_P_3", 32 },
{ "PAC_KEY_P_3_NS", 33 },
{ "PAC_KEY_U_0", 34 },
{ "PAC_KEY_U_0_NS", 35 },
{ "PAC_KEY_U_1", 36 },
{ "PAC_KEY_U_1_NS", 37 },
{ "PAC_KEY_U_2", 38 },
{ "PAC_KEY_U_2_NS", 39 },
{ "PAC_KEY_U_3", 40 },
{ "PAC_KEY_U_3_NS", 41 },
{ "PRIMASK", 42 },
{ "PRIMASK_NS", 43 },
{ "PSP", 44 },
{ "PSPLIM", 45 },
{ "PSPLIM_NS", 46 },
{ "PSP_NS", 47 },
{ "SP_NS", 48 },
{ "XPSR", 49 },
{ "XPSR_G", 50 },
{ "XPSR_NZCVQ", 51 },
{ "XPSR_NZCVQG", 52 },
};
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
if (i == -1)
return NULL;
else
return &MClassSysRegsList[Index[i].index];
}
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12) {
static const struct IndexType Index[] = {
{ 0x400, 1 },
{ 0x401, 17 },
{ 0x402, 10 },
{ 0x403, 50 },
{ 0x800, 0 },
{ 0x801, 16 },
{ 0x802, 9 },
{ 0x803, 49 },
{ 0x805, 21 },
{ 0x806, 13 },
{ 0x807, 20 },
{ 0x808, 22 },
{ 0x809, 44 },
{ 0x80A, 23 },
{ 0x80B, 45 },
{ 0x810, 42 },
{ 0x811, 4 },
{ 0x812, 5 },
{ 0x813, 14 },
{ 0x814, 7 },
{ 0x820, 26 },
{ 0x821, 28 },
{ 0x822, 30 },
{ 0x823, 32 },
{ 0x824, 34 },
{ 0x825, 36 },
{ 0x826, 38 },
{ 0x827, 40 },
{ 0x888, 25 },
{ 0x889, 47 },
{ 0x88A, 24 },
{ 0x88B, 46 },
{ 0x890, 43 },
{ 0x891, 6 },
{ 0x893, 15 },
{ 0x894, 8 },
{ 0x898, 48 },
{ 0x8A0, 27 },
{ 0x8A1, 29 },
{ 0x8A2, 31 },
{ 0x8A3, 33 },
{ 0x8A4, 35 },
{ 0x8A5, 37 },
{ 0x8A6, 39 },
{ 0x8A7, 41 },
{ 0xC00, 3 },
{ 0xC01, 19 },
{ 0xC02, 12 },
{ 0xC03, 52 },
{ 0x1800, 2 },
{ 0x1801, 18 },
{ 0x1802, 11 },
{ 0x1803, 51 },
};
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M1Encoding12);
if (i == -1)
return NULL;
else
return &MClassSysRegsList[Index[i].index];
}
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8) {
static const struct IndexType Index[] = {
{ 0x0, 1 },
{ 0x1, 17 },
{ 0x2, 10 },
{ 0x3, 50 },
{ 0x100, 0 },
{ 0x101, 16 },
{ 0x102, 9 },
{ 0x103, 49 },
{ 0x105, 21 },
{ 0x106, 13 },
{ 0x107, 20 },
{ 0x108, 22 },
{ 0x109, 44 },
{ 0x10A, 23 },
{ 0x10B, 45 },
{ 0x110, 42 },
{ 0x111, 4 },
{ 0x112, 5 },
{ 0x113, 14 },
{ 0x114, 7 },
{ 0x120, 26 },
{ 0x121, 28 },
{ 0x122, 30 },
{ 0x123, 32 },
{ 0x124, 34 },
{ 0x125, 36 },
{ 0x126, 38 },
{ 0x127, 40 },
{ 0x188, 25 },
{ 0x189, 47 },
{ 0x18A, 24 },
{ 0x18B, 46 },
{ 0x190, 43 },
{ 0x191, 6 },
{ 0x193, 15 },
{ 0x194, 8 },
{ 0x198, 48 },
{ 0x1A0, 27 },
{ 0x1A1, 29 },
{ 0x1A2, 31 },
{ 0x1A3, 33 },
{ 0x1A4, 35 },
{ 0x1A5, 37 },
{ 0x1A6, 39 },
{ 0x1A7, 41 },
{ 0x200, 2 },
{ 0x201, 18 },
{ 0x202, 11 },
{ 0x203, 51 },
{ 0x300, 3 },
{ 0x301, 19 },
{ 0x302, 12 },
{ 0x303, 52 },
};
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M2M3Encoding8);
if (i == -1)
return NULL;
else
return &MClassSysRegsList[Index[i].index];
}
const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding) {
static const struct IndexType Index[] = {
{ 0x400, 1 },
{ 0x401, 17 },
{ 0x402, 10 },
{ 0x403, 50 },
{ 0x800, 0 },
{ 0x800, 2 },
{ 0x801, 16 },
{ 0x801, 18 },
{ 0x802, 9 },
{ 0x802, 11 },
{ 0x803, 49 },
{ 0x803, 51 },
{ 0x805, 21 },
{ 0x806, 13 },
{ 0x807, 20 },
{ 0x808, 22 },
{ 0x809, 44 },
{ 0x80A, 23 },
{ 0x80B, 45 },
{ 0x810, 42 },
{ 0x811, 4 },
{ 0x812, 5 },
{ 0x813, 14 },
{ 0x814, 7 },
{ 0x820, 26 },
{ 0x821, 28 },
{ 0x822, 30 },
{ 0x823, 32 },
{ 0x824, 34 },
{ 0x825, 36 },
{ 0x826, 38 },
{ 0x827, 40 },
{ 0x888, 25 },
{ 0x889, 47 },
{ 0x88A, 24 },
{ 0x88B, 46 },
{ 0x890, 43 },
{ 0x891, 6 },
{ 0x893, 15 },
{ 0x894, 8 },
{ 0x898, 48 },
{ 0x8A0, 27 },
{ 0x8A1, 29 },
{ 0x8A2, 31 },
{ 0x8A3, 33 },
{ 0x8A4, 35 },
{ 0x8A5, 37 },
{ 0x8A6, 39 },
{ 0x8A7, 41 },
{ 0xC00, 3 },
{ 0xC01, 19 },
{ 0xC02, 12 },
{ 0xC03, 52 },
};
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
if (i == -1)
return NULL;
else
return &MClassSysRegsList[Index[i].index];
}
#endif
#undef GET_BANKEDREG_DECL
#undef GET_BANKEDREG_IMPL
#undef GET_MCLASSSYSREG_DECL
#undef GET_MCLASSSYSREG_IMPL
arch/ARM/ARMInsnEnum.inc
+162
View File
@@ -0,0 +1,162 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* By Rot127 <unisono@quyllur.org>, 2023 */
/* Auto generated file. Do not edit. */
/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
ARM_INS___BRKDIV0, ARM_INS_ADC, ARM_INS_ADD, ARM_INS_ADDW, ARM_INS_ADR,
ARM_INS_AESD, ARM_INS_AESE, ARM_INS_AESIMC, ARM_INS_AESMC, ARM_INS_AND,
ARM_INS_ASR, ARM_INS_ASRL, ARM_INS_AUT, ARM_INS_AUTG, ARM_INS_B,
ARM_INS_BF, ARM_INS_BFC, ARM_INS_BFCSEL, ARM_INS_BFI, ARM_INS_BFL,
ARM_INS_BFLX, ARM_INS_BFX, ARM_INS_BIC, ARM_INS_BKPT, ARM_INS_BL,
ARM_INS_BLX, ARM_INS_BLXNS, ARM_INS_BTI, ARM_INS_BX, ARM_INS_BXAUT,
ARM_INS_BXJ, ARM_INS_BXNS, ARM_INS_CBNZ, ARM_INS_CBZ, ARM_INS_CDP,
ARM_INS_CDP2, ARM_INS_CINC, ARM_INS_CINV, ARM_INS_CLRBHB, ARM_INS_CLREX,
ARM_INS_CLRM, ARM_INS_CLZ, ARM_INS_CMN, ARM_INS_CMP, ARM_INS_CNEG,
ARM_INS_CPS, ARM_INS_CRC32B, ARM_INS_CRC32CB, ARM_INS_CRC32CH,
ARM_INS_CRC32CW, ARM_INS_CRC32H, ARM_INS_CRC32W, ARM_INS_CSDB,
ARM_INS_CSEL, ARM_INS_CSET, ARM_INS_CSETM, ARM_INS_CSINC, ARM_INS_CSINV,
ARM_INS_CSNEG, ARM_INS_CX1, ARM_INS_CX1A, ARM_INS_CX1D, ARM_INS_CX1DA,
ARM_INS_CX2, ARM_INS_CX2A, ARM_INS_CX2D, ARM_INS_CX2DA, ARM_INS_CX3,
ARM_INS_CX3A, ARM_INS_CX3D, ARM_INS_CX3DA, ARM_INS_DBG, ARM_INS_DCPS1,
ARM_INS_DCPS2, ARM_INS_DCPS3, ARM_INS_DFB, ARM_INS_DLS, ARM_INS_DLSTP,
ARM_INS_DMB, ARM_INS_DSB, ARM_INS_EOR, ARM_INS_ERET, ARM_INS_ESB,
ARM_INS_FADDD, ARM_INS_FADDS, ARM_INS_FCMPZD, ARM_INS_FCMPZS,
ARM_INS_FCONSTD, ARM_INS_FCONSTS, ARM_INS_FLDMDBX, ARM_INS_FLDMIAX,
ARM_INS_FMDHR, ARM_INS_FMDLR, ARM_INS_FMSTAT, ARM_INS_FSTMDBX,
ARM_INS_FSTMIAX, ARM_INS_FSUBD, ARM_INS_FSUBS, ARM_INS_HINT,
ARM_INS_HLT, ARM_INS_HVC, ARM_INS_ISB, ARM_INS_IT, ARM_INS_LCTP,
ARM_INS_LDA, ARM_INS_LDAB, ARM_INS_LDAEX, ARM_INS_LDAEXB,
ARM_INS_LDAEXD, ARM_INS_LDAEXH, ARM_INS_LDAH, ARM_INS_LDC, ARM_INS_LDC2,
ARM_INS_LDC2L, ARM_INS_LDCL, ARM_INS_LDM, ARM_INS_LDMDA, ARM_INS_LDMDB,
ARM_INS_LDMIB, ARM_INS_LDR, ARM_INS_LDRB, ARM_INS_LDRBT, ARM_INS_LDRD,
ARM_INS_LDREX, ARM_INS_LDREXB, ARM_INS_LDREXD, ARM_INS_LDREXH,
ARM_INS_LDRH, ARM_INS_LDRHT, ARM_INS_LDRSB, ARM_INS_LDRSBT,
ARM_INS_LDRSH, ARM_INS_LDRSHT, ARM_INS_LDRT, ARM_INS_LE, ARM_INS_LETP,
ARM_INS_LSL, ARM_INS_LSLL, ARM_INS_LSR, ARM_INS_LSRL, ARM_INS_MCR,
ARM_INS_MCR2, ARM_INS_MCRR, ARM_INS_MCRR2, ARM_INS_MLA, ARM_INS_MLS,
ARM_INS_MOV, ARM_INS_MOVS, ARM_INS_MOVT, ARM_INS_MOVW, ARM_INS_MRC,
ARM_INS_MRC2, ARM_INS_MRRC, ARM_INS_MRRC2, ARM_INS_MRS, ARM_INS_MSR,
ARM_INS_MUL, ARM_INS_MVN, ARM_INS_NEG, ARM_INS_NOP, ARM_INS_ORN,
ARM_INS_ORR, ARM_INS_PAC, ARM_INS_PACBTI, ARM_INS_PACG, ARM_INS_PKHBT,
ARM_INS_PKHTB, ARM_INS_PLD, ARM_INS_PLDW, ARM_INS_PLI, ARM_INS_POP,
ARM_INS_PSSBB, ARM_INS_PUSH, ARM_INS_QADD, ARM_INS_QADD16,
ARM_INS_QADD8, ARM_INS_QASX, ARM_INS_QDADD, ARM_INS_QDSUB, ARM_INS_QSAX,
ARM_INS_QSUB, ARM_INS_QSUB16, ARM_INS_QSUB8, ARM_INS_RBIT, ARM_INS_REV,
ARM_INS_REV16, ARM_INS_REVSH, ARM_INS_RFEDA, ARM_INS_RFEDB,
ARM_INS_RFEIA, ARM_INS_RFEIB, ARM_INS_ROR, ARM_INS_RRX, ARM_INS_RSB,
ARM_INS_RSC, ARM_INS_SADD16, ARM_INS_SADD8, ARM_INS_SASX, ARM_INS_SB,
ARM_INS_SBC, ARM_INS_SBFX, ARM_INS_SDIV, ARM_INS_SEL, ARM_INS_SETEND,
ARM_INS_SETPAN, ARM_INS_SEV, ARM_INS_SEVL, ARM_INS_SG, ARM_INS_SHA1C,
ARM_INS_SHA1H, ARM_INS_SHA1M, ARM_INS_SHA1P, ARM_INS_SHA1SU0,
ARM_INS_SHA1SU1, ARM_INS_SHA256H, ARM_INS_SHA256H2, ARM_INS_SHA256SU0,
ARM_INS_SHA256SU1, ARM_INS_SHADD16, ARM_INS_SHADD8, ARM_INS_SHASX,
ARM_INS_SHSAX, ARM_INS_SHSUB16, ARM_INS_SHSUB8, ARM_INS_SMC,
ARM_INS_SMLABB, ARM_INS_SMLABT, ARM_INS_SMLAD, ARM_INS_SMLADX,
ARM_INS_SMLAL, ARM_INS_SMLALBB, ARM_INS_SMLALBT, ARM_INS_SMLALD,
ARM_INS_SMLALDX, ARM_INS_SMLALTB, ARM_INS_SMLALTT, ARM_INS_SMLATB,
ARM_INS_SMLATT, ARM_INS_SMLAWB, ARM_INS_SMLAWT, ARM_INS_SMLSD,
ARM_INS_SMLSDX, ARM_INS_SMLSLD, ARM_INS_SMLSLDX, ARM_INS_SMMLA,
ARM_INS_SMMLAR, ARM_INS_SMMLS, ARM_INS_SMMLSR, ARM_INS_SMMUL,
ARM_INS_SMMULR, ARM_INS_SMUAD, ARM_INS_SMUADX, ARM_INS_SMULBB,
ARM_INS_SMULBT, ARM_INS_SMULL, ARM_INS_SMULTB, ARM_INS_SMULTT,
ARM_INS_SMULWB, ARM_INS_SMULWT, ARM_INS_SMUSD, ARM_INS_SMUSDX,
ARM_INS_SQRSHR, ARM_INS_SQRSHRL, ARM_INS_SQSHL, ARM_INS_SQSHLL,
ARM_INS_SRSDA, ARM_INS_SRSDB, ARM_INS_SRSHR, ARM_INS_SRSHRL,
ARM_INS_SRSIA, ARM_INS_SRSIB, ARM_INS_SSAT, ARM_INS_SSAT16,
ARM_INS_SSAX, ARM_INS_SSBB, ARM_INS_SSUB16, ARM_INS_SSUB8, ARM_INS_STC,
ARM_INS_STC2, ARM_INS_STC2L, ARM_INS_STCL, ARM_INS_STL, ARM_INS_STLB,
ARM_INS_STLEX, ARM_INS_STLEXB, ARM_INS_STLEXD, ARM_INS_STLEXH,
ARM_INS_STLH, ARM_INS_STM, ARM_INS_STMDA, ARM_INS_STMDB, ARM_INS_STMIB,
ARM_INS_STR, ARM_INS_STRB, ARM_INS_STRBT, ARM_INS_STRD, ARM_INS_STREX,
ARM_INS_STREXB, ARM_INS_STREXD, ARM_INS_STREXH, ARM_INS_STRH,
ARM_INS_STRHT, ARM_INS_STRT, ARM_INS_SUB, ARM_INS_SUBS, ARM_INS_SUBW,
ARM_INS_SVC, ARM_INS_SWP, ARM_INS_SWPB, ARM_INS_SXTAB, ARM_INS_SXTAB16,
ARM_INS_SXTAH, ARM_INS_SXTB, ARM_INS_SXTB16, ARM_INS_SXTH, ARM_INS_TBB,
ARM_INS_TBH, ARM_INS_TEQ, ARM_INS_TRAP, ARM_INS_TSB, ARM_INS_TST,
ARM_INS_TT, ARM_INS_TTA, ARM_INS_TTAT, ARM_INS_TTT, ARM_INS_UADD16,
ARM_INS_UADD8, ARM_INS_UASX, ARM_INS_UBFX, ARM_INS_UDF, ARM_INS_UDIV,
ARM_INS_UHADD16, ARM_INS_UHADD8, ARM_INS_UHASX, ARM_INS_UHSAX,
ARM_INS_UHSUB16, ARM_INS_UHSUB8, ARM_INS_UMAAL, ARM_INS_UMLAL,
ARM_INS_UMULL, ARM_INS_UQADD16, ARM_INS_UQADD8, ARM_INS_UQASX,
ARM_INS_UQRSHL, ARM_INS_UQRSHLL, ARM_INS_UQSAX, ARM_INS_UQSHL,
ARM_INS_UQSHLL, ARM_INS_UQSUB16, ARM_INS_UQSUB8, ARM_INS_URSHR,
ARM_INS_URSHRL, ARM_INS_USAD8, ARM_INS_USADA8, ARM_INS_USAT,
ARM_INS_USAT16, ARM_INS_USAX, ARM_INS_USUB16, ARM_INS_USUB8,
ARM_INS_UXTAB, ARM_INS_UXTAB16, ARM_INS_UXTAH, ARM_INS_UXTB,
ARM_INS_UXTB16, ARM_INS_UXTH, ARM_INS_VABA, ARM_INS_VABAL,
ARM_INS_VABAV, ARM_INS_VABD, ARM_INS_VABDL, ARM_INS_VABS, ARM_INS_VACGE,
ARM_INS_VACGT, ARM_INS_VACLE, ARM_INS_VACLT, ARM_INS_VADC,
ARM_INS_VADCI, ARM_INS_VADD, ARM_INS_VADDHN, ARM_INS_VADDL,
ARM_INS_VADDLV, ARM_INS_VADDLVA, ARM_INS_VADDV, ARM_INS_VADDVA,
ARM_INS_VADDW, ARM_INS_VAND, ARM_INS_VBIC, ARM_INS_VBIF, ARM_INS_VBIT,
ARM_INS_VBRSR, ARM_INS_VBSL, ARM_INS_VCADD, ARM_INS_VCEQ, ARM_INS_VCGE,
ARM_INS_VCGT, ARM_INS_VCLE, ARM_INS_VCLS, ARM_INS_VCLT, ARM_INS_VCLZ,
ARM_INS_VCMLA, ARM_INS_VCMP, ARM_INS_VCMPE, ARM_INS_VCMUL, ARM_INS_VCNT,
ARM_INS_VCTP, ARM_INS_VCVT, ARM_INS_VCVTA, ARM_INS_VCVTB, ARM_INS_VCVTM,
ARM_INS_VCVTN, ARM_INS_VCVTP, ARM_INS_VCVTR, ARM_INS_VCVTT,
ARM_INS_VCX1, ARM_INS_VCX1A, ARM_INS_VCX2, ARM_INS_VCX2A, ARM_INS_VCX3,
ARM_INS_VCX3A, ARM_INS_VDDUP, ARM_INS_VDIV, ARM_INS_VDOT, ARM_INS_VDUP,
ARM_INS_VDWDUP, ARM_INS_VEOR, ARM_INS_VEXT, ARM_INS_VFMA, ARM_INS_VFMAB,
ARM_INS_VFMAL, ARM_INS_VFMAS, ARM_INS_VFMAT, ARM_INS_VFMS,
ARM_INS_VFMSL, ARM_INS_VFNMA, ARM_INS_VFNMS, ARM_INS_VHADD,
ARM_INS_VHCADD, ARM_INS_VHSUB, ARM_INS_VIDUP, ARM_INS_VINS,
ARM_INS_VIWDUP, ARM_INS_VJCVT, ARM_INS_VLD1, ARM_INS_VLD2,
ARM_INS_VLD20, ARM_INS_VLD21, ARM_INS_VLD3, ARM_INS_VLD4, ARM_INS_VLD40,
ARM_INS_VLD41, ARM_INS_VLD42, ARM_INS_VLD43, ARM_INS_VLDMDB,
ARM_INS_VLDMIA, ARM_INS_VLDR, ARM_INS_VLDRB, ARM_INS_VLDRD,
ARM_INS_VLDRH, ARM_INS_VLDRW, ARM_INS_VLLDM, ARM_INS_VLSTM,
ARM_INS_VMAX, ARM_INS_VMAXA, ARM_INS_VMAXAV, ARM_INS_VMAXNM,
ARM_INS_VMAXNMA, ARM_INS_VMAXNMAV, ARM_INS_VMAXNMV, ARM_INS_VMAXV,
ARM_INS_VMIN, ARM_INS_VMINA, ARM_INS_VMINAV, ARM_INS_VMINNM,
ARM_INS_VMINNMA, ARM_INS_VMINNMAV, ARM_INS_VMINNMV, ARM_INS_VMINV,
ARM_INS_VMLA, ARM_INS_VMLADAV, ARM_INS_VMLADAVA, ARM_INS_VMLADAVAX,
ARM_INS_VMLADAVX, ARM_INS_VMLAL, ARM_INS_VMLALDAV, ARM_INS_VMLALDAVA,
ARM_INS_VMLALDAVAX, ARM_INS_VMLALDAVX, ARM_INS_VMLALV, ARM_INS_VMLALVA,
ARM_INS_VMLAS, ARM_INS_VMLAV, ARM_INS_VMLAVA, ARM_INS_VMLS,
ARM_INS_VMLSDAV, ARM_INS_VMLSDAVA, ARM_INS_VMLSDAVAX, ARM_INS_VMLSDAVX,
ARM_INS_VMLSL, ARM_INS_VMLSLDAV, ARM_INS_VMLSLDAVA, ARM_INS_VMLSLDAVAX,
ARM_INS_VMLSLDAVX, ARM_INS_VMMLA, ARM_INS_VMOV, ARM_INS_VMOVL,
ARM_INS_VMOVLB, ARM_INS_VMOVLT, ARM_INS_VMOVN, ARM_INS_VMOVNB,
ARM_INS_VMOVNT, ARM_INS_VMOVX, ARM_INS_VMRS, ARM_INS_VMSR, ARM_INS_VMUL,
ARM_INS_VMULH, ARM_INS_VMULL, ARM_INS_VMULLB, ARM_INS_VMULLT,
ARM_INS_VMVN, ARM_INS_VNEG, ARM_INS_VNMLA, ARM_INS_VNMLS, ARM_INS_VNMUL,
ARM_INS_VORN, ARM_INS_VORR, ARM_INS_VPADAL, ARM_INS_VPADD,
ARM_INS_VPADDL, ARM_INS_VPMAX, ARM_INS_VPMIN, ARM_INS_VPNOT,
ARM_INS_VPOP, ARM_INS_VPSEL, ARM_INS_VPST, ARM_INS_VPT, ARM_INS_VPUSH,
ARM_INS_VQABS, ARM_INS_VQADD, ARM_INS_VQDMLADH, ARM_INS_VQDMLADHX,
ARM_INS_VQDMLAH, ARM_INS_VQDMLAL, ARM_INS_VQDMLASH, ARM_INS_VQDMLSDH,
ARM_INS_VQDMLSDHX, ARM_INS_VQDMLSL, ARM_INS_VQDMULH, ARM_INS_VQDMULL,
ARM_INS_VQDMULLB, ARM_INS_VQDMULLT, ARM_INS_VQMOVN, ARM_INS_VQMOVNB,
ARM_INS_VQMOVNT, ARM_INS_VQMOVUN, ARM_INS_VQMOVUNB, ARM_INS_VQMOVUNT,
ARM_INS_VQNEG, ARM_INS_VQRDMLADH, ARM_INS_VQRDMLADHX, ARM_INS_VQRDMLAH,
ARM_INS_VQRDMLASH, ARM_INS_VQRDMLSDH, ARM_INS_VQRDMLSDHX,
ARM_INS_VQRDMLSH, ARM_INS_VQRDMULH, ARM_INS_VQRSHL, ARM_INS_VQRSHRN,
ARM_INS_VQRSHRNB, ARM_INS_VQRSHRNT, ARM_INS_VQRSHRUN, ARM_INS_VQRSHRUNB,
ARM_INS_VQRSHRUNT, ARM_INS_VQSHL, ARM_INS_VQSHLU, ARM_INS_VQSHRN,
ARM_INS_VQSHRNB, ARM_INS_VQSHRNT, ARM_INS_VQSHRUN, ARM_INS_VQSHRUNB,
ARM_INS_VQSHRUNT, ARM_INS_VQSUB, ARM_INS_VRADDHN, ARM_INS_VRECPE,
ARM_INS_VRECPS, ARM_INS_VREV16, ARM_INS_VREV32, ARM_INS_VREV64,
ARM_INS_VRHADD, ARM_INS_VRINTA, ARM_INS_VRINTM, ARM_INS_VRINTN,
ARM_INS_VRINTP, ARM_INS_VRINTR, ARM_INS_VRINTX, ARM_INS_VRINTZ,
ARM_INS_VRMLALDAVH, ARM_INS_VRMLALDAVHA, ARM_INS_VRMLALDAVHAX,
ARM_INS_VRMLALDAVHX, ARM_INS_VRMLALVH, ARM_INS_VRMLALVHA,
ARM_INS_VRMLSLDAVH, ARM_INS_VRMLSLDAVHA, ARM_INS_VRMLSLDAVHAX,
ARM_INS_VRMLSLDAVHX, ARM_INS_VRMULH, ARM_INS_VRSHL, ARM_INS_VRSHR,
ARM_INS_VRSHRN, ARM_INS_VRSHRNB, ARM_INS_VRSHRNT, ARM_INS_VRSQRTE,
ARM_INS_VRSQRTS, ARM_INS_VRSRA, ARM_INS_VRSUBHN, ARM_INS_VSBC,
ARM_INS_VSBCI, ARM_INS_VSCCLRM, ARM_INS_VSDOT, ARM_INS_VSELEQ,
ARM_INS_VSELGE, ARM_INS_VSELGT, ARM_INS_VSELVS, ARM_INS_VSHL,
ARM_INS_VSHLC, ARM_INS_VSHLL, ARM_INS_VSHLLB, ARM_INS_VSHLLT,
ARM_INS_VSHR, ARM_INS_VSHRN, ARM_INS_VSHRNB, ARM_INS_VSHRNT,
ARM_INS_VSLI, ARM_INS_VSMMLA, ARM_INS_VSQRT, ARM_INS_VSRA, ARM_INS_VSRI,
ARM_INS_VST1, ARM_INS_VST2, ARM_INS_VST20, ARM_INS_VST21, ARM_INS_VST3,
ARM_INS_VST4, ARM_INS_VST40, ARM_INS_VST41, ARM_INS_VST42,
ARM_INS_VST43, ARM_INS_VSTMDB, ARM_INS_VSTMIA, ARM_INS_VSTR,
ARM_INS_VSTRB, ARM_INS_VSTRD, ARM_INS_VSTRH, ARM_INS_VSTRW,
ARM_INS_VSUB, ARM_INS_VSUBHN, ARM_INS_VSUBL, ARM_INS_VSUBW,
ARM_INS_VSUDOT, ARM_INS_VSWP, ARM_INS_VTBL, ARM_INS_VTBX, ARM_INS_VTRN,
ARM_INS_VTST, ARM_INS_VUDOT, ARM_INS_VUMMLA, ARM_INS_VUSDOT,
ARM_INS_VUSMMLA, ARM_INS_VUZP, ARM_INS_VZIP, ARM_INS_WFE, ARM_INS_WFI,
ARM_INS_WLS, ARM_INS_WLSTP, ARM_INS_YIELD,
arch/ARM/ARMInstPrinter.c
+2020
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arch/ARM/ARMInstPrinter.h
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARM MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef CS_ARM_INSTPRINTER_H
#define CS_ARM_INSTPRINTER_H
unsigned translateShiftImm(unsigned imm);
#endif // CS_ARM_INSTPRINTER_H
arch/ARM/ARMLinkage.h
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_ARM_LINKAGE_H
#define CS_ARM_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI, uint16_t *Size,
uint64_t Address, void *Info);
const char *ARM_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
void ARM_LLVM_printInstruction(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
#endif // CS_ARM_LINKAGE_H
arch/ARM/ARMMapping.c
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arch/ARM/ARMMapping.h
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_ARM_MAPPING_H
#define CS_ARM_MAPPING_H
#include "../../include/capstone/capstone.h"
#include "../../utils.h"
#include "../../Mapping.h"
#include "ARMBaseInfo.h"
typedef enum {
#include "ARMGenCSOpGroup.inc"
} arm_op_group;
extern const ARMBankedReg_BankedReg *
ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
extern const ARMSysReg_MClassSysReg *
ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
// return name of register in friendly string
const char *ARM_reg_name(csh handle, unsigned int reg);
void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
// given internal insn id, return public instruction ID
void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *ARM_insn_name(csh handle, unsigned int id);
const char *ARM_group_name(csh handle, unsigned int id);
// check if this insn is relative branch
bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
void ARM_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
const ARMBankedReg_BankedReg *
ARMBankedReg_lookupBankedRegByEncoding(uint8_t encoding);
bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
void ARM_set_instr_map_data(MCInst *MI);
void ARM_init_mri(MCRegisterInfo *MRI);
// cs_detail related functions
void ARM_init_cs_detail(MCInst *MI);
void ARM_add_cs_detail_0(MCInst *MI, int /* arm_op_group */ op_group,
size_t op_num);
void ARM_add_cs_detail_1(MCInst *MI, int /* arm_op_group */ op_group,
size_t op_num, uint64_t templ_arg_0);
void ARM_add_cs_detail_2(MCInst *MI, int /* arm_op_group */ op_group,
size_t op_num, uint64_t templ_arg_0,
uint64_t templ_arg_1);
void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg,
cs_ac_type access);
void ARM_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val,
cs_ac_type access);
void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg);
void ARM_set_detail_op_sysop(MCInst *MI, int SysReg, arm_op_type type,
bool IsOutReg, uint8_t Mask, uint16_t Sysm);
void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType,
int64_t Imm);
void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm);
void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg,
int scale, uint64_t Val);
void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val,
bool subtracted);
void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum);
void ARM_check_updates_flags(MCInst *MI);
void ARM_setup_op(cs_arm_op *op);
void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type);
void ARM_add_vector_size(MCInst *MI, unsigned size);
#endif // CS_ARM_MAPPING_H
arch/ARM/ARMModule.c
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/* Capstone Disassembly Engine */
/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
#include "capstone/capstone.h"
#ifdef CAPSTONE_HAS_ARM
#include "ARMModule.h"
#include "../../MCRegisterInfo.h"
#include "../../cs_priv.h"
#include "ARMInstPrinter.h"
#include "ARMMapping.h"
cs_err ARM_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
if (!mri)
return CS_ERR_MEM;
ARM_init_mri(mri);
ud->printer = ARM_printer;
ud->printer_info = mri;
ud->reg_name = ARM_reg_name;
ud->insn_id = ARM_get_insn_id;
ud->insn_name = ARM_insn_name;
ud->group_name = ARM_group_name;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = ARM_reg_access;
#endif
ud->disasm = ARM_getInstruction;
return CS_ERR_OK;
}
cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value)
{
switch (type) {
case CS_OPT_MODE:
handle->mode |= (cs_mode)value;
break;
case CS_OPT_SYNTAX:
handle->syntax |= (int)value;
break;
default:
break;
}
return CS_ERR_OK;
}
#endif
arch/ARM/ARMModule.h
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/* Capstone Disassembly Engine */
/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
#ifndef CS_ARM_MODULE_H
#define CS_ARM_MODULE_H
#include "../../utils.h"
cs_err ARM_global_init(cs_struct *ud);
cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif
arch/Alpha/AlphaDisassembler.c
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <string.h>
#include "../../utils.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../Mapping.h"
#include "AlphaDisassembler.h"
#include "AlphaLinkage.h"
static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
#include "AlphaGenDisassemblerTables.inc"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "AlphaGenRegisterInfo.inc"
static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned Register = GPRC[RegNo];
MCOperand_CreateReg0(Inst, (Register));
return MCDisassembler_Success;
}
static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned Register = F4RC[RegNo];
MCOperand_CreateReg0(Inst, (Register));
return MCDisassembler_Success;
}
static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned Register = F8RC[RegNo];
MCOperand_CreateReg0(Inst, (Register));
return MCDisassembler_Success;
}
#define GET_SUBTARGETINFO_ENUM
#include "AlphaGenInstrInfo.inc"
DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI,
uint16_t *Size, uint64_t Address,
void *Info)
{
if (!handle) {
return MCDisassembler_Fail;
}
if (ByteLen < 4) {
*Size = 0;
return MCDisassembler_Fail;
}
uint32_t Insn = readBytes32(MI, Bytes);
// Calling the auto-generated decoder function.
DecodeStatus Result =
decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL);
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
*Size = 4;
return MCDisassembler_Fail;
}
void Alpha_init(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(
MRI, AlphaRegDesc, ARR_SIZE(AlphaRegDesc), 0, 0,
AlphaMCRegisterClasses, ARR_SIZE(AlphaMCRegisterClasses), 0, 0,
AlphaRegDiffLists, 0, AlphaSubRegIdxLists, 1, 0);
}
#endif
arch/Alpha/AlphaDisassembler.h
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CS_ALPHADISASSEMBLER_H
#define CS_ALPHADISASSEMBLER_H
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include <capstone/capstone.h>
void Alpha_init(MCRegisterInfo *MRI);
#endif // CS_ALPHADISASSEMBLER_H
arch/Alpha/AlphaGenAsmWriter.inc
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arch/Alpha/AlphaGenCSMappingInsn.inc
+3800
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arch/Alpha/AlphaGenCSMappingInsnName.inc
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
"invalid", // Alpha_INS_INVALID
"addl", // Alpha_INS_ADDL
"addq", // Alpha_INS_ADDQ
"adds/su", // Alpha_INS_ADDSsSU
"addt/su", // Alpha_INS_ADDTsSU
"and", // Alpha_INS_AND
"beq", // Alpha_INS_BEQ
"bge", // Alpha_INS_BGE
"bgt", // Alpha_INS_BGT
"bic", // Alpha_INS_BIC
"bis", // Alpha_INS_BIS
"blbc", // Alpha_INS_BLBC
"blbs", // Alpha_INS_BLBS
"ble", // Alpha_INS_BLE
"blt", // Alpha_INS_BLT
"bne", // Alpha_INS_BNE
"br", // Alpha_INS_BR
"bsr", // Alpha_INS_BSR
"cmoveq", // Alpha_INS_CMOVEQ
"cmovge", // Alpha_INS_CMOVGE
"cmovgt", // Alpha_INS_CMOVGT
"cmovlbc", // Alpha_INS_CMOVLBC
"cmovlbs", // Alpha_INS_CMOVLBS
"cmovle", // Alpha_INS_CMOVLE
"cmovlt", // Alpha_INS_CMOVLT
"cmovne", // Alpha_INS_CMOVNE
"cmpbge", // Alpha_INS_CMPBGE
"cmpeq", // Alpha_INS_CMPEQ
"cmple", // Alpha_INS_CMPLE
"cmplt", // Alpha_INS_CMPLT
"cmpteq/su", // Alpha_INS_CMPTEQsSU
"cmptle/su", // Alpha_INS_CMPTLEsSU
"cmptlt/su", // Alpha_INS_CMPTLTsSU
"cmptun/su", // Alpha_INS_CMPTUNsSU
"cmpule", // Alpha_INS_CMPULE
"cmpult", // Alpha_INS_CMPULT
"COND_BRANCH", // Alpha_INS_COND_BRANCH
"cpyse", // Alpha_INS_CPYSE
"cpysn", // Alpha_INS_CPYSN
"cpys", // Alpha_INS_CPYS
"ctlz", // Alpha_INS_CTLZ
"ctpop", // Alpha_INS_CTPOP
"cttz", // Alpha_INS_CTTZ
"cvtqs/sui", // Alpha_INS_CVTQSsSUI
"cvtqt/sui", // Alpha_INS_CVTQTsSUI
"cvtst/s", // Alpha_INS_CVTSTsS
"cvttq/svc", // Alpha_INS_CVTTQsSVC
"cvtts/sui", // Alpha_INS_CVTTSsSUI
"divs/su", // Alpha_INS_DIVSsSU
"divt/su", // Alpha_INS_DIVTsSU
"ecb", // Alpha_INS_ECB
"eqv", // Alpha_INS_EQV
"excb", // Alpha_INS_EXCB
"extbl", // Alpha_INS_EXTBL
"extlh", // Alpha_INS_EXTLH
"extll", // Alpha_INS_EXTLL
"extqh", // Alpha_INS_EXTQH
"extql", // Alpha_INS_EXTQL
"extwh", // Alpha_INS_EXTWH
"extwl", // Alpha_INS_EXTWL
"fbeq", // Alpha_INS_FBEQ
"fbge", // Alpha_INS_FBGE
"fbgt", // Alpha_INS_FBGT
"fble", // Alpha_INS_FBLE
"fblt", // Alpha_INS_FBLT
"fbne", // Alpha_INS_FBNE
"fcmoveq", // Alpha_INS_FCMOVEQ
"fcmovge", // Alpha_INS_FCMOVGE
"fcmovgt", // Alpha_INS_FCMOVGT
"fcmovle", // Alpha_INS_FCMOVLE
"fcmovlt", // Alpha_INS_FCMOVLT
"fcmovne", // Alpha_INS_FCMOVNE
"fetch", // Alpha_INS_FETCH
"fetch_m", // Alpha_INS_FETCH_M
"ftois", // Alpha_INS_FTOIS
"ftoit", // Alpha_INS_FTOIT
"insbl", // Alpha_INS_INSBL
"inslh", // Alpha_INS_INSLH
"insll", // Alpha_INS_INSLL
"insqh", // Alpha_INS_INSQH
"insql", // Alpha_INS_INSQL
"inswh", // Alpha_INS_INSWH
"inswl", // Alpha_INS_INSWL
"itofs", // Alpha_INS_ITOFS
"itoft", // Alpha_INS_ITOFT
"jmp", // Alpha_INS_JMP
"jsr", // Alpha_INS_JSR
"jsr_coroutine", // Alpha_INS_JSR_COROUTINE
"lda", // Alpha_INS_LDA
"ldah", // Alpha_INS_LDAH
"ldbu", // Alpha_INS_LDBU
"ldl", // Alpha_INS_LDL
"ldl_l", // Alpha_INS_LDL_L
"ldq", // Alpha_INS_LDQ
"ldq_l", // Alpha_INS_LDQ_L
"ldq_u", // Alpha_INS_LDQ_U
"lds", // Alpha_INS_LDS
"ldt", // Alpha_INS_LDT
"ldwu", // Alpha_INS_LDWU
"mb", // Alpha_INS_MB
"mskbl", // Alpha_INS_MSKBL
"msklh", // Alpha_INS_MSKLH
"mskll", // Alpha_INS_MSKLL
"mskqh", // Alpha_INS_MSKQH
"mskql", // Alpha_INS_MSKQL
"mskwh", // Alpha_INS_MSKWH
"mskwl", // Alpha_INS_MSKWL
"mull", // Alpha_INS_MULL
"mulq", // Alpha_INS_MULQ
"muls/su", // Alpha_INS_MULSsSU
"mult/su", // Alpha_INS_MULTsSU
"ornot", // Alpha_INS_ORNOT
"rc", // Alpha_INS_RC
"ret", // Alpha_INS_RET
"rpcc", // Alpha_INS_RPCC
"rs", // Alpha_INS_RS
"s4addl", // Alpha_INS_S4ADDL
"s4addq", // Alpha_INS_S4ADDQ
"s4subl", // Alpha_INS_S4SUBL
"s4subq", // Alpha_INS_S4SUBQ
"s8addl", // Alpha_INS_S8ADDL
"s8addq", // Alpha_INS_S8ADDQ
"s8subl", // Alpha_INS_S8SUBL
"s8subq", // Alpha_INS_S8SUBQ
"sextb", // Alpha_INS_SEXTB
"sextw", // Alpha_INS_SEXTW
"sll", // Alpha_INS_SLL
"sqrts/su", // Alpha_INS_SQRTSsSU
"sqrtt/su", // Alpha_INS_SQRTTsSU
"sra", // Alpha_INS_SRA
"srl", // Alpha_INS_SRL
"stb", // Alpha_INS_STB
"stl", // Alpha_INS_STL
"stl_c", // Alpha_INS_STL_C
"stq", // Alpha_INS_STQ
"stq_c", // Alpha_INS_STQ_C
"stq_u", // Alpha_INS_STQ_U
"sts", // Alpha_INS_STS
"stt", // Alpha_INS_STT
"stw", // Alpha_INS_STW
"subl", // Alpha_INS_SUBL
"subq", // Alpha_INS_SUBQ
"subs/su", // Alpha_INS_SUBSsSU
"subt/su", // Alpha_INS_SUBTsSU
"trapb", // Alpha_INS_TRAPB
"umulh", // Alpha_INS_UMULH
"wh64", // Alpha_INS_WH64
"wh64en", // Alpha_INS_WH64EN
"wmb", // Alpha_INS_WMB
"xor", // Alpha_INS_XOR
"zapnot", // Alpha_INS_ZAPNOT
arch/Alpha/AlphaGenCSMappingInsnOp.inc
+2467
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arch/Alpha/AlphaGenCSOpGroup.inc
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
Alpha_OP_GROUP_Operand = 0,
arch/Alpha/AlphaGenDisassemblerTables.inc
+1062
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arch/Alpha/AlphaGenInstrInfo.inc
+1119
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arch/Alpha/AlphaGenRegisterInfo.inc
+280
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@@ -0,0 +1,280 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
Alpha_NoRegister,
Alpha_F0 = 1,
Alpha_F1 = 2,
Alpha_F2 = 3,
Alpha_F3 = 4,
Alpha_F4 = 5,
Alpha_F5 = 6,
Alpha_F6 = 7,
Alpha_F7 = 8,
Alpha_F8 = 9,
Alpha_F9 = 10,
Alpha_F10 = 11,
Alpha_F11 = 12,
Alpha_F12 = 13,
Alpha_F13 = 14,
Alpha_F14 = 15,
Alpha_F15 = 16,
Alpha_F16 = 17,
Alpha_F17 = 18,
Alpha_F18 = 19,
Alpha_F19 = 20,
Alpha_F20 = 21,
Alpha_F21 = 22,
Alpha_F22 = 23,
Alpha_F23 = 24,
Alpha_F24 = 25,
Alpha_F25 = 26,
Alpha_F26 = 27,
Alpha_F27 = 28,
Alpha_F28 = 29,
Alpha_F29 = 30,
Alpha_F30 = 31,
Alpha_F31 = 32,
Alpha_R0 = 33,
Alpha_R1 = 34,
Alpha_R2 = 35,
Alpha_R3 = 36,
Alpha_R4 = 37,
Alpha_R5 = 38,
Alpha_R6 = 39,
Alpha_R7 = 40,
Alpha_R8 = 41,
Alpha_R9 = 42,
Alpha_R10 = 43,
Alpha_R11 = 44,
Alpha_R12 = 45,
Alpha_R13 = 46,
Alpha_R14 = 47,
Alpha_R15 = 48,
Alpha_R16 = 49,
Alpha_R17 = 50,
Alpha_R18 = 51,
Alpha_R19 = 52,
Alpha_R20 = 53,
Alpha_R21 = 54,
Alpha_R22 = 55,
Alpha_R23 = 56,
Alpha_R24 = 57,
Alpha_R25 = 58,
Alpha_R26 = 59,
Alpha_R27 = 60,
Alpha_R28 = 61,
Alpha_R29 = 62,
Alpha_R30 = 63,
Alpha_R31 = 64,
NUM_TARGET_REGS // 65
};
// Register classes
enum {
Alpha_F4RCRegClassID = 0,
Alpha_F8RCRegClassID = 1,
Alpha_GPRCRegClassID = 2,
};
#endif // GET_REGINFO_ENUM
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg AlphaRegDiffLists[] = {
/* 0 */ -1, 0,
};
static const uint16_t AlphaSubRegIdxLists[] = {
/* 0 */ 0,
};
static const MCRegisterDesc AlphaRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 24, 1, 1, 0, 1, 0 },
{ 54, 1, 1, 0, 1, 0 },
{ 76, 1, 1, 0, 1, 0 },
{ 98, 1, 1, 0, 1, 0 },
{ 120, 1, 1, 0, 1, 0 },
{ 142, 1, 1, 0, 1, 0 },
{ 164, 1, 1, 0, 1, 0 },
{ 186, 1, 1, 0, 1, 0 },
{ 208, 1, 1, 0, 1, 0 },
{ 230, 1, 1, 0, 1, 0 },
{ 0, 1, 1, 0, 1, 0 },
{ 30, 1, 1, 0, 1, 0 },
{ 60, 1, 1, 0, 1, 0 },
{ 82, 1, 1, 0, 1, 0 },
{ 104, 1, 1, 0, 1, 0 },
{ 126, 1, 1, 0, 1, 0 },
{ 148, 1, 1, 0, 1, 0 },
{ 170, 1, 1, 0, 1, 0 },
{ 192, 1, 1, 0, 1, 0 },
{ 214, 1, 1, 0, 1, 0 },
{ 8, 1, 1, 0, 1, 0 },
{ 38, 1, 1, 0, 1, 0 },
{ 68, 1, 1, 0, 1, 0 },
{ 90, 1, 1, 0, 1, 0 },
{ 112, 1, 1, 0, 1, 0 },
{ 134, 1, 1, 0, 1, 0 },
{ 156, 1, 1, 0, 1, 0 },
{ 178, 1, 1, 0, 1, 0 },
{ 200, 1, 1, 0, 1, 0 },
{ 222, 1, 1, 0, 1, 0 },
{ 16, 1, 1, 0, 1, 0 },
{ 46, 1, 1, 0, 1, 0 },
{ 27, 1, 1, 0, 1, 0 },
{ 57, 1, 1, 0, 1, 0 },
{ 79, 1, 1, 0, 1, 0 },
{ 101, 1, 1, 0, 1, 0 },
{ 123, 1, 1, 0, 1, 0 },
{ 145, 1, 1, 0, 1, 0 },
{ 167, 1, 1, 0, 1, 0 },
{ 189, 1, 1, 0, 1, 0 },
{ 211, 1, 1, 0, 1, 0 },
{ 233, 1, 1, 0, 1, 0 },
{ 4, 1, 1, 0, 1, 0 },
{ 34, 1, 1, 0, 1, 0 },
{ 64, 1, 1, 0, 1, 0 },
{ 86, 1, 1, 0, 1, 0 },
{ 108, 1, 1, 0, 1, 0 },
{ 130, 1, 1, 0, 1, 0 },
{ 152, 1, 1, 0, 1, 0 },
{ 174, 1, 1, 0, 1, 0 },
{ 196, 1, 1, 0, 1, 0 },
{ 218, 1, 1, 0, 1, 0 },
{ 12, 1, 1, 0, 1, 0 },
{ 42, 1, 1, 0, 1, 0 },
{ 72, 1, 1, 0, 1, 0 },
{ 94, 1, 1, 0, 1, 0 },
{ 116, 1, 1, 0, 1, 0 },
{ 138, 1, 1, 0, 1, 0 },
{ 160, 1, 1, 0, 1, 0 },
{ 182, 1, 1, 0, 1, 0 },
{ 204, 1, 1, 0, 1, 0 },
{ 226, 1, 1, 0, 1, 0 },
{ 20, 1, 1, 0, 1, 0 },
{ 50, 1, 1, 0, 1, 0 },
};
// F4RC Register Class...
static const MCPhysReg F4RC[] = {
Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31,
};
// F4RC Bit set.
static const uint8_t F4RCBits[] = {
0xfe, 0xff, 0xff, 0xff, 0x01,
};
// F8RC Register Class...
static const MCPhysReg F8RC[] = {
Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31,
};
// F8RC Bit set.
static const uint8_t F8RCBits[] = {
0xfe, 0xff, 0xff, 0xff, 0x01,
};
// GPRC Register Class...
static const MCPhysReg GPRC[] = {
Alpha_R0, Alpha_R1, Alpha_R2, Alpha_R3, Alpha_R4, Alpha_R5, Alpha_R6, Alpha_R7, Alpha_R8, Alpha_R16, Alpha_R17, Alpha_R18, Alpha_R19, Alpha_R20, Alpha_R21, Alpha_R22, Alpha_R23, Alpha_R24, Alpha_R25, Alpha_R28, Alpha_R27, Alpha_R26, Alpha_R29, Alpha_R9, Alpha_R10, Alpha_R11, Alpha_R12, Alpha_R13, Alpha_R14, Alpha_R15, Alpha_R30, Alpha_R31,
};
// GPRC Bit set.
static const uint8_t GPRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
};
static const MCRegisterClass AlphaMCRegisterClasses[] = {
{ F4RC, F4RCBits, sizeof(F4RCBits) },
{ F8RC, F8RCBits, sizeof(F8RCBits) },
{ GPRC, GPRCBits, sizeof(GPRCBits) },
};
static const uint16_t AlphaRegEncodingTable[] = {
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
};
#endif // GET_REGINFO_MC_DESC
arch/Alpha/AlphaGenSubtargetInfo.inc
+24
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
Alpha_FeatureCIX = 0,
Alpha_NumSubtargetFeatures = 1
};
#endif // GET_SUBTARGETINFO_ENUM
arch/Alpha/AlphaInstPrinter.c
+92
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include <platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../utils.h"
#include "../../Mapping.h"
#include "../../MCInstPrinter.h"
#include "AlphaLinkage.h"
#include "AlphaMapping.h"
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *, uint64_t, SStream *);
static void printOperand(MCInst *MI, int OpNum, SStream *O);
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
#define GET_INSTRINFO_ENUM
#include "AlphaGenInstrInfo.inc"
#define GET_REGINFO_ENUM
#include "AlphaGenRegisterInfo.inc"
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
if (OpNum >= MI->size)
return;
Alpha_add_cs_detail(MI, OpNum);
MCOperand *Op;
Op = MCInst_getOperand(MI, OpNum);
if (MCOperand_isReg(Op)) {
unsigned reg = MCOperand_getReg(Op);
SStream_concat(O, "%s", getRegisterName(reg));
} else if (MCOperand_isImm(Op)) {
int64_t Imm = MCOperand_getImm(Op);
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%" PRIx64, Imm);
else
SStream_concat(O, "%" PRIu64, Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%" PRIx64, -Imm);
else
SStream_concat(O, "-%" PRIu64, -Imm);
}
}
}
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
uint64_t Imm = MCOperand_getImm(Op);
uint64_t Target = Address + 4 + (int16_t)(Imm << 2);
Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM, Target);
printUInt64(O, Target);
}
#define PRINT_ALIAS_INSTR
#include "AlphaGenAsmWriter.inc"
const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return getRegisterName(id);
#else
return NULL;
#endif
}
void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info)
{
printAliasInstr(MI, MI->address, O);
printInstruction(MI, MI->address, O);
}
#endif
arch/Alpha/AlphaLinkage.h
+21
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CS_ALPHA_LINKAGE_H
#define CS_ALPHA_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "AlphaMapping.h"
const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id);
void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info);
DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI,
uint16_t *Size, uint64_t Address,
void *Info);
#endif // CS_ALPHA_LINKAGE_H
arch/Alpha/AlphaMapping.c
+232
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include <stdio.h> // debug
#include <string.h>
#include "../../Mapping.h"
#include "../../cs_priv.h"
#include "../../cs_simple_types.h"
#include "../../utils.h"
#include "AlphaLinkage.h"
#include "AlphaMapping.h"
#include "./AlphaDisassembler.h"
#define GET_INSTRINFO_ENUM
#include "AlphaGenInstrInfo.inc"
static const insn_map insns[] = {
#include "AlphaGenCSMappingInsn.inc"
};
const insn_map *Alpha_insns = insns;
const unsigned int Alpha_insn_count = ARR_SIZE(insns);
static const map_insn_ops insn_operands[] = {
#include "AlphaGenCSMappingInsnOp.inc"
};
void Alpha_init_cs_detail(MCInst *MI)
{
if (detail_is_set(MI)) {
memset(get_detail(MI), 0,
offsetof(cs_detail, alpha) + sizeof(cs_alpha));
}
}
void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum)
{
if (!detail_is_set(MI))
return;
cs_op_type op_type = map_get_op_type(MI, OpNum);
if (op_type == CS_OP_IMM)
Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM,
MCInst_getOpVal(MI, OpNum));
else if (op_type == CS_OP_REG)
Alpha_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
else
CS_ASSERT_RET(0 && "Op type not handled.");
}
void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
int64_t Imm)
{
if (!detail_is_set(MI))
return;
CS_ASSERT_RET(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
CS_ASSERT_RET(map_get_op_type(MI, OpNum) == CS_OP_IMM);
CS_ASSERT_RET(ImmType == ALPHA_OP_IMM);
Alpha_get_detail_op(MI, 0)->type = ImmType;
Alpha_get_detail_op(MI, 0)->imm = Imm;
Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
Alpha_inc_op_count(MI);
}
void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg)
{
if (!detail_is_set(MI))
return;
CS_ASSERT_RET(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
CS_ASSERT_RET(map_get_op_type(MI, OpNum) == CS_OP_REG);
Alpha_get_detail_op(MI, 0)->type = ALPHA_OP_REG;
Alpha_get_detail_op(MI, 0)->reg = Reg;
Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
Alpha_inc_op_count(MI);
}
// given internal insn id, return public instruction info
void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
insn_map const *insn_map = NULL;
if (!(insn_map = lookup_insn_map(h, id)))
return;
insn->id = insn_map->mapid;
if (insn->detail) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insn_map->regs_use,
sizeof(insn_map->regs_use));
insn->detail->regs_read_count =
(uint8_t)count_positive(insn_map->regs_use);
memcpy(insn->detail->regs_write, insn_map->regs_mod,
sizeof(insn_map->regs_mod));
insn->detail->regs_write_count =
(uint8_t)count_positive(insn_map->regs_mod);
memcpy(insn->detail->groups, insn_map->groups,
sizeof(insn_map->groups));
insn->detail->groups_count =
(uint8_t)count_positive8(insn_map->groups);
#endif
}
}
#ifndef CAPSTONE_DIET
static const char *const insn_names[] = {
#include "AlphaGenCSMappingInsnName.inc"
};
// special alias insn
// static name_map alias_insn_names[] = {{0, NULL}};
#endif
const char *Alpha_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id >= ALPHA_INS_ENDING)
return NULL;
if (id < ARR_SIZE(insn_names))
return insn_names[id];
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
{ Alpha_GRP_INVALID, NULL },
{ Alpha_GRP_CALL, "call" },
{ Alpha_GRP_JUMP, "jump" },
{ Alpha_GRP_BRANCH_RELATIVE, "branch_relative" },
};
#endif
const char *Alpha_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
const char *Alpha_getRegisterName(csh handle, unsigned int id)
{
return Alpha_LLVM_getRegisterName(handle, id);
}
void Alpha_printInst(MCInst *MI, SStream *O, void *Info)
{
Alpha_LLVM_printInstruction(MI, O, Info);
}
void Alpha_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, insns, ARR_SIZE(insns));
map_implicit_reads(MI, insns);
map_implicit_writes(MI, insns);
map_groups(MI, insns);
}
bool Alpha_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info)
{
Alpha_init_cs_detail(instr);
DecodeStatus Result = Alpha_LLVM_getInstruction(
handle, code, code_len, instr, size, address, info);
Alpha_set_instr_map_data(instr);
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
#ifndef CAPSTONE_DIET
void Alpha_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_alpha *alpha = &(insn->detail->alpha);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read,
read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write,
write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < alpha->op_count; i++) {
cs_alpha_op *op = &(alpha->operands[i]);
switch ((int)op->type) {
case ALPHA_OP_REG:
if ((op->access & CS_AC_READ) &&
!arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) &&
!arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
#endif
#endif
arch/Alpha/AlphaMapping.h
+42
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CS_ALPHA_MAP_H
#define CS_ALPHA_MAP_H
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../SStream.h"
#include <capstone/capstone.h>
// unsigned int Alpha_map_insn_id(cs_struct *h, unsigned int id);
extern const insn_map *Alpha_insns;
extern const unsigned int Alpha_insn_count;
// given internal insn id, return public instruction info
void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *Alpha_insn_name(csh handle, unsigned int id);
const char *Alpha_group_name(csh handle, unsigned int id);
void Alpha_printInst(MCInst *MI, SStream *O, void *Info);
const char *Alpha_getRegisterName(csh handle, unsigned int id);
bool Alpha_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
void Alpha_init_cs_detail(MCInst *MI);
void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum);
void Alpha_set_instr_map_data(MCInst *MI);
void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
int64_t Imm);
void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg);
void Alpha_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
#endif
arch/Alpha/AlphaModule.c
+51
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "AlphaDisassembler.h"
#include "AlphaMapping.h"
#include "AlphaModule.h"
cs_err ALPHA_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
if (!mri)
return CS_ERR_MEM;
Alpha_init(mri);
ud->printer = Alpha_printInst;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = Alpha_getInstruction;
ud->post_printer = NULL;
ud->reg_name = Alpha_getRegisterName;
ud->insn_id = Alpha_get_insn_id;
ud->insn_name = Alpha_insn_name;
ud->group_name = Alpha_group_name;
#ifndef CAPSTONE_DIET
ud->reg_access = Alpha_reg_access;
#endif
ud->insn_map = Alpha_insns;
ud->insn_map_size = Alpha_insn_count;
return CS_ERR_OK;
}
cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX) {
handle->syntax = (int)value;
} else if (type == CS_OPT_MODE) {
handle->mode = (cs_mode)value;
}
return CS_ERR_OK;
}
#endif
arch/Alpha/AlphaModule.h
+12
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@@ -0,0 +1,12 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CAPSTONE_ALPHAMODULE_H
#define CAPSTONE_ALPHAMODULE_H
#include "../../utils.h"
cs_err ALPHA_global_init(cs_struct *ud);
cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif // CAPSTONE_ALPHAMODULE_H
arch/BPF/BPFConstants.h
+132
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/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
/* SPDX-License-Identifier: BSD-3 */
/* This file defines constants and macros used for parsing a BPF instruction */
#ifndef CS_BPF_CONSTANTS_H
#define CS_BPF_CONSTANTS_H
#define BPF_CLASS(code) ((code) & 0x7)
/// Instruction classes
#define BPF_CLASS_LD 0x00
#define BPF_CLASS_LDX 0x01
#define BPF_CLASS_ST 0x02
#define BPF_CLASS_STX 0x03
#define BPF_CLASS_ALU 0x04
#define BPF_CLASS_JMP 0x05
/// cBPF only
#define BPF_CLASS_RET 0x06
/// eBPF only
#define BPF_CLASS_JMP32 0x06
/// cBPF only
#define BPF_CLASS_MISC 0x07
/// eBPF only
#define BPF_CLASS_ALU64 0x07
#define BPF_OP(code) ((code) & 0xf0)
///< Types of ALU instruction
#define BPF_ALU_ADD 0x00
#define BPF_ALU_SUB 0x10
#define BPF_ALU_MUL 0x20
#define BPF_ALU_DIV 0x30
#define BPF_ALU_OR 0x40
#define BPF_ALU_AND 0x50
#define BPF_ALU_LSH 0x60
#define BPF_ALU_RSH 0x70
#define BPF_ALU_NEG 0x80
#define BPF_ALU_MOD 0x90
#define BPF_ALU_XOR 0xa0
/// eBPF only: mov reg to reg
#define BPF_ALU_MOV 0xb0
/// eBPF only: sign extending shift right
#define BPF_ALU_ARSH 0xc0
/// eBPF only: endianness conversion
#define BPF_ALU_END 0xd0
///< Types of jmp instruction
/// goto
#define BPF_JUMP_JA 0x00
/// '=='
#define BPF_JUMP_JEQ 0x10
/// unsigned '>'
#define BPF_JUMP_JGT 0x20
/// unsigned '>='
#define BPF_JUMP_JGE 0x30
/// '&'
#define BPF_JUMP_JSET 0x40
/// eBPF only: '!=' */
#define BPF_JUMP_JNE 0x50
/// eBPF only: signed '>'
#define BPF_JUMP_JSGT 0x60
/// eBPF only: signed '>='
#define BPF_JUMP_JSGE 0x70
/// eBPF only: function call
#define BPF_JUMP_CALL 0x80
/// eBPF only: exit
#define BPF_JUMP_EXIT 0x90
/// eBPF only: unsigned '<'
#define BPF_JUMP_JLT 0xa0
/// eBPF only: unsigned '<='
#define BPF_JUMP_JLE 0xb0
/// eBPF only: signed '<'
#define BPF_JUMP_JSLT 0xc0
/// eBPF only: signed '<='
#define BPF_JUMP_JSLE 0xd0
/// Types of complex atomic instructions
/// eBPF only: atomic exchange
#define BPF_ATOMIC_XCHG 0xe0
/// eBPF only: atomic compare and exchange
#define BPF_ATOMIC_CMPXCHG 0xf0
#define BPF_SRC(code) ((code) & 0x08)
/// cBPF only: for return types
#define BPF_RVAL(code) ((code) & 0x18)
/// Source operand
#define BPF_SRC_K 0x00
#define BPF_SRC_X 0x08
/// cBPF only
#define BPF_SRC_A 0x10
#define BPF_SRC_LITTLE BPF_SRC_K
#define BPF_SRC_BIG BPF_SRC_X
#define BPF_SIZE(code) ((code) & 0x18)
/// Size modifier
/// word
#define BPF_SIZE_W 0x00
/// half word
#define BPF_SIZE_H 0x08
/// byte
#define BPF_SIZE_B 0x10
/// eBPF only: double word
#define BPF_SIZE_DW 0x18
#define BPF_MODE(code) ((code) & 0xe0)
///< Mode modifier
#define BPF_MODE_IMM 0x00 ///< used for 32-bit mov in cBPF and 64-bit in eBPF
#define BPF_MODE_ABS \
0x20 ///< absolute indexing of socket buffer. eBPF only, but deprecated in new versions
#define BPF_MODE_IND \
0x40 ///< indirect indexing of socket buffer. eBPF only, but deprecated in new versions
#define BPF_MODE_MEM 0x60
/// cBPF only, reserved in eBPF
#define BPF_MODE_LEN 0x80
/// cBPF only, reserved in eBPF
#define BPF_MODE_MSH 0xa0
/// eBPF only: atomic operations. Originally BPF_MODE_XADD
#define BPF_MODE_ATOMIC 0xc0
/// eBPF only: overwrite 'src' with what was in the modified mem address before it was modified.
/// NOTE: in contrast to regular modifiers, this one is encoded in the 'imm' field, not opcode!
/// Must be used for BPF_XCHG and BPF_CMPXCHG. Optional for the other atomic operations.
#define BPF_MODE_FETCH 0x01
#define BPF_MISCOP(code) ((code) & 0x80)
/// Operation of misc
#define BPF_MISCOP_TAX 0x00
#define BPF_MISCOP_TXA 0x80
#endif
arch/BPF/BPFDisassembler.c
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/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
/* SPDX-License-Identifier: BSD-3 */
#ifdef CAPSTONE_HAS_BPF
#include <string.h>
#include <stddef.h> // offsetof macro
#include "BPFConstants.h"
#include "BPFDisassembler.h"
#include "BPFMapping.h"
#include "../../Mapping.h"
#include "../../cs_priv.h"
#include "../../utils.h"
///< Malloc bpf_internal, also checks if code_len is large enough.
static bpf_internal *alloc_bpf_internal(const size_t code_len)
{
bpf_internal *bpf;
if (code_len < 8)
return NULL;
bpf = cs_mem_malloc(sizeof(bpf_internal));
if (bpf == NULL)
return NULL;
/* default value */
bpf->insn_size = 8;
return bpf;
}
///< Fetch a cBPF structure from code
static bpf_internal *fetch_cbpf(MCInst *instr, const uint8_t *code,
const size_t code_len)
{
bpf_internal *bpf;
bpf = alloc_bpf_internal(code_len);
if (bpf == NULL)
return NULL;
bpf->op = readBytes16(instr, code);
bpf->jt = code[2];
bpf->jf = code[3];
bpf->k = readBytes32(instr, code + 4);
return bpf;
}
///< Fetch an eBPF structure from code
static bpf_internal *fetch_ebpf(MCInst *instr, const uint8_t *code,
const size_t code_len)
{
bpf_internal *bpf;
bpf = alloc_bpf_internal(code_len);
if (bpf == NULL)
return NULL;
bpf->op = (uint16_t)code[0];
bpf->dst = code[1] & 0xf;
bpf->src = (code[1] & 0xf0) >> 4;
// eBPF has one 16-byte instruction: BPF_LD | BPF_DW | BPF_IMM,
// in this case imm is combined with the next block's imm.
if (bpf->op == (BPF_CLASS_LD | BPF_SIZE_DW | BPF_MODE_IMM)) {
if (code_len < 16) {
cs_mem_free(bpf);
return NULL;
}
bpf->k = readBytes32(instr, code + 4) |
(((uint64_t)readBytes32(instr, code + 12)) << 32);
bpf->insn_size = 16;
} else {
bpf->offset = readBytes16(instr, code + 2);
bpf->k = readBytes32(instr, code + 4);
}
return bpf;
}
#define CHECK_READABLE_REG(ud, reg) \
do { \
if (!((reg) >= BPF_REG_R0 && (reg) <= BPF_REG_R10)) \
return false; \
} while (0)
#define CHECK_WRITEABLE_REG(ud, reg) \
do { \
if (!((reg) >= BPF_REG_R0 && (reg) < BPF_REG_R10)) \
return false; \
} while (0)
#define CHECK_READABLE_AND_PUSH(ud, MI, r) \
do { \
CHECK_READABLE_REG(ud, r + BPF_REG_R0); \
MCOperand_CreateReg0(MI, r + BPF_REG_R0); \
} while (0)
#define CHECK_WRITABLE_AND_PUSH(ud, MI, r) \
do { \
CHECK_WRITEABLE_REG(ud, r + BPF_REG_R0); \
MCOperand_CreateReg0(MI, r + BPF_REG_R0); \
} while (0)
static bool decodeLoad(MCInst *MI, bpf_internal *bpf)
{
if (!EBPF_MODE(MI->csh->mode)) {
/*
* +-----+-----------+--------------------+
* | ldb | [k] | [x+k] |
* | ldh | [k] | [x+k] |
* +-----+-----------+--------------------+
*/
if (BPF_SIZE(bpf->op) == BPF_SIZE_DW)
return false;
if (BPF_SIZE(bpf->op) == BPF_SIZE_B ||
BPF_SIZE(bpf->op) == BPF_SIZE_H) {
/* no ldx */
if (BPF_CLASS(bpf->op) != BPF_CLASS_LD)
return false;
/* can only be BPF_ABS and BPF_IND */
if (BPF_MODE(bpf->op) == BPF_MODE_ABS) {
MCOperand_CreateImm0(MI, bpf->k);
return true;
} else if (BPF_MODE(bpf->op) == BPF_MODE_IND) {
MCOperand_CreateReg0(MI, BPF_REG_X);
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
return false;
}
/*
* +-----+----+------+------+-----+-------+
* | ld | #k | #len | M[k] | [k] | [x+k] |
* +-----+----+------+------+-----+-------+
* | ldx | #k | #len | M[k] | 4*([k]&0xf) |
* +-----+----+------+------+-------------+
*/
switch (BPF_MODE(bpf->op)) {
default:
break;
case BPF_MODE_IMM:
MCOperand_CreateImm0(MI, bpf->k);
return true;
case BPF_MODE_LEN:
return true;
case BPF_MODE_MEM:
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
if (BPF_CLASS(bpf->op) == BPF_CLASS_LD) {
if (BPF_MODE(bpf->op) == BPF_MODE_ABS) {
MCOperand_CreateImm0(MI, bpf->k);
return true;
} else if (BPF_MODE(bpf->op) == BPF_MODE_IND) {
MCOperand_CreateReg0(MI, BPF_REG_X);
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
} else { /* LDX */
if (BPF_MODE(bpf->op) == BPF_MODE_MSH) {
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
}
return false;
}
/* eBPF mode */
/*
* - IMM: lddw dst, imm64
* - ABS: ld{w,h,b} [k]
* - IND: ld{w,h,b} [src]
* - MEM: ldx{w,h,b,dw} dst, [src+off]
*/
if (BPF_CLASS(bpf->op) == BPF_CLASS_LD) {
switch (BPF_MODE(bpf->op)) {
case BPF_MODE_IMM:
if (bpf->op !=
(BPF_CLASS_LD | BPF_SIZE_DW | BPF_MODE_IMM))
return false;
CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst);
MCOperand_CreateImm0(MI, bpf->k);
return true;
case BPF_MODE_ABS:
MCOperand_CreateImm0(MI, bpf->k);
return true;
case BPF_MODE_IND:
CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
return true;
}
return false;
}
/* LDX */
if (BPF_MODE(bpf->op) == BPF_MODE_MEM) {
CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst);
CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
MCOperand_CreateImm0(MI, bpf->offset);
return true;
}
return false;
}
static bool decodeStore(MCInst *MI, bpf_internal *bpf)
{
/* in cBPF, only BPF_ST* | BPF_MEM | BPF_W is valid
* while in eBPF:
* - BPF_STX | BPF_XADD | BPF_{W,DW}
* - BPF_ST* | BPF_MEM | BPF_{W,H,B,DW}
* are valid
*/
if (!EBPF_MODE(MI->csh->mode)) {
/* can only store to M[] */
if (bpf->op != (BPF_CLASS(bpf->op) | BPF_MODE_MEM | BPF_SIZE_W))
return false;
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
/* eBPF */
if (BPF_MODE(bpf->op) == BPF_MODE_ATOMIC) {
if (BPF_CLASS(bpf->op) != BPF_CLASS_STX)
return false;
if (BPF_SIZE(bpf->op) != BPF_SIZE_W &&
BPF_SIZE(bpf->op) != BPF_SIZE_DW)
return false;
/* xadd [dst + off], src */
CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst);
MCOperand_CreateImm0(MI, bpf->offset);
CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
return true;
}
if (BPF_MODE(bpf->op) != BPF_MODE_MEM)
return false;
/* st [dst + off], src */
CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst);
MCOperand_CreateImm0(MI, bpf->offset);
if (BPF_CLASS(bpf->op) == BPF_CLASS_ST)
MCOperand_CreateImm0(MI, bpf->k);
else
CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
return true;
}
static bool decodeALU(MCInst *MI, bpf_internal *bpf)
{
/* Set MI->Operands */
/* cBPF */
if (!EBPF_MODE(MI->csh->mode)) {
if (BPF_OP(bpf->op) > BPF_ALU_XOR)
return false;
/* cBPF's NEG has no operands */
if (BPF_OP(bpf->op) == BPF_ALU_NEG)
return true;
if (BPF_SRC(bpf->op) == BPF_SRC_K)
MCOperand_CreateImm0(MI, bpf->k);
else /* BPF_SRC_X */
MCOperand_CreateReg0(MI, BPF_REG_X);
return true;
}
/* eBPF */
if (BPF_OP(bpf->op) > BPF_ALU_END)
return false;
/* ENDian's imm must be one of 16, 32, 64 */
if (BPF_OP(bpf->op) == BPF_ALU_END) {
if (bpf->k != 16 && bpf->k != 32 && bpf->k != 64)
return false;
if (BPF_CLASS(bpf->op) == BPF_CLASS_ALU64 &&
BPF_SRC(bpf->op) != BPF_SRC_LITTLE)
return false;
}
/* - op dst, imm
* - op dst, src
* - neg dst
* - le<imm> dst
*/
/* every ALU instructions have dst op */
CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst);
/* special cases */
if (BPF_OP(bpf->op) == BPF_ALU_NEG)
return true;
if (BPF_OP(bpf->op) == BPF_ALU_END) {
/* bpf->k must be one of 16, 32, 64 */
bpf->op |= ((uint32_t)bpf->k << 4);
return true;
}
/* normal cases */
if (BPF_SRC(bpf->op) == BPF_SRC_K) {
MCOperand_CreateImm0(MI, bpf->k);
} else { /* BPF_SRC_X */
CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
}
return true;
}
static bool decodeJump(MCInst *MI, bpf_internal *bpf)
{
/* cBPF and eBPF are very different in class jump */
if (!EBPF_MODE(MI->csh->mode)) {
if (BPF_OP(bpf->op) > BPF_JUMP_JSET)
return false;
/* ja is a special case of jumps */
if (BPF_OP(bpf->op) == BPF_JUMP_JA) {
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
if (BPF_SRC(bpf->op) == BPF_SRC_K)
MCOperand_CreateImm0(MI, bpf->k);
else /* BPF_SRC_X */
MCOperand_CreateReg0(MI, BPF_REG_X);
MCOperand_CreateImm0(MI, bpf->jt);
MCOperand_CreateImm0(MI, bpf->jf);
} else {
if (BPF_OP(bpf->op) > BPF_JUMP_JSLE)
return false;
/* JMP32 has no CALL/EXIT instruction */
/* No operands for exit */
if (BPF_OP(bpf->op) == BPF_JUMP_EXIT)
return bpf->op == (BPF_CLASS_JMP | BPF_JUMP_EXIT);
if (BPF_OP(bpf->op) == BPF_JUMP_CALL) {
if (bpf->op == (BPF_CLASS_JMP | BPF_JUMP_CALL)) {
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
if (bpf->op ==
(BPF_CLASS_JMP | BPF_JUMP_CALL | BPF_SRC_X)) {
CHECK_READABLE_AND_PUSH(ud, MI, bpf->k);
return true;
}
return false;
}
/* ja is a special case of jumps */
if (BPF_OP(bpf->op) == BPF_JUMP_JA) {
if (BPF_SRC(bpf->op) != BPF_SRC_K)
return false;
if (BPF_CLASS(bpf->op) == BPF_CLASS_JMP)
MCOperand_CreateImm0(MI, bpf->offset);
else
MCOperand_CreateImm0(MI, bpf->k);
return true;
}
/* <j> dst, src, +off */
CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst);
if (BPF_SRC(bpf->op) == BPF_SRC_K)
MCOperand_CreateImm0(MI, bpf->k);
else
CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
MCOperand_CreateImm0(MI, bpf->offset);
}
return true;
}
static bool decodeReturn(MCInst *MI, bpf_internal *bpf)
{
/* Here only handles the BPF_RET class in cBPF */
switch (BPF_RVAL(bpf->op)) {
case BPF_SRC_K:
MCOperand_CreateImm0(MI, bpf->k);
return true;
case BPF_SRC_X:
MCOperand_CreateReg0(MI, BPF_REG_X);
return true;
case BPF_SRC_A:
MCOperand_CreateReg0(MI, BPF_REG_A);
return true;
}
return false;
}
static bool decodeMISC(MCInst *MI, bpf_internal *bpf)
{
uint16_t op = bpf->op ^ BPF_CLASS_MISC;
return op == BPF_MISCOP_TAX || op == BPF_MISCOP_TXA;
}
///< 1. Check if the instruction is valid
///< 2. Set MI->opcode
///< 3. Set MI->Operands
static bool getInstruction(MCInst *MI, bpf_internal *bpf)
{
cs_detail *detail;
detail = MI->flat_insn->detail;
// initialize detail
if (detail) {
memset(detail, 0, offsetof(cs_detail, bpf) + sizeof(cs_bpf));
}
MCInst_clear(MI);
switch (BPF_CLASS(bpf->op)) {
default: /* should never happen */
return false;
case BPF_CLASS_LD:
case BPF_CLASS_LDX:
return decodeLoad(MI, bpf);
case BPF_CLASS_ST:
case BPF_CLASS_STX:
return decodeStore(MI, bpf);
case BPF_CLASS_ALU:
return decodeALU(MI, bpf);
case BPF_CLASS_JMP:
return decodeJump(MI, bpf);
case BPF_CLASS_RET:
/* case BPF_CLASS_JMP32: */
if (EBPF_MODE(MI->csh->mode))
return decodeJump(MI, bpf);
else
return decodeReturn(MI, bpf);
case BPF_CLASS_MISC:
/* case BPF_CLASS_ALU64: */
if (EBPF_MODE(MI->csh->mode))
return decodeALU(MI, bpf);
else
return decodeMISC(MI, bpf);
}
}
// Check for regular load instructions
#define REG_LOAD_CASE(c) \
case BPF_SIZE_##c: \
if (BPF_CLASS(opcode) == BPF_CLASS_LD) \
return BPF_INS_LD##c; \
else \
return BPF_INS_LDX##c;
static bpf_insn op2insn_ld_cbpf(unsigned opcode)
{
switch (BPF_SIZE(opcode)) {
REG_LOAD_CASE(W);
REG_LOAD_CASE(H);
REG_LOAD_CASE(B);
REG_LOAD_CASE(DW);
}
return BPF_INS_INVALID;
}
#undef REG_LOAD_CASE
// Check for packet load instructions
#define PACKET_LOAD_CASE(c) \
case BPF_SIZE_##c: \
if (BPF_MODE(opcode) == BPF_MODE_ABS) \
return BPF_INS_LDABS##c; \
else if (BPF_MODE(opcode) == BPF_MODE_IND) \
return BPF_INS_LDIND##c; \
else \
return BPF_INS_INVALID;
static bpf_insn op2insn_ld_ebpf(unsigned opcode)
{
if (BPF_CLASS(opcode) == BPF_CLASS_LD) {
switch (BPF_SIZE(opcode)) {
PACKET_LOAD_CASE(W);
PACKET_LOAD_CASE(H);
PACKET_LOAD_CASE(B);
}
}
// If it's not a packet load instruction, it must be a regular load instruction
return op2insn_ld_cbpf(opcode);
}
#undef PACKET_LOAD_CASE
/* During parsing we already checked to make sure the size is D/DW and
* mode is STX and not ST, so we don't need to check again*/
#define ALU_CASE_REG(c) \
case BPF_ALU_##c: \
if (BPF_SIZE(opcode) == BPF_SIZE_W) \
return BPF_INS_A##c; \
else \
return BPF_INS_A##c##64;
#define ALU_CASE_FETCH(c) \
case BPF_ALU_##c | BPF_MODE_FETCH: \
if (BPF_SIZE(opcode) == BPF_SIZE_W) \
return BPF_INS_AF##c; \
else \
return BPF_INS_AF##c##64;
#define COMPLEX_CASE(c) \
case BPF_ATOMIC_##c | BPF_MODE_FETCH: \
if (BPF_SIZE(opcode) == BPF_SIZE_DW) \
return BPF_INS_A##c##64; \
else \
return BPF_INS_INVALID;
#define CASE(c) \
case BPF_SIZE_##c: \
if (BPF_CLASS(opcode) == BPF_CLASS_ST) \
return BPF_INS_ST##c; \
else \
return BPF_INS_STX##c;
static bpf_insn op2insn_st(unsigned opcode, const uint32_t imm)
{
/*
* - BPF_STX | ALU atomic operations | BPF_{W,DW}
* - BPF_STX | Complex atomic operations | BPF_{DW}
* - BPF_ST* | BPF_MEM | BPF_{W,H,B,DW}
*/
if (BPF_MODE(opcode) == BPF_MODE_ATOMIC) {
switch (imm) {
ALU_CASE_REG(ADD);
ALU_CASE_REG(OR);
ALU_CASE_REG(AND);
ALU_CASE_REG(XOR);
ALU_CASE_FETCH(ADD);
ALU_CASE_FETCH(OR);
ALU_CASE_FETCH(AND);
ALU_CASE_FETCH(XOR);
COMPLEX_CASE(XCHG);
COMPLEX_CASE(CMPXCHG);
default: // Reached if complex atomic operation is used without fetch modifier
return BPF_INS_INVALID;
}
}
/* should be BPF_MEM */
switch (BPF_SIZE(opcode)) {
CASE(W);
CASE(H);
CASE(B);
CASE(DW);
}
return BPF_INS_INVALID;
}
#undef CASE
#define CASE(c) \
case BPF_ALU_##c: \
CASE_IF(c)
#define CASE_IF(c) \
do { \
if (BPF_CLASS(opcode) == BPF_CLASS_ALU) \
return BPF_INS_##c; \
else \
return BPF_INS_##c##64; \
} while (0)
static bpf_insn op2insn_alu(unsigned opcode, const uint16_t off,
const bool is_ebpf)
{
/* Endian is a special case */
if (BPF_OP(opcode) == BPF_ALU_END) {
if (BPF_CLASS(opcode) == BPF_CLASS_ALU64) {
switch (opcode ^ BPF_CLASS_ALU64 ^ BPF_ALU_END ^
BPF_SRC_LITTLE) {
case (16 << 4):
return BPF_INS_BSWAP16;
case (32 << 4):
return BPF_INS_BSWAP32;
case (64 << 4):
return BPF_INS_BSWAP64;
default:
return BPF_INS_INVALID;
}
}
switch (opcode ^ BPF_CLASS_ALU ^ BPF_ALU_END) {
case BPF_SRC_LITTLE | (16 << 4):
return BPF_INS_LE16;
case BPF_SRC_LITTLE | (32 << 4):
return BPF_INS_LE32;
case BPF_SRC_LITTLE | (64 << 4):
return BPF_INS_LE64;
case BPF_SRC_BIG | (16 << 4):
return BPF_INS_BE16;
case BPF_SRC_BIG | (32 << 4):
return BPF_INS_BE32;
case BPF_SRC_BIG | (64 << 4):
return BPF_INS_BE64;
}
return BPF_INS_INVALID;
}
switch (BPF_OP(opcode)) {
CASE(ADD);
CASE(SUB);
CASE(MUL);
CASE(OR);
CASE(AND);
CASE(LSH);
CASE(RSH);
CASE(NEG);
CASE(XOR);
CASE(ARSH);
case BPF_ALU_DIV:
if (!is_ebpf || off == 0)
CASE_IF(DIV);
else if (off == 1)
CASE_IF(SDIV);
else
return BPF_INS_INVALID;
case BPF_ALU_MOD:
if (!is_ebpf || off == 0)
CASE_IF(MOD);
else if (off == 1)
CASE_IF(SMOD);
else
return BPF_INS_INVALID;
case BPF_ALU_MOV:
/* BPF_CLASS_ALU can have: mov, mov8s, mov16s
* BPF_CLASS_ALU64 can have: mov, mov8s, mov16s, mov32s
* */
if (off == 0)
CASE_IF(MOV);
else if (off == 8)
CASE_IF(MOVSB);
else if (off == 16)
CASE_IF(MOVSH);
else if (off == 32 && BPF_CLASS(opcode) == BPF_CLASS_ALU64)
return BPF_INS_MOVSW64;
else
return BPF_INS_INVALID;
}
return BPF_INS_INVALID;
}
#undef CASE_IF
#undef CASE
#define BPF_CALLX (BPF_CLASS_JMP | BPF_JUMP_CALL | BPF_SRC_X)
#define CASE(c) \
case BPF_JUMP_##c: \
if (BPF_CLASS(opcode) == BPF_CLASS_JMP) \
return BPF_INS_##c; \
else \
return BPF_INS_##c##32;
#define SPEC_CASE(c) \
case BPF_JUMP_##c: \
if (BPF_CLASS(opcode) == BPF_CLASS_JMP) \
return BPF_INS_##c; \
else \
return BPF_INS_INVALID;
static bpf_insn op2insn_jmp(unsigned opcode)
{
if (opcode == BPF_CALLX) {
return BPF_INS_CALLX;
}
switch (BPF_OP(opcode)) {
case BPF_JUMP_JA:
if (BPF_CLASS(opcode) == BPF_CLASS_JMP)
return BPF_INS_JA;
else
return BPF_INS_JAL;
CASE(JEQ);
CASE(JGT);
CASE(JGE);
CASE(JSET);
CASE(JNE);
CASE(JSGT);
CASE(JSGE);
SPEC_CASE(CALL);
SPEC_CASE(EXIT);
CASE(JLT);
CASE(JLE);
CASE(JSLT);
CASE(JSLE);
}
return BPF_INS_INVALID;
}
#undef SPEC_CASE
#undef CASE
#undef BPF_CALLX
#ifndef CAPSTONE_DIET
static void update_regs_access(MCInst *MI, cs_detail *detail, bpf_insn insn_id,
unsigned int opcode)
{
if (insn_id == BPF_INS_INVALID)
return;
/*
* In eBPF mode, only these instructions have implicit registers access:
* - legacy ld{w,h,b,dw} * // w: r0
* - exit // r: r0
*/
if (EBPF_MODE(MI->csh->mode)) {
switch (insn_id) {
default:
break;
case BPF_INS_LDABSW:
case BPF_INS_LDABSH:
case BPF_INS_LDABSB:
case BPF_INS_LDINDW:
case BPF_INS_LDINDH:
case BPF_INS_LDINDB:
case BPF_INS_LDDW:
if (BPF_MODE(opcode) == BPF_MODE_ABS ||
BPF_MODE(opcode) == BPF_MODE_IND)
map_add_implicit_write(MI, BPF_REG_R0);
break;
case BPF_INS_EXIT:
map_add_implicit_read(MI, BPF_REG_R0);
break;
}
return;
}
/* cBPF mode */
switch (BPF_CLASS(opcode)) {
default:
break;
case BPF_CLASS_LD:
map_add_implicit_write(MI, BPF_REG_A);
break;
case BPF_CLASS_LDX:
map_add_implicit_write(MI, BPF_REG_X);
break;
case BPF_CLASS_ST:
map_add_implicit_read(MI, BPF_REG_A);
break;
case BPF_CLASS_STX:
map_add_implicit_read(MI, BPF_REG_X);
break;
case BPF_CLASS_ALU:
map_add_implicit_read(MI, BPF_REG_A);
map_add_implicit_write(MI, BPF_REG_A);
break;
case BPF_CLASS_JMP:
if (insn_id != BPF_INS_JA) // except the unconditional jump
map_add_implicit_read(MI, BPF_REG_A);
break;
/* case BPF_CLASS_RET: */
case BPF_CLASS_MISC:
if (insn_id == BPF_INS_TAX) {
map_add_implicit_read(MI, BPF_REG_A);
map_add_implicit_write(MI, BPF_REG_X);
} else {
map_add_implicit_read(MI, BPF_REG_X);
map_add_implicit_write(MI, BPF_REG_A);
}
break;
}
}
#endif
static bool setFinalOpcode(MCInst *MI, const bpf_internal *bpf)
{
bpf_insn id = BPF_INS_INVALID;
#ifndef CAPSTONE_DIET
cs_detail *detail;
detail = get_detail(MI);
#endif
const uint16_t opcode = bpf->op;
switch (BPF_CLASS(opcode)) {
default: // will never happen
break;
case BPF_CLASS_LD:
case BPF_CLASS_LDX:
if (EBPF_MODE(MI->csh->mode))
id = op2insn_ld_ebpf(opcode);
else
id = op2insn_ld_cbpf(opcode);
add_group(MI, BPF_GRP_LOAD);
break;
case BPF_CLASS_ST:
case BPF_CLASS_STX:
id = op2insn_st(opcode, bpf->k);
add_group(MI, BPF_GRP_STORE);
break;
case BPF_CLASS_ALU:
id = op2insn_alu(opcode, bpf->offset, EBPF_MODE(MI->csh->mode));
add_group(MI, BPF_GRP_ALU);
break;
case BPF_CLASS_JMP:
id = op2insn_jmp(opcode);
#ifndef CAPSTONE_DIET
if (id == BPF_INS_CALL || id == BPF_INS_CALLX)
add_group(MI, BPF_GRP_CALL);
else if (id == BPF_INS_EXIT)
add_group(MI, BPF_GRP_RETURN);
else
add_group(MI, BPF_GRP_JUMP);
#endif
break;
case BPF_CLASS_RET:
/* case BPF_CLASS_JMP32: */
if (EBPF_MODE(MI->csh->mode)) {
id = op2insn_jmp(opcode);
add_group(MI, BPF_GRP_JUMP);
} else {
id = BPF_INS_RET;
add_group(MI, BPF_GRP_RETURN);
}
break;
// BPF_CLASS_MISC and BPF_CLASS_ALU64 have exactly same value
case BPF_CLASS_MISC:
/* case BPF_CLASS_ALU64: */
if (EBPF_MODE(MI->csh->mode)) {
// ALU64 in eBPF
id = op2insn_alu(opcode, bpf->offset, true);
add_group(MI, BPF_GRP_ALU);
} else {
if (BPF_MISCOP(opcode) == BPF_MISCOP_TXA)
id = BPF_INS_TXA;
else
id = BPF_INS_TAX;
add_group(MI, BPF_GRP_MISC);
}
break;
}
if (id == BPF_INS_INVALID)
return false;
MCInst_setOpcodePub(MI, id);
#undef PUSH_GROUP
#ifndef CAPSTONE_DIET
if (detail) {
update_regs_access(MI, detail, id, opcode);
}
#endif
return true;
}
bool BPF_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info)
{
bpf_internal *bpf;
if (EBPF_MODE(instr->csh->mode))
bpf = fetch_ebpf(instr, code, code_len);
else
bpf = fetch_cbpf(instr, code, code_len);
if (bpf == NULL)
return false;
if (!getInstruction(instr, bpf) || !setFinalOpcode(instr, bpf)) {
cs_mem_free(bpf);
return false;
}
MCInst_setOpcode(instr, bpf->op);
*size = bpf->insn_size;
cs_mem_free(bpf);
return true;
}
#endif
arch/BPF/BPFDisassembler.h
+28
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@@ -0,0 +1,28 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
#ifndef CS_BPF_DISASSEMBLER_H
#define CS_BPF_DISASSEMBLER_H
#include "../../MCInst.h"
typedef struct bpf_internal {
uint16_t op;
uint64_t k;
/* for cBPF */
uint8_t jt;
uint8_t jf;
/* for eBPF */
uint8_t dst;
uint8_t src;
uint16_t offset;
/* length of this bpf instruction */
uint8_t insn_size;
} bpf_internal;
bool BPF_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
#endif
arch/BPF/BPFInstPrinter.c
+371
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@@ -0,0 +1,371 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
/* SPDX-License-Identifier: BSD-3 */
#include <capstone/platform.h>
#include "BPFConstants.h"
#include "BPFInstPrinter.h"
#include "BPFMapping.h"
#include "../../Mapping.h"
static cs_bpf_op *expand_bpf_operands(cs_bpf *bpf)
{
assert(bpf->op_count < 3);
return &bpf->operands[bpf->op_count++];
}
static void push_op_reg(cs_bpf *bpf, bpf_op_type val, uint8_t ac_mode)
{
cs_bpf_op *op = expand_bpf_operands(bpf);
op->type = BPF_OP_REG;
op->reg = val;
op->access = ac_mode;
}
static void push_op_imm(cs_bpf *bpf, uint64_t val, const bool is_signed)
{
cs_bpf_op *op = expand_bpf_operands(bpf);
op->type = BPF_OP_IMM;
op->imm = val;
op->is_signed = is_signed;
}
static void push_op_off(cs_bpf *bpf, uint32_t val, const bool is_signed)
{
cs_bpf_op *op = expand_bpf_operands(bpf);
op->type = BPF_OP_OFF;
op->off = val;
op->is_signed = is_signed;
}
static void push_op_mem(cs_bpf *bpf, bpf_reg reg, uint32_t val,
const bool is_signed, const bool is_pkt)
{
cs_bpf_op *op = expand_bpf_operands(bpf);
op->type = BPF_OP_MEM;
op->mem.base = reg;
op->mem.disp = val;
op->is_signed = is_signed;
op->is_pkt = is_pkt;
}
static void push_op_mmem(cs_bpf *bpf, uint32_t val)
{
cs_bpf_op *op = expand_bpf_operands(bpf);
op->type = BPF_OP_MMEM;
op->mmem = val;
}
static void push_op_msh(cs_bpf *bpf, uint32_t val)
{
cs_bpf_op *op = expand_bpf_operands(bpf);
op->type = BPF_OP_MSH;
op->msh = val;
}
static void push_op_ext(cs_bpf *bpf, bpf_ext_type val)
{
cs_bpf_op *op = expand_bpf_operands(bpf);
op->type = BPF_OP_EXT;
op->ext = val;
}
static void convert_operands(MCInst *MI, cs_bpf *bpf)
{
unsigned opcode = MCInst_getOpcode(MI);
unsigned mc_op_count = MCInst_getNumOperands(MI);
MCOperand *op;
MCOperand *op2;
bpf->op_count = 0;
if (BPF_CLASS(opcode) == BPF_CLASS_LD ||
BPF_CLASS(opcode) == BPF_CLASS_LDX) {
switch (BPF_MODE(opcode)) {
case BPF_MODE_IMM:
if (EBPF_MODE(MI->csh->mode)) {
push_op_reg(bpf,
MCOperand_getReg(
MCInst_getOperand(MI, 0)),
CS_AC_WRITE);
push_op_imm(bpf,
MCOperand_getImm(
MCInst_getOperand(MI, 1)),
false);
} else {
push_op_imm(bpf,
MCOperand_getImm(
MCInst_getOperand(MI, 0)),
false);
}
break;
case BPF_MODE_ABS:
op = MCInst_getOperand(MI, 0);
push_op_mem(bpf, BPF_REG_INVALID,
(uint32_t)MCOperand_getImm(op),
EBPF_MODE(MI->csh->mode), true);
break;
case BPF_MODE_IND:
op = MCInst_getOperand(MI, 0);
if (EBPF_MODE(MI->csh->mode))
push_op_mem(bpf, MCOperand_getReg(op), 0x0,
true, true);
else {
op2 = MCInst_getOperand(MI, 1);
push_op_mem(bpf, MCOperand_getReg(op),
(uint32_t)MCOperand_getImm(op2),
false, true);
}
break;
case BPF_MODE_MEM:
if (EBPF_MODE(MI->csh->mode)) {
/* ldx{w,h,b,dw} dst, [src+off] */
push_op_reg(bpf,
MCOperand_getReg(
MCInst_getOperand(MI, 0)),
CS_AC_WRITE);
op = MCInst_getOperand(MI, 1);
op2 = MCInst_getOperand(MI, 2);
push_op_mem(bpf, MCOperand_getReg(op),
(uint32_t)MCOperand_getImm(op2),
true, false);
} else {
push_op_mmem(bpf,
(uint32_t)MCOperand_getImm(
MCInst_getOperand(MI, 0)));
}
break;
case BPF_MODE_LEN:
push_op_ext(bpf, BPF_EXT_LEN);
break;
case BPF_MODE_MSH:
op = MCInst_getOperand(MI, 0);
push_op_msh(bpf, (uint32_t)MCOperand_getImm(op));
break;
/* case BPF_MODE_XADD: // not exists */
}
return;
}
if (BPF_CLASS(opcode) == BPF_CLASS_ST ||
BPF_CLASS(opcode) == BPF_CLASS_STX) {
if (!EBPF_MODE(MI->csh->mode)) {
// cBPF has only one case - st* M[k]
push_op_mmem(bpf, (uint32_t)MCOperand_getImm(
MCInst_getOperand(MI, 0)));
return;
}
/* eBPF has two cases:
* - st [dst + off], src
* - xadd [dst + off], src
* they have same form of operands.
*/
op = MCInst_getOperand(MI, 0);
op2 = MCInst_getOperand(MI, 1);
push_op_mem(bpf, MCOperand_getReg(op),
(uint32_t)MCOperand_getImm(op2), true, false);
op = MCInst_getOperand(MI, 2);
if (MCOperand_isImm(op))
push_op_imm(bpf, MCOperand_getImm(op), false);
else if (MCOperand_isReg(op))
push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
return;
}
{
const bool is_jmp32 = EBPF_MODE(MI->csh->mode) &&
(BPF_CLASS(opcode) == BPF_CLASS_JMP32);
if (BPF_CLASS(opcode) == BPF_CLASS_JMP || is_jmp32) {
for (size_t i = 0; i < mc_op_count; i++) {
op = MCInst_getOperand(MI, i);
if (MCOperand_isImm(op)) {
/* Decide if we're using IMM or OFF here (and if OFF, then signed or unsigned):
*
* 1. any jump/jump32 + signed off (not including exit/call and ja on jump32) // eBPF
* 2. exit/call/ja + k // eBPF
* 3. ja + unsigned off // cBPF (cBPF programs can only jump forwards)
* 4. any jump {x,k}, +jt, +jf // cBPF
* */
if ((BPF_OP(opcode) == BPF_JUMP_JA &&
!is_jmp32) ||
(!EBPF_MODE(MI->csh->mode) &&
i >= 1) ||
(EBPF_MODE(MI->csh->mode) &&
i == 2))
push_op_off(
bpf,
MCOperand_getImm(op),
EBPF_MODE(
MI->csh->mode));
else
push_op_imm(
bpf,
MCOperand_getImm(op),
true);
} else if (MCOperand_isReg(op)) {
push_op_reg(bpf, MCOperand_getReg(op),
CS_AC_READ);
}
}
return;
}
}
if (!EBPF_MODE(MI->csh->mode)) {
/* In cBPF mode, all registers in operands are accessed as read */
for (size_t i = 0; i < mc_op_count; i++) {
op = MCInst_getOperand(MI, i);
if (MCOperand_isImm(op))
push_op_imm(bpf, MCOperand_getImm(op), false);
else if (MCOperand_isReg(op))
push_op_reg(bpf, MCOperand_getReg(op),
CS_AC_READ);
}
return;
}
/* remain cases are: eBPF mode && ALU */
/* if (BPF_CLASS(opcode) == BPF_CLASS_ALU || BPF_CLASS(opcode) == BPF_CLASS_ALU64) */
/* We have three types:
* 1. {l,b}e dst // dst = byteswap(dst)
* 2. neg dst // dst = -dst
* 3. <op> dst, {src_reg, imm} // dst = dst <op> src
* so we can simply check the number of operands,
* exactly one operand means we are in case 1. and 2.,
* otherwise in case 3.
*/
if (mc_op_count == 1) {
op = MCInst_getOperand(MI, 0);
push_op_reg(bpf, MCOperand_getReg(op),
CS_AC_READ | CS_AC_WRITE);
} else { // if (mc_op_count == 2)
op = MCInst_getOperand(MI, 0);
push_op_reg(bpf, MCOperand_getReg(op),
CS_AC_READ | CS_AC_WRITE);
op = MCInst_getOperand(MI, 1);
if (MCOperand_isImm(op))
push_op_imm(bpf, MCOperand_getImm(op), false);
else if (MCOperand_isReg(op))
push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
}
}
static void print_operand(MCInst *MI, struct SStream *O, const cs_bpf_op *op)
{
switch (op->type) {
case BPF_OP_INVALID:
SStream_concat(O, "invalid");
break;
case BPF_OP_REG:
SStream_concat(O, BPF_reg_name((csh)MI->csh, op->reg));
break;
case BPF_OP_IMM:
if (op->is_signed)
printInt32Hex(O, op->imm);
else
SStream_concat(O, "0x%" PRIx64, op->imm);
break;
case BPF_OP_OFF:
if (op->is_signed)
printInt16HexOffset(O, op->off);
else
SStream_concat(O, "+0x%" PRIx32, op->off);
break;
case BPF_OP_MEM:
SStream_concat(O, "[");
if (op->is_pkt && EBPF_MODE(MI->csh->mode)) {
SStream_concat(O, "skb");
if (op->mem.base != BPF_REG_INVALID)
SStream_concat(O, "+%s",
BPF_reg_name((csh)MI->csh,
op->mem.base));
else {
if (op->is_signed)
printInt32HexOffset(O, op->mem.disp);
else
SStream_concat(O, "+0x%" PRIx32,
op->mem.disp);
}
} else {
if (op->mem.base != BPF_REG_INVALID)
SStream_concat(O, BPF_reg_name((csh)MI->csh,
op->mem.base));
if (op->mem.disp != 0) {
if (op->mem.base != BPF_REG_INVALID) {
// if operation is signed, then it always uses off, not k
if (op->is_signed)
printInt16HexOffset(
O, op->mem.disp);
else if (op->is_pkt)
SStream_concat(O, "+0x%" PRIx32,
op->mem.disp);
else
SStream_concat(O, "+0x%" PRIx16,
op->mem.disp);
} else
SStream_concat(O, "0x%" PRIx32,
op->mem.disp);
}
if (op->mem.base == BPF_REG_INVALID &&
op->mem.disp == 0)
SStream_concat(O, "0x0");
}
SStream_concat(O, "]");
break;
case BPF_OP_MMEM:
SStream_concat(O, "m[0x%x]", op->mmem);
break;
case BPF_OP_MSH:
SStream_concat(O, "4*([0x%x]&0xf)", op->msh);
break;
case BPF_OP_EXT:
switch (op->ext) {
case BPF_EXT_LEN:
SStream_concat(O, "#len");
break;
}
break;
}
}
/*
* 1. human readable mnemonic
* 2. set pubOpcode (BPF_INSN_*)
* 3. set detail->bpf.operands
* */
void BPF_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
{
cs_bpf bpf = { 0 };
/* set pubOpcode as instruction id */
SStream_concat(O, BPF_insn_name((csh)MI->csh, MCInst_getOpcodePub(MI)));
convert_operands(MI, &bpf);
for (size_t i = 0; i < bpf.op_count; i++) {
if (i == 0)
SStream_concat(O, "\t");
else
SStream_concat(O, ", ");
print_operand(MI, O, &bpf.operands[i]);
}
#ifndef CAPSTONE_DIET
if (detail_is_set(MI)) {
MI->flat_insn->detail->bpf = bpf;
}
#endif
}
arch/BPF/BPFInstPrinter.h
+16
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@@ -0,0 +1,16 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
#ifndef CS_BPFINSTPRINTER_H
#define CS_BPFINSTPRINTER_H
#include <capstone/capstone.h>
#include "../../MCInst.h"
#include "../../SStream.h"
struct SStream;
void BPF_printInst(MCInst *MI, struct SStream *O, void *Info);
#endif
arch/BPF/BPFMapping.c
+238
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@@ -0,0 +1,238 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
/* SPDX-License-Identifier: BSD-3 */
#include <string.h>
#include "BPFConstants.h"
#include "BPFMapping.h"
#include "../../Mapping.h"
#include "../../utils.h"
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
{ BPF_GRP_INVALID, NULL },
{ BPF_GRP_LOAD, "load" }, { BPF_GRP_STORE, "store" },
{ BPF_GRP_ALU, "alu" }, { BPF_GRP_JUMP, "jump" },
{ BPF_GRP_CALL, "call" }, { BPF_GRP_RETURN, "return" },
{ BPF_GRP_MISC, "misc" },
};
#endif
const char *BPF_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map insn_name_maps[BPF_INS_ENDING] = {
{ BPF_INS_INVALID, NULL },
{ BPF_INS_ADD, "add" }, { BPF_INS_SUB, "sub" },
{ BPF_INS_MUL, "mul" }, { BPF_INS_DIV, "div" },
{ BPF_INS_SDIV, "sdiv" }, { BPF_INS_OR, "or" },
{ BPF_INS_AND, "and" }, { BPF_INS_LSH, "lsh" },
{ BPF_INS_RSH, "rsh" }, { BPF_INS_NEG, "neg" },
{ BPF_INS_MOD, "mod" }, { BPF_INS_SMOD, "smod" },
{ BPF_INS_XOR, "xor" }, { BPF_INS_MOV, "mov" },
{ BPF_INS_MOVSB, "movsb" }, { BPF_INS_MOVSH, "movsh" },
{ BPF_INS_ARSH, "arsh" },
{ BPF_INS_ADD64, "add64" }, { BPF_INS_SUB64, "sub64" },
{ BPF_INS_MUL64, "mul64" }, { BPF_INS_DIV64, "div64" },
{ BPF_INS_SDIV64, "sdiv64" }, { BPF_INS_OR64, "or64" },
{ BPF_INS_AND64, "and64" }, { BPF_INS_LSH64, "lsh64" },
{ BPF_INS_RSH64, "rsh64" }, { BPF_INS_NEG64, "neg64" },
{ BPF_INS_MOD64, "mod64" }, { BPF_INS_SMOD64, "smod64" },
{ BPF_INS_XOR64, "xor64" }, { BPF_INS_MOV64, "mov64" },
{ BPF_INS_MOVSB64, "movsb64" }, { BPF_INS_MOVSH64, "movsh64" },
{ BPF_INS_MOVSW64, "movsw64" }, { BPF_INS_ARSH64, "arsh64" },
{ BPF_INS_LE16, "le16" }, { BPF_INS_LE32, "le32" },
{ BPF_INS_LE64, "le64" }, { BPF_INS_BE16, "be16" },
{ BPF_INS_BE32, "be32" }, { BPF_INS_BE64, "be64" },
{ BPF_INS_BSWAP16, "bswap16" }, { BPF_INS_BSWAP32, "bswap32" },
{ BPF_INS_BSWAP64, "bswap64" },
{ BPF_INS_LDW, "ldw" }, { BPF_INS_LDH, "ldh" },
{ BPF_INS_LDB, "ldb" }, { BPF_INS_LDDW, "lddw" },
{ BPF_INS_LDXW, "ldxw" }, { BPF_INS_LDXH, "ldxh" },
{ BPF_INS_LDXB, "ldxb" }, { BPF_INS_LDXDW, "ldxdw" },
{ BPF_INS_LDABSW, "ldabsw" }, { BPF_INS_LDABSH, "ldabsh" },
{ BPF_INS_LDABSB, "ldabsb" }, { BPF_INS_LDINDW, "ldindw" },
{ BPF_INS_LDINDH, "ldindh" }, { BPF_INS_LDINDB, "ldindb" },
{ BPF_INS_STW, "stw" }, { BPF_INS_STH, "sth" },
{ BPF_INS_STB, "stb" }, { BPF_INS_STDW, "stdw" },
{ BPF_INS_STXW, "stxw" }, { BPF_INS_STXH, "stxh" },
{ BPF_INS_STXB, "stxb" }, { BPF_INS_STXDW, "stxdw" },
{ BPF_INS_XADDW, "xaddw" }, { BPF_INS_XADDDW, "xadddw" },
{ BPF_INS_JA, "ja" }, { BPF_INS_JEQ, "jeq" },
{ BPF_INS_JGT, "jgt" }, { BPF_INS_JGE, "jge" },
{ BPF_INS_JSET, "jset" }, { BPF_INS_JNE, "jne" },
{ BPF_INS_JSGT, "jsgt" }, { BPF_INS_JSGE, "jsge" },
{ BPF_INS_CALL, "call" }, { BPF_INS_CALLX, "callx" },
{ BPF_INS_EXIT, "exit" }, { BPF_INS_JLT, "jlt" },
{ BPF_INS_JLE, "jle" }, { BPF_INS_JSLT, "jslt" },
{ BPF_INS_JSLE, "jsle" },
{ BPF_INS_JAL, "jal" }, { BPF_INS_JEQ32, "jeq32" },
{ BPF_INS_JGT32, "jgt32" }, { BPF_INS_JGE32, "jge32" },
{ BPF_INS_JSET32, "jset32" }, { BPF_INS_JNE32, "jne32" },
{ BPF_INS_JSGT32, "jsgt32" }, { BPF_INS_JSGE32, "jsge32" },
{ BPF_INS_JLT32, "jlt32" }, { BPF_INS_JLE32, "jle32" },
{ BPF_INS_JSLT32, "jslt32" }, { BPF_INS_JSLE32, "jsle32" },
{ BPF_INS_RET, "ret" },
{ BPF_INS_AADD, "aadd" }, { BPF_INS_AOR, "aor" },
{ BPF_INS_AAND, "aand" }, { BPF_INS_AXOR, "axor" },
{ BPF_INS_AFADD, "afadd" }, { BPF_INS_AFOR, "afor" },
{ BPF_INS_AFAND, "afand" }, { BPF_INS_AFXOR, "afxor" },
{ BPF_INS_AXCHG64, "axchg64" }, { BPF_INS_ACMPXCHG64, "acmpxchg64" },
{ BPF_INS_AADD64, "aadd64" }, { BPF_INS_AOR64, "aor64" },
{ BPF_INS_AAND64, "aand64" }, { BPF_INS_AXOR64, "axor64" },
{ BPF_INS_AFADD64, "afadd64" }, { BPF_INS_AFOR64, "afor64" },
{ BPF_INS_AFAND64, "afand64" }, { BPF_INS_AFXOR64, "afxor64" },
{ BPF_INS_TAX, "tax" }, { BPF_INS_TXA, "txa" },
};
#endif
bool BPF_getFeature(const cs_mode mode, const cs_mode feature)
{
return (mode & feature);
}
const char *BPF_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
/* We have some special cases because 'ld' in cBPF is equivalent to 'ldw'
* in eBPF, and we don't want to see 'ldw' appears in cBPF mode.
*/
if (!EBPF_MODE(((cs_struct *)handle)->mode)) {
switch (id) {
case BPF_INS_LD:
return "ld";
case BPF_INS_LDX:
return "ldx";
case BPF_INS_ST:
return "st";
case BPF_INS_STX:
return "stx";
}
}
return id2name(insn_name_maps, ARR_SIZE(insn_name_maps), id);
#else
return NULL;
#endif
}
const char *BPF_reg_name(csh handle, unsigned int reg)
{
#ifndef CAPSTONE_DIET
if (EBPF_MODE(((cs_struct *)handle)->mode)) {
if (reg < BPF_REG_R0 || reg > BPF_REG_R10)
return NULL;
static const char reg_names[11][4] = { "r0", "r1", "r2", "r3",
"r4", "r5", "r6", "r7",
"r8", "r9", "r10" };
return reg_names[reg - BPF_REG_R0];
}
/* cBPF mode */
if (reg == BPF_REG_A)
return "a";
else if (reg == BPF_REG_X)
return "x";
else
return NULL;
#else
return NULL;
#endif
}
void BPF_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// Not used by BPF. Information is set after disassembly.
}
static void sort_and_uniq(cs_regs arr, uint8_t n, uint8_t *new_n)
{
/* arr is always a tiny (usually n < 3) array,
* a simple O(n^2) sort is efficient enough. */
size_t iMin;
size_t tmp;
/* a modified selection sort for sorting and making unique */
for (size_t j = 0; j < n; j++) {
/* arr[iMin] will be min(arr[j .. n-1]) */
iMin = j;
for (size_t i = j + 1; i < n; i++) {
if (arr[i] < arr[iMin])
iMin = i;
}
if (j != 0 && arr[iMin] == arr[j - 1]) { // duplicate ele found
arr[iMin] = arr[n - 1];
--n;
} else {
tmp = arr[iMin];
arr[iMin] = arr[j];
arr[j] = tmp;
}
}
*new_n = n;
}
void BPF_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count)
{
unsigned i;
uint8_t read_count, write_count;
const cs_bpf *bpf = &(insn->detail->bpf);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read,
read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write,
write_count * sizeof(insn->detail->regs_write[0]));
for (i = 0; i < bpf->op_count; i++) {
const cs_bpf_op *op = &(bpf->operands[i]);
switch (op->type) {
default:
break;
case BPF_OP_REG:
if (op->access & CS_AC_READ) {
regs_read[read_count] = op->reg;
read_count++;
}
if (op->access & CS_AC_WRITE) {
regs_write[write_count] = op->reg;
write_count++;
}
break;
case BPF_OP_MEM:
if (op->mem.base != BPF_REG_INVALID) {
regs_read[read_count] = op->mem.base;
read_count++;
}
break;
}
}
sort_and_uniq(regs_read, read_count, regs_read_count);
sort_and_uniq(regs_write, write_count, regs_write_count);
}
arch/BPF/BPFMapping.h
+23
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@@ -0,0 +1,23 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
#ifndef CS_BPFMAPPING_H
#define CS_BPFMAPPING_H
#include <capstone/capstone.h>
#include "../../cs_priv.h"
bool BPF_getFeature(const cs_mode mode, const cs_mode feature);
#define EBPF_MODE(mode) BPF_getFeature(mode, CS_MODE_BPF_EXTENDED)
const char *BPF_group_name(csh handle, unsigned int id);
const char *BPF_insn_name(csh handle, unsigned int id);
const char *BPF_reg_name(csh handle, unsigned int reg);
void BPF_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
void BPF_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
#endif
arch/BPF/BPFModule.c
+34
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@@ -0,0 +1,34 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
#ifdef CAPSTONE_HAS_BPF
#include "BPFDisassembler.h"
#include "BPFInstPrinter.h"
#include "BPFMapping.h"
#include "BPFModule.h"
cs_err BPF_global_init(cs_struct *ud)
{
ud->printer = BPF_printInst;
ud->reg_name = BPF_reg_name;
ud->insn_id = BPF_get_insn_id;
ud->insn_name = BPF_insn_name;
ud->group_name = BPF_group_name;
#ifndef CAPSTONE_DIET
ud->reg_access = BPF_reg_access;
#endif
ud->disasm = BPF_getInstruction;
return CS_ERR_OK;
}
cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_MODE)
handle->mode = (cs_mode)value;
return CS_ERR_OK;
}
#endif
arch/BPF/BPFModule.h
+12
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@@ -0,0 +1,12 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
#ifndef CS_BPF_MODULE_H
#define CS_BPF_MODULE_H
#include "../../utils.h"
cs_err BPF_global_init(cs_struct *ud);
cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif
arch/EVM/EVMDisassembler.c
+405
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@@ -0,0 +1,405 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh, 2018 */
/* By Andelf, 2025 */
#include <string.h>
#include <stddef.h>
#include "EVMDisassembler.h"
#include "EVMMapping.h"
static const short opcodes[256] = {
EVM_INS_STOP,
EVM_INS_ADD,
EVM_INS_MUL,
EVM_INS_SUB,
EVM_INS_DIV,
EVM_INS_SDIV,
EVM_INS_MOD,
EVM_INS_SMOD,
EVM_INS_ADDMOD,
EVM_INS_MULMOD,
EVM_INS_EXP,
EVM_INS_SIGNEXTEND,
-1,
-1,
-1,
-1,
EVM_INS_LT,
EVM_INS_GT,
EVM_INS_SLT,
EVM_INS_SGT,
EVM_INS_EQ,
EVM_INS_ISZERO,
EVM_INS_AND,
EVM_INS_OR,
EVM_INS_XOR,
EVM_INS_NOT,
EVM_INS_BYTE,
EVM_INS_SHL,
EVM_INS_SHR,
EVM_INS_SAR,
-1,
-1,
EVM_INS_SHA3,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
EVM_INS_ADDRESS,
EVM_INS_BALANCE,
EVM_INS_ORIGIN,
EVM_INS_CALLER,
EVM_INS_CALLVALUE,
EVM_INS_CALLDATALOAD,
EVM_INS_CALLDATASIZE,
EVM_INS_CALLDATACOPY,
EVM_INS_CODESIZE,
EVM_INS_CODECOPY,
EVM_INS_GASPRICE,
EVM_INS_EXTCODESIZE,
EVM_INS_EXTCODECOPY,
EVM_INS_RETURNDATASIZE,
EVM_INS_RETURNDATACOPY,
-1,
EVM_INS_BLOCKHASH,
EVM_INS_COINBASE,
EVM_INS_TIMESTAMP,
EVM_INS_NUMBER,
EVM_INS_DIFFICULTY,
EVM_INS_GASLIMIT,
EVM_INS_CHAINID,
EVM_INS_SELFBALANCE,
EVM_INS_BASEFEE,
EVM_INS_BLOBHASH,
EVM_INS_BLOBBASEFEE,
-1,
-1,
-1,
-1,
-1,
EVM_INS_POP,
EVM_INS_MLOAD,
EVM_INS_MSTORE,
EVM_INS_MSTORE8,
EVM_INS_SLOAD,
EVM_INS_SSTORE,
EVM_INS_JUMP,
EVM_INS_JUMPI,
EVM_INS_PC,
EVM_INS_MSIZE,
EVM_INS_GAS,
EVM_INS_JUMPDEST,
EVM_INS_TLOAD,
EVM_INS_TSTORE,
EVM_INS_MCOPY,
EVM_INS_PUSH0,
EVM_INS_PUSH1,
EVM_INS_PUSH2,
EVM_INS_PUSH3,
EVM_INS_PUSH4,
EVM_INS_PUSH5,
EVM_INS_PUSH6,
EVM_INS_PUSH7,
EVM_INS_PUSH8,
EVM_INS_PUSH9,
EVM_INS_PUSH10,
EVM_INS_PUSH11,
EVM_INS_PUSH12,
EVM_INS_PUSH13,
EVM_INS_PUSH14,
EVM_INS_PUSH15,
EVM_INS_PUSH16,
EVM_INS_PUSH17,
EVM_INS_PUSH18,
EVM_INS_PUSH19,
EVM_INS_PUSH20,
EVM_INS_PUSH21,
EVM_INS_PUSH22,
EVM_INS_PUSH23,
EVM_INS_PUSH24,
EVM_INS_PUSH25,
EVM_INS_PUSH26,
EVM_INS_PUSH27,
EVM_INS_PUSH28,
EVM_INS_PUSH29,
EVM_INS_PUSH30,
EVM_INS_PUSH31,
EVM_INS_PUSH32,
EVM_INS_DUP1,
EVM_INS_DUP2,
EVM_INS_DUP3,
EVM_INS_DUP4,
EVM_INS_DUP5,
EVM_INS_DUP6,
EVM_INS_DUP7,
EVM_INS_DUP8,
EVM_INS_DUP9,
EVM_INS_DUP10,
EVM_INS_DUP11,
EVM_INS_DUP12,
EVM_INS_DUP13,
EVM_INS_DUP14,
EVM_INS_DUP15,
EVM_INS_DUP16,
EVM_INS_SWAP1,
EVM_INS_SWAP2,
EVM_INS_SWAP3,
EVM_INS_SWAP4,
EVM_INS_SWAP5,
EVM_INS_SWAP6,
EVM_INS_SWAP7,
EVM_INS_SWAP8,
EVM_INS_SWAP9,
EVM_INS_SWAP10,
EVM_INS_SWAP11,
EVM_INS_SWAP12,
EVM_INS_SWAP13,
EVM_INS_SWAP14,
EVM_INS_SWAP15,
EVM_INS_SWAP16,
EVM_INS_LOG0,
EVM_INS_LOG1,
EVM_INS_LOG2,
EVM_INS_LOG3,
EVM_INS_LOG4,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
EVM_INS_CREATE,
EVM_INS_CALL,
EVM_INS_CALLCODE,
EVM_INS_RETURN,
EVM_INS_DELEGATECALL,
EVM_INS_CREATE2,
-1,
-1,
-1,
-1,
EVM_INS_STATICCALL,
-1,
-1,
EVM_INS_REVERT,
-1,
EVM_INS_SELFDESTRUCT,
};
bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *MI, uint16_t *size, uint64_t address,
void *inst_info)
{
unsigned char opcode;
if (code_len == 0)
return false;
opcode = code[0];
if (opcodes[opcode] == -1) {
// invalid opcode
return false;
}
// valid opcode
MI->address = address;
MI->OpcodePub = MI->Opcode = opcode;
if (opcode >= EVM_INS_PUSH1 && opcode <= EVM_INS_PUSH32) {
unsigned char len = (opcode - EVM_INS_PUSH1 + 1);
if (code_len < 1 + len) {
// not enough data
return false;
}
*size = 1 + len;
memcpy(MI->evm_data, code + 1, len);
} else
*size = 1;
if (MI->flat_insn->detail) {
memset(MI->flat_insn->detail, 0,
offsetof(cs_detail, evm) + sizeof(cs_evm));
EVM_get_insn_id((cs_struct *)ud, MI->flat_insn, opcode);
if (MI->flat_insn->detail->evm.pop) {
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_STACK_READ;
MI->flat_insn->detail->groups_count++;
}
if (MI->flat_insn->detail->evm.push) {
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_STACK_WRITE;
MI->flat_insn->detail->groups_count++;
}
// setup groups
switch (opcode) {
default:
break;
case EVM_INS_ADD:
case EVM_INS_MUL:
case EVM_INS_SUB:
case EVM_INS_DIV:
case EVM_INS_SDIV:
case EVM_INS_MOD:
case EVM_INS_SMOD:
case EVM_INS_ADDMOD:
case EVM_INS_MULMOD:
case EVM_INS_EXP:
case EVM_INS_SIGNEXTEND:
case EVM_INS_SHL:
case EVM_INS_SHR:
case EVM_INS_SAR:
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_MATH;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_MSTORE:
case EVM_INS_MSTORE8:
case EVM_INS_CALLDATACOPY:
case EVM_INS_CODECOPY:
case EVM_INS_EXTCODECOPY:
case EVM_INS_MCOPY:
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_MEM_WRITE;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_MLOAD:
case EVM_INS_CREATE:
case EVM_INS_CALL:
case EVM_INS_CALLCODE:
case EVM_INS_RETURN:
case EVM_INS_DELEGATECALL:
case EVM_INS_REVERT:
case EVM_INS_CREATE2:
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_MEM_READ;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_SSTORE:
case EVM_INS_TSTORE:
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_STORE_WRITE;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_SLOAD:
case EVM_INS_TLOAD:
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_STORE_READ;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_JUMP:
case EVM_INS_JUMPI:
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_JUMP;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_STOP:
case EVM_INS_SELFDESTRUCT:
MI->flat_insn->detail
->groups[MI->flat_insn->detail->groups_count] =
EVM_GRP_HALT;
MI->flat_insn->detail->groups_count++;
break;
}
}
return true;
}

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