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Squashed 'external/capstone/' content from commit e46f64fa

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git-subtree-dir: external/capstone
git-subtree-split: e46f64fadb351e9ecd05264fab26f2772feb0994
This commit is contained in:
iris
2026-05-11 11:55:07 +02:00
commit 802798ce3c
3968 changed files with 2967598 additions and 0 deletions
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include/capstone/aarch64.h
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include/capstone/alpha.h
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#ifndef CAPSTONE_ALPHA_H
#define CAPSTONE_ALPHA_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "cs_operand.h"
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
#define NUM_ALPHA_OPS 3
//> Operand type for instruction's operands
typedef enum alpha_op_type {
ALPHA_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
ALPHA_OP_REG = CS_OP_REG, ///< CS_OP_REG (Register operand).
ALPHA_OP_IMM = CS_OP_IMM, ///< CS_OP_IMM (Immediate operand).
} alpha_op_type;
// Instruction operand
typedef struct cs_alpha_op {
alpha_op_type type; // operand type
union {
unsigned int reg; // register value for REG operand
int64_t imm; // immediate value for IMM operand
};
enum cs_ac_type access;
} cs_alpha_op;
// Instruction structure
typedef struct cs_alpha {
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
cs_alpha_op operands[NUM_ALPHA_OPS]; // operands for this instruction.
} cs_alpha;
//> Alpha registers
typedef enum alpha_reg {
// generated content <AlphaGenCSRegEnum.inc> begin
// clang-format off
Alpha_REG_INVALID = 0,
Alpha_REG_F0 = 1,
Alpha_REG_F1 = 2,
Alpha_REG_F2 = 3,
Alpha_REG_F3 = 4,
Alpha_REG_F4 = 5,
Alpha_REG_F5 = 6,
Alpha_REG_F6 = 7,
Alpha_REG_F7 = 8,
Alpha_REG_F8 = 9,
Alpha_REG_F9 = 10,
Alpha_REG_F10 = 11,
Alpha_REG_F11 = 12,
Alpha_REG_F12 = 13,
Alpha_REG_F13 = 14,
Alpha_REG_F14 = 15,
Alpha_REG_F15 = 16,
Alpha_REG_F16 = 17,
Alpha_REG_F17 = 18,
Alpha_REG_F18 = 19,
Alpha_REG_F19 = 20,
Alpha_REG_F20 = 21,
Alpha_REG_F21 = 22,
Alpha_REG_F22 = 23,
Alpha_REG_F23 = 24,
Alpha_REG_F24 = 25,
Alpha_REG_F25 = 26,
Alpha_REG_F26 = 27,
Alpha_REG_F27 = 28,
Alpha_REG_F28 = 29,
Alpha_REG_F29 = 30,
Alpha_REG_F30 = 31,
Alpha_REG_F31 = 32,
Alpha_REG_R0 = 33,
Alpha_REG_R1 = 34,
Alpha_REG_R2 = 35,
Alpha_REG_R3 = 36,
Alpha_REG_R4 = 37,
Alpha_REG_R5 = 38,
Alpha_REG_R6 = 39,
Alpha_REG_R7 = 40,
Alpha_REG_R8 = 41,
Alpha_REG_R9 = 42,
Alpha_REG_R10 = 43,
Alpha_REG_R11 = 44,
Alpha_REG_R12 = 45,
Alpha_REG_R13 = 46,
Alpha_REG_R14 = 47,
Alpha_REG_R15 = 48,
Alpha_REG_R16 = 49,
Alpha_REG_R17 = 50,
Alpha_REG_R18 = 51,
Alpha_REG_R19 = 52,
Alpha_REG_R20 = 53,
Alpha_REG_R21 = 54,
Alpha_REG_R22 = 55,
Alpha_REG_R23 = 56,
Alpha_REG_R24 = 57,
Alpha_REG_R25 = 58,
Alpha_REG_R26 = 59,
Alpha_REG_R27 = 60,
Alpha_REG_R28 = 61,
Alpha_REG_R29 = 62,
Alpha_REG_R30 = 63,
Alpha_REG_R31 = 64,
Alpha_REG_ENDING, // 65
// clang-format on
// generated content <AlphaGenCSRegEnum.inc> end
} alpha_reg;
//> Alpha instruction
typedef enum alpha_insn {
// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> begin
// clang-format off
Alpha_INS_INVALID,
Alpha_INS_ADDL,
Alpha_INS_ADDQ,
Alpha_INS_ADDSsSU,
Alpha_INS_ADDTsSU,
Alpha_INS_AND,
Alpha_INS_BEQ,
Alpha_INS_BGE,
Alpha_INS_BGT,
Alpha_INS_BIC,
Alpha_INS_BIS,
Alpha_INS_BLBC,
Alpha_INS_BLBS,
Alpha_INS_BLE,
Alpha_INS_BLT,
Alpha_INS_BNE,
Alpha_INS_BR,
Alpha_INS_BSR,
Alpha_INS_CMOVEQ,
Alpha_INS_CMOVGE,
Alpha_INS_CMOVGT,
Alpha_INS_CMOVLBC,
Alpha_INS_CMOVLBS,
Alpha_INS_CMOVLE,
Alpha_INS_CMOVLT,
Alpha_INS_CMOVNE,
Alpha_INS_CMPBGE,
Alpha_INS_CMPEQ,
Alpha_INS_CMPLE,
Alpha_INS_CMPLT,
Alpha_INS_CMPTEQsSU,
Alpha_INS_CMPTLEsSU,
Alpha_INS_CMPTLTsSU,
Alpha_INS_CMPTUNsSU,
Alpha_INS_CMPULE,
Alpha_INS_CMPULT,
Alpha_INS_COND_BRANCH,
Alpha_INS_CPYSE,
Alpha_INS_CPYSN,
Alpha_INS_CPYS,
Alpha_INS_CTLZ,
Alpha_INS_CTPOP,
Alpha_INS_CTTZ,
Alpha_INS_CVTQSsSUI,
Alpha_INS_CVTQTsSUI,
Alpha_INS_CVTSTsS,
Alpha_INS_CVTTQsSVC,
Alpha_INS_CVTTSsSUI,
Alpha_INS_DIVSsSU,
Alpha_INS_DIVTsSU,
Alpha_INS_ECB,
Alpha_INS_EQV,
Alpha_INS_EXCB,
Alpha_INS_EXTBL,
Alpha_INS_EXTLH,
Alpha_INS_EXTLL,
Alpha_INS_EXTQH,
Alpha_INS_EXTQL,
Alpha_INS_EXTWH,
Alpha_INS_EXTWL,
Alpha_INS_FBEQ,
Alpha_INS_FBGE,
Alpha_INS_FBGT,
Alpha_INS_FBLE,
Alpha_INS_FBLT,
Alpha_INS_FBNE,
Alpha_INS_FCMOVEQ,
Alpha_INS_FCMOVGE,
Alpha_INS_FCMOVGT,
Alpha_INS_FCMOVLE,
Alpha_INS_FCMOVLT,
Alpha_INS_FCMOVNE,
Alpha_INS_FETCH,
Alpha_INS_FETCH_M,
Alpha_INS_FTOIS,
Alpha_INS_FTOIT,
Alpha_INS_INSBL,
Alpha_INS_INSLH,
Alpha_INS_INSLL,
Alpha_INS_INSQH,
Alpha_INS_INSQL,
Alpha_INS_INSWH,
Alpha_INS_INSWL,
Alpha_INS_ITOFS,
Alpha_INS_ITOFT,
Alpha_INS_JMP,
Alpha_INS_JSR,
Alpha_INS_JSR_COROUTINE,
Alpha_INS_LDA,
Alpha_INS_LDAH,
Alpha_INS_LDBU,
Alpha_INS_LDL,
Alpha_INS_LDL_L,
Alpha_INS_LDQ,
Alpha_INS_LDQ_L,
Alpha_INS_LDQ_U,
Alpha_INS_LDS,
Alpha_INS_LDT,
Alpha_INS_LDWU,
Alpha_INS_MB,
Alpha_INS_MSKBL,
Alpha_INS_MSKLH,
Alpha_INS_MSKLL,
Alpha_INS_MSKQH,
Alpha_INS_MSKQL,
Alpha_INS_MSKWH,
Alpha_INS_MSKWL,
Alpha_INS_MULL,
Alpha_INS_MULQ,
Alpha_INS_MULSsSU,
Alpha_INS_MULTsSU,
Alpha_INS_ORNOT,
Alpha_INS_RC,
Alpha_INS_RET,
Alpha_INS_RPCC,
Alpha_INS_RS,
Alpha_INS_S4ADDL,
Alpha_INS_S4ADDQ,
Alpha_INS_S4SUBL,
Alpha_INS_S4SUBQ,
Alpha_INS_S8ADDL,
Alpha_INS_S8ADDQ,
Alpha_INS_S8SUBL,
Alpha_INS_S8SUBQ,
Alpha_INS_SEXTB,
Alpha_INS_SEXTW,
Alpha_INS_SLL,
Alpha_INS_SQRTSsSU,
Alpha_INS_SQRTTsSU,
Alpha_INS_SRA,
Alpha_INS_SRL,
Alpha_INS_STB,
Alpha_INS_STL,
Alpha_INS_STL_C,
Alpha_INS_STQ,
Alpha_INS_STQ_C,
Alpha_INS_STQ_U,
Alpha_INS_STS,
Alpha_INS_STT,
Alpha_INS_STW,
Alpha_INS_SUBL,
Alpha_INS_SUBQ,
Alpha_INS_SUBSsSU,
Alpha_INS_SUBTsSU,
Alpha_INS_TRAPB,
Alpha_INS_UMULH,
Alpha_INS_WH64,
Alpha_INS_WH64EN,
Alpha_INS_WMB,
Alpha_INS_XOR,
Alpha_INS_ZAPNOT,
// clang-format on
// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> end
ALPHA_INS_ENDING, // <-- mark the end of the list of instructions
} alpha_insn;
//> Group of Alpha instructions
typedef enum alpha_insn_group {
Alpha_GRP_INVALID, ///< = CS_GRP_INVALID
//> Generic groups
Alpha_GRP_CALL, ///< = CS_GRP_CALL
Alpha_GRP_JUMP, ///< = CS_GRP_JUMP
Alpha_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
Alpha_GRP_ENDING, ///< = mark the end of the list of groups
} alpha_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/arc.h
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#ifndef CAPSTONE_ARC_H
#define CAPSTONE_ARC_H
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "platform.h"
#include "cs_operand.h"
/// Operand type for instruction's operands
typedef enum arc_op_type {
ARC_OP_INVALID = CS_OP_INVALID, ///< Invalid
ARC_OP_REG = CS_OP_REG, ///< Register operand
ARC_OP_IMM = CS_OP_IMM, ///< Immediate operand
} arc_op_type;
/// Instruction operand
typedef struct cs_arc_op {
arc_op_type type; //< operand type
union {
unsigned int reg; /// register value for REG operand
int64_t imm; /// immediate value for IMM operand
};
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
enum cs_ac_type access;
} cs_arc_op;
#define NUM_ARC_OPS 8
/// Instruction structure
typedef struct cs_arc {
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_arc_op operands[NUM_ARC_OPS]; ///< operands for this instruction.
} cs_arc;
/// ARC registers
typedef enum arc_reg {
// generated content <ARCGenCSRegEnum.inc> begin
// clang-format off
ARC_REG_INVALID = 0,
ARC_REG_BLINK = 1,
ARC_REG_FP = 2,
ARC_REG_GP = 3,
ARC_REG_ILINK = 4,
ARC_REG_SP = 5,
ARC_REG_R0 = 6,
ARC_REG_R1 = 7,
ARC_REG_R2 = 8,
ARC_REG_R3 = 9,
ARC_REG_R4 = 10,
ARC_REG_R5 = 11,
ARC_REG_R6 = 12,
ARC_REG_R7 = 13,
ARC_REG_R8 = 14,
ARC_REG_R9 = 15,
ARC_REG_R10 = 16,
ARC_REG_R11 = 17,
ARC_REG_R12 = 18,
ARC_REG_R13 = 19,
ARC_REG_R14 = 20,
ARC_REG_R15 = 21,
ARC_REG_R16 = 22,
ARC_REG_R17 = 23,
ARC_REG_R18 = 24,
ARC_REG_R19 = 25,
ARC_REG_R20 = 26,
ARC_REG_R21 = 27,
ARC_REG_R22 = 28,
ARC_REG_R23 = 29,
ARC_REG_R24 = 30,
ARC_REG_R25 = 31,
ARC_REG_R30 = 32,
ARC_REG_R32 = 33,
ARC_REG_R33 = 34,
ARC_REG_R34 = 35,
ARC_REG_R35 = 36,
ARC_REG_R36 = 37,
ARC_REG_R37 = 38,
ARC_REG_R38 = 39,
ARC_REG_R39 = 40,
ARC_REG_R40 = 41,
ARC_REG_R41 = 42,
ARC_REG_R42 = 43,
ARC_REG_R43 = 44,
ARC_REG_R44 = 45,
ARC_REG_R45 = 46,
ARC_REG_R46 = 47,
ARC_REG_R47 = 48,
ARC_REG_R48 = 49,
ARC_REG_R49 = 50,
ARC_REG_R50 = 51,
ARC_REG_R51 = 52,
ARC_REG_R52 = 53,
ARC_REG_R53 = 54,
ARC_REG_R54 = 55,
ARC_REG_R55 = 56,
ARC_REG_R56 = 57,
ARC_REG_R57 = 58,
ARC_REG_R58 = 59,
ARC_REG_R59 = 60,
ARC_REG_R60 = 61,
ARC_REG_R61 = 62,
ARC_REG_R62 = 63,
ARC_REG_R63 = 64,
ARC_REG_STATUS32 = 65,
ARC_REG_ENDING, // 66
// clang-format on
// generated content <ARCGenCSRegEnum.inc> end
} arc_reg;
/// ARC instruction
typedef enum arc_insn {
// generated content <ARCGenCSInsnEnum.inc> begin
// clang-format off
ARC_INS_INVALID,
ARC_INS_h,
ARC_INS_PBR,
ARC_INS_ERROR_FLS,
ARC_INS_ERROR_FFS,
ARC_INS_PLDFI,
ARC_INS_STB_FAR,
ARC_INS_STH_FAR,
ARC_INS_ST_FAR,
ARC_INS_ADC,
ARC_INS_ADC_F,
ARC_INS_ADD_S,
ARC_INS_ADD,
ARC_INS_ADD_F,
ARC_INS_AND,
ARC_INS_AND_F,
ARC_INS_ASL_S,
ARC_INS_ASL,
ARC_INS_ASL_F,
ARC_INS_ASR_S,
ARC_INS_ASR,
ARC_INS_ASR_F,
ARC_INS_BCLR_S,
ARC_INS_BEQ_S,
ARC_INS_BGE_S,
ARC_INS_BGT_S,
ARC_INS_BHI_S,
ARC_INS_BHS_S,
ARC_INS_BL,
ARC_INS_BLE_S,
ARC_INS_BLO_S,
ARC_INS_BLS_S,
ARC_INS_BLT_S,
ARC_INS_BL_S,
ARC_INS_BMSK_S,
ARC_INS_BNE_S,
ARC_INS_B,
ARC_INS_BREQ_S,
ARC_INS_BRNE_S,
ARC_INS_BR,
ARC_INS_BSET_S,
ARC_INS_BTST_S,
ARC_INS_B_S,
ARC_INS_CMP_S,
ARC_INS_CMP,
ARC_INS_LD_S,
ARC_INS_MOV_S,
ARC_INS_EI_S,
ARC_INS_ENTER_S,
ARC_INS_FFS_F,
ARC_INS_FFS,
ARC_INS_FLS_F,
ARC_INS_FLS,
ARC_INS_ABS_S,
ARC_INS_ADD1_S,
ARC_INS_ADD2_S,
ARC_INS_ADD3_S,
ARC_INS_AND_S,
ARC_INS_BIC_S,
ARC_INS_BRK_S,
ARC_INS_EXTB_S,
ARC_INS_EXTH_S,
ARC_INS_JEQ_S,
ARC_INS_JL_S,
ARC_INS_JL_S_D,
ARC_INS_JNE_S,
ARC_INS_J_S,
ARC_INS_J_S_D,
ARC_INS_LSR_S,
ARC_INS_MPYUW_S,
ARC_INS_MPYW_S,
ARC_INS_MPY_S,
ARC_INS_NEG_S,
ARC_INS_NOP_S,
ARC_INS_NOT_S,
ARC_INS_OR_S,
ARC_INS_SEXB_S,
ARC_INS_SEXH_S,
ARC_INS_SUB_S,
ARC_INS_SUB_S_NE,
ARC_INS_SWI_S,
ARC_INS_TRAP_S,
ARC_INS_TST_S,
ARC_INS_UNIMP_S,
ARC_INS_XOR_S,
ARC_INS_LDB_S,
ARC_INS_LDH_S,
ARC_INS_J,
ARC_INS_JL,
ARC_INS_JLI_S,
ARC_INS_LDB_AB,
ARC_INS_LDB_AW,
ARC_INS_LDB_DI_AB,
ARC_INS_LDB_DI_AW,
ARC_INS_LDB_DI,
ARC_INS_LDB_X_AB,
ARC_INS_LDB_X_AW,
ARC_INS_LDB_X_DI_AB,
ARC_INS_LDB_X_DI_AW,
ARC_INS_LDB_X_DI,
ARC_INS_LDB_X,
ARC_INS_LDB,
ARC_INS_LDH_AB,
ARC_INS_LDH_AW,
ARC_INS_LDH_DI_AB,
ARC_INS_LDH_DI_AW,
ARC_INS_LDH_DI,
ARC_INS_LDH_S_X,
ARC_INS_LDH_X_AB,
ARC_INS_LDH_X_AW,
ARC_INS_LDH_X_DI_AB,
ARC_INS_LDH_X_DI_AW,
ARC_INS_LDH_X_DI,
ARC_INS_LDH_X,
ARC_INS_LDH,
ARC_INS_LDI_S,
ARC_INS_LD_AB,
ARC_INS_LD_AW,
ARC_INS_LD_DI_AB,
ARC_INS_LD_DI_AW,
ARC_INS_LD_DI,
ARC_INS_LD_S_AS,
ARC_INS_LD,
ARC_INS_LEAVE_S,
ARC_INS_LR,
ARC_INS_LSR,
ARC_INS_LSR_F,
ARC_INS_MAX,
ARC_INS_MAX_F,
ARC_INS_MIN,
ARC_INS_MIN_F,
ARC_INS_MOV_S_NE,
ARC_INS_MOV,
ARC_INS_MOV_F,
ARC_INS_MPYMU,
ARC_INS_MPYMU_F,
ARC_INS_MPYM,
ARC_INS_MPYM_F,
ARC_INS_MPY,
ARC_INS_MPY_F,
ARC_INS_NORMH_F,
ARC_INS_NORMH,
ARC_INS_NORM_F,
ARC_INS_NORM,
ARC_INS_OR,
ARC_INS_OR_F,
ARC_INS_POP_S,
ARC_INS_PUSH_S,
ARC_INS_ROR,
ARC_INS_ROR_F,
ARC_INS_RSUB,
ARC_INS_RSUB_F,
ARC_INS_SBC,
ARC_INS_SBC_F,
ARC_INS_SETEQ,
ARC_INS_SETEQ_F,
ARC_INS_SEXB_F,
ARC_INS_SEXB,
ARC_INS_SEXH_F,
ARC_INS_SEXH,
ARC_INS_STB_S,
ARC_INS_ST_S,
ARC_INS_STB_AB,
ARC_INS_STB_AW,
ARC_INS_STB_DI_AB,
ARC_INS_STB_DI_AW,
ARC_INS_STB_DI,
ARC_INS_STB,
ARC_INS_STH_AB,
ARC_INS_STH_AW,
ARC_INS_STH_DI_AB,
ARC_INS_STH_DI_AW,
ARC_INS_STH_DI,
ARC_INS_STH_S,
ARC_INS_STH,
ARC_INS_ST_AB,
ARC_INS_ST_AW,
ARC_INS_ST_DI_AB,
ARC_INS_ST_DI_AW,
ARC_INS_ST_DI,
ARC_INS_ST,
ARC_INS_SUB1,
ARC_INS_SUB1_F,
ARC_INS_SUB2,
ARC_INS_SUB2_F,
ARC_INS_SUB3,
ARC_INS_SUB3_F,
ARC_INS_SUB,
ARC_INS_SUB_F,
ARC_INS_XOR,
ARC_INS_XOR_F,
// clang-format on
// generated content <ARCGenCSInsnEnum.inc> end
} arc_insn;
//> Group of ARC instructions
typedef enum arc_insn_group {
ARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
/// Generic groups
/// all jump instructions (conditional+direct+indirect jumps)
ARC_GRP_JUMP, ///< = CS_GRP_JUMP
/// all call instructions
ARC_GRP_CALL, ///< = CS_GRP_CALL
/// all return instructions
ARC_GRP_RET, ///< = CS_GRP_RET
/// all relative branching instructions
ARC_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
ARC_GRP_ENDING,
} arc_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/arm.h
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include/capstone/arm64.h
+4663
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include/capstone/bpf.h
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/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
/* SPDX-License-Identifier: BSD-3 */
#ifndef CAPSTONE_BPF_H
#define CAPSTONE_BPF_H
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
#define NUM_BPF_OPS 3
/// Operand type for instruction's operands
typedef enum bpf_op_type {
BPF_OP_INVALID = CS_OP_INVALID,
BPF_OP_REG = CS_OP_REG,
BPF_OP_IMM = CS_OP_IMM,
BPF_OP_OFF = CS_OP_SPECIAL + 0,
BPF_OP_MSH = CS_OP_SPECIAL + 1, ///< corresponds to cBPF's BPF_MSH mode
BPF_OP_EXT = CS_OP_SPECIAL + 2, ///< cBPF's extension (not eBPF)
BPF_OP_MMEM = CS_OP_MEM | (CS_OP_SPECIAL + 3), ///< M[k] in cBPF
BPF_OP_MEM = CS_OP_MEM,
} bpf_op_type;
/// BPF registers
typedef enum bpf_reg {
BPF_REG_INVALID = 0,
///< cBPF
BPF_REG_A,
BPF_REG_X,
///< eBPF
BPF_REG_R0,
BPF_REG_R1,
BPF_REG_R2,
BPF_REG_R3,
BPF_REG_R4,
BPF_REG_R5,
BPF_REG_R6,
BPF_REG_R7,
BPF_REG_R8,
BPF_REG_R9,
BPF_REG_R10,
BPF_REG_ENDING,
} bpf_reg;
/// Instruction's operand referring to memory
/// This is associated with BPF_OP_MEM operand type above
typedef struct bpf_op_mem {
bpf_reg base; ///< base register
uint32_t disp; ///< offset value
} bpf_op_mem;
typedef enum bpf_ext_type {
BPF_EXT_INVALID = 0,
BPF_EXT_LEN,
} bpf_ext_type;
/// Instruction operand
typedef struct cs_bpf_op {
bpf_op_type type;
union {
uint8_t reg; ///< register value for REG operand
uint64_t imm; ///< immediate value IMM operand
uint32_t off; ///< offset value, used in jump & call
bpf_op_mem mem; ///< base/disp value for MEM operand
/* cBPF only */
uint32_t mmem; ///< M[k] in cBPF
uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode
uint32_t ext; ///< cBPF's extension (not eBPF)
};
bool is_signed; ///< is this operand signed? It is set for memory, immediate and offset operands.
bool is_pkt; ///< is this operand referring to packet data? It is set for memory operands.
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
cs_ac_type access;
} cs_bpf_op;
/// Instruction structure
typedef struct cs_bpf {
uint8_t op_count;
cs_bpf_op operands[4];
} cs_bpf;
/// BPF instruction
typedef enum bpf_insn {
BPF_INS_INVALID = 0,
///< ALU
BPF_INS_ADD,
BPF_INS_SUB,
BPF_INS_MUL,
BPF_INS_DIV,
BPF_INS_SDIV,
BPF_INS_OR,
BPF_INS_AND,
BPF_INS_LSH,
BPF_INS_RSH,
BPF_INS_NEG,
BPF_INS_MOD,
BPF_INS_SMOD,
BPF_INS_XOR,
BPF_INS_MOV, ///< eBPF only
BPF_INS_MOVSB, ///< eBPF only
BPF_INS_MOVSH, ///< eBPF only
BPF_INS_ARSH, ///< eBPF only
///< ALU64, eBPF only
BPF_INS_ADD64,
BPF_INS_SUB64,
BPF_INS_MUL64,
BPF_INS_DIV64,
BPF_INS_SDIV64,
BPF_INS_OR64,
BPF_INS_AND64,
BPF_INS_LSH64,
BPF_INS_RSH64,
BPF_INS_NEG64,
BPF_INS_MOD64,
BPF_INS_SMOD64,
BPF_INS_XOR64,
BPF_INS_MOV64,
BPF_INS_MOVSB64,
BPF_INS_MOVSH64,
BPF_INS_MOVSW64,
BPF_INS_ARSH64,
///< Byteswap, eBPF only
BPF_INS_LE16,
BPF_INS_LE32,
BPF_INS_LE64,
BPF_INS_BE16,
BPF_INS_BE32,
BPF_INS_BE64,
BPF_INS_BSWAP16,
BPF_INS_BSWAP32,
BPF_INS_BSWAP64,
///< Load
BPF_INS_LDW, ///< eBPF only
BPF_INS_LDH,
BPF_INS_LDB,
BPF_INS_LDDW, ///< eBPF only: load 64-bit imm
BPF_INS_LDXW, ///< eBPF only
BPF_INS_LDXH, ///< eBPF only
BPF_INS_LDXB, ///< eBPF only
BPF_INS_LDXDW, ///< eBPF only
///< Packet data access
BPF_INS_LDABSW, ///< eBPF only
BPF_INS_LDABSH, ///< eBPF only
BPF_INS_LDABSB, ///< eBPF only
BPF_INS_LDINDW, ///< eBPF only
BPF_INS_LDINDH, ///< eBPF only
BPF_INS_LDINDB, ///< eBPF only
///< Store
BPF_INS_STW, ///< eBPF only
BPF_INS_STH, ///< eBPF only
BPF_INS_STB, ///< eBPF only
BPF_INS_STDW, ///< eBPF only
BPF_INS_STXW, ///< eBPF only
BPF_INS_STXH, ///< eBPF only
BPF_INS_STXB, ///< eBPF only
BPF_INS_STXDW, ///< eBPF only
BPF_INS_XADDW, ///< eBPF only
BPF_INS_XADDDW, ///< eBPF only
///< Jump
BPF_INS_JA,
BPF_INS_JEQ,
BPF_INS_JGT,
BPF_INS_JGE,
BPF_INS_JSET,
BPF_INS_JNE, ///< eBPF only
BPF_INS_JSGT, ///< eBPF only
BPF_INS_JSGE, ///< eBPF only
BPF_INS_CALL, ///< eBPF only
BPF_INS_CALLX, ///< eBPF only
BPF_INS_EXIT, ///< eBPF only
BPF_INS_JLT, ///< eBPF only
BPF_INS_JLE, ///< eBPF only
BPF_INS_JSLT, ///< eBPF only
BPF_INS_JSLE, ///< eBPF only
///< Jump32, eBPF only
BPF_INS_JAL,
BPF_INS_JEQ32,
BPF_INS_JGT32,
BPF_INS_JGE32,
BPF_INS_JSET32,
BPF_INS_JNE32,
BPF_INS_JSGT32,
BPF_INS_JSGE32,
BPF_INS_JLT32,
BPF_INS_JLE32,
BPF_INS_JSLT32,
BPF_INS_JSLE32,
///< Return, cBPF only
BPF_INS_RET,
///< Atomic, eBPF only
BPF_INS_AADD,
BPF_INS_AOR,
BPF_INS_AAND,
BPF_INS_AXOR,
BPF_INS_AFADD,
BPF_INS_AFOR,
BPF_INS_AFAND,
BPF_INS_AFXOR,
///< Atomic 64-bit, eBPF only
BPF_INS_AXCHG64,
BPF_INS_ACMPXCHG64,
BPF_INS_AADD64,
BPF_INS_AOR64,
BPF_INS_AAND64,
BPF_INS_AXOR64,
BPF_INS_AFADD64,
BPF_INS_AFOR64,
BPF_INS_AFAND64,
BPF_INS_AFXOR64,
///< Misc, cBPF only
BPF_INS_TAX,
BPF_INS_TXA,
BPF_INS_ENDING,
// alias instructions
BPF_INS_LD = BPF_INS_LDW, ///< cBPF only
BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only
BPF_INS_ST = BPF_INS_STW, ///< cBPF only
BPF_INS_STX = BPF_INS_STXW, ///< cBPF only
} bpf_insn;
/// Group of BPF instructions
typedef enum bpf_insn_group {
BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID
BPF_GRP_LOAD,
BPF_GRP_STORE,
BPF_GRP_ALU,
BPF_GRP_JUMP,
BPF_GRP_CALL, ///< eBPF only
BPF_GRP_RETURN,
BPF_GRP_MISC, ///< cBPF only
BPF_GRP_ENDING,
} bpf_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/capstone.h
+1046
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include/capstone/cs_operand.h
+49
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#ifndef CS_OPERAND_H
#define CS_OPERAND_H
/// Common instruction operand types - to be consistent across all architectures.
typedef enum cs_op_type {
CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
CS_OP_REG = 1, ///< Register operand.
CS_OP_IMM = 2, ///< Immediate operand.
CS_OP_FP = 3, ///< Floating-Point operand.
CS_OP_PRED = 4, ///< Predicate operand.
CS_OP_RESERVED_5 = 5,
CS_OP_RESERVED_6 = 6,
CS_OP_RESERVED_7 = 7,
CS_OP_RESERVED_8 = 8,
CS_OP_RESERVED_9 = 9,
CS_OP_RESERVED_10 = 10,
CS_OP_RESERVED_11 = 11,
CS_OP_RESERVED_12 = 12,
CS_OP_RESERVED_13 = 13,
CS_OP_RESERVED_14 = 14,
CS_OP_RESERVED_15 = 15,
CS_OP_SPECIAL = 0x10, ///< Special operands from archs
CS_OP_BOUND =
0x40, ///< Operand is associated with a previous operand. Used by AArch64 for SME operands.
CS_OP_MEM =
0x80, ///< Memory operand. Can be ORed with another operand type.
CS_OP_MEM_REG = CS_OP_MEM |
CS_OP_REG, ///< Memory referencing register operand.
CS_OP_MEM_IMM = CS_OP_MEM |
CS_OP_IMM, ///< Memory referencing immediate operand.
} cs_op_type;
/// Common instruction operand access types - to be consistent across all architectures.
/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
typedef enum cs_ac_type {
CS_AC_INVALID = 0, ///< Uninitialized/invalid access type.
CS_AC_READ = 1 << 0, ///< Operand read from memory or register.
CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register.
CS_AC_READ_WRITE =
CS_AC_READ |
CS_AC_WRITE, ///< Operand reads and writes from/to memory or register.
} cs_ac_type;
#endif // CS_OPERAND_H
include/capstone/evm.h
+201
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#ifndef CAPSTONE_EVM_H
#define CAPSTONE_EVM_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2018 */
/* By Andelf <andelf@gmail.com>, 2025 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
/// Instruction structure
typedef struct cs_evm {
unsigned char pop; ///< number of items popped from the stack
unsigned char push; ///< number of items pushed into the stack
unsigned int fee; ///< gas fee for the instruction
} cs_evm;
/// EVM instruction
typedef enum evm_insn {
EVM_INS_STOP = 0,
EVM_INS_ADD = 1,
EVM_INS_MUL = 2,
EVM_INS_SUB = 3,
EVM_INS_DIV = 4,
EVM_INS_SDIV = 5,
EVM_INS_MOD = 6,
EVM_INS_SMOD = 7,
EVM_INS_ADDMOD = 8,
EVM_INS_MULMOD = 9,
EVM_INS_EXP = 10,
EVM_INS_SIGNEXTEND = 11,
EVM_INS_LT = 16,
EVM_INS_GT = 17,
EVM_INS_SLT = 18,
EVM_INS_SGT = 19,
EVM_INS_EQ = 20,
EVM_INS_ISZERO = 21,
EVM_INS_AND = 22,
EVM_INS_OR = 23,
EVM_INS_XOR = 24,
EVM_INS_NOT = 25,
EVM_INS_BYTE = 26,
EVM_INS_SHL = 27,
EVM_INS_SHR = 28,
EVM_INS_SAR = 29,
EVM_INS_SHA3 = 32,
EVM_INS_ADDRESS = 48,
EVM_INS_BALANCE = 49,
EVM_INS_ORIGIN = 50,
EVM_INS_CALLER = 51,
EVM_INS_CALLVALUE = 52,
EVM_INS_CALLDATALOAD = 53,
EVM_INS_CALLDATASIZE = 54,
EVM_INS_CALLDATACOPY = 55,
EVM_INS_CODESIZE = 56,
EVM_INS_CODECOPY = 57,
EVM_INS_GASPRICE = 58,
EVM_INS_EXTCODESIZE = 59,
EVM_INS_EXTCODECOPY = 60,
EVM_INS_RETURNDATASIZE = 61,
EVM_INS_RETURNDATACOPY = 62,
EVM_INS_BLOCKHASH = 64,
EVM_INS_COINBASE = 65,
EVM_INS_TIMESTAMP = 66,
EVM_INS_NUMBER = 67,
EVM_INS_DIFFICULTY = 68,
EVM_INS_GASLIMIT = 69,
EVM_INS_CHAINID = 70,
EVM_INS_SELFBALANCE = 71,
EVM_INS_BASEFEE = 72,
EVM_INS_BLOBHASH = 73,
EVM_INS_BLOBBASEFEE = 74,
EVM_INS_POP = 80,
EVM_INS_MLOAD = 81,
EVM_INS_MSTORE = 82,
EVM_INS_MSTORE8 = 83,
EVM_INS_SLOAD = 84,
EVM_INS_SSTORE = 85,
EVM_INS_JUMP = 86,
EVM_INS_JUMPI = 87,
EVM_INS_PC = 88,
EVM_INS_MSIZE = 89,
EVM_INS_GAS = 90,
EVM_INS_JUMPDEST = 91,
EVM_INS_TLOAD = 92,
EVM_INS_TSTORE = 93,
EVM_INS_MCOPY = 94,
EVM_INS_PUSH0 = 95,
EVM_INS_PUSH1 = 96,
EVM_INS_PUSH2 = 97,
EVM_INS_PUSH3 = 98,
EVM_INS_PUSH4 = 99,
EVM_INS_PUSH5 = 100,
EVM_INS_PUSH6 = 101,
EVM_INS_PUSH7 = 102,
EVM_INS_PUSH8 = 103,
EVM_INS_PUSH9 = 104,
EVM_INS_PUSH10 = 105,
EVM_INS_PUSH11 = 106,
EVM_INS_PUSH12 = 107,
EVM_INS_PUSH13 = 108,
EVM_INS_PUSH14 = 109,
EVM_INS_PUSH15 = 110,
EVM_INS_PUSH16 = 111,
EVM_INS_PUSH17 = 112,
EVM_INS_PUSH18 = 113,
EVM_INS_PUSH19 = 114,
EVM_INS_PUSH20 = 115,
EVM_INS_PUSH21 = 116,
EVM_INS_PUSH22 = 117,
EVM_INS_PUSH23 = 118,
EVM_INS_PUSH24 = 119,
EVM_INS_PUSH25 = 120,
EVM_INS_PUSH26 = 121,
EVM_INS_PUSH27 = 122,
EVM_INS_PUSH28 = 123,
EVM_INS_PUSH29 = 124,
EVM_INS_PUSH30 = 125,
EVM_INS_PUSH31 = 126,
EVM_INS_PUSH32 = 127,
EVM_INS_DUP1 = 128,
EVM_INS_DUP2 = 129,
EVM_INS_DUP3 = 130,
EVM_INS_DUP4 = 131,
EVM_INS_DUP5 = 132,
EVM_INS_DUP6 = 133,
EVM_INS_DUP7 = 134,
EVM_INS_DUP8 = 135,
EVM_INS_DUP9 = 136,
EVM_INS_DUP10 = 137,
EVM_INS_DUP11 = 138,
EVM_INS_DUP12 = 139,
EVM_INS_DUP13 = 140,
EVM_INS_DUP14 = 141,
EVM_INS_DUP15 = 142,
EVM_INS_DUP16 = 143,
EVM_INS_SWAP1 = 144,
EVM_INS_SWAP2 = 145,
EVM_INS_SWAP3 = 146,
EVM_INS_SWAP4 = 147,
EVM_INS_SWAP5 = 148,
EVM_INS_SWAP6 = 149,
EVM_INS_SWAP7 = 150,
EVM_INS_SWAP8 = 151,
EVM_INS_SWAP9 = 152,
EVM_INS_SWAP10 = 153,
EVM_INS_SWAP11 = 154,
EVM_INS_SWAP12 = 155,
EVM_INS_SWAP13 = 156,
EVM_INS_SWAP14 = 157,
EVM_INS_SWAP15 = 158,
EVM_INS_SWAP16 = 159,
EVM_INS_LOG0 = 160,
EVM_INS_LOG1 = 161,
EVM_INS_LOG2 = 162,
EVM_INS_LOG3 = 163,
EVM_INS_LOG4 = 164,
EVM_INS_CREATE = 240,
EVM_INS_CALL = 241,
EVM_INS_CALLCODE = 242,
EVM_INS_RETURN = 243,
EVM_INS_DELEGATECALL = 244,
EVM_INS_CREATE2 = 245,
EVM_INS_STATICCALL = 250,
EVM_INS_REVERT = 253,
EVM_INS_INVALID = 254,
EVM_INS_SELFDESTRUCT = 255, // originally called SUICIDE
EVM_INS_ENDING, // <-- mark the end of the list of instructions
} evm_insn;
/// Group of EVM instructions
typedef enum evm_insn_group {
EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
EVM_GRP_JUMP, ///< all jump instructions
EVM_GRP_MATH = 8, ///< math instructions
EVM_GRP_STACK_WRITE, ///< instructions write to stack
EVM_GRP_STACK_READ, ///< instructions read from stack
EVM_GRP_MEM_WRITE, ///< instructions write to memory
EVM_GRP_MEM_READ, ///< instructions read from memory
EVM_GRP_STORE_WRITE, ///< instructions write to storage
EVM_GRP_STORE_READ, ///< instructions read from storage
EVM_GRP_HALT, ///< instructions halt execution
EVM_GRP_ENDING, ///< <-- mark the end of the list of groups
} evm_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/hppa.h
+541
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#ifndef CAPSTONE_HPPA_H
#define CAPSTONE_HPPA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cs_operand.h"
#include "platform.h"
#define NUM_HPPA_OPS 5
#define HPPA_STR_MODIFIER_LEN 8
#define HPPA_MAX_MODIFIERS_LEN 5
/// Operand type for instruction's operands
typedef enum hppa_op_type {
HPPA_OP_INVALID = CS_OP_INVALID,
HPPA_OP_REG = CS_OP_REG,
HPPA_OP_IMM = CS_OP_IMM,
HPPA_OP_IDX_REG = CS_OP_SPECIAL + 0,
HPPA_OP_DISP = CS_OP_SPECIAL + 1,
HPPA_OP_TARGET = CS_OP_SPECIAL + 2,
HPPA_OP_MEM = CS_OP_MEM,
} hppa_op_type;
//> HPPA registers
typedef enum hppa_reg {
HPPA_REG_INVALID = 0,
///> General registers
HPPA_REG_GR0,
HPPA_REG_GR1,
HPPA_REG_GR2,
HPPA_REG_GR3,
HPPA_REG_GR4,
HPPA_REG_GR5,
HPPA_REG_GR6,
HPPA_REG_GR7,
HPPA_REG_GR8,
HPPA_REG_GR9,
HPPA_REG_GR10,
HPPA_REG_GR11,
HPPA_REG_GR12,
HPPA_REG_GR13,
HPPA_REG_GR14,
HPPA_REG_GR15,
HPPA_REG_GR16,
HPPA_REG_GR17,
HPPA_REG_GR18,
HPPA_REG_GR19,
HPPA_REG_GR20,
HPPA_REG_GR21,
HPPA_REG_GR22,
HPPA_REG_GR23,
HPPA_REG_GR24,
HPPA_REG_GR25,
HPPA_REG_GR26,
HPPA_REG_GR27,
HPPA_REG_GR28,
HPPA_REG_GR29,
HPPA_REG_GR30,
HPPA_REG_GR31,
///> Floating-point registers
HPPA_REG_FPR0,
HPPA_REG_FPR1,
HPPA_REG_FPR2,
HPPA_REG_FPR3,
HPPA_REG_FPR4,
HPPA_REG_FPR5,
HPPA_REG_FPR6,
HPPA_REG_FPR7,
HPPA_REG_FPR8,
HPPA_REG_FPR9,
HPPA_REG_FPR10,
HPPA_REG_FPR11,
HPPA_REG_FPR12,
HPPA_REG_FPR13,
HPPA_REG_FPR14,
HPPA_REG_FPR15,
HPPA_REG_FPR16,
HPPA_REG_FPR17,
HPPA_REG_FPR18,
HPPA_REG_FPR19,
HPPA_REG_FPR20,
HPPA_REG_FPR21,
HPPA_REG_FPR22,
HPPA_REG_FPR23,
HPPA_REG_FPR24,
HPPA_REG_FPR25,
HPPA_REG_FPR26,
HPPA_REG_FPR27,
HPPA_REG_FPR28,
HPPA_REG_FPR29,
HPPA_REG_FPR30,
HPPA_REG_FPR31,
///> Space registers
HPPA_REG_SR0,
HPPA_REG_SR1,
HPPA_REG_SR2,
HPPA_REG_SR3,
HPPA_REG_SR4,
HPPA_REG_SR5,
HPPA_REG_SR6,
HPPA_REG_SR7,
///> Control registers
HPPA_REG_CR0,
HPPA_REG_CR1,
HPPA_REG_CR2,
HPPA_REG_CR3,
HPPA_REG_CR4,
HPPA_REG_CR5,
HPPA_REG_CR6,
HPPA_REG_CR7,
HPPA_REG_CR8,
HPPA_REG_CR9,
HPPA_REG_CR10,
HPPA_REG_CR11,
HPPA_REG_CR12,
HPPA_REG_CR13,
HPPA_REG_CR14,
HPPA_REG_CR15,
HPPA_REG_CR16,
HPPA_REG_CR17,
HPPA_REG_CR18,
HPPA_REG_CR19,
HPPA_REG_CR20,
HPPA_REG_CR21,
HPPA_REG_CR22,
HPPA_REG_CR23,
HPPA_REG_CR24,
HPPA_REG_CR25,
HPPA_REG_CR26,
HPPA_REG_CR27,
HPPA_REG_CR28,
HPPA_REG_CR29,
HPPA_REG_CR30,
HPPA_REG_CR31,
///> Special floating point exception registers
HPPA_REG_FPE0,
HPPA_REG_FPE1,
HPPA_REG_FPE2,
HPPA_REG_FPE3,
HPPA_REG_FPE4,
HPPA_REG_FPE5,
HPPA_REG_FPE6,
HPPA_REG_FPE7,
HPPA_REG_FPE8,
HPPA_REG_FPE9,
HPPA_REG_FPE10,
HPPA_REG_FPE11,
HPPA_REG_FPE12,
HPPA_REG_FPE13,
HPPA_REG_FPE14,
HPPA_REG_FPE15,
HPPA_REG_FPE16,
HPPA_REG_FPE17,
HPPA_REG_FPE18,
HPPA_REG_FPE19,
HPPA_REG_FPE20,
HPPA_REG_FPE21,
HPPA_REG_FPE22,
HPPA_REG_FPE23,
HPPA_REG_FPE24,
HPPA_REG_FPE25,
HPPA_REG_FPE26,
HPPA_REG_FPE27,
HPPA_REG_FPE28,
HPPA_REG_FPE29,
HPPA_REG_FPE30,
HPPA_REG_FPE31,
///> Single-precision floating point registers
HPPA_REG_SP_FPR0,
HPPA_REG_SP_FPR1,
HPPA_REG_SP_FPR2,
HPPA_REG_SP_FPR3,
HPPA_REG_SP_FPR4,
HPPA_REG_SP_FPR5,
HPPA_REG_SP_FPR6,
HPPA_REG_SP_FPR7,
HPPA_REG_SP_FPR8,
HPPA_REG_SP_FPR9,
HPPA_REG_SP_FPR10,
HPPA_REG_SP_FPR11,
HPPA_REG_SP_FPR12,
HPPA_REG_SP_FPR13,
HPPA_REG_SP_FPR14,
HPPA_REG_SP_FPR15,
HPPA_REG_SP_FPR16,
HPPA_REG_SP_FPR17,
HPPA_REG_SP_FPR18,
HPPA_REG_SP_FPR19,
HPPA_REG_SP_FPR20,
HPPA_REG_SP_FPR21,
HPPA_REG_SP_FPR22,
HPPA_REG_SP_FPR23,
HPPA_REG_SP_FPR24,
HPPA_REG_SP_FPR25,
HPPA_REG_SP_FPR26,
HPPA_REG_SP_FPR27,
HPPA_REG_SP_FPR28,
HPPA_REG_SP_FPR29,
HPPA_REG_SP_FPR30,
HPPA_REG_SP_FPR31,
HPPA_REG_ENDING,
} hppa_reg;
/// HPPA instruction
typedef enum hppa_insn {
HPPA_INS_INVALID = 0,
HPPA_INS_ADD,
HPPA_INS_ADDI,
HPPA_INS_ADDIO,
HPPA_INS_ADDIT,
HPPA_INS_ADDITO,
HPPA_INS_ADDB,
HPPA_INS_ADDBT,
HPPA_INS_ADDBF,
HPPA_INS_ADDIB,
HPPA_INS_ADDIBT,
HPPA_INS_ADDIBF,
HPPA_INS_ADDIL,
HPPA_INS_ADDC,
HPPA_INS_ADDCO,
HPPA_INS_ADDL,
HPPA_INS_ADDO,
HPPA_INS_AND,
HPPA_INS_ANDCM,
HPPA_INS_B,
HPPA_INS_BB,
HPPA_INS_BE,
HPPA_INS_BL,
HPPA_INS_BLE,
HPPA_INS_BLR,
HPPA_INS_BREAK,
HPPA_INS_BV,
HPPA_INS_BVB,
HPPA_INS_BVE,
HPPA_INS_CALL,
HPPA_INS_CLDD,
HPPA_INS_CLDDS,
HPPA_INS_CLDDX,
HPPA_INS_CLDW,
HPPA_INS_CLDWS,
HPPA_INS_CLDWX,
HPPA_INS_CLRBTS,
HPPA_INS_CMPB,
HPPA_INS_CMPCLR,
HPPA_INS_CMPIB,
HPPA_INS_CMPICLR,
HPPA_INS_COMB,
HPPA_INS_COMBT,
HPPA_INS_COMBF,
HPPA_INS_COMCLR,
HPPA_INS_COMIB,
HPPA_INS_COMIBT,
HPPA_INS_COMIBF,
HPPA_INS_COMICLR,
HPPA_INS_COPR,
HPPA_INS_COPY,
HPPA_INS_CSTD,
HPPA_INS_CSTDS,
HPPA_INS_CSTDX,
HPPA_INS_CSTW,
HPPA_INS_CSTWS,
HPPA_INS_CSTWX,
HPPA_INS_DCOR,
HPPA_INS_DEP,
HPPA_INS_DEPI,
HPPA_INS_DEPD,
HPPA_INS_DEPDI,
HPPA_INS_DEPW,
HPPA_INS_DEPWI,
HPPA_INS_DIAG,
HPPA_INS_DS,
HPPA_INS_EXTRD,
HPPA_INS_EXTRS,
HPPA_INS_EXTRU,
HPPA_INS_EXTRW,
HPPA_INS_FABS,
HPPA_INS_FADD,
HPPA_INS_FCMP,
HPPA_INS_FCNV,
HPPA_INS_FCNVFF,
HPPA_INS_FCNVFX,
HPPA_INS_FCNVFXT,
HPPA_INS_FCNVXF,
HPPA_INS_FCPY,
HPPA_INS_FDC,
HPPA_INS_FDCE,
HPPA_INS_FDIV,
HPPA_INS_FIC,
HPPA_INS_FICE,
HPPA_INS_FID,
HPPA_INS_FLDD,
HPPA_INS_FLDDS,
HPPA_INS_FLDDX,
HPPA_INS_FLDW,
HPPA_INS_FLDWS,
HPPA_INS_FLDWX,
HPPA_INS_FMPY,
HPPA_INS_FMPYADD,
HPPA_INS_FMPYFADD,
HPPA_INS_FMPYNFADD,
HPPA_INS_FMPYSUB,
HPPA_INS_FNEG,
HPPA_INS_FNEGABS,
HPPA_INS_FREM,
HPPA_INS_FRND,
HPPA_INS_FSQRT,
HPPA_INS_FSTD,
HPPA_INS_FSTDS,
HPPA_INS_FSTDX,
HPPA_INS_FSTW,
HPPA_INS_FSTWS,
HPPA_INS_FSTWX,
HPPA_INS_FSTQS,
HPPA_INS_FSTQX,
HPPA_INS_FSUB,
HPPA_INS_FTEST,
HPPA_INS_GATE,
HPPA_INS_GFR,
HPPA_INS_GFW,
HPPA_INS_GRSHDW,
HPPA_INS_HADD,
HPPA_INS_HAVG,
HPPA_INS_HSHL,
HPPA_INS_HSHLADD,
HPPA_INS_HSHR,
HPPA_INS_HSHRADD,
HPPA_INS_HSUB,
HPPA_INS_IDTLBA,
HPPA_INS_IDTLBP,
HPPA_INS_IDTLBT,
HPPA_INS_IDCOR,
HPPA_INS_IITLBA,
HPPA_INS_IITLBP,
HPPA_INS_IITLBT,
HPPA_INS_LCI,
HPPA_INS_LDB,
HPPA_INS_LDBS,
HPPA_INS_LDBX,
HPPA_INS_LDCD,
HPPA_INS_LDCW,
HPPA_INS_LDCWS,
HPPA_INS_LDCWX,
HPPA_INS_LDD,
HPPA_INS_LDDA,
HPPA_INS_LDH,
HPPA_INS_LDHS,
HPPA_INS_LDHX,
HPPA_INS_LDI,
HPPA_INS_LDIL,
HPPA_INS_LDO,
HPPA_INS_LDSID,
HPPA_INS_LDW,
HPPA_INS_LDWA,
HPPA_INS_LDWAS,
HPPA_INS_LDWAX,
HPPA_INS_LDWM,
HPPA_INS_LDWS,
HPPA_INS_LDWX,
HPPA_INS_LPA,
HPPA_INS_MFCPU,
HPPA_INS_MFCTL,
HPPA_INS_MFIA,
HPPA_INS_MFSP,
HPPA_INS_MIXH,
HPPA_INS_MIXW,
HPPA_INS_MOVB,
HPPA_INS_MOVIB,
HPPA_INS_MTCPU,
HPPA_INS_MTCTL,
HPPA_INS_MTSAR,
HPPA_INS_MTSARCM,
HPPA_INS_MTSM,
HPPA_INS_MTSP,
HPPA_INS_NOP,
HPPA_INS_OR,
HPPA_INS_PDC,
HPPA_INS_PDTLB,
HPPA_INS_PDTLBE,
HPPA_INS_PERMH,
HPPA_INS_PITLB,
HPPA_INS_PITLBE,
HPPA_INS_PMDIS,
HPPA_INS_PMENB,
HPPA_INS_POPBTS,
HPPA_INS_PROBE,
HPPA_INS_PROBEI,
HPPA_INS_PROBER,
HPPA_INS_PROBERI,
HPPA_INS_PROBEW,
HPPA_INS_PROBEWI,
HPPA_INS_PUSHBTS,
HPPA_INS_PUSHNOM,
HPPA_INS_RET,
HPPA_INS_RFI,
HPPA_INS_RFIR,
HPPA_INS_RSM,
HPPA_INS_SHDWGR,
HPPA_INS_SHLADD,
HPPA_INS_SH1ADD,
HPPA_INS_SH1ADDL,
HPPA_INS_SH1ADDO,
HPPA_INS_SH2ADD,
HPPA_INS_SH2ADDL,
HPPA_INS_SH2ADDO,
HPPA_INS_SH3ADD,
HPPA_INS_SH3ADDL,
HPPA_INS_SH3ADDO,
HPPA_INS_SHD,
HPPA_INS_SHRPD,
HPPA_INS_SHRPW,
HPPA_INS_SPOP0,
HPPA_INS_SPOP1,
HPPA_INS_SPOP2,
HPPA_INS_SPOP3,
HPPA_INS_SSM,
HPPA_INS_STB,
HPPA_INS_STBS,
HPPA_INS_STBY,
HPPA_INS_STBYS,
HPPA_INS_STD,
HPPA_INS_STDA,
HPPA_INS_STDBY,
HPPA_INS_STH,
HPPA_INS_STHS,
HPPA_INS_STW,
HPPA_INS_STWA,
HPPA_INS_STWAS,
HPPA_INS_STWS,
HPPA_INS_STWM,
HPPA_INS_SUB,
HPPA_INS_SUBB,
HPPA_INS_SUBBO,
HPPA_INS_SUBI,
HPPA_INS_SUBIO,
HPPA_INS_SUBO,
HPPA_INS_SUBT,
HPPA_INS_SUBTO,
HPPA_INS_SYNC,
HPPA_INS_SYNCDMA,
HPPA_INS_TOCDIS,
HPPA_INS_TOCEN,
HPPA_INS_UADDCM,
HPPA_INS_UADDCMT,
HPPA_INS_UXOR,
HPPA_INS_VDEP,
HPPA_INS_VDEPI,
HPPA_INS_VEXTRS,
HPPA_INS_VEXTRU,
HPPA_INS_VSHD,
HPPA_INS_XMPYU,
HPPA_INS_XOR,
HPPA_INS_ZDEP,
HPPA_INS_ZDEPI,
HPPA_INS_ZVDEP,
HPPA_INS_ZVDEPI,
HPPA_INS_ENDING
} hppa_insn;
/// HPPA space select operand
typedef struct hppa_mem {
hppa_reg base;
hppa_reg space;
} hppa_mem;
// Instruction operand
typedef struct cs_hppa_op {
hppa_op_type type; ///< operand type
union {
hppa_reg reg; ///< register value for REG operand
int64_t imm; ///< immediate value for IMM operand
hppa_mem mem;
};
cs_ac_type access;
} cs_hppa_op;
// Instruction structure
typedef struct cs_hppa {
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
cs_hppa_op operands[NUM_HPPA_OPS]; ///< operands for hppa instruction.
} cs_hppa;
/// HPPA modifiers type. Can be string (most of them) or int (uid, sop)
typedef enum hppa_modifier_type {
HPPA_MOD_STR = 0,
HPPA_MOD_INT = 1
} hppa_modifier_type;
/// hppa string/integer modifier
typedef struct hppa_modifier {
hppa_modifier_type type;
union {
char str_mod[HPPA_STR_MODIFIER_LEN];
uint32_t int_mod;
};
} hppa_modifier;
// Additional instruction info
typedef struct hppa_ext {
hppa_modifier
modifiers[HPPA_MAX_MODIFIERS_LEN]; ///< instruction modifiers array
uint8_t mod_num; ///< number of modifiers of current instruction
bool b_writeble; ///< true if some load/store modifier has modify base register bit
bool is_alternative; ///< true if some modifier affects instruction format
} hppa_ext;
// Group of HPPA instructions
typedef enum hppa_insn_group {
HPPA_GRP_INVALID = 0, ///< = CS_GRP_INVALID
HPPA_GRP_COMPUTATION = 128,
HPPA_GRP_MULTIMEDIA,
HPPA_GRP_MEM_REF,
HPPA_GRP_LONG_IMM,
HPPA_GRP_BRANCH,
HPPA_GRP_SYSCTRL,
HPPA_GRP_ASSIST,
HPPA_GRP_FLOAT,
HPPA_GRP_PERFMON,
HPPA_GRP_ENDING,
} hppa_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/loongarch.h
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include/capstone/m680x.h
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#ifndef CAPSTONE_M680X_H
#define CAPSTONE_M680X_H
/* Capstone Disassembly Engine */
/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
#define M680X_OPERAND_COUNT 9
/// M680X registers and special registers
typedef enum m680x_reg {
M680X_REG_INVALID = 0,
M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9
M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9
M680X_REG_E, ///< HD6309
M680X_REG_F, ///< HD6309
M680X_REG_0, ///< HD6309
M680X_REG_D, ///< M6801/3/9, HD6301/9
M680X_REG_W, ///< HD6309
M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9
M680X_REG_DP, ///< M6809/M6309
M680X_REG_MD, ///< M6309
M680X_REG_HX, ///< M6808
M680X_REG_H, ///< M6808
M680X_REG_X, ///< M6800/1/2/3/9, M6301/9
M680X_REG_Y, ///< M6809/M6309
M680X_REG_S, ///< M6809/M6309
M680X_REG_U, ///< M6809/M6309
M680X_REG_V, ///< M6309
M680X_REG_Q, ///< M6309
M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9
M680X_REG_SPC, ///< RS08
M680X_REG_TMP2, ///< CPU12
M680X_REG_TMP3, ///< CPU12
M680X_REG_ENDING, ///< <-- mark the end of the list of registers
} m680x_reg;
/// Operand type for instruction's operands
typedef enum m680x_op_type {
M680X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
M680X_OP_REGISTER = CS_OP_REG, ///< = Register operand.
M680X_OP_IMMEDIATE = CS_OP_IMM, ///< = Immediate operand.
// = Indexed addressing operand.
M680X_OP_INDEXED = CS_OP_SPECIAL + 0,
// = Extended addressing operand.
M680X_OP_EXTENDED = CS_OP_SPECIAL + 1,
M680X_OP_DIRECT = CS_OP_SPECIAL + 2, ///< = Direct addressing operand.
// = Relative addressing operand.
M680X_OP_RELATIVE = CS_OP_SPECIAL + 3,
// = constant operand (Displayed as number only).
// Used e.g. for a bit index or page number.
M680X_OP_CONSTANT = CS_OP_SPECIAL + 4,
} m680x_op_type;
// Supported bit values for mem.idx.offset_bits
#define M680X_OFFSET_NONE 0
#define M680X_OFFSET_BITS_5 5
#define M680X_OFFSET_BITS_8 8
#define M680X_OFFSET_BITS_9 9
#define M680X_OFFSET_BITS_16 16
// Supported bit flags for mem.idx.flags
// These flags can be combined
#define M680X_IDX_INDIRECT 1
#define M680X_IDX_NO_COMMA 2
#define M680X_IDX_POST_INC_DEC 4
/// Instruction's operand referring to indexed addressing
typedef struct m680x_op_idx {
m680x_reg base_reg; ///< base register (or M680X_REG_INVALID if
///< irrelevant)
m680x_reg offset_reg; ///< offset register (or M680X_REG_INVALID if
///< irrelevant)
int16_t offset; ///< 5-,8- or 16-bit offset. See also offset_bits.
uint16_t offset_addr; ///< = offset addr. if base_reg == M680X_REG_PC.
///< calculated as offset + PC
uint8_t offset_bits; ///< offset width in bits for indexed addressing
int8_t inc_dec; ///< inc. or dec. value:
///< 0: no inc-/decrement
///< 1 .. 8: increment by 1 .. 8
///< -1 .. -8: decrement by 1 .. 8
///< if flag M680X_IDX_POST_INC_DEC set it is post
///< inc-/decrement otherwise pre inc-/decrement
uint8_t flags; ///< 8-bit flags (see above)
} m680x_op_idx;
/// Instruction's memory operand referring to relative addressing (Bcc/LBcc)
typedef struct m680x_op_rel {
uint16_t address; ///< The absolute address.
///< calculated as PC + offset. PC is the first
///< address after the instruction.
int16_t offset; ///< the offset/displacement value
} m680x_op_rel;
/// Instruction's operand referring to extended addressing
typedef struct m680x_op_ext {
uint16_t address; ///< The absolute address
bool indirect; ///< true if extended indirect addressing
} m680x_op_ext;
/// Instruction operand
typedef struct cs_m680x_op {
m680x_op_type type;
union {
int32_t imm; ///< immediate value for IMM operand
m680x_reg reg; ///< register value for REG operand
m680x_op_idx idx; ///< Indexed addressing operand
m680x_op_rel rel; ///< Relative address. operand (Bcc/LBcc)
m680x_op_ext ext; ///< Extended address
uint8_t direct_addr; ///<</ Direct address (lower 8-bit)
uint8_t const_val; ///< constant value (bit index, page nr.)
};
uint8_t size; ///< size of this operand (in bytes)
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET
cs_ac_type access;
} cs_m680x_op;
/// Group of M680X instructions
typedef enum m680x_group_type {
M680X_GRP_INVALID = 0, /// = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
M680X_GRP_JUMP, ///< = CS_GRP_JUMP
// all call instructions
M680X_GRP_CALL, ///< = CS_GRP_CALL
// all return instructions
M680X_GRP_RET, ///< = CS_GRP_RET
// all interrupt instructions (int+syscall)
M680X_GRP_INT, ///< = CS_GRP_INT
// all interrupt return instructions
M680X_GRP_IRET, ///< = CS_GRP_IRET
// all privileged instructions
M680X_GRP_PRIV, ///< = CS_GRP_PRIVILEDGE; not used
// all relative branching instructions
M680X_GRP_BRAREL, ///< = CS_GRP_BRANCH_RELATIVE
// Architecture-specific groups
M680X_GRP_ENDING, // <-- mark the end of the list of groups
} m680x_group_type;
// M680X instruction flags:
/// The first (register) operand is part of the
/// instruction mnemonic
#define M680X_FIRST_OP_IN_MNEM 1
/// The second (register) operand is part of the
/// instruction mnemonic
#define M680X_SECOND_OP_IN_MNEM 2
/// The M680X instruction and its operands
typedef struct cs_m680x {
uint8_t flags; ///< See: M680X instruction flags
uint8_t op_count; ///< number of operands for the instruction or 0
cs_m680x_op operands[M680X_OPERAND_COUNT]; ///< operands for this insn.
} cs_m680x;
/// M680X instruction IDs
typedef enum m680x_insn {
M680X_INS_INVLD = 0,
M680X_INS_ABA, ///< M6800/1/2/3
M680X_INS_ABX,
M680X_INS_ABY,
M680X_INS_ADC,
M680X_INS_ADCA,
M680X_INS_ADCB,
M680X_INS_ADCD,
M680X_INS_ADCR,
M680X_INS_ADD,
M680X_INS_ADDA,
M680X_INS_ADDB,
M680X_INS_ADDD,
M680X_INS_ADDE,
M680X_INS_ADDF,
M680X_INS_ADDR,
M680X_INS_ADDW,
M680X_INS_ADDX, ///< HCS12X
M680X_INS_ADDY, ///< HCS12X
M680X_INS_ADED, ///< HCS12X
M680X_INS_ADEX, ///< HCS12X
M680X_INS_ADEY, ///< HCS12X
M680X_INS_AIM,
M680X_INS_AIS,
M680X_INS_AIX,
M680X_INS_AND,
M680X_INS_ANDA,
M680X_INS_ANDB,
M680X_INS_ANDX, ///< HCS12X
M680X_INS_ANDY, ///< HCS12X
M680X_INS_ANDCC,
M680X_INS_ANDD,
M680X_INS_ANDR,
M680X_INS_ASL,
M680X_INS_ASLA,
M680X_INS_ASLB,
M680X_INS_ASLD, ///< or LSLD
M680X_INS_ASLW, ///< HCS12X
M680X_INS_ASLX, ///< HCS12X
M680X_INS_ASLY, ///< HCS12X
M680X_INS_ASR,
M680X_INS_ASRA,
M680X_INS_ASRB,
M680X_INS_ASRD,
M680X_INS_ASRW, ///< HCS12X
M680X_INS_ASRX,
M680X_INS_ASRY, ///< HCS12X
M680X_INS_BAND,
M680X_INS_BCC, ///< or BHS
M680X_INS_BCLR,
M680X_INS_BCS, ///< or BLO
M680X_INS_BEOR,
M680X_INS_BEQ,
M680X_INS_BGE,
M680X_INS_BGND,
M680X_INS_BGT,
M680X_INS_BHCC,
M680X_INS_BHCS,
M680X_INS_BHI,
M680X_INS_BIAND,
M680X_INS_BIEOR,
M680X_INS_BIH,
M680X_INS_BIL,
M680X_INS_BIOR,
M680X_INS_BIT,
M680X_INS_BITA,
M680X_INS_BITB,
M680X_INS_BITD,
M680X_INS_BITMD,
M680X_INS_BITX, ///< HCS12X
M680X_INS_BITY, ///< HCS12X
M680X_INS_BLE,
M680X_INS_BLS,
M680X_INS_BLT,
M680X_INS_BMC,
M680X_INS_BMI,
M680X_INS_BMS,
M680X_INS_BNE,
M680X_INS_BOR,
M680X_INS_BPL,
M680X_INS_BRCLR,
M680X_INS_BRSET,
M680X_INS_BRA,
M680X_INS_BRN,
M680X_INS_BSET,
M680X_INS_BSR,
M680X_INS_BTAS, ///< HCS12X
M680X_INS_BVC,
M680X_INS_BVS,
M680X_INS_CALL,
M680X_INS_CBA, ///< M6800/1/2/3
M680X_INS_CBEQ,
M680X_INS_CBEQA,
M680X_INS_CBEQX,
M680X_INS_CLC, ///< M6800/1/2/3
M680X_INS_CLI, ///< M6800/1/2/3
M680X_INS_CLR,
M680X_INS_CLRA,
M680X_INS_CLRB,
M680X_INS_CLRD,
M680X_INS_CLRE,
M680X_INS_CLRF,
M680X_INS_CLRH,
M680X_INS_CLRW,
M680X_INS_CLRX,
M680X_INS_CLRY,
M680X_INS_CLV, ///< M6800/1/2/3
M680X_INS_CMP,
M680X_INS_CMPA,
M680X_INS_CMPB,
M680X_INS_CMPD,
M680X_INS_CMPE,
M680X_INS_CMPF,
M680X_INS_CMPR,
M680X_INS_CMPS,
M680X_INS_CMPU,
M680X_INS_CMPW,
M680X_INS_CMPX,
M680X_INS_CMPY,
M680X_INS_COM,
M680X_INS_COMA,
M680X_INS_COMB,
M680X_INS_COMD,
M680X_INS_COME,
M680X_INS_COMF,
M680X_INS_COMW,
M680X_INS_COMX,
M680X_INS_COMY,
M680X_INS_CPD,
M680X_INS_CPED, ///< HCS12X
M680X_INS_CPES, ///< HCS12X
M680X_INS_CPEX, ///< HCS12X
M680X_INS_CPEY, ///< HCS12X
M680X_INS_CPHX,
M680X_INS_CPS,
M680X_INS_CPX, ///< M6800/1/2/3
M680X_INS_CPY,
M680X_INS_CWAI,
M680X_INS_DAA,
M680X_INS_DBEQ,
M680X_INS_DBNE,
M680X_INS_DBNZ,
M680X_INS_DBNZA,
M680X_INS_DBNZX,
M680X_INS_DEC,
M680X_INS_DECA,
M680X_INS_DECB,
M680X_INS_DECD,
M680X_INS_DECE,
M680X_INS_DECF,
M680X_INS_DECW,
M680X_INS_DECX,
M680X_INS_DECY,
M680X_INS_DES, ///< M6800/1/2/3
M680X_INS_DEX, ///< M6800/1/2/3
M680X_INS_DEY,
M680X_INS_DIV,
M680X_INS_DIVD,
M680X_INS_DIVQ,
M680X_INS_EDIV,
M680X_INS_EDIVS,
M680X_INS_EIM,
M680X_INS_EMACS,
M680X_INS_EMAXD,
M680X_INS_EMAXM,
M680X_INS_EMIND,
M680X_INS_EMINM,
M680X_INS_EMUL,
M680X_INS_EMULS,
M680X_INS_EOR,
M680X_INS_EORA,
M680X_INS_EORB,
M680X_INS_EORD,
M680X_INS_EORR,
M680X_INS_EORX, ///< HCS12X
M680X_INS_EORY, ///< HCS12X
M680X_INS_ETBL,
M680X_INS_EXG,
M680X_INS_FDIV,
M680X_INS_GLDAA, ///< HCS12X
M680X_INS_GLDAB, ///< HCS12X
M680X_INS_GLDD, ///< HCS12X
M680X_INS_GLDS, ///< HCS12X
M680X_INS_GLDX, ///< HCS12X
M680X_INS_GLDY, ///< HCS12X
M680X_INS_GSTAA, ///< HCS12X
M680X_INS_GSTAB, ///< HCS12X
M680X_INS_GSTD, ///< HCS12X
M680X_INS_GSTS, ///< HCS12X
M680X_INS_GSTX, ///< HCS12X
M680X_INS_GSTY, ///< HCS12X
M680X_INS_IBEQ,
M680X_INS_IBNE,
M680X_INS_IDIV,
M680X_INS_IDIVS,
M680X_INS_ILLGL,
M680X_INS_INC,
M680X_INS_INCA,
M680X_INS_INCB,
M680X_INS_INCD,
M680X_INS_INCE,
M680X_INS_INCF,
M680X_INS_INCW,
M680X_INS_INCX,
M680X_INS_INCY,
M680X_INS_INS, ///< M6800/1/2/3
M680X_INS_INX, ///< M6800/1/2/3
M680X_INS_INY,
M680X_INS_JMP,
M680X_INS_JSR,
M680X_INS_LBCC, ///< or LBHS
M680X_INS_LBCS, ///< or LBLO
M680X_INS_LBEQ,
M680X_INS_LBGE,
M680X_INS_LBGT,
M680X_INS_LBHI,
M680X_INS_LBLE,
M680X_INS_LBLS,
M680X_INS_LBLT,
M680X_INS_LBMI,
M680X_INS_LBNE,
M680X_INS_LBPL,
M680X_INS_LBRA,
M680X_INS_LBRN,
M680X_INS_LBSR,
M680X_INS_LBVC,
M680X_INS_LBVS,
M680X_INS_LDA,
M680X_INS_LDAA, ///< M6800/1/2/3
M680X_INS_LDAB, ///< M6800/1/2/3
M680X_INS_LDB,
M680X_INS_LDBT,
M680X_INS_LDD,
M680X_INS_LDE,
M680X_INS_LDF,
M680X_INS_LDHX,
M680X_INS_LDMD,
M680X_INS_LDQ,
M680X_INS_LDS,
M680X_INS_LDU,
M680X_INS_LDW,
M680X_INS_LDX,
M680X_INS_LDY,
M680X_INS_LEAS,
M680X_INS_LEAU,
M680X_INS_LEAX,
M680X_INS_LEAY,
M680X_INS_LSL,
M680X_INS_LSLA,
M680X_INS_LSLB,
M680X_INS_LSLD,
M680X_INS_LSLX,
M680X_INS_LSR,
M680X_INS_LSRA,
M680X_INS_LSRB,
M680X_INS_LSRD, ///< or ASRD
M680X_INS_LSRW,
M680X_INS_LSRX,
M680X_INS_LSRY,
M680X_INS_MAXA,
M680X_INS_MAXM,
M680X_INS_MEM,
M680X_INS_MINA,
M680X_INS_MINM,
M680X_INS_MOV,
M680X_INS_MOVB,
M680X_INS_MOVW,
M680X_INS_MUL,
M680X_INS_MULD,
M680X_INS_NEG,
M680X_INS_NEGA,
M680X_INS_NEGB,
M680X_INS_NEGD,
M680X_INS_NEGW, ///< HCS12X
M680X_INS_NEGX,
M680X_INS_NEGY, ///< HCS12X
M680X_INS_NOP,
M680X_INS_NSA,
M680X_INS_OIM,
M680X_INS_ORA,
M680X_INS_ORAA, ///< M6800/1/2/3
M680X_INS_ORAB, ///< M6800/1/2/3
M680X_INS_ORB,
M680X_INS_ORCC,
M680X_INS_ORD,
M680X_INS_ORR,
M680X_INS_ORX, ///< HCS12X
M680X_INS_ORY, ///< HCS12X
M680X_INS_PSHA, ///< M6800/1/2/3
M680X_INS_PSHB, ///< M6800/1/2/3
M680X_INS_PSHC,
M680X_INS_PSHCW, ///< HCS12X
M680X_INS_PSHD,
M680X_INS_PSHH,
M680X_INS_PSHS,
M680X_INS_PSHSW,
M680X_INS_PSHU,
M680X_INS_PSHUW,
M680X_INS_PSHX, ///< M6800/1/2/3
M680X_INS_PSHY,
M680X_INS_PULA, ///< M6800/1/2/3
M680X_INS_PULB, ///< M6800/1/2/3
M680X_INS_PULC,
M680X_INS_PULCW, ///< HCS12X
M680X_INS_PULD,
M680X_INS_PULH,
M680X_INS_PULS,
M680X_INS_PULSW,
M680X_INS_PULU,
M680X_INS_PULUW,
M680X_INS_PULX, ///< M6800/1/2/3
M680X_INS_PULY,
M680X_INS_REV,
M680X_INS_REVW,
M680X_INS_ROL,
M680X_INS_ROLA,
M680X_INS_ROLB,
M680X_INS_ROLD,
M680X_INS_ROLW,
M680X_INS_ROLX,
M680X_INS_ROLY,
M680X_INS_ROR,
M680X_INS_RORA,
M680X_INS_RORB,
M680X_INS_RORD,
M680X_INS_RORW,
M680X_INS_RORX,
M680X_INS_RORY,
M680X_INS_RSP,
M680X_INS_RTC,
M680X_INS_RTI,
M680X_INS_RTS,
M680X_INS_SBA, ///< M6800/1/2/3
M680X_INS_SBC,
M680X_INS_SBCA,
M680X_INS_SBCB,
M680X_INS_SBCD,
M680X_INS_SBCR,
M680X_INS_SBED, ///< HCS12X
M680X_INS_SBEX, ///< HCS12X
M680X_INS_SBEY, ///< HCS12X
M680X_INS_SEC,
M680X_INS_SEI,
M680X_INS_SEV,
M680X_INS_SEX,
M680X_INS_SEXW,
M680X_INS_SHA, ///< RS08
M680X_INS_SLA, ///< RS08
M680X_INS_SLP,
M680X_INS_STA,
M680X_INS_STAA, ///< M6800/1/2/3
M680X_INS_STAB, ///< M6800/1/2/3
M680X_INS_STB,
M680X_INS_STBT,
M680X_INS_STD,
M680X_INS_STE,
M680X_INS_STF,
M680X_INS_STOP,
M680X_INS_STHX,
M680X_INS_STQ,
M680X_INS_STS,
M680X_INS_STU,
M680X_INS_STW,
M680X_INS_STX,
M680X_INS_STY,
M680X_INS_SUB,
M680X_INS_SUBA,
M680X_INS_SUBB,
M680X_INS_SUBD,
M680X_INS_SUBE,
M680X_INS_SUBF,
M680X_INS_SUBR,
M680X_INS_SUBW,
M680X_INS_SUBX, ///< HCS12X
M680X_INS_SUBY, ///< HCS12X
M680X_INS_SWI,
M680X_INS_SWI2,
M680X_INS_SWI3,
M680X_INS_SYNC,
M680X_INS_SYS, ///< HCS12X
M680X_INS_TAB, ///< M6800/1/2/3
M680X_INS_TAP, ///< M6800/1/2/3
M680X_INS_TAX,
M680X_INS_TBA, ///< M6800/1/2/3
M680X_INS_TBEQ,
M680X_INS_TBL,
M680X_INS_TBNE,
M680X_INS_TEST,
M680X_INS_TFM,
M680X_INS_TFR,
M680X_INS_TIM,
M680X_INS_TPA, ///< M6800/1/2/3
M680X_INS_TRAP,
M680X_INS_TST,
M680X_INS_TSTA,
M680X_INS_TSTB,
M680X_INS_TSTD,
M680X_INS_TSTE,
M680X_INS_TSTF,
M680X_INS_TSTW,
M680X_INS_TSTX,
M680X_INS_TSTY,
M680X_INS_TSX, ///< M6800/1/2/3
M680X_INS_TSY,
M680X_INS_TXA,
M680X_INS_TXS, ///< M6800/1/2/3
M680X_INS_TYS,
M680X_INS_WAI, ///< M6800/1/2/3
M680X_INS_WAIT,
M680X_INS_WAV,
M680X_INS_WAVR,
M680X_INS_XGDX, ///< HD6301
M680X_INS_XGDY,
M680X_INS_ENDING, // <-- mark the end of the list of instructions
} m680x_insn;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/m68k.h
+638
View File
@@ -0,0 +1,638 @@
#ifndef CAPSTONE_M68K_H
#define CAPSTONE_M68K_H
/* Capstone Disassembly Engine */
/* By Daniel Collin <daniel@collin.com>, 2015-2016 */
#ifdef __cplusplus
extern "C" {
#endif
#include "cs_operand.h"
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
#define M68K_OPERAND_COUNT 4
/// M68K registers and special registers
typedef enum m68k_reg {
M68K_REG_INVALID = 0,
M68K_REG_D0,
M68K_REG_D1,
M68K_REG_D2,
M68K_REG_D3,
M68K_REG_D4,
M68K_REG_D5,
M68K_REG_D6,
M68K_REG_D7,
M68K_REG_A0,
M68K_REG_A1,
M68K_REG_A2,
M68K_REG_A3,
M68K_REG_A4,
M68K_REG_A5,
M68K_REG_A6,
M68K_REG_A7,
M68K_REG_FP0,
M68K_REG_FP1,
M68K_REG_FP2,
M68K_REG_FP3,
M68K_REG_FP4,
M68K_REG_FP5,
M68K_REG_FP6,
M68K_REG_FP7,
M68K_REG_PC,
M68K_REG_SR,
M68K_REG_CCR,
M68K_REG_SFC,
M68K_REG_DFC,
M68K_REG_USP,
M68K_REG_VBR,
M68K_REG_CACR,
M68K_REG_CAAR,
M68K_REG_MSP,
M68K_REG_ISP,
M68K_REG_TC,
M68K_REG_ITT0,
M68K_REG_ITT1,
M68K_REG_DTT0,
M68K_REG_DTT1,
M68K_REG_MMUSR,
M68K_REG_URP,
M68K_REG_SRP,
M68K_REG_FPCR,
M68K_REG_FPSR,
M68K_REG_FPIAR,
M68K_REG_TT0,
M68K_REG_TT1,
M68K_REG_CRP,
M68K_REG_ENDING, // <-- mark the end of the list of registers
} m68k_reg;
/// M68K Addressing Modes
typedef enum m68k_address_mode {
M68K_AM_NONE = 0, ///< No address mode.
M68K_AM_REG_DIRECT_DATA, ///< Register Direct - Data
M68K_AM_REG_DIRECT_ADDR, ///< Register Direct - Address
M68K_AM_REGI_ADDR, ///< Register Indirect - Address
M68K_AM_REGI_ADDR_POST_INC, ///< Register Indirect - Address with Postincrement
M68K_AM_REGI_ADDR_PRE_DEC, ///< Register Indirect - Address with Predecrement
M68K_AM_REGI_ADDR_DISP, ///< Register Indirect - Address with Displacement
M68K_AM_AREGI_INDEX_8_BIT_DISP, ///< Address Register Indirect With Index- 8-bit displacement
M68K_AM_AREGI_INDEX_BASE_DISP, ///< Address Register Indirect With Index- Base displacement
M68K_AM_MEMI_POST_INDEX, ///< Memory indirect - Postindex
M68K_AM_MEMI_PRE_INDEX, ///< Memory indirect - Preindex
M68K_AM_PCI_DISP, ///< Program Counter Indirect - with Displacement
M68K_AM_PCI_INDEX_8_BIT_DISP, ///< Program Counter Indirect with Index - with 8-Bit Displacement
M68K_AM_PCI_INDEX_BASE_DISP, ///< Program Counter Indirect with Index - with Base Displacement
M68K_AM_PC_MEMI_POST_INDEX, ///< Program Counter Memory Indirect - Postindexed
M68K_AM_PC_MEMI_PRE_INDEX, ///< Program Counter Memory Indirect - Preindexed
M68K_AM_ABSOLUTE_DATA_SHORT, ///< Absolute Data Addressing - Short
M68K_AM_ABSOLUTE_DATA_LONG, ///< Absolute Data Addressing - Long
M68K_AM_IMMEDIATE, ///< Immediate value
M68K_AM_BRANCH_DISPLACEMENT, ///< Address as displacement from (PC+2) used by branches
} m68k_address_mode;
/// Operand type for instruction's operands
typedef enum m68k_op_type {
M68K_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
M68K_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
M68K_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
// single precision Floating-Point operand
M68K_OP_FP_SINGLE = CS_OP_SPECIAL + 0,
// double precision Floating-Point operand
M68K_OP_FP_DOUBLE = CS_OP_SPECIAL + 1,
M68K_OP_REG_BITS = CS_OP_SPECIAL + 2, ///< Register bits move
// Register pair in the same op (upper 4 bits for first reg, lower for second)
M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3,
M68K_OP_BR_DISP = CS_OP_SPECIAL + 4, ///< Branch displacement
M68K_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} m68k_op_type;
/// Instruction's operand referring to memory
/// This is associated with M68K_OP_MEM operand type above
typedef struct m68k_op_mem {
m68k_reg base_reg; ///< base register (or M68K_REG_INVALID if irrelevant)
m68k_reg index_reg; ///< index register (or M68K_REG_INVALID if irrelevant)
m68k_reg in_base_reg; ///< indirect base register (or M68K_REG_INVALID if irrelevant)
int32_t in_disp; ///< indirect displacement
int32_t out_disp; ///< outer displacement
int16_t disp; ///< displacement value
uint8_t scale; ///< scale for index register
uint8_t bitfield; ///< set to true if the two values below should be used
uint8_t width; ///< bitfield width (bf* insns): static 1-32, or register-encoded (see M68K_BF_*)
uint8_t offset; ///< bitfield offset (bf* insns): static 0-31, or register-encoded (see M68K_BF_*)
uint8_t index_size; ///< 0 = word, 1 = long
uint8_t in_disp_size; ///< 0 = word, 1 = long
uint8_t out_disp_size; ///< 0 = word, 1 = long
uint8_t disp_size; ///< 0 = byte, 1 = word
} m68k_op_mem;
/// Bitfield offset/width helpers for m68k_op_mem.
/// When bitfield is true, offset and width hold either a static value
/// or an encoded data-register number (bit 7 set).
#define M68K_BF_REG_FLAG 0x80
#define M68K_BF_IS_REG(v) ((v) & M68K_BF_REG_FLAG)
#define M68K_BF_REG_NUM(v) ((v) & 7)
/// Operand type for instruction's operands
typedef enum m68k_op_br_disp_size {
M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
M68K_OP_BR_DISP_SIZE_BYTE = 1, ///< signed 8-bit displacement
M68K_OP_BR_DISP_SIZE_WORD = 2, ///< signed 16-bit displacement
M68K_OP_BR_DISP_SIZE_LONG = 4, ///< signed 32-bit displacement
} m68k_op_br_disp_size;
typedef struct m68k_op_br_disp {
int32_t disp; ///< displacement value
uint8_t disp_size; ///< Size from m68k_op_br_disp_size type above
} m68k_op_br_disp;
/// Register pair in one operand.
typedef struct cs_m68k_op_reg_pair {
m68k_reg reg_0;
m68k_reg reg_1;
} cs_m68k_op_reg_pair;
/// Instruction operand
typedef struct cs_m68k_op {
union {
uint64_t imm; ///< immediate value for IMM operand
double dimm; ///< double imm
float simm; ///< float imm
m68k_reg reg; ///< register value for REG operand
cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand
};
m68k_op_mem mem; ///< data when operand is targeting memory
m68k_op_br_disp br_disp; ///< data when operand is a branch displacement
uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)
m68k_op_type type;
m68k_address_mode address_mode; ///< M68K addressing mode for this op
} cs_m68k_op;
/// Operation size of the CPU instructions
typedef enum m68k_cpu_size {
M68K_CPU_SIZE_NONE = 0, ///< unsized or unspecified
M68K_CPU_SIZE_BYTE = 1, ///< 1 byte in size
M68K_CPU_SIZE_WORD = 2, ///< 2 bytes in size
M68K_CPU_SIZE_LONG = 4, ///< 4 bytes in size
} m68k_cpu_size;
/// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)
typedef enum m68k_fpu_size {
M68K_FPU_SIZE_NONE = 0, ///< unsized like fsave/frestore
M68K_FPU_SIZE_SINGLE = 4, ///< 4 byte in size (single float)
M68K_FPU_SIZE_DOUBLE = 8, ///< 8 byte in size (double)
M68K_FPU_SIZE_EXTENDED = 12, ///< 12 byte in size (extended real format)
} m68k_fpu_size;
/// Type of size that is being used for the current instruction
typedef enum m68k_size_type {
M68K_SIZE_TYPE_INVALID = 0,
M68K_SIZE_TYPE_CPU,
M68K_SIZE_TYPE_FPU,
} m68k_size_type;
/// Operation size of the current instruction (NOT the actually size of instruction)
typedef struct m68k_op_size {
m68k_size_type type;
union {
m68k_cpu_size cpu_size;
m68k_fpu_size fpu_size;
};
} m68k_op_size;
/// The M68K instruction and its operands
typedef struct cs_m68k {
// Number of operands of this instruction or 0 when instruction has no operand.
cs_m68k_op
operands[M68K_OPERAND_COUNT]; ///< operands for this instruction.
m68k_op_size
op_size; ///< size of data operand works on in bytes (.b, .w, .l, etc)
uint8_t op_count; ///< number of operands for the instruction
} cs_m68k;
/// M68K instruction
typedef enum m68k_insn {
M68K_INS_INVALID = 0,
M68K_INS_ABCD,
M68K_INS_ADD,
M68K_INS_ADDA,
M68K_INS_ADDI,
M68K_INS_ADDQ,
M68K_INS_ADDX,
M68K_INS_AND,
M68K_INS_ANDI,
M68K_INS_ASL,
M68K_INS_ASR,
M68K_INS_BHS,
M68K_INS_BLO,
M68K_INS_BHI,
M68K_INS_BLS,
M68K_INS_BCC,
M68K_INS_BCS,
M68K_INS_BNE,
M68K_INS_BEQ,
M68K_INS_BVC,
M68K_INS_BVS,
M68K_INS_BPL,
M68K_INS_BMI,
M68K_INS_BGE,
M68K_INS_BLT,
M68K_INS_BGT,
M68K_INS_BLE,
M68K_INS_BRA,
M68K_INS_BSR,
M68K_INS_BCHG,
M68K_INS_BCLR,
M68K_INS_BSET,
M68K_INS_BTST,
M68K_INS_BFCHG,
M68K_INS_BFCLR,
M68K_INS_BFEXTS,
M68K_INS_BFEXTU,
M68K_INS_BFFFO,
M68K_INS_BFINS,
M68K_INS_BFSET,
M68K_INS_BFTST,
M68K_INS_BKPT,
M68K_INS_CALLM,
M68K_INS_CAS,
M68K_INS_CAS2,
M68K_INS_CHK,
M68K_INS_CHK2,
M68K_INS_CLR,
M68K_INS_CMP,
M68K_INS_CMPA,
M68K_INS_CMPI,
M68K_INS_CMPM,
M68K_INS_CMP2,
M68K_INS_CINVL,
M68K_INS_CINVP,
M68K_INS_CINVA,
M68K_INS_CPUSHL,
M68K_INS_CPUSHP,
M68K_INS_CPUSHA,
M68K_INS_DBT,
M68K_INS_DBF,
M68K_INS_DBHI,
M68K_INS_DBLS,
M68K_INS_DBCC,
M68K_INS_DBCS,
M68K_INS_DBNE,
M68K_INS_DBEQ,
M68K_INS_DBVC,
M68K_INS_DBVS,
M68K_INS_DBPL,
M68K_INS_DBMI,
M68K_INS_DBGE,
M68K_INS_DBLT,
M68K_INS_DBGT,
M68K_INS_DBLE,
M68K_INS_DBRA,
M68K_INS_DIVS,
M68K_INS_DIVSL,
M68K_INS_DIVU,
M68K_INS_DIVUL,
M68K_INS_EOR,
M68K_INS_EORI,
M68K_INS_EXG,
M68K_INS_EXT,
M68K_INS_EXTB,
M68K_INS_FABS,
M68K_INS_FSABS,
M68K_INS_FDABS,
M68K_INS_FACOS,
M68K_INS_FADD,
M68K_INS_FSADD,
M68K_INS_FDADD,
M68K_INS_FASIN,
M68K_INS_FATAN,
M68K_INS_FATANH,
M68K_INS_FBF,
M68K_INS_FBEQ,
M68K_INS_FBOGT,
M68K_INS_FBOGE,
M68K_INS_FBOLT,
M68K_INS_FBOLE,
M68K_INS_FBOGL,
M68K_INS_FBOR,
M68K_INS_FBUN,
M68K_INS_FBUEQ,
M68K_INS_FBUGT,
M68K_INS_FBUGE,
M68K_INS_FBULT,
M68K_INS_FBULE,
M68K_INS_FBNE,
M68K_INS_FBT,
M68K_INS_FBSF,
M68K_INS_FBSEQ,
M68K_INS_FBGT,
M68K_INS_FBGE,
M68K_INS_FBLT,
M68K_INS_FBLE,
M68K_INS_FBGL,
M68K_INS_FBGLE,
M68K_INS_FBNGLE,
M68K_INS_FBNGL,
M68K_INS_FBNLE,
M68K_INS_FBNLT,
M68K_INS_FBNGE,
M68K_INS_FBNGT,
M68K_INS_FBSNE,
M68K_INS_FBST,
M68K_INS_FCMP,
M68K_INS_FCOS,
M68K_INS_FCOSH,
M68K_INS_FDBF,
M68K_INS_FDBEQ,
M68K_INS_FDBOGT,
M68K_INS_FDBOGE,
M68K_INS_FDBOLT,
M68K_INS_FDBOLE,
M68K_INS_FDBOGL,
M68K_INS_FDBOR,
M68K_INS_FDBUN,
M68K_INS_FDBUEQ,
M68K_INS_FDBUGT,
M68K_INS_FDBUGE,
M68K_INS_FDBULT,
M68K_INS_FDBULE,
M68K_INS_FDBNE,
M68K_INS_FDBT,
M68K_INS_FDBSF,
M68K_INS_FDBSEQ,
M68K_INS_FDBGT,
M68K_INS_FDBGE,
M68K_INS_FDBLT,
M68K_INS_FDBLE,
M68K_INS_FDBGL,
M68K_INS_FDBGLE,
M68K_INS_FDBNGLE,
M68K_INS_FDBNGL,
M68K_INS_FDBNLE,
M68K_INS_FDBNLT,
M68K_INS_FDBNGE,
M68K_INS_FDBNGT,
M68K_INS_FDBSNE,
M68K_INS_FDBST,
M68K_INS_FDIV,
M68K_INS_FSDIV,
M68K_INS_FDDIV,
M68K_INS_FETOX,
M68K_INS_FETOXM1,
M68K_INS_FGETEXP,
M68K_INS_FGETMAN,
M68K_INS_FINT,
M68K_INS_FINTRZ,
M68K_INS_FLOG10,
M68K_INS_FLOG2,
M68K_INS_FLOGN,
M68K_INS_FLOGNP1,
M68K_INS_FMOD,
M68K_INS_FMOVE,
M68K_INS_FSMOVE,
M68K_INS_FDMOVE,
M68K_INS_FMOVECR,
M68K_INS_FMOVEM,
M68K_INS_FMUL,
M68K_INS_FSMUL,
M68K_INS_FDMUL,
M68K_INS_FNEG,
M68K_INS_FSNEG,
M68K_INS_FDNEG,
M68K_INS_FNOP,
M68K_INS_FREM,
M68K_INS_FRESTORE,
M68K_INS_FSAVE,
M68K_INS_FSCALE,
M68K_INS_FSGLDIV,
M68K_INS_FSGLMUL,
M68K_INS_FSIN,
M68K_INS_FSINCOS,
M68K_INS_FSINH,
M68K_INS_FSQRT,
M68K_INS_FSSQRT,
M68K_INS_FDSQRT,
M68K_INS_FSF,
M68K_INS_FSBEQ,
M68K_INS_FSOGT,
M68K_INS_FSOGE,
M68K_INS_FSOLT,
M68K_INS_FSOLE,
M68K_INS_FSOGL,
M68K_INS_FSOR,
M68K_INS_FSUN,
M68K_INS_FSUEQ,
M68K_INS_FSUGT,
M68K_INS_FSUGE,
M68K_INS_FSULT,
M68K_INS_FSULE,
M68K_INS_FSNE,
M68K_INS_FST,
M68K_INS_FSSF,
M68K_INS_FSSEQ,
M68K_INS_FSGT,
M68K_INS_FSGE,
M68K_INS_FSLT,
M68K_INS_FSLE,
M68K_INS_FSGL,
M68K_INS_FSGLE,
M68K_INS_FSNGLE,
M68K_INS_FSNGL,
M68K_INS_FSNLE,
M68K_INS_FSNLT,
M68K_INS_FSNGE,
M68K_INS_FSNGT,
M68K_INS_FSSNE,
M68K_INS_FSST,
M68K_INS_FSUB,
M68K_INS_FSSUB,
M68K_INS_FDSUB,
M68K_INS_FTAN,
M68K_INS_FTANH,
M68K_INS_FTENTOX,
M68K_INS_FTRAPF,
M68K_INS_FTRAPEQ,
M68K_INS_FTRAPOGT,
M68K_INS_FTRAPOGE,
M68K_INS_FTRAPOLT,
M68K_INS_FTRAPOLE,
M68K_INS_FTRAPOGL,
M68K_INS_FTRAPOR,
M68K_INS_FTRAPUN,
M68K_INS_FTRAPUEQ,
M68K_INS_FTRAPUGT,
M68K_INS_FTRAPUGE,
M68K_INS_FTRAPULT,
M68K_INS_FTRAPULE,
M68K_INS_FTRAPNE,
M68K_INS_FTRAPT,
M68K_INS_FTRAPSF,
M68K_INS_FTRAPSEQ,
M68K_INS_FTRAPGT,
M68K_INS_FTRAPGE,
M68K_INS_FTRAPLT,
M68K_INS_FTRAPLE,
M68K_INS_FTRAPGL,
M68K_INS_FTRAPGLE,
M68K_INS_FTRAPNGLE,
M68K_INS_FTRAPNGL,
M68K_INS_FTRAPNLE,
M68K_INS_FTRAPNLT,
M68K_INS_FTRAPNGE,
M68K_INS_FTRAPNGT,
M68K_INS_FTRAPSNE,
M68K_INS_FTRAPST,
M68K_INS_FTST,
M68K_INS_FTWOTOX,
M68K_INS_HALT,
M68K_INS_ILLEGAL,
M68K_INS_JMP,
M68K_INS_JSR,
M68K_INS_LEA,
M68K_INS_LINK,
M68K_INS_LPSTOP,
M68K_INS_LSL,
M68K_INS_LSR,
M68K_INS_MOVE,
M68K_INS_MOVEA,
M68K_INS_MOVEC,
M68K_INS_MOVEM,
M68K_INS_MOVEP,
M68K_INS_MOVEQ,
M68K_INS_MOVES,
M68K_INS_MOVE16,
M68K_INS_MULS,
M68K_INS_MULU,
M68K_INS_NBCD,
M68K_INS_NEG,
M68K_INS_NEGX,
M68K_INS_NOP,
M68K_INS_NOT,
M68K_INS_OR,
M68K_INS_ORI,
M68K_INS_PACK,
M68K_INS_PEA,
M68K_INS_PFLUSH,
M68K_INS_PFLUSHA,
M68K_INS_PFLUSHAN,
M68K_INS_PFLUSHN,
M68K_INS_PLOADR,
M68K_INS_PLOADW,
M68K_INS_PLPAR,
M68K_INS_PLPAW,
M68K_INS_PMOVE,
M68K_INS_PMOVEFD,
M68K_INS_PTESTR,
M68K_INS_PTESTW,
M68K_INS_PULSE,
M68K_INS_REMS,
M68K_INS_REMU,
M68K_INS_RESET,
M68K_INS_ROL,
M68K_INS_ROR,
M68K_INS_ROXL,
M68K_INS_ROXR,
M68K_INS_RTD,
M68K_INS_RTE,
M68K_INS_RTM,
M68K_INS_RTR,
M68K_INS_RTS,
M68K_INS_SBCD,
M68K_INS_ST,
M68K_INS_SF,
M68K_INS_SHI,
M68K_INS_SLS,
M68K_INS_SCC,
M68K_INS_SHS,
M68K_INS_SCS,
M68K_INS_SLO,
M68K_INS_SNE,
M68K_INS_SEQ,
M68K_INS_SVC,
M68K_INS_SVS,
M68K_INS_SPL,
M68K_INS_SMI,
M68K_INS_SGE,
M68K_INS_SLT,
M68K_INS_SGT,
M68K_INS_SLE,
M68K_INS_STOP,
M68K_INS_SUB,
M68K_INS_SUBA,
M68K_INS_SUBI,
M68K_INS_SUBQ,
M68K_INS_SUBX,
M68K_INS_SWAP,
M68K_INS_TAS,
M68K_INS_TRAP,
M68K_INS_TRAPV,
M68K_INS_TRAPT,
M68K_INS_TRAPF,
M68K_INS_TRAPHI,
M68K_INS_TRAPLS,
M68K_INS_TRAPCC,
M68K_INS_TRAPHS,
M68K_INS_TRAPCS,
M68K_INS_TRAPLO,
M68K_INS_TRAPNE,
M68K_INS_TRAPEQ,
M68K_INS_TRAPVC,
M68K_INS_TRAPVS,
M68K_INS_TRAPPL,
M68K_INS_TRAPMI,
M68K_INS_TRAPGE,
M68K_INS_TRAPLT,
M68K_INS_TRAPGT,
M68K_INS_TRAPLE,
M68K_INS_TST,
M68K_INS_UNLK,
M68K_INS_UNPK,
M68K_INS_BGND,
M68K_INS_TBLS,
M68K_INS_TBLU,
M68K_INS_TBLSN,
M68K_INS_TBLUN,
M68K_INS_ENDING, // <-- mark the end of the list of instructions
} m68k_insn;
/// Group of M68K instructions
typedef enum m68k_group_type {
M68K_GRP_INVALID = 0, ///< CS_GRUP_INVALID
M68K_GRP_JUMP, ///< = CS_GRP_JUMP
M68K_GRP_RET = 3, ///< = CS_GRP_RET
M68K_GRP_IRET = 5, ///< = CS_GRP_IRET
M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE
M68K_GRP_ENDING, // <-- mark the end of the list of groups
} m68k_group_type;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/mips.h
+2293
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include/capstone/mos65xx.h
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#ifndef CAPSTONE_MOS65XX_H
#define CAPSTONE_MOS65XX_H
/* Capstone Disassembly Engine */
/* By Sebastian Macke <sebastian@macke.de, 2018 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
/// MOS65XX registers and special registers
typedef enum mos65xx_reg {
MOS65XX_REG_INVALID = 0,
MOS65XX_REG_ACC, ///< accumulator
MOS65XX_REG_X, ///< X index register
MOS65XX_REG_Y, ///< Y index register
MOS65XX_REG_P, ///< status register
MOS65XX_REG_SP, ///< stack pointer register
MOS65XX_REG_DP, ///< direct page register
MOS65XX_REG_B, ///< data bank register
MOS65XX_REG_K, ///< program bank register
MOS65XX_REG_ENDING, // <-- mark the end of the list of registers
} mos65xx_reg;
/// MOS65XX Addressing Modes
typedef enum mos65xx_address_mode {
MOS65XX_AM_NONE = 0, ///< No address mode.
MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)
MOS65XX_AM_ACC, ///< accumulator addressing
MOS65XX_AM_IMM, ///< 8/16 Bit immediate value
MOS65XX_AM_REL, ///< relative addressing used by branches
MOS65XX_AM_INT, ///< interrupt addressing
MOS65XX_AM_BLOCK, ///< memory block addressing
MOS65XX_AM_ZP, ///< zeropage addressing
MOS65XX_AM_ZP_X, ///< indexed zeropage addressing by the X index register
MOS65XX_AM_ZP_Y, ///< indexed zeropage addressing by the Y index register
MOS65XX_AM_ZP_REL, ///< zero page address, branch relative address
MOS65XX_AM_ZP_IND, ///< indirect zeropage addressing
MOS65XX_AM_ZP_X_IND, ///< indexed zeropage indirect addressing by the X index register
MOS65XX_AM_ZP_IND_Y, ///< indirect zeropage indexed addressing by the Y index register
MOS65XX_AM_ZP_IND_LONG, ///< zeropage indirect long addressing
MOS65XX_AM_ZP_IND_LONG_Y, ///< zeropage indirect long addressing indexed by Y register
MOS65XX_AM_ABS, ///< absolute addressing
MOS65XX_AM_ABS_X, ///< indexed absolute addressing by the X index register
MOS65XX_AM_ABS_Y, ///< indexed absolute addressing by the Y index register
MOS65XX_AM_ABS_IND, ///< absolute indirect addressing
MOS65XX_AM_ABS_X_IND, ///< indexed absolute indirect addressing by the X index register
MOS65XX_AM_ABS_IND_LONG, ///< absolute indirect long addressing
MOS65XX_AM_ABS_LONG, ///< absolute long address mode
MOS65XX_AM_ABS_LONG_X, ///< absolute long address mode, indexed by X register
MOS65XX_AM_SR, ///< stack relative addressing
MOS65XX_AM_SR_IND_Y, ///< indirect stack relative addressing indexed by the Y index register
} mos65xx_address_mode;
/// MOS65XX instruction
typedef enum mos65xx_insn {
MOS65XX_INS_INVALID = 0,
MOS65XX_INS_ADC,
MOS65XX_INS_AND,
MOS65XX_INS_ASL,
MOS65XX_INS_BBR,
MOS65XX_INS_BBS,
MOS65XX_INS_BCC,
MOS65XX_INS_BCS,
MOS65XX_INS_BEQ,
MOS65XX_INS_BIT,
MOS65XX_INS_BMI,
MOS65XX_INS_BNE,
MOS65XX_INS_BPL,
MOS65XX_INS_BRA,
MOS65XX_INS_BRK,
MOS65XX_INS_BRL,
MOS65XX_INS_BVC,
MOS65XX_INS_BVS,
MOS65XX_INS_CLC,
MOS65XX_INS_CLD,
MOS65XX_INS_CLI,
MOS65XX_INS_CLV,
MOS65XX_INS_CMP,
MOS65XX_INS_COP,
MOS65XX_INS_CPX,
MOS65XX_INS_CPY,
MOS65XX_INS_DEC,
MOS65XX_INS_DEX,
MOS65XX_INS_DEY,
MOS65XX_INS_EOR,
MOS65XX_INS_INC,
MOS65XX_INS_INX,
MOS65XX_INS_INY,
MOS65XX_INS_JML,
MOS65XX_INS_JMP,
MOS65XX_INS_JSL,
MOS65XX_INS_JSR,
MOS65XX_INS_LDA,
MOS65XX_INS_LDX,
MOS65XX_INS_LDY,
MOS65XX_INS_LSR,
MOS65XX_INS_MVN,
MOS65XX_INS_MVP,
MOS65XX_INS_NOP,
MOS65XX_INS_ORA,
MOS65XX_INS_PEA,
MOS65XX_INS_PEI,
MOS65XX_INS_PER,
MOS65XX_INS_PHA,
MOS65XX_INS_PHB,
MOS65XX_INS_PHD,
MOS65XX_INS_PHK,
MOS65XX_INS_PHP,
MOS65XX_INS_PHX,
MOS65XX_INS_PHY,
MOS65XX_INS_PLA,
MOS65XX_INS_PLB,
MOS65XX_INS_PLD,
MOS65XX_INS_PLP,
MOS65XX_INS_PLX,
MOS65XX_INS_PLY,
MOS65XX_INS_REP,
MOS65XX_INS_RMB,
MOS65XX_INS_ROL,
MOS65XX_INS_ROR,
MOS65XX_INS_RTI,
MOS65XX_INS_RTL,
MOS65XX_INS_RTS,
MOS65XX_INS_SBC,
MOS65XX_INS_SEC,
MOS65XX_INS_SED,
MOS65XX_INS_SEI,
MOS65XX_INS_SEP,
MOS65XX_INS_SMB,
MOS65XX_INS_STA,
MOS65XX_INS_STP,
MOS65XX_INS_STX,
MOS65XX_INS_STY,
MOS65XX_INS_STZ,
MOS65XX_INS_TAX,
MOS65XX_INS_TAY,
MOS65XX_INS_TCD,
MOS65XX_INS_TCS,
MOS65XX_INS_TDC,
MOS65XX_INS_TRB,
MOS65XX_INS_TSB,
MOS65XX_INS_TSC,
MOS65XX_INS_TSX,
MOS65XX_INS_TXA,
MOS65XX_INS_TXS,
MOS65XX_INS_TXY,
MOS65XX_INS_TYA,
MOS65XX_INS_TYX,
MOS65XX_INS_WAI,
MOS65XX_INS_WDM,
MOS65XX_INS_XBA,
MOS65XX_INS_XCE,
MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions
} mos65xx_insn;
/// Group of MOS65XX instructions
typedef enum mos65xx_group_type {
MOS65XX_GRP_INVALID = 0, ///< CS_GRP_INVALID
MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP
MOS65XX_GRP_CALL, ///< = CS_GRP_RET
MOS65XX_GRP_RET, ///< = CS_GRP_RET
MOS65XX_GRP_INT, ///< = CS_GRP_INT
MOS65XX_GRP_IRET = 5, ///< = CS_GRP_IRET
MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE
MOS65XX_GRP_ENDING, // <-- mark the end of the list of groups
} mos65xx_group_type;
/// Operand type for instruction's operands
typedef enum mos65xx_op_type {
// = CS_OP_INVALID (Uninitialized).
MOS65XX_OP_INVALID = CS_OP_INVALID,
MOS65XX_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
MOS65XX_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
MOS65XX_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} mos65xx_op_type;
/// Instruction operand
typedef struct cs_mos65xx_op {
mos65xx_op_type type; ///< operand type
union {
mos65xx_reg reg; ///< register value for REG operand
uint16_t imm; ///< immediate value for IMM operand
uint32_t mem; ///< address for MEM operand
};
} cs_mos65xx_op;
/// The MOS65XX address mode and its operands
typedef struct cs_mos65xx {
mos65xx_address_mode am;
bool modifies_flags;
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_mos65xx_op operands[3]; ///< operands for this instruction.
} cs_mos65xx;
#ifdef __cplusplus
}
#endif
#endif //CAPSTONE_MOS65XX_H
include/capstone/platform.h
+123
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/* Capstone Disassembly Engine */
/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
#ifndef CAPSTONE_PLATFORM_H
#define CAPSTONE_PLATFORM_H
// handle C99 issue (for pre-2013 VisualStudio)
#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && \
(defined(WIN32) || defined(WIN64) || defined(_WIN32) || \
defined(_WIN64))
// MSVC
// stdbool.h
#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
// this system does not have stdbool.h
#ifndef __cplusplus
typedef unsigned char bool;
#define false 0
#define true 1
#endif // __cplusplus
#else
// VisualStudio 2013+ -> C99 is supported
#include <stdbool.h>
#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE)
#else
// not MSVC -> C99 is supported
#include <stdbool.h>
#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
// handle inttypes.h / stdint.h compatibility
#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
#include "windowsce/stdint.h"
#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
#if defined(CAPSTONE_HAS_OSXKERNEL) || \
(defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
// this system does not have inttypes.h
#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
// this system does not have stdint.h
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
#endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
#define INT8_MIN (-127i8 - 1)
#define INT16_MIN (-32767i16 - 1)
#define INT32_MIN (-2147483647i32 - 1)
#define INT64_MIN (-9223372036854775807i64 - 1)
#define INT8_MAX 127i8
#define INT16_MAX 32767i16
#define INT32_MAX 2147483647i32
#define INT64_MAX 9223372036854775807i64
#define UINT8_MAX 0xffui8
#define UINT16_MAX 0xffffui16
#define UINT32_MAX 0xffffffffui32
#define UINT64_MAX 0xffffffffffffffffui64
#endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
#ifdef CAPSTONE_HAS_OSXKERNEL
// this system has stdint.h
#include <stdint.h>
#endif
#define __PRI_8_LENGTH_MODIFIER__ "hh"
#define __PRI_64_LENGTH_MODIFIER__ "ll"
#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
#define PRId16 "hd"
#define PRIi16 "hi"
#define PRIo16 "ho"
#define PRIu16 "hu"
#define PRIx16 "hx"
#define PRIX16 "hX"
#if defined(_MSC_VER) && _MSC_VER <= 1700
#define PRId32 "ld"
#define PRIi32 "li"
#define PRIo32 "lo"
#define PRIu32 "lu"
#define PRIx32 "lx"
#define PRIX32 "lX"
#else // OSX
#define PRId32 "d"
#define PRIi32 "i"
#define PRIo32 "o"
#define PRIu32 "u"
#define PRIx32 "x"
#define PRIX32 "X"
#endif // defined(_MSC_VER) && _MSC_VER <= 1700
#if defined(_MSC_VER) && _MSC_VER <= 1700
// redefine functions from inttypes.h used in cstool
#define strtoull _strtoui64
#endif
#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
#else
// this system has inttypes.h by default
#include <inttypes.h>
#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
#endif
include/capstone/ppc.h
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include/capstone/riscv.h
+2872
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include/capstone/sh.h
+459
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#ifndef CAPSTONE_SH_H
#define CAPSTONE_SH_H
/* Capstone Disassembly Engine */
/* By Yoshinori Sato, 2022 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
/// SH registers and special registers
typedef enum {
SH_REG_INVALID = 0,
SH_REG_R0,
SH_REG_R1,
SH_REG_R2,
SH_REG_R3,
SH_REG_R4,
SH_REG_R5,
SH_REG_R6,
SH_REG_R7,
SH_REG_R8,
SH_REG_R9,
SH_REG_R10,
SH_REG_R11,
SH_REG_R12,
SH_REG_R13,
SH_REG_R14,
SH_REG_R15,
SH_REG_R0_BANK,
SH_REG_R1_BANK,
SH_REG_R2_BANK,
SH_REG_R3_BANK,
SH_REG_R4_BANK,
SH_REG_R5_BANK,
SH_REG_R6_BANK,
SH_REG_R7_BANK,
SH_REG_FR0,
SH_REG_FR1,
SH_REG_FR2,
SH_REG_FR3,
SH_REG_FR4,
SH_REG_FR5,
SH_REG_FR6,
SH_REG_FR7,
SH_REG_FR8,
SH_REG_FR9,
SH_REG_FR10,
SH_REG_FR11,
SH_REG_FR12,
SH_REG_FR13,
SH_REG_FR14,
SH_REG_FR15,
SH_REG_DR0,
SH_REG_DR2,
SH_REG_DR4,
SH_REG_DR6,
SH_REG_DR8,
SH_REG_DR10,
SH_REG_DR12,
SH_REG_DR14,
SH_REG_XD0,
SH_REG_XD2,
SH_REG_XD4,
SH_REG_XD6,
SH_REG_XD8,
SH_REG_XD10,
SH_REG_XD12,
SH_REG_XD14,
SH_REG_XF0,
SH_REG_XF1,
SH_REG_XF2,
SH_REG_XF3,
SH_REG_XF4,
SH_REG_XF5,
SH_REG_XF6,
SH_REG_XF7,
SH_REG_XF8,
SH_REG_XF9,
SH_REG_XF10,
SH_REG_XF11,
SH_REG_XF12,
SH_REG_XF13,
SH_REG_XF14,
SH_REG_XF15,
SH_REG_FV0,
SH_REG_FV4,
SH_REG_FV8,
SH_REG_FV12,
SH_REG_XMATRX,
SH_REG_PC,
SH_REG_PR,
SH_REG_MACH,
SH_REG_MACL,
SH_REG_SR,
SH_REG_GBR,
SH_REG_SSR,
SH_REG_SPC,
SH_REG_SGR,
SH_REG_DBR,
SH_REG_VBR,
SH_REG_TBR,
SH_REG_RS,
SH_REG_RE,
SH_REG_MOD,
SH_REG_FPUL,
SH_REG_FPSCR,
SH_REG_DSP_X0,
SH_REG_DSP_X1,
SH_REG_DSP_Y0,
SH_REG_DSP_Y1,
SH_REG_DSP_A0,
SH_REG_DSP_A1,
SH_REG_DSP_A0G,
SH_REG_DSP_A1G,
SH_REG_DSP_M0,
SH_REG_DSP_M1,
SH_REG_DSP_DSR,
SH_REG_DSP_RSV0,
SH_REG_DSP_RSV1,
SH_REG_DSP_RSV2,
SH_REG_DSP_RSV3,
SH_REG_DSP_RSV4,
SH_REG_DSP_RSV5,
SH_REG_DSP_RSV6,
SH_REG_DSP_RSV7,
SH_REG_DSP_RSV8,
SH_REG_DSP_RSV9,
SH_REG_DSP_RSVA,
SH_REG_DSP_RSVB,
SH_REG_DSP_RSVC,
SH_REG_DSP_RSVD,
SH_REG_DSP_RSVE,
SH_REG_DSP_RSVF,
SH_REG_ENDING, // <-- mark the end of the list of registers
} sh_reg;
typedef enum {
SH_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
SH_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
SH_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
SH_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} sh_op_type;
typedef enum {
SH_OP_MEM_INVALID = 0, /// <= Invalid
SH_OP_MEM_REG_IND, /// <= Register indirect
SH_OP_MEM_REG_POST, /// <= Register post increment
SH_OP_MEM_REG_PRE, /// <= Register pre decrement
SH_OP_MEM_REG_DISP, /// <= displacement
SH_OP_MEM_REG_R0, /// <= R0 indexed
SH_OP_MEM_GBR_DISP, /// <= GBR based displacement
SH_OP_MEM_GBR_R0, /// <= GBR based R0 indexed
SH_OP_MEM_PCR, /// <= PC relative
SH_OP_MEM_TBR_DISP, /// <= TBR based displaysment
} sh_op_mem_type;
typedef struct sh_op_mem {
sh_op_mem_type address; /// <= memory address
sh_reg reg; /// <= base register
uint32_t disp; /// <= displacement
} sh_op_mem;
typedef enum sh_dsp_insn {
SH_INS_DSP_INVALID = 0,
SH_INS_DSP_NOP = 1,
SH_INS_DSP_MOV,
SH_INS_DSP_PSHL,
SH_INS_DSP_PSHA,
SH_INS_DSP_PMULS,
SH_INS_DSP_PCLR_PMULS,
SH_INS_DSP_PSUB_PMULS,
SH_INS_DSP_PADD_PMULS,
SH_INS_DSP_PSUBC,
SH_INS_DSP_PADDC,
SH_INS_DSP_PCMP,
SH_INS_DSP_PABS,
SH_INS_DSP_PRND,
SH_INS_DSP_PSUB,
SH_INS_DSP_PSUBr,
SH_INS_DSP_PADD,
SH_INS_DSP_PAND,
SH_INS_DSP_PXOR,
SH_INS_DSP_POR,
SH_INS_DSP_PDEC,
SH_INS_DSP_PINC,
SH_INS_DSP_PCLR,
SH_INS_DSP_PDMSB,
SH_INS_DSP_PNEG,
SH_INS_DSP_PCOPY,
SH_INS_DSP_PSTS,
SH_INS_DSP_PLDS,
SH_INS_DSP_PSWAP,
SH_INS_DSP_PWAD,
SH_INS_DSP_PWSB,
} sh_dsp_insn;
typedef enum sh_dsp_operand {
SH_OP_DSP_INVALID,
SH_OP_DSP_REG_PRE,
SH_OP_DSP_REG_IND,
SH_OP_DSP_REG_POST,
SH_OP_DSP_REG_INDEX,
SH_OP_DSP_REG,
SH_OP_DSP_IMM,
} sh_dsp_operand;
typedef enum sh_dsp_cc {
SH_DSP_CC_INVALID,
SH_DSP_CC_NONE,
SH_DSP_CC_DCT,
SH_DSP_CC_DCF,
} sh_dsp_cc;
typedef struct sh_op_dsp {
sh_dsp_insn insn;
sh_dsp_operand operand[2];
sh_reg r[6];
sh_dsp_cc cc;
uint8_t imm;
int size;
} sh_op_dsp;
/// Instruction operand
typedef struct cs_sh_op {
sh_op_type type;
union {
uint64_t imm; ///< immediate value for IMM operand
sh_reg reg; ///< register value for REG operand
sh_op_mem mem; ///< data when operand is targeting memory
sh_op_dsp dsp; ///< dsp instruction
};
} cs_sh_op;
/// SH instruction
typedef enum sh_insn {
SH_INS_INVALID,
SH_INS_ADD_r,
SH_INS_ADD,
SH_INS_ADDC,
SH_INS_ADDV,
SH_INS_AND,
SH_INS_BAND,
SH_INS_BANDNOT,
SH_INS_BCLR,
SH_INS_BF,
SH_INS_BF_S,
SH_INS_BLD,
SH_INS_BLDNOT,
SH_INS_BOR,
SH_INS_BORNOT,
SH_INS_BRA,
SH_INS_BRAF,
SH_INS_BSET,
SH_INS_BSR,
SH_INS_BSRF,
SH_INS_BST,
SH_INS_BT,
SH_INS_BT_S,
SH_INS_BXOR,
SH_INS_CLIPS,
SH_INS_CLIPU,
SH_INS_CLRDMXY,
SH_INS_CLRMAC,
SH_INS_CLRS,
SH_INS_CLRT,
SH_INS_CMP_EQ,
SH_INS_CMP_GE,
SH_INS_CMP_GT,
SH_INS_CMP_HI,
SH_INS_CMP_HS,
SH_INS_CMP_PL,
SH_INS_CMP_PZ,
SH_INS_CMP_STR,
SH_INS_DIV0S,
SH_INS_DIV0U,
SH_INS_DIV1,
SH_INS_DIVS,
SH_INS_DIVU,
SH_INS_DMULS_L,
SH_INS_DMULU_L,
SH_INS_DT,
SH_INS_EXTS_B,
SH_INS_EXTS_W,
SH_INS_EXTU_B,
SH_INS_EXTU_W,
SH_INS_FABS,
SH_INS_FADD,
SH_INS_FCMP_EQ,
SH_INS_FCMP_GT,
SH_INS_FCNVDS,
SH_INS_FCNVSD,
SH_INS_FDIV,
SH_INS_FIPR,
SH_INS_FLDI0,
SH_INS_FLDI1,
SH_INS_FLDS,
SH_INS_FLOAT,
SH_INS_FMAC,
SH_INS_FMOV,
SH_INS_FMUL,
SH_INS_FNEG,
SH_INS_FPCHG,
SH_INS_FRCHG,
SH_INS_FSCA,
SH_INS_FSCHG,
SH_INS_FSQRT,
SH_INS_FSRRA,
SH_INS_FSTS,
SH_INS_FSUB,
SH_INS_FTRC,
SH_INS_FTRV,
SH_INS_ICBI,
SH_INS_JMP,
SH_INS_JSR,
SH_INS_JSR_N,
SH_INS_LDBANK,
SH_INS_LDC,
SH_INS_LDRC,
SH_INS_LDRE,
SH_INS_LDRS,
SH_INS_LDS,
SH_INS_LDTLB,
SH_INS_MAC_L,
SH_INS_MAC_W,
SH_INS_MOV,
SH_INS_MOVA,
SH_INS_MOVCA,
SH_INS_MOVCO,
SH_INS_MOVI20,
SH_INS_MOVI20S,
SH_INS_MOVLI,
SH_INS_MOVML,
SH_INS_MOVMU,
SH_INS_MOVRT,
SH_INS_MOVT,
SH_INS_MOVU,
SH_INS_MOVUA,
SH_INS_MUL_L,
SH_INS_MULR,
SH_INS_MULS_W,
SH_INS_MULU_W,
SH_INS_NEG,
SH_INS_NEGC,
SH_INS_NOP,
SH_INS_NOT,
SH_INS_NOTT,
SH_INS_OCBI,
SH_INS_OCBP,
SH_INS_OCBWB,
SH_INS_OR,
SH_INS_PREF,
SH_INS_PREFI,
SH_INS_RESBANK,
SH_INS_ROTCL,
SH_INS_ROTCR,
SH_INS_ROTL,
SH_INS_ROTR,
SH_INS_RTE,
SH_INS_RTS,
SH_INS_RTS_N,
SH_INS_RTV_N,
SH_INS_SETDMX,
SH_INS_SETDMY,
SH_INS_SETRC,
SH_INS_SETS,
SH_INS_SETT,
SH_INS_SHAD,
SH_INS_SHAL,
SH_INS_SHAR,
SH_INS_SHLD,
SH_INS_SHLL,
SH_INS_SHLL16,
SH_INS_SHLL2,
SH_INS_SHLL8,
SH_INS_SHLR,
SH_INS_SHLR16,
SH_INS_SHLR2,
SH_INS_SHLR8,
SH_INS_SLEEP,
SH_INS_STBANK,
SH_INS_STC,
SH_INS_STS,
SH_INS_SUB,
SH_INS_SUBC,
SH_INS_SUBV,
SH_INS_SWAP_B,
SH_INS_SWAP_W,
SH_INS_SYNCO,
SH_INS_TAS,
SH_INS_TRAPA,
SH_INS_TST,
SH_INS_XOR,
SH_INS_XTRCT,
SH_INS_DSP,
SH_INS_ENDING, // <-- mark the end of the list of instructions
} sh_insn;
/// Instruction structure
typedef struct cs_sh {
sh_insn insn;
uint8_t size;
uint8_t op_count;
cs_sh_op operands[3];
} cs_sh;
/// Group of SH instructions
typedef enum sh_insn_group {
SH_GRP_INVALID = 0, ///< CS_GRUP_INVALID
SH_GRP_JUMP, ///< = CS_GRP_JUMP
SH_GRP_CALL, ///< = CS_GRP_CALL
SH_GRP_INT, ///< = CS_GRP_INT
SH_GRP_RET, ///< = CS_GRP_RET
SH_GRP_IRET, ///< = CS_GRP_IRET
SH_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
SH_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
SH_GRP_SH1,
SH_GRP_SH2,
SH_GRP_SH2E,
SH_GRP_SH2DSP,
SH_GRP_SH2A,
SH_GRP_SH2AFPU,
SH_GRP_SH3,
SH_GRP_SH3DSP,
SH_GRP_SH4,
SH_GRP_SH4A,
SH_GRP_ENDING, // <-- mark the end of the list of groups
} sh_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/sparc.h
+1349
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File diff suppressed because it is too large Load Diff
include/capstone/systemz.h
+3033
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File diff suppressed because it is too large Load Diff
include/capstone/systemz_compatibility.h
+2991
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include/capstone/tms320c64x.h
+362
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@@ -0,0 +1,362 @@
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
#ifndef CAPSTONE_TMS320C64X_H
#define CAPSTONE_TMS320C64X_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
typedef enum tms320c64x_op_type {
// = CS_OP_INVALID (Uninitialized).
TMS320C64X_OP_INVALID = CS_OP_INVALID,
TMS320C64X_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
TMS320C64X_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
// Register pair for double word ops
TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL + 0,
TMS320C64X_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} tms320c64x_op_type;
typedef enum tms320c64x_mem_disp {
TMS320C64X_MEM_DISP_INVALID = 0,
TMS320C64X_MEM_DISP_CONSTANT,
TMS320C64X_MEM_DISP_REGISTER,
} tms320c64x_mem_disp;
typedef enum tms320c64x_mem_dir {
TMS320C64X_MEM_DIR_INVALID = 0,
TMS320C64X_MEM_DIR_FW,
TMS320C64X_MEM_DIR_BW,
} tms320c64x_mem_dir;
typedef enum tms320c64x_mem_mod {
TMS320C64X_MEM_MOD_INVALID = 0,
TMS320C64X_MEM_MOD_NO,
TMS320C64X_MEM_MOD_PRE,
TMS320C64X_MEM_MOD_POST,
} tms320c64x_mem_mod;
typedef struct tms320c64x_op_mem {
unsigned int base; ///< base register
unsigned int disp; ///< displacement/offset value
unsigned int unit; ///< unit of base and offset register
unsigned int scaled; ///< offset scaled
unsigned int disptype; ///< displacement type
unsigned int direction; ///< direction
unsigned int modify; ///< modification
} tms320c64x_op_mem;
typedef struct cs_tms320c64x_op {
tms320c64x_op_type type; ///< operand type
union {
unsigned int
reg; ///< register value for REG operand or first register for REGPAIR operand
int32_t imm; ///< immediate value for IMM operand
tms320c64x_op_mem mem; ///< base/disp value for MEM operand
};
} cs_tms320c64x_op;
typedef struct cs_tms320c64x {
uint8_t op_count;
cs_tms320c64x_op operands[8]; ///< operands for this instruction.
struct {
unsigned int reg;
unsigned int zero;
} condition;
struct {
unsigned int unit;
unsigned int side;
unsigned int crosspath;
} funit;
unsigned int parallel;
} cs_tms320c64x;
typedef enum tms320c64x_reg {
TMS320C64X_REG_INVALID = 0,
TMS320C64X_REG_AMR,
TMS320C64X_REG_CSR,
TMS320C64X_REG_DIER,
TMS320C64X_REG_DNUM,
TMS320C64X_REG_ECR,
TMS320C64X_REG_GFPGFR,
TMS320C64X_REG_GPLYA,
TMS320C64X_REG_GPLYB,
TMS320C64X_REG_ICR,
TMS320C64X_REG_IER,
TMS320C64X_REG_IERR,
TMS320C64X_REG_ILC,
TMS320C64X_REG_IRP,
TMS320C64X_REG_ISR,
TMS320C64X_REG_ISTP,
TMS320C64X_REG_ITSR,
TMS320C64X_REG_NRP,
TMS320C64X_REG_NTSR,
TMS320C64X_REG_REP,
TMS320C64X_REG_RILC,
TMS320C64X_REG_SSR,
TMS320C64X_REG_TSCH,
TMS320C64X_REG_TSCL,
TMS320C64X_REG_TSR,
TMS320C64X_REG_A0,
TMS320C64X_REG_A1,
TMS320C64X_REG_A2,
TMS320C64X_REG_A3,
TMS320C64X_REG_A4,
TMS320C64X_REG_A5,
TMS320C64X_REG_A6,
TMS320C64X_REG_A7,
TMS320C64X_REG_A8,
TMS320C64X_REG_A9,
TMS320C64X_REG_A10,
TMS320C64X_REG_A11,
TMS320C64X_REG_A12,
TMS320C64X_REG_A13,
TMS320C64X_REG_A14,
TMS320C64X_REG_A15,
TMS320C64X_REG_A16,
TMS320C64X_REG_A17,
TMS320C64X_REG_A18,
TMS320C64X_REG_A19,
TMS320C64X_REG_A20,
TMS320C64X_REG_A21,
TMS320C64X_REG_A22,
TMS320C64X_REG_A23,
TMS320C64X_REG_A24,
TMS320C64X_REG_A25,
TMS320C64X_REG_A26,
TMS320C64X_REG_A27,
TMS320C64X_REG_A28,
TMS320C64X_REG_A29,
TMS320C64X_REG_A30,
TMS320C64X_REG_A31,
TMS320C64X_REG_B0,
TMS320C64X_REG_B1,
TMS320C64X_REG_B2,
TMS320C64X_REG_B3,
TMS320C64X_REG_B4,
TMS320C64X_REG_B5,
TMS320C64X_REG_B6,
TMS320C64X_REG_B7,
TMS320C64X_REG_B8,
TMS320C64X_REG_B9,
TMS320C64X_REG_B10,
TMS320C64X_REG_B11,
TMS320C64X_REG_B12,
TMS320C64X_REG_B13,
TMS320C64X_REG_B14,
TMS320C64X_REG_B15,
TMS320C64X_REG_B16,
TMS320C64X_REG_B17,
TMS320C64X_REG_B18,
TMS320C64X_REG_B19,
TMS320C64X_REG_B20,
TMS320C64X_REG_B21,
TMS320C64X_REG_B22,
TMS320C64X_REG_B23,
TMS320C64X_REG_B24,
TMS320C64X_REG_B25,
TMS320C64X_REG_B26,
TMS320C64X_REG_B27,
TMS320C64X_REG_B28,
TMS320C64X_REG_B29,
TMS320C64X_REG_B30,
TMS320C64X_REG_B31,
TMS320C64X_REG_PCE1,
TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers
// Alias registers
TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
} tms320c64x_reg;
typedef enum tms320c64x_insn {
TMS320C64X_INS_INVALID = 0,
TMS320C64X_INS_ABS,
TMS320C64X_INS_ABS2,
TMS320C64X_INS_ADD,
TMS320C64X_INS_ADD2,
TMS320C64X_INS_ADD4,
TMS320C64X_INS_ADDAB,
TMS320C64X_INS_ADDAD,
TMS320C64X_INS_ADDAH,
TMS320C64X_INS_ADDAW,
TMS320C64X_INS_ADDK,
TMS320C64X_INS_ADDKPC,
TMS320C64X_INS_ADDU,
TMS320C64X_INS_AND,
TMS320C64X_INS_ANDN,
TMS320C64X_INS_AVG2,
TMS320C64X_INS_AVGU4,
TMS320C64X_INS_B,
TMS320C64X_INS_BDEC,
TMS320C64X_INS_BITC4,
TMS320C64X_INS_BNOP,
TMS320C64X_INS_BPOS,
TMS320C64X_INS_CLR,
TMS320C64X_INS_CMPEQ,
TMS320C64X_INS_CMPEQ2,
TMS320C64X_INS_CMPEQ4,
TMS320C64X_INS_CMPGT,
TMS320C64X_INS_CMPGT2,
TMS320C64X_INS_CMPGTU4,
TMS320C64X_INS_CMPLT,
TMS320C64X_INS_CMPLTU,
TMS320C64X_INS_DEAL,
TMS320C64X_INS_DOTP2,
TMS320C64X_INS_DOTPN2,
TMS320C64X_INS_DOTPNRSU2,
TMS320C64X_INS_DOTPRSU2,
TMS320C64X_INS_DOTPSU4,
TMS320C64X_INS_DOTPU4,
TMS320C64X_INS_EXT,
TMS320C64X_INS_EXTU,
TMS320C64X_INS_GMPGTU,
TMS320C64X_INS_GMPY4,
TMS320C64X_INS_LDB,
TMS320C64X_INS_LDBU,
TMS320C64X_INS_LDDW,
TMS320C64X_INS_LDH,
TMS320C64X_INS_LDHU,
TMS320C64X_INS_LDNDW,
TMS320C64X_INS_LDNW,
TMS320C64X_INS_LDW,
TMS320C64X_INS_LMBD,
TMS320C64X_INS_MAX2,
TMS320C64X_INS_MAXU4,
TMS320C64X_INS_MIN2,
TMS320C64X_INS_MINU4,
TMS320C64X_INS_MPY,
TMS320C64X_INS_MPY2,
TMS320C64X_INS_MPYH,
TMS320C64X_INS_MPYHI,
TMS320C64X_INS_MPYHIR,
TMS320C64X_INS_MPYHL,
TMS320C64X_INS_MPYHLU,
TMS320C64X_INS_MPYHSLU,
TMS320C64X_INS_MPYHSU,
TMS320C64X_INS_MPYHU,
TMS320C64X_INS_MPYHULS,
TMS320C64X_INS_MPYHUS,
TMS320C64X_INS_MPYLH,
TMS320C64X_INS_MPYLHU,
TMS320C64X_INS_MPYLI,
TMS320C64X_INS_MPYLIR,
TMS320C64X_INS_MPYLSHU,
TMS320C64X_INS_MPYLUHS,
TMS320C64X_INS_MPYSU,
TMS320C64X_INS_MPYSU4,
TMS320C64X_INS_MPYU,
TMS320C64X_INS_MPYU4,
TMS320C64X_INS_MPYUS,
TMS320C64X_INS_MVC,
TMS320C64X_INS_MVD,
TMS320C64X_INS_MVK,
TMS320C64X_INS_MVKL,
TMS320C64X_INS_MVKLH,
TMS320C64X_INS_NOP,
TMS320C64X_INS_NORM,
TMS320C64X_INS_OR,
TMS320C64X_INS_PACK2,
TMS320C64X_INS_PACKH2,
TMS320C64X_INS_PACKH4,
TMS320C64X_INS_PACKHL2,
TMS320C64X_INS_PACKL4,
TMS320C64X_INS_PACKLH2,
TMS320C64X_INS_ROTL,
TMS320C64X_INS_SADD,
TMS320C64X_INS_SADD2,
TMS320C64X_INS_SADDU4,
TMS320C64X_INS_SADDUS2,
TMS320C64X_INS_SAT,
TMS320C64X_INS_SET,
TMS320C64X_INS_SHFL,
TMS320C64X_INS_SHL,
TMS320C64X_INS_SHLMB,
TMS320C64X_INS_SHR,
TMS320C64X_INS_SHR2,
TMS320C64X_INS_SHRMB,
TMS320C64X_INS_SHRU,
TMS320C64X_INS_SHRU2,
TMS320C64X_INS_SMPY,
TMS320C64X_INS_SMPY2,
TMS320C64X_INS_SMPYH,
TMS320C64X_INS_SMPYHL,
TMS320C64X_INS_SMPYLH,
TMS320C64X_INS_SPACK2,
TMS320C64X_INS_SPACKU4,
TMS320C64X_INS_SSHL,
TMS320C64X_INS_SSHVL,
TMS320C64X_INS_SSHVR,
TMS320C64X_INS_SSUB,
TMS320C64X_INS_STB,
TMS320C64X_INS_STDW,
TMS320C64X_INS_STH,
TMS320C64X_INS_STNDW,
TMS320C64X_INS_STNW,
TMS320C64X_INS_STW,
TMS320C64X_INS_SUB,
TMS320C64X_INS_SUB2,
TMS320C64X_INS_SUB4,
TMS320C64X_INS_SUBAB,
TMS320C64X_INS_SUBABS4,
TMS320C64X_INS_SUBAH,
TMS320C64X_INS_SUBAW,
TMS320C64X_INS_SUBC,
TMS320C64X_INS_SUBU,
TMS320C64X_INS_SWAP4,
TMS320C64X_INS_UNPKHU4,
TMS320C64X_INS_UNPKLU4,
TMS320C64X_INS_XOR,
TMS320C64X_INS_XPND2,
TMS320C64X_INS_XPND4,
// Aliases
TMS320C64X_INS_IDLE,
TMS320C64X_INS_MV,
TMS320C64X_INS_NEG,
TMS320C64X_INS_NOT,
TMS320C64X_INS_SWAP2,
TMS320C64X_INS_ZERO,
TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions
} tms320c64x_insn;
typedef enum tms320c64x_insn_group {
TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP
TMS320C64X_GRP_FUNIT_D = 128,
TMS320C64X_GRP_FUNIT_L,
TMS320C64X_GRP_FUNIT_M,
TMS320C64X_GRP_FUNIT_S,
TMS320C64X_GRP_FUNIT_NO,
TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups
} tms320c64x_insn_group;
typedef enum tms320c64x_funit {
TMS320C64X_FUNIT_INVALID = 0,
TMS320C64X_FUNIT_D,
TMS320C64X_FUNIT_L,
TMS320C64X_FUNIT_M,
TMS320C64X_FUNIT_S,
TMS320C64X_FUNIT_NO
} tms320c64x_funit;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/tricore.h
+618
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@@ -0,0 +1,618 @@
#ifndef CAPSTONE_TRICORE_H
#define CAPSTONE_TRICORE_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "cs_operand.h"
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
/// Operand type for instruction's operands
typedef enum tricore_op_type {
TRICORE_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
TRICORE_OP_REG = CS_OP_REG, ///< CS_OP_REG (Register operand).
TRICORE_OP_IMM = CS_OP_IMM, ///< CS_OP_IMM (Immediate operand).
TRICORE_OP_MEM = CS_OP_MEM, ///< CS_OP_MEM (Memory operand).
} tricore_op_type;
/// Instruction's operand referring to memory
/// This is associated with TRICORE_OP_MEM operand type above
typedef struct tricore_op_mem {
uint8_t base; ///< base register
int64_t disp; ///< displacement/offset value
} tricore_op_mem;
/// Instruction operand
typedef struct cs_tricore_op {
tricore_op_type type; ///< operand type
union {
unsigned int reg; ///< register value for REG operand
int64_t imm; ///< immediate value for IMM operand
tricore_op_mem mem; ///< base/disp value for MEM operand
};
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
cs_ac_type
access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
} cs_tricore_op;
#define NUM_TRICORE_OPS 8
/// Instruction structure
typedef struct cs_tricore {
uint8_t op_count; ///< number of operands of this instruction.
cs_tricore_op
operands[NUM_TRICORE_OPS]; ///< operands for this instruction.
/// TODO: Mark the modified flags register in td files and regenerate inc files
bool update_flags; ///< whether the flags register is updated.
} cs_tricore;
/// TriCore registers
typedef enum tricore_reg {
// generated content <TriCoreGenCSRegEnum.inc> begin
// clang-format off
TRICORE_REG_INVALID = 0,
TRICORE_REG_FCX = 1,
TRICORE_REG_PC = 2,
TRICORE_REG_PCXI = 3,
TRICORE_REG_PSW = 4,
TRICORE_REG_A0 = 5,
TRICORE_REG_A1 = 6,
TRICORE_REG_A2 = 7,
TRICORE_REG_A3 = 8,
TRICORE_REG_A4 = 9,
TRICORE_REG_A5 = 10,
TRICORE_REG_A6 = 11,
TRICORE_REG_A7 = 12,
TRICORE_REG_A8 = 13,
TRICORE_REG_A9 = 14,
TRICORE_REG_A10 = 15,
TRICORE_REG_A11 = 16,
TRICORE_REG_A12 = 17,
TRICORE_REG_A13 = 18,
TRICORE_REG_A14 = 19,
TRICORE_REG_A15 = 20,
TRICORE_REG_D0 = 21,
TRICORE_REG_D1 = 22,
TRICORE_REG_D2 = 23,
TRICORE_REG_D3 = 24,
TRICORE_REG_D4 = 25,
TRICORE_REG_D5 = 26,
TRICORE_REG_D6 = 27,
TRICORE_REG_D7 = 28,
TRICORE_REG_D8 = 29,
TRICORE_REG_D9 = 30,
TRICORE_REG_D10 = 31,
TRICORE_REG_D11 = 32,
TRICORE_REG_D12 = 33,
TRICORE_REG_D13 = 34,
TRICORE_REG_D14 = 35,
TRICORE_REG_D15 = 36,
TRICORE_REG_E0 = 37,
TRICORE_REG_E2 = 38,
TRICORE_REG_E4 = 39,
TRICORE_REG_E6 = 40,
TRICORE_REG_E8 = 41,
TRICORE_REG_E10 = 42,
TRICORE_REG_E12 = 43,
TRICORE_REG_E14 = 44,
TRICORE_REG_P0 = 45,
TRICORE_REG_P2 = 46,
TRICORE_REG_P4 = 47,
TRICORE_REG_P6 = 48,
TRICORE_REG_P8 = 49,
TRICORE_REG_P10 = 50,
TRICORE_REG_P12 = 51,
TRICORE_REG_P14 = 52,
TRICORE_REG_A0_A1 = 53,
TRICORE_REG_A2_A3 = 54,
TRICORE_REG_A4_A5 = 55,
TRICORE_REG_A6_A7 = 56,
TRICORE_REG_A8_A9 = 57,
TRICORE_REG_A10_A11 = 58,
TRICORE_REG_A12_A13 = 59,
TRICORE_REG_A14_A15 = 60,
TRICORE_REG_ENDING, // 61
// clang-format on
// generated content <TriCoreGenCSRegEnum.inc> end
} tricore_reg;
/// TriCore instruction
typedef enum tricore_insn {
// generated content <TriCoreGenCSInsnEnum.inc> begin
// clang-format off
TRICORE_INS_INVALID,
TRICORE_INS_ABSDIFS_B,
TRICORE_INS_ABSDIFS_H,
TRICORE_INS_ABSDIFS,
TRICORE_INS_ABSDIF_B,
TRICORE_INS_ABSDIF_H,
TRICORE_INS_ABSDIF,
TRICORE_INS_ABSS_B,
TRICORE_INS_ABSS_H,
TRICORE_INS_ABSS,
TRICORE_INS_ABS_B,
TRICORE_INS_ABS_DF,
TRICORE_INS_ABS_F,
TRICORE_INS_ABS_H,
TRICORE_INS_ABS,
TRICORE_INS_ADDC,
TRICORE_INS_ADDIH_A,
TRICORE_INS_ADDIH,
TRICORE_INS_ADDI,
TRICORE_INS_ADDSC_AT,
TRICORE_INS_ADDSC_A,
TRICORE_INS_ADDS_BU,
TRICORE_INS_ADDS_B,
TRICORE_INS_ADDS_H,
TRICORE_INS_ADDS_HU,
TRICORE_INS_ADDS_U,
TRICORE_INS_ADDS,
TRICORE_INS_ADDX,
TRICORE_INS_ADD_A,
TRICORE_INS_ADD_B,
TRICORE_INS_ADD_DF,
TRICORE_INS_ADD_F,
TRICORE_INS_ADD_H,
TRICORE_INS_ADD,
TRICORE_INS_ANDN_T,
TRICORE_INS_ANDN,
TRICORE_INS_AND_ANDN_T,
TRICORE_INS_AND_AND_T,
TRICORE_INS_AND_EQ,
TRICORE_INS_AND_GE_U,
TRICORE_INS_AND_GE,
TRICORE_INS_AND_LT_U,
TRICORE_INS_AND_LT,
TRICORE_INS_AND_NE,
TRICORE_INS_AND_NOR_T,
TRICORE_INS_AND_OR_T,
TRICORE_INS_AND_T,
TRICORE_INS_AND,
TRICORE_INS_BISR,
TRICORE_INS_BMERGE,
TRICORE_INS_BSPLIT,
TRICORE_INS_CACHEA_I,
TRICORE_INS_CACHEA_WI,
TRICORE_INS_CACHEA_W,
TRICORE_INS_CACHEI_I,
TRICORE_INS_CACHEI_WI,
TRICORE_INS_CACHEI_W,
TRICORE_INS_CADDN_A,
TRICORE_INS_CADDN,
TRICORE_INS_CADD_A,
TRICORE_INS_CADD,
TRICORE_INS_CALLA,
TRICORE_INS_CALLI,
TRICORE_INS_CALL,
TRICORE_INS_CLO_B,
TRICORE_INS_CLO_H,
TRICORE_INS_CLO,
TRICORE_INS_CLS_B,
TRICORE_INS_CLS_H,
TRICORE_INS_CLS,
TRICORE_INS_CLZ_B,
TRICORE_INS_CLZ_H,
TRICORE_INS_CLZ,
TRICORE_INS_CMOVN,
TRICORE_INS_CMOV,
TRICORE_INS_CMPSWAP_W,
TRICORE_INS_CMP_DF,
TRICORE_INS_CMP_F,
TRICORE_INS_CRC32B_W,
TRICORE_INS_CRC32L_W,
TRICORE_INS_CRC32_B,
TRICORE_INS_CRCN,
TRICORE_INS_CSUBN_A,
TRICORE_INS_CSUBN,
TRICORE_INS_CSUB_A,
TRICORE_INS_CSUB,
TRICORE_INS_DEBUG,
TRICORE_INS_DEXTR,
TRICORE_INS_DFTOF,
TRICORE_INS_DFTOIN,
TRICORE_INS_DFTOIZ,
TRICORE_INS_DFTOI,
TRICORE_INS_DFTOLZ,
TRICORE_INS_DFTOL,
TRICORE_INS_DFTOULZ,
TRICORE_INS_DFTOUL,
TRICORE_INS_DFTOUZ,
TRICORE_INS_DFTOU,
TRICORE_INS_DIFSC_A,
TRICORE_INS_DISABLE,
TRICORE_INS_DIV64_U,
TRICORE_INS_DIV64,
TRICORE_INS_DIV_DF,
TRICORE_INS_DIV_F,
TRICORE_INS_DIV_U,
TRICORE_INS_DIV,
TRICORE_INS_DSYNC,
TRICORE_INS_DVADJ,
TRICORE_INS_DVINIT_BU,
TRICORE_INS_DVINIT_B,
TRICORE_INS_DVINIT_HU,
TRICORE_INS_DVINIT_H,
TRICORE_INS_DVINIT_U,
TRICORE_INS_DVINIT,
TRICORE_INS_DVSTEP_U,
TRICORE_INS_DVSTEP,
TRICORE_INS_ENABLE,
TRICORE_INS_EQANY_B,
TRICORE_INS_EQANY_H,
TRICORE_INS_EQZ_A,
TRICORE_INS_EQ_A,
TRICORE_INS_EQ_B,
TRICORE_INS_EQ_H,
TRICORE_INS_EQ_W,
TRICORE_INS_EQ,
TRICORE_INS_EXTR_U,
TRICORE_INS_EXTR,
TRICORE_INS_FCALLA,
TRICORE_INS_FCALLI,
TRICORE_INS_FCALL,
TRICORE_INS_FRET,
TRICORE_INS_FTODF,
TRICORE_INS_FTOHP,
TRICORE_INS_FTOIN,
TRICORE_INS_FTOIZ,
TRICORE_INS_FTOI,
TRICORE_INS_FTOQ31Z,
TRICORE_INS_FTOQ31,
TRICORE_INS_FTOUZ,
TRICORE_INS_FTOU,
TRICORE_INS_GE_A,
TRICORE_INS_GE_U,
TRICORE_INS_GE,
TRICORE_INS_HPTOF,
TRICORE_INS_IMASK,
TRICORE_INS_INSERT,
TRICORE_INS_INSN_T,
TRICORE_INS_INS_T,
TRICORE_INS_ISYNC,
TRICORE_INS_ITODF,
TRICORE_INS_ITOF,
TRICORE_INS_IXMAX_U,
TRICORE_INS_IXMAX,
TRICORE_INS_IXMIN_U,
TRICORE_INS_IXMIN,
TRICORE_INS_JA,
TRICORE_INS_JEQ_A,
TRICORE_INS_JEQ,
TRICORE_INS_JGEZ,
TRICORE_INS_JGE_U,
TRICORE_INS_JGE,
TRICORE_INS_JGTZ,
TRICORE_INS_JI,
TRICORE_INS_JLA,
TRICORE_INS_JLEZ,
TRICORE_INS_JLI,
TRICORE_INS_JLTZ,
TRICORE_INS_JLT_U,
TRICORE_INS_JLT,
TRICORE_INS_JL,
TRICORE_INS_JNED,
TRICORE_INS_JNEI,
TRICORE_INS_JNE_A,
TRICORE_INS_JNE,
TRICORE_INS_JNZ_A,
TRICORE_INS_JNZ_T,
TRICORE_INS_JNZ,
TRICORE_INS_JZ_A,
TRICORE_INS_JZ_T,
TRICORE_INS_JZ,
TRICORE_INS_J,
TRICORE_INS_LDLCX,
TRICORE_INS_LDMST,
TRICORE_INS_LDUCX,
TRICORE_INS_LD_A,
TRICORE_INS_LD_BU,
TRICORE_INS_LD_B,
TRICORE_INS_LD_DA,
TRICORE_INS_LD_D,
TRICORE_INS_LD_HU,
TRICORE_INS_LD_H,
TRICORE_INS_LD_Q,
TRICORE_INS_LD_W,
TRICORE_INS_LEA,
TRICORE_INS_LHA,
TRICORE_INS_LOOPU,
TRICORE_INS_LOOP,
TRICORE_INS_LTODF,
TRICORE_INS_LT_A,
TRICORE_INS_LT_B,
TRICORE_INS_LT_BU,
TRICORE_INS_LT_H,
TRICORE_INS_LT_HU,
TRICORE_INS_LT_U,
TRICORE_INS_LT_W,
TRICORE_INS_LT_WU,
TRICORE_INS_LT,
TRICORE_INS_MADDMS_H,
TRICORE_INS_MADDMS_U,
TRICORE_INS_MADDMS,
TRICORE_INS_MADDM_H,
TRICORE_INS_MADDM_Q,
TRICORE_INS_MADDM_U,
TRICORE_INS_MADDM,
TRICORE_INS_MADDRS_H,
TRICORE_INS_MADDRS_Q,
TRICORE_INS_MADDR_H,
TRICORE_INS_MADDR_Q,
TRICORE_INS_MADDSUMS_H,
TRICORE_INS_MADDSUM_H,
TRICORE_INS_MADDSURS_H,
TRICORE_INS_MADDSUR_H,
TRICORE_INS_MADDSUS_H,
TRICORE_INS_MADDSU_H,
TRICORE_INS_MADDS_H,
TRICORE_INS_MADDS_Q,
TRICORE_INS_MADDS_U,
TRICORE_INS_MADDS,
TRICORE_INS_MADD_DF,
TRICORE_INS_MADD_F,
TRICORE_INS_MADD_H,
TRICORE_INS_MADD_Q,
TRICORE_INS_MADD_U,
TRICORE_INS_MADD,
TRICORE_INS_MAX_B,
TRICORE_INS_MAX_BU,
TRICORE_INS_MAX_DF,
TRICORE_INS_MAX_F,
TRICORE_INS_MAX_H,
TRICORE_INS_MAX_HU,
TRICORE_INS_MAX_U,
TRICORE_INS_MAX,
TRICORE_INS_MFCR,
TRICORE_INS_MIN_B,
TRICORE_INS_MIN_BU,
TRICORE_INS_MIN_DF,
TRICORE_INS_MIN_F,
TRICORE_INS_MIN_H,
TRICORE_INS_MIN_HU,
TRICORE_INS_MIN_U,
TRICORE_INS_MIN,
TRICORE_INS_MOVH_A,
TRICORE_INS_MOVH,
TRICORE_INS_MOVZ_A,
TRICORE_INS_MOV_AA,
TRICORE_INS_MOV_A,
TRICORE_INS_MOV_D,
TRICORE_INS_MOV_U,
TRICORE_INS_MOV,
TRICORE_INS_MSUBADMS_H,
TRICORE_INS_MSUBADM_H,
TRICORE_INS_MSUBADRS_H,
TRICORE_INS_MSUBADR_H,
TRICORE_INS_MSUBADS_H,
TRICORE_INS_MSUBAD_H,
TRICORE_INS_MSUBMS_H,
TRICORE_INS_MSUBMS_U,
TRICORE_INS_MSUBMS,
TRICORE_INS_MSUBM_H,
TRICORE_INS_MSUBM_Q,
TRICORE_INS_MSUBM_U,
TRICORE_INS_MSUBM,
TRICORE_INS_MSUBRS_H,
TRICORE_INS_MSUBRS_Q,
TRICORE_INS_MSUBR_H,
TRICORE_INS_MSUBR_Q,
TRICORE_INS_MSUBS_H,
TRICORE_INS_MSUBS_Q,
TRICORE_INS_MSUBS_U,
TRICORE_INS_MSUBS,
TRICORE_INS_MSUB_DF,
TRICORE_INS_MSUB_F,
TRICORE_INS_MSUB_H,
TRICORE_INS_MSUB_Q,
TRICORE_INS_MSUB_U,
TRICORE_INS_MSUB,
TRICORE_INS_MTCR,
TRICORE_INS_MULMS_H,
TRICORE_INS_MULM_H,
TRICORE_INS_MULM_U,
TRICORE_INS_MULM,
TRICORE_INS_MULR_H,
TRICORE_INS_MULR_Q,
TRICORE_INS_MULS_U,
TRICORE_INS_MULS,
TRICORE_INS_MUL_DF,
TRICORE_INS_MUL_F,
TRICORE_INS_MUL_H,
TRICORE_INS_MUL_Q,
TRICORE_INS_MUL_U,
TRICORE_INS_MUL,
TRICORE_INS_NAND_T,
TRICORE_INS_NAND,
TRICORE_INS_NEG_DF,
TRICORE_INS_NEG_F,
TRICORE_INS_NEZ_A,
TRICORE_INS_NE_A,
TRICORE_INS_NE,
TRICORE_INS_NOP,
TRICORE_INS_NOR_T,
TRICORE_INS_NOR,
TRICORE_INS_NOT,
TRICORE_INS_ORN_T,
TRICORE_INS_ORN,
TRICORE_INS_OR_ANDN_T,
TRICORE_INS_OR_AND_T,
TRICORE_INS_OR_EQ,
TRICORE_INS_OR_GE_U,
TRICORE_INS_OR_GE,
TRICORE_INS_OR_LT_U,
TRICORE_INS_OR_LT,
TRICORE_INS_OR_NE,
TRICORE_INS_OR_NOR_T,
TRICORE_INS_OR_OR_T,
TRICORE_INS_OR_T,
TRICORE_INS_OR,
TRICORE_INS_PACK,
TRICORE_INS_PARITY,
TRICORE_INS_POPCNT_W,
TRICORE_INS_Q31TOF,
TRICORE_INS_QSEED_DF,
TRICORE_INS_QSEED_F,
TRICORE_INS_REM64_U,
TRICORE_INS_REM64,
TRICORE_INS_RESTORE,
TRICORE_INS_RET,
TRICORE_INS_RFE,
TRICORE_INS_RFM,
TRICORE_INS_RSLCX,
TRICORE_INS_RSTV,
TRICORE_INS_RSUBS_U,
TRICORE_INS_RSUBS,
TRICORE_INS_RSUB,
TRICORE_INS_SAT_BU,
TRICORE_INS_SAT_B,
TRICORE_INS_SAT_HU,
TRICORE_INS_SAT_H,
TRICORE_INS_SELN_A,
TRICORE_INS_SELN,
TRICORE_INS_SEL_A,
TRICORE_INS_SEL,
TRICORE_INS_SHAS,
TRICORE_INS_SHA_B,
TRICORE_INS_SHA_H,
TRICORE_INS_SHA,
TRICORE_INS_SHUFFLE,
TRICORE_INS_SH_ANDN_T,
TRICORE_INS_SH_AND_T,
TRICORE_INS_SH_B,
TRICORE_INS_SH_EQ,
TRICORE_INS_SH_GE_U,
TRICORE_INS_SH_GE,
TRICORE_INS_SH_H,
TRICORE_INS_SH_LT_U,
TRICORE_INS_SH_LT,
TRICORE_INS_SH_NAND_T,
TRICORE_INS_SH_NE,
TRICORE_INS_SH_NOR_T,
TRICORE_INS_SH_ORN_T,
TRICORE_INS_SH_OR_T,
TRICORE_INS_SH_XNOR_T,
TRICORE_INS_SH_XOR_T,
TRICORE_INS_SH,
TRICORE_INS_STLCX,
TRICORE_INS_STUCX,
TRICORE_INS_ST_A,
TRICORE_INS_ST_B,
TRICORE_INS_ST_DA,
TRICORE_INS_ST_D,
TRICORE_INS_ST_H,
TRICORE_INS_ST_Q,
TRICORE_INS_ST_T,
TRICORE_INS_ST_W,
TRICORE_INS_SUBC,
TRICORE_INS_SUBSC_A,
TRICORE_INS_SUBS_BU,
TRICORE_INS_SUBS_B,
TRICORE_INS_SUBS_HU,
TRICORE_INS_SUBS_H,
TRICORE_INS_SUBS_U,
TRICORE_INS_SUBS,
TRICORE_INS_SUBX,
TRICORE_INS_SUB_A,
TRICORE_INS_SUB_B,
TRICORE_INS_SUB_DF,
TRICORE_INS_SUB_F,
TRICORE_INS_SUB_H,
TRICORE_INS_SUB,
TRICORE_INS_SVLCX,
TRICORE_INS_SWAPMSK_W,
TRICORE_INS_SWAP_A,
TRICORE_INS_SWAP_W,
TRICORE_INS_SYSCALL,
TRICORE_INS_TLBDEMAP,
TRICORE_INS_TLBFLUSH_A,
TRICORE_INS_TLBFLUSH_B,
TRICORE_INS_TLBMAP,
TRICORE_INS_TLBPROBE_A,
TRICORE_INS_TLBPROBE_I,
TRICORE_INS_TRAPSV,
TRICORE_INS_TRAPV,
TRICORE_INS_ULTODF,
TRICORE_INS_UNPACK,
TRICORE_INS_UPDFL,
TRICORE_INS_UTODF,
TRICORE_INS_UTOF,
TRICORE_INS_WAIT,
TRICORE_INS_XNOR_T,
TRICORE_INS_XNOR,
TRICORE_INS_XOR_EQ,
TRICORE_INS_XOR_GE_U,
TRICORE_INS_XOR_GE,
TRICORE_INS_XOR_LT_U,
TRICORE_INS_XOR_LT,
TRICORE_INS_XOR_NE,
TRICORE_INS_XOR_T,
TRICORE_INS_XOR,
// clang-format on
// generated content <TriCoreGenCSInsnEnum.inc> end
TRICORE_INS_ENDING, // <-- mark the end of the list of instructions
} tricore_insn;
/// Group of TriCore instructions
typedef enum tricore_insn_group {
TRICORE_GRP_INVALID, ///< = CS_GRP_INVALID
/// Generic groups
TRICORE_GRP_CALL, ///< = CS_GRP_CALL
TRICORE_GRP_JUMP, ///< = CS_GRP_JUMP
TRICORE_GRP_ENDING, ///< mark the end of the list of groups
} tricore_insn_group;
typedef enum tricore_feature_t {
TRICORE_FEATURE_INVALID = 0,
// generated content <TriCoreGenCSFeatureEnum.inc> begin
// clang-format off
TRICORE_FEATURE_HASV110 = 128,
TRICORE_FEATURE_HASV120,
TRICORE_FEATURE_HASV130,
TRICORE_FEATURE_HASV131,
TRICORE_FEATURE_HASV160,
TRICORE_FEATURE_HASV161,
TRICORE_FEATURE_HASV162,
TRICORE_FEATURE_HASV180,
TRICORE_FEATURE_HASV120_UP,
TRICORE_FEATURE_HASV130_UP,
TRICORE_FEATURE_HASV131_UP,
TRICORE_FEATURE_HASV160_UP,
TRICORE_FEATURE_HASV161_UP,
TRICORE_FEATURE_HASV162_UP,
TRICORE_FEATURE_HASV180_UP,
TRICORE_FEATURE_HASV120_DN,
TRICORE_FEATURE_HASV130_DN,
TRICORE_FEATURE_HASV131_DN,
TRICORE_FEATURE_HASV160_DN,
TRICORE_FEATURE_HASV161_DN,
TRICORE_FEATURE_HASV162_DN,
TRICORE_FEATURE_HASV180_DN,
// clang-format on
// generated content <TriCoreGenCSFeatureEnum.inc> end
TRICORE_FEATURE_ENDING, ///< mark the end of the list of features
} tricore_feature;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/wasm.h
+251
View File
@@ -0,0 +1,251 @@
/* Capstone Disassembly Engine */
/* By Spike <spikeinhouse@gmail.com>, xwings 2019 */
#ifndef CAPSTONE_WASM_H
#define CAPSTONE_WASM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
typedef enum wasm_op_type {
WASM_OP_INVALID = CS_OP_INVALID,
WASM_OP_IMM = CS_OP_IMM,
WASM_OP_NONE = CS_OP_SPECIAL + 0,
WASM_OP_INT7 = CS_OP_SPECIAL + 1,
WASM_OP_VARUINT32 = CS_OP_SPECIAL + 2,
WASM_OP_VARUINT64 = CS_OP_SPECIAL + 3,
WASM_OP_UINT32 = CS_OP_SPECIAL + 4,
WASM_OP_UINT64 = CS_OP_SPECIAL + 5,
WASM_OP_BRTABLE = CS_OP_SPECIAL + 6,
} wasm_op_type;
typedef struct cs_wasm_brtable {
uint32_t length;
uint64_t address;
uint32_t default_target;
} cs_wasm_brtable;
typedef struct cs_wasm_op {
wasm_op_type type;
uint32_t size;
union {
int8_t int7;
uint32_t varuint32;
uint64_t varuint64;
uint32_t uint32;
uint64_t uint64;
uint32_t immediate[2];
cs_wasm_brtable brtable;
};
} cs_wasm_op;
/// Instruction structure
typedef struct cs_wasm {
uint8_t op_count;
cs_wasm_op operands[2];
} cs_wasm;
/// WASM instruction
typedef enum wasm_insn {
WASM_INS_UNREACHABLE = 0x0,
WASM_INS_NOP = 0x1,
WASM_INS_BLOCK = 0x2,
WASM_INS_LOOP = 0x3,
WASM_INS_IF = 0x4,
WASM_INS_ELSE = 0x5,
WASM_INS_END = 0xb,
WASM_INS_BR = 0xc,
WASM_INS_BR_IF = 0xd,
WASM_INS_BR_TABLE = 0xe,
WASM_INS_RETURN = 0xf,
WASM_INS_CALL = 0x10,
WASM_INS_CALL_INDIRECT = 0x11,
WASM_INS_DROP = 0x1a,
WASM_INS_SELECT = 0x1b,
WASM_INS_GET_LOCAL = 0x20,
WASM_INS_SET_LOCAL = 0x21,
WASM_INS_TEE_LOCAL = 0x22,
WASM_INS_GET_GLOBAL = 0x23,
WASM_INS_SET_GLOBAL = 0x24,
WASM_INS_I32_LOAD = 0x28,
WASM_INS_I64_LOAD = 0x29,
WASM_INS_F32_LOAD = 0x2a,
WASM_INS_F64_LOAD = 0x2b,
WASM_INS_I32_LOAD8_S = 0x2c,
WASM_INS_I32_LOAD8_U = 0x2d,
WASM_INS_I32_LOAD16_S = 0x2e,
WASM_INS_I32_LOAD16_U = 0x2f,
WASM_INS_I64_LOAD8_S = 0x30,
WASM_INS_I64_LOAD8_U = 0x31,
WASM_INS_I64_LOAD16_S = 0x32,
WASM_INS_I64_LOAD16_U = 0x33,
WASM_INS_I64_LOAD32_S = 0x34,
WASM_INS_I64_LOAD32_U = 0x35,
WASM_INS_I32_STORE = 0x36,
WASM_INS_I64_STORE = 0x37,
WASM_INS_F32_STORE = 0x38,
WASM_INS_F64_STORE = 0x39,
WASM_INS_I32_STORE8 = 0x3a,
WASM_INS_I32_STORE16 = 0x3b,
WASM_INS_I64_STORE8 = 0x3c,
WASM_INS_I64_STORE16 = 0x3d,
WASM_INS_I64_STORE32 = 0x3e,
WASM_INS_CURRENT_MEMORY = 0x3f,
WASM_INS_GROW_MEMORY = 0x40,
WASM_INS_I32_CONST = 0x41,
WASM_INS_I64_CONST = 0x42,
WASM_INS_F32_CONST = 0x43,
WASM_INS_F64_CONST = 0x44,
WASM_INS_I32_EQZ = 0x45,
WASM_INS_I32_EQ = 0x46,
WASM_INS_I32_NE = 0x47,
WASM_INS_I32_LT_S = 0x48,
WASM_INS_I32_LT_U = 0x49,
WASM_INS_I32_GT_S = 0x4a,
WASM_INS_I32_GT_U = 0x4b,
WASM_INS_I32_LE_S = 0x4c,
WASM_INS_I32_LE_U = 0x4d,
WASM_INS_I32_GE_S = 0x4e,
WASM_INS_I32_GE_U = 0x4f,
WASM_INS_I64_EQZ = 0x50,
WASM_INS_I64_EQ = 0x51,
WASM_INS_I64_NE = 0x52,
WASM_INS_I64_LT_S = 0x53,
WASM_INS_I64_LT_U = 0x54,
WASN_INS_I64_GT_S = 0x55,
WASM_INS_I64_GT_U = 0x56,
WASM_INS_I64_LE_S = 0x57,
WASM_INS_I64_LE_U = 0x58,
WASM_INS_I64_GE_S = 0x59,
WASM_INS_I64_GE_U = 0x5a,
WASM_INS_F32_EQ = 0x5b,
WASM_INS_F32_NE = 0x5c,
WASM_INS_F32_LT = 0x5d,
WASM_INS_F32_GT = 0x5e,
WASM_INS_F32_LE = 0x5f,
WASM_INS_F32_GE = 0x60,
WASM_INS_F64_EQ = 0x61,
WASM_INS_F64_NE = 0x62,
WASM_INS_F64_LT = 0x63,
WASM_INS_F64_GT = 0x64,
WASM_INS_F64_LE = 0x65,
WASM_INS_F64_GE = 0x66,
WASM_INS_I32_CLZ = 0x67,
WASM_INS_I32_CTZ = 0x68,
WASM_INS_I32_POPCNT = 0x69,
WASM_INS_I32_ADD = 0x6a,
WASM_INS_I32_SUB = 0x6b,
WASM_INS_I32_MUL = 0x6c,
WASM_INS_I32_DIV_S = 0x6d,
WASM_INS_I32_DIV_U = 0x6e,
WASM_INS_I32_REM_S = 0x6f,
WASM_INS_I32_REM_U = 0x70,
WASM_INS_I32_AND = 0x71,
WASM_INS_I32_OR = 0x72,
WASM_INS_I32_XOR = 0x73,
WASM_INS_I32_SHL = 0x74,
WASM_INS_I32_SHR_S = 0x75,
WASM_INS_I32_SHR_U = 0x76,
WASM_INS_I32_ROTL = 0x77,
WASM_INS_I32_ROTR = 0x78,
WASM_INS_I64_CLZ = 0x79,
WASM_INS_I64_CTZ = 0x7a,
WASM_INS_I64_POPCNT = 0x7b,
WASM_INS_I64_ADD = 0x7c,
WASM_INS_I64_SUB = 0x7d,
WASM_INS_I64_MUL = 0x7e,
WASM_INS_I64_DIV_S = 0x7f,
WASM_INS_I64_DIV_U = 0x80,
WASM_INS_I64_REM_S = 0x81,
WASM_INS_I64_REM_U = 0x82,
WASM_INS_I64_AND = 0x83,
WASM_INS_I64_OR = 0x84,
WASM_INS_I64_XOR = 0x85,
WASM_INS_I64_SHL = 0x86,
WASM_INS_I64_SHR_S = 0x87,
WASM_INS_I64_SHR_U = 0x88,
WASM_INS_I64_ROTL = 0x89,
WASM_INS_I64_ROTR = 0x8a,
WASM_INS_F32_ABS = 0x8b,
WASM_INS_F32_NEG = 0x8c,
WASM_INS_F32_CEIL = 0x8d,
WASM_INS_F32_FLOOR = 0x8e,
WASM_INS_F32_TRUNC = 0x8f,
WASM_INS_F32_NEAREST = 0x90,
WASM_INS_F32_SQRT = 0x91,
WASM_INS_F32_ADD = 0x92,
WASM_INS_F32_SUB = 0x93,
WASM_INS_F32_MUL = 0x94,
WASM_INS_F32_DIV = 0x95,
WASM_INS_F32_MIN = 0x96,
WASM_INS_F32_MAX = 0x97,
WASM_INS_F32_COPYSIGN = 0x98,
WASM_INS_F64_ABS = 0x99,
WASM_INS_F64_NEG = 0x9a,
WASM_INS_F64_CEIL = 0x9b,
WASM_INS_F64_FLOOR = 0x9c,
WASM_INS_F64_TRUNC = 0x9d,
WASM_INS_F64_NEAREST = 0x9e,
WASM_INS_F64_SQRT = 0x9f,
WASM_INS_F64_ADD = 0xa0,
WASM_INS_F64_SUB = 0xa1,
WASM_INS_F64_MUL = 0xa2,
WASM_INS_F64_DIV = 0xa3,
WASM_INS_F64_MIN = 0xa4,
WASM_INS_F64_MAX = 0xa5,
WASM_INS_F64_COPYSIGN = 0xa6,
WASM_INS_I32_WARP_I64 = 0xa7,
WASP_INS_I32_TRUNC_S_F32 = 0xa8,
WASM_INS_I32_TRUNC_U_F32 = 0xa9,
WASM_INS_I32_TRUNC_S_F64 = 0xaa,
WASM_INS_I32_TRUNC_U_F64 = 0xab,
WASM_INS_I64_EXTEND_S_I32 = 0xac,
WASM_INS_I64_EXTEND_U_I32 = 0xad,
WASM_INS_I64_TRUNC_S_F32 = 0xae,
WASM_INS_I64_TRUNC_U_F32 = 0xaf,
WASM_INS_I64_TRUNC_S_F64 = 0xb0,
WASM_INS_I64_TRUNC_U_F64 = 0xb1,
WASM_INS_F32_CONVERT_S_I32 = 0xb2,
WASM_INS_F32_CONVERT_U_I32 = 0xb3,
WASM_INS_F32_CONVERT_S_I64 = 0xb4,
WASM_INS_F32_CONVERT_U_I64 = 0xb5,
WASM_INS_F32_DEMOTE_F64 = 0xb6,
WASM_INS_F64_CONVERT_S_I32 = 0xb7,
WASM_INS_F64_CONVERT_U_I32 = 0xb8,
WASM_INS_F64_CONVERT_S_I64 = 0xb9,
WASM_INS_F64_CONVERT_U_I64 = 0xba,
WASM_INS_F64_PROMOTE_F32 = 0xbb,
WASM_INS_I32_REINTERPRET_F32 = 0xbc,
WASM_INS_I64_REINTERPRET_F64 = 0xbd,
WASM_INS_F32_REINTERPRET_I32 = 0xbe,
WASM_INS_F64_REINTERPRET_I64 = 0xbf,
WASM_INS_INVALID = 512,
WASM_INS_ENDING,
} wasm_insn;
/// Group of WASM instructions
typedef enum wasm_insn_group {
WASM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
WASM_GRP_NUMBERIC = 8,
WASM_GRP_PARAMETRIC,
WASM_GRP_VARIABLE,
WASM_GRP_MEMORY,
WASM_GRP_CONTROL,
WASM_GRP_ENDING, ///< <-- mark the end of the list of groups
} wasm_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/x86.h
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include/capstone/xcore.h
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#ifndef CAPSTONE_XCORE_H
#define CAPSTONE_XCORE_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
/// Operand type for instruction's operands
typedef enum xcore_op_type {
XCORE_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
XCORE_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
XCORE_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
XCORE_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} xcore_op_type;
/// XCore registers
typedef enum xcore_reg {
XCORE_REG_INVALID = 0,
XCORE_REG_CP,
XCORE_REG_DP,
XCORE_REG_LR,
XCORE_REG_SP,
XCORE_REG_R0,
XCORE_REG_R1,
XCORE_REG_R2,
XCORE_REG_R3,
XCORE_REG_R4,
XCORE_REG_R5,
XCORE_REG_R6,
XCORE_REG_R7,
XCORE_REG_R8,
XCORE_REG_R9,
XCORE_REG_R10,
XCORE_REG_R11,
// pseudo registers
XCORE_REG_PC, ///< pc
// internal thread registers
// see The-XMOS-XS1-Architecture(X7879A).pdf
XCORE_REG_SCP, ///< save pc
XCORE_REG_SSR, //< save status
XCORE_REG_ET, //< exception type
XCORE_REG_ED, //< exception data
XCORE_REG_SED, //< save exception data
XCORE_REG_KEP, //< kernel entry pointer
XCORE_REG_KSP, //< kernel stack pointer
XCORE_REG_ID, //< thread ID
XCORE_REG_ENDING, // <-- mark the end of the list of registers
} xcore_reg;
/// Instruction's operand referring to memory
/// This is associated with XCORE_OP_MEM operand type above
typedef struct xcore_op_mem {
uint8_t base; ///< base register, can be safely interpreted as
///< a value of type `xcore_reg`, but it is only
///< one byte wide
uint8_t index; ///< index register, same conditions apply here
int32_t disp; ///< displacement/offset value
int direct; ///< +1: forward, -1: backward
} xcore_op_mem;
/// Instruction operand
typedef struct cs_xcore_op {
xcore_op_type type; ///< operand type
union {
xcore_reg reg; ///< register value for REG operand
int32_t imm; ///< immediate value for IMM operand
xcore_op_mem mem; ///< base/disp value for MEM operand
};
} cs_xcore_op;
/// Instruction structure
typedef struct cs_xcore {
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_xcore_op operands[8]; ///< operands for this instruction.
} cs_xcore;
/// XCore instruction
typedef enum xcore_insn {
XCORE_INS_INVALID = 0,
XCORE_INS_ADD,
XCORE_INS_ANDNOT,
XCORE_INS_AND,
XCORE_INS_ASHR,
XCORE_INS_BAU,
XCORE_INS_BITREV,
XCORE_INS_BLA,
XCORE_INS_BLAT,
XCORE_INS_BL,
XCORE_INS_BF,
XCORE_INS_BT,
XCORE_INS_BU,
XCORE_INS_BRU,
XCORE_INS_BYTEREV,
XCORE_INS_CHKCT,
XCORE_INS_CLRE,
XCORE_INS_CLRPT,
XCORE_INS_CLRSR,
XCORE_INS_CLZ,
XCORE_INS_CRC8,
XCORE_INS_CRC32,
XCORE_INS_DCALL,
XCORE_INS_DENTSP,
XCORE_INS_DGETREG,
XCORE_INS_DIVS,
XCORE_INS_DIVU,
XCORE_INS_DRESTSP,
XCORE_INS_DRET,
XCORE_INS_ECALLF,
XCORE_INS_ECALLT,
XCORE_INS_EDU,
XCORE_INS_EEF,
XCORE_INS_EET,
XCORE_INS_EEU,
XCORE_INS_ENDIN,
XCORE_INS_ENTSP,
XCORE_INS_EQ,
XCORE_INS_EXTDP,
XCORE_INS_EXTSP,
XCORE_INS_FREER,
XCORE_INS_FREET,
XCORE_INS_GETD,
XCORE_INS_GET,
XCORE_INS_GETN,
XCORE_INS_GETR,
XCORE_INS_GETSR,
XCORE_INS_GETST,
XCORE_INS_GETTS,
XCORE_INS_INCT,
XCORE_INS_INIT,
XCORE_INS_INPW,
XCORE_INS_INSHR,
XCORE_INS_INT,
XCORE_INS_IN,
XCORE_INS_KCALL,
XCORE_INS_KENTSP,
XCORE_INS_KRESTSP,
XCORE_INS_KRET,
XCORE_INS_LADD,
XCORE_INS_LD16S,
XCORE_INS_LD8U,
XCORE_INS_LDA16,
XCORE_INS_LDAP,
XCORE_INS_LDAW,
XCORE_INS_LDC,
XCORE_INS_LDW,
XCORE_INS_LDIVU,
XCORE_INS_LMUL,
XCORE_INS_LSS,
XCORE_INS_LSUB,
XCORE_INS_LSU,
XCORE_INS_MACCS,
XCORE_INS_MACCU,
XCORE_INS_MJOIN,
XCORE_INS_MKMSK,
XCORE_INS_MSYNC,
XCORE_INS_MUL,
XCORE_INS_NEG,
XCORE_INS_NOT,
XCORE_INS_OR,
XCORE_INS_OUTCT,
XCORE_INS_OUTPW,
XCORE_INS_OUTSHR,
XCORE_INS_OUTT,
XCORE_INS_OUT,
XCORE_INS_PEEK,
XCORE_INS_REMS,
XCORE_INS_REMU,
XCORE_INS_RETSP,
XCORE_INS_SETCLK,
XCORE_INS_SET,
XCORE_INS_SETC,
XCORE_INS_SETD,
XCORE_INS_SETEV,
XCORE_INS_SETN,
XCORE_INS_SETPSC,
XCORE_INS_SETPT,
XCORE_INS_SETRDY,
XCORE_INS_SETSR,
XCORE_INS_SETTW,
XCORE_INS_SETV,
XCORE_INS_SEXT,
XCORE_INS_SHL,
XCORE_INS_SHR,
XCORE_INS_SSYNC,
XCORE_INS_ST16,
XCORE_INS_ST8,
XCORE_INS_STW,
XCORE_INS_SUB,
XCORE_INS_SYNCR,
XCORE_INS_TESTCT,
XCORE_INS_TESTLCL,
XCORE_INS_TESTWCT,
XCORE_INS_TSETMR,
XCORE_INS_START,
XCORE_INS_WAITEF,
XCORE_INS_WAITET,
XCORE_INS_WAITEU,
XCORE_INS_XOR,
XCORE_INS_ZEXT,
XCORE_INS_ENDING, // <-- mark the end of the list of instructions
} xcore_insn;
/// Group of XCore instructions
typedef enum xcore_insn_group {
XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
XCORE_GRP_JUMP, ///< = CS_GRP_JUMP
XCORE_GRP_ENDING, // <-- mark the end of the list of groups
} xcore_insn_group;
#ifdef __cplusplus
}
#endif
#endif
include/capstone/xtensa.h
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