Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'
This commit is contained in:
@@ -0,0 +1,415 @@
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../MCInst.h"
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#include "../../MathExtras.h"
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#include "../../MCInstPrinter.h"
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#include "../../MCDisassembler.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "SystemZMCTargetDesc.h"
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#include "SystemZDisassemblerExtension.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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#define DEBUG_TYPE "systemz-disassembler"
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static DecodeStatus getInstruction(MCInst *Instr, uint16_t *Size,
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const uint8_t *Bytes, size_t BytesLen,
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uint64_t Address, SStream *CStream);
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/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
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/// immediate Value in the MCInst.
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///
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/// @param Value - The immediate Value, has had any PC adjustment made by
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/// the caller.
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/// @param isBranch - If the instruction is a branch instruction
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/// @param Address - The starting address of the instruction
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/// @param Offset - The byte offset to this immediate in the instruction
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/// @param Width - The byte width of this immediate in the instruction
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///
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/// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
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/// called then that function is called to get any symbolic information for the
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/// immediate in the instruction using the Address, Offset and Width. If that
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/// returns non-zero then the symbolic information it returns is used to create
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/// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
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/// returns zero and isBranch is true then a symbol look up for immediate Value
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/// is done and if a symbol is found an MCExpr is created with that, else
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/// an MCExpr with the immediate Value is created. This function returns true
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/// if it adds an operand to the MCInst and false otherwise.
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static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst *MI,
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const void *Decoder)
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{
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// return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch,
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// Offset, Width, /*InstSize=*/0);
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return false;
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}
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static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
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const unsigned *Regs, unsigned Size,
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bool IsAddr)
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{
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CS_ASSERT((RegNo < Size && "Invalid register"));
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if (IsAddr && RegNo == 0) {
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RegNo = SystemZ_NoRegister;
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} else {
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RegNo = Regs[RegNo];
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if (RegNo == 0)
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return MCDisassembler_Fail;
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}
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MCOperand_CreateReg0(Inst, (RegNo));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs, 16, false);
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}
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static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs, 16, false);
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}
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static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs, 16, false);
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}
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static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs, 16, false);
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}
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static DecodeStatus DecodeADDR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs, 16, true);
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}
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static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs, 16, true);
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}
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static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs, 16, false);
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}
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static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs, 16, false);
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}
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static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs, 16, false);
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}
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static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs, 32, false);
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}
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static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs, 32, false);
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}
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static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs, 32, false);
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}
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static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs, 16, false);
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}
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static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs, 16, false);
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}
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#define DEFINE_decodeUImmOperand(N) \
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static DecodeStatus CONCAT(decodeUImmOperand, N)(MCInst * Inst, \
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uint64_t Imm) \
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{ \
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if (!isUIntN(N, Imm)) \
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return MCDisassembler_Fail; \
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MCOperand_CreateImm0(Inst, (Imm)); \
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return MCDisassembler_Success; \
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}
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DEFINE_decodeUImmOperand(1);
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DEFINE_decodeUImmOperand(2);
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DEFINE_decodeUImmOperand(3);
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DEFINE_decodeUImmOperand(4);
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DEFINE_decodeUImmOperand(8);
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DEFINE_decodeUImmOperand(12);
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DEFINE_decodeUImmOperand(16);
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DEFINE_decodeUImmOperand(32);
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#define DEFINE_decodeSImmOperand(N) \
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static DecodeStatus CONCAT(decodeSImmOperand, N)(MCInst * Inst, \
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uint64_t Imm) \
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{ \
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if (!isUIntN(N, Imm)) \
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return MCDisassembler_Fail; \
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MCOperand_CreateImm0(Inst, (SignExtend64((Imm), N))); \
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return MCDisassembler_Success; \
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}
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DEFINE_decodeSImmOperand(8);
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DEFINE_decodeSImmOperand(16);
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DEFINE_decodeSImmOperand(20);
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DEFINE_decodeSImmOperand(32);
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static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 1)(Inst, Imm);
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}
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static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 2)(Inst, Imm);
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}
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static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 3)(Inst, Imm);
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}
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static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 4)(Inst, Imm);
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}
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static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 8)(Inst, Imm);
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}
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static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 12)(Inst, Imm);
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}
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static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 16)(Inst, Imm);
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}
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static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeUImmOperand, 32)(Inst, Imm);
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}
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static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeSImmOperand, 8)(Inst, Imm);
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}
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static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeSImmOperand, 16)(Inst, Imm);
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}
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static DecodeStatus decodeS20ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeSImmOperand, 20)(Inst, Imm);
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}
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static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return CONCAT(decodeSImmOperand, 32)(Inst, Imm);
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}
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#define DEFINE_decodeLenOperand(N) \
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static DecodeStatus CONCAT(decodeLenOperand, \
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N)(MCInst * Inst, uint64_t Imm, \
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uint64_t Address, const void *Decoder) \
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{ \
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if (!isUIntN(N, Imm)) \
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return MCDisassembler_Fail; \
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MCOperand_CreateImm0(Inst, (Imm + 1)); \
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return MCDisassembler_Success; \
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}
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DEFINE_decodeLenOperand(8);
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DEFINE_decodeLenOperand(4);
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#define DEFINE_decodePCDBLOperand(N) \
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static DecodeStatus CONCAT(decodePCDBLOperand, N)( \
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MCInst * Inst, uint64_t Imm, uint64_t Address, bool isBranch, \
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const void *Decoder) \
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{ \
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CS_ASSERT((isUIntN(N, Imm) && "Invalid PC-relative offset")); \
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uint64_t Value = SignExtend64((Imm), N) * 2 + Address; \
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\
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if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, \
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N / 8, Inst, Decoder)) \
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MCOperand_CreateImm0(Inst, (Value)); \
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\
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return MCDisassembler_Success; \
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}
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DEFINE_decodePCDBLOperand(12);
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DEFINE_decodePCDBLOperand(16);
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DEFINE_decodePCDBLOperand(24);
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DEFINE_decodePCDBLOperand(32);
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static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm,
|
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uint64_t Address,
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const void *Decoder)
|
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{
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return CONCAT(decodePCDBLOperand, 12)(Inst, Imm, Address, true,
|
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Decoder);
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}
|
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static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder)
|
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{
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return CONCAT(decodePCDBLOperand, 16)(Inst, Imm, Address, true,
|
||||
Decoder);
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}
|
||||
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||||
static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
return CONCAT(decodePCDBLOperand, 24)(Inst, Imm, Address, true,
|
||||
Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
return CONCAT(decodePCDBLOperand, 32)(Inst, Imm, Address, true,
|
||||
Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
return CONCAT(decodePCDBLOperand, 32)(Inst, Imm, Address, false,
|
||||
Decoder);
|
||||
}
|
||||
|
||||
#include "SystemZGenDisassemblerTables.inc"
|
||||
|
||||
static DecodeStatus getInstruction(MCInst *MI, uint16_t *Size,
|
||||
const uint8_t *Bytes, size_t BytesLen,
|
||||
uint64_t Address, SStream *CS)
|
||||
{
|
||||
// Get the first two bytes of the instruction.
|
||||
*Size = 0;
|
||||
if (BytesLen < 2)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
// The top 2 bits of the first byte specify the size.
|
||||
const uint8_t *Table;
|
||||
uint64_t Inst = 0;
|
||||
if (Bytes[0] < 0x40) {
|
||||
*Size = 2;
|
||||
Table = DecoderTable16;
|
||||
Inst = readBytes16(MI, Bytes);
|
||||
} else if (Bytes[0] < 0xc0) {
|
||||
if (BytesLen < 4) {
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
*Size = 4;
|
||||
Table = DecoderTable32;
|
||||
Inst = readBytes32(MI, Bytes);
|
||||
} else {
|
||||
if (BytesLen < 6) {
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
*Size = 6;
|
||||
Table = DecoderTable48;
|
||||
Inst = readBytes48(MI, Bytes);
|
||||
}
|
||||
|
||||
// Read any remaining bytes.
|
||||
if (BytesLen < *Size) {
|
||||
*Size = BytesLen;
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
|
||||
return decodeInstruction_8(Table, MI, Inst, Address, NULL);
|
||||
}
|
||||
|
||||
DecodeStatus SystemZ_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
|
||||
size_t BytesLen, MCInst *MI,
|
||||
uint16_t *Size, uint64_t Address,
|
||||
void *Info)
|
||||
{
|
||||
return getInstruction(MI, Size, Bytes, BytesLen, MI->address, NULL);
|
||||
}
|
||||
@@ -0,0 +1,118 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Rot127 <unisono@quyllur.org>, 2022-2023 */
|
||||
|
||||
#include <capstone/systemz.h>
|
||||
#include "SystemZDisassemblerExtension.h"
|
||||
#include "../../utils.h"
|
||||
|
||||
#include "SystemZMCTargetDesc.h"
|
||||
|
||||
static int systemz_arch9_features[] = {
|
||||
SystemZ_FeatureDistinctOps,
|
||||
SystemZ_FeatureFastSerialization,
|
||||
SystemZ_FeatureFPExtension,
|
||||
SystemZ_FeatureHighWord,
|
||||
SystemZ_FeatureInterlockedAccess1,
|
||||
SystemZ_FeatureLoadStoreOnCond,
|
||||
SystemZ_FeaturePopulationCount,
|
||||
SystemZ_FeatureMessageSecurityAssist3,
|
||||
SystemZ_FeatureMessageSecurityAssist4,
|
||||
SystemZ_FeatureResetReferenceBitsMultiple
|
||||
};
|
||||
|
||||
static int systemz_arch10_features[] = { SystemZ_FeatureExecutionHint,
|
||||
SystemZ_FeatureLoadAndTrap,
|
||||
SystemZ_FeatureMiscellaneousExtensions,
|
||||
SystemZ_FeatureProcessorAssist,
|
||||
SystemZ_FeatureTransactionalExecution,
|
||||
SystemZ_FeatureDFPZonedConversion,
|
||||
SystemZ_FeatureEnhancedDAT2 };
|
||||
|
||||
static int systemz_arch11_features[] = {
|
||||
SystemZ_FeatureLoadAndZeroRightmostByte,
|
||||
SystemZ_FeatureLoadStoreOnCond2, SystemZ_FeatureMessageSecurityAssist5,
|
||||
SystemZ_FeatureDFPPackedConversion, SystemZ_FeatureVector
|
||||
};
|
||||
|
||||
static int systemz_arch12_features[] = {
|
||||
SystemZ_FeatureMiscellaneousExtensions2,
|
||||
SystemZ_FeatureGuardedStorage,
|
||||
SystemZ_FeatureMessageSecurityAssist7,
|
||||
SystemZ_FeatureMessageSecurityAssist8,
|
||||
SystemZ_FeatureVectorEnhancements1,
|
||||
SystemZ_FeatureVectorPackedDecimal,
|
||||
SystemZ_FeatureInsertReferenceBitsMultiple
|
||||
};
|
||||
|
||||
static int systemz_arch13_features[] = {
|
||||
SystemZ_FeatureMiscellaneousExtensions3,
|
||||
SystemZ_FeatureMessageSecurityAssist9,
|
||||
SystemZ_FeatureVectorEnhancements2,
|
||||
SystemZ_FeatureVectorPackedDecimalEnhancement,
|
||||
SystemZ_FeatureEnhancedSort,
|
||||
SystemZ_FeatureDeflateConversion
|
||||
};
|
||||
|
||||
static int systemz_arch14_features[] = {
|
||||
SystemZ_FeatureVectorPackedDecimalEnhancement2,
|
||||
SystemZ_FeatureNNPAssist, SystemZ_FeatureBEAREnhancement,
|
||||
SystemZ_FeatureResetDATProtection,
|
||||
SystemZ_FeatureProcessorActivityInstrumentation
|
||||
};
|
||||
|
||||
bool SystemZ_getFeatureBits(unsigned int mode, unsigned int feature)
|
||||
{
|
||||
switch (mode & ~CS_MODE_BIG_ENDIAN) {
|
||||
case CS_MODE_SYSTEMZ_ARCH14:
|
||||
case CS_MODE_SYSTEMZ_Z16:
|
||||
if (arr_exist_int(systemz_arch14_features,
|
||||
ARR_SIZE(systemz_arch14_features), feature)) {
|
||||
return true;
|
||||
}
|
||||
// fallthrough
|
||||
case CS_MODE_SYSTEMZ_ARCH13:
|
||||
case CS_MODE_SYSTEMZ_Z15:
|
||||
if (arr_exist_int(systemz_arch13_features,
|
||||
ARR_SIZE(systemz_arch13_features), feature)) {
|
||||
return true;
|
||||
}
|
||||
// fallthrough
|
||||
case CS_MODE_SYSTEMZ_ARCH12:
|
||||
case CS_MODE_SYSTEMZ_Z14:
|
||||
if (arr_exist_int(systemz_arch12_features,
|
||||
ARR_SIZE(systemz_arch12_features), feature)) {
|
||||
return true;
|
||||
}
|
||||
// fallthrough
|
||||
case CS_MODE_SYSTEMZ_ARCH11:
|
||||
case CS_MODE_SYSTEMZ_Z13:
|
||||
if (arr_exist_int(systemz_arch11_features,
|
||||
ARR_SIZE(systemz_arch11_features), feature)) {
|
||||
return true;
|
||||
}
|
||||
// fallthrough
|
||||
case CS_MODE_SYSTEMZ_ARCH10:
|
||||
case CS_MODE_SYSTEMZ_ZEC12:
|
||||
if (arr_exist_int(systemz_arch10_features,
|
||||
ARR_SIZE(systemz_arch10_features), feature)) {
|
||||
return true;
|
||||
}
|
||||
// fallthrough
|
||||
case CS_MODE_SYSTEMZ_ARCH9:
|
||||
case CS_MODE_SYSTEMZ_Z196:
|
||||
if (arr_exist_int(systemz_arch9_features,
|
||||
ARR_SIZE(systemz_arch9_features), feature)) {
|
||||
return true;
|
||||
}
|
||||
// fallthrough
|
||||
case CS_MODE_SYSTEMZ_GENERIC:
|
||||
case CS_MODE_SYSTEMZ_ARCH8:
|
||||
case CS_MODE_SYSTEMZ_Z10:
|
||||
// There are no features defined for Arch8
|
||||
return false;
|
||||
default:
|
||||
// Default case is the "allow all features", which is normal Capstone behavior
|
||||
// until https://github.com/capstone-engine/capstone/issues/1992 is implemented.
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Rot127 <unisono@quyllur.org>, 2022-2023 */
|
||||
|
||||
#ifndef CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H
|
||||
#define CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H
|
||||
|
||||
#include <capstone/capstone.h>
|
||||
|
||||
bool SystemZ_getFeatureBits(unsigned int mode, unsigned int feature);
|
||||
|
||||
#endif // CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H
|
||||
+13192
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,55 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
{ SYSTEMZ_INS_ALIAS_VISTRB, "vistrb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VISTR, "vistr" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFEEB, "vfeeb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFEE, "vfee" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEB, "vfaeb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEBS, "vfaebs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAE, "vfae" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRSB, "vstrsb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRS, "vstrs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCB, "vstrcb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCBS, "vstrcbs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRC, "vstrc" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEH, "vfaeh" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEHS, "vfaehs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEF, "vfaef" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEFS, "vfaefs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEZB, "vfaezb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEZBS, "vfaezbs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEZH, "vfaezh" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEZHS, "vfaezhs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEZF, "vfaezf" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFAEZFS, "vfaezfs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFEEH, "vfeeh" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFEEF, "vfeef" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFENE, "vfene" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFENEB, "vfeneb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFENEH, "vfeneh" },
|
||||
{ SYSTEMZ_INS_ALIAS_VFENEF, "vfenef" },
|
||||
{ SYSTEMZ_INS_ALIAS_VISTRH, "vistrh" },
|
||||
{ SYSTEMZ_INS_ALIAS_VISTRF, "vistrf" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCH, "vstrch" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCHS, "vstrchs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCF, "vstrcf" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCFS, "vstrcfs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCZB, "vstrczb" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCZBS, "vstrczbs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCZH, "vstrczh" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCZHS, "vstrczhs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCZF, "vstrczf" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRCZFS, "vstrczfs" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRSH, "vstrsh" },
|
||||
{ SYSTEMZ_INS_ALIAS_VSTRSF, "vstrsf" },
|
||||
@@ -0,0 +1,55 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
{ SYSTEMZ_FEATURE_FEATURESOFTFLOAT, "FeatureSoftFloat" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREBACKCHAIN, "FeatureBackChain" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, "FeatureDistinctOps" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREFASTSERIALIZATION, "FeatureFastSerialization" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREFPEXTENSION, "FeatureFPExtension" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREHIGHWORD, "FeatureHighWord" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, "FeatureInterlockedAccess1" },
|
||||
{ SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, "FeatureLoadStoreOnCond" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREPOPULATIONCOUNT, "FeaturePopulationCount" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST3, "FeatureMessageSecurityAssist3" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, "FeatureMessageSecurityAssist4" },
|
||||
{ SYSTEMZ_FEATURE_FEATURERESETREFERENCEBITSMULTIPLE, "FeatureResetReferenceBitsMultiple" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT, "FeatureExecutionHint" },
|
||||
{ SYSTEMZ_FEATURE_FEATURELOADANDTRAP, "FeatureLoadAndTrap" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, "FeatureMiscellaneousExtensions" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREPROCESSORASSIST, "FeatureProcessorAssist" },
|
||||
{ SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, "FeatureTransactionalExecution" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, "FeatureDFPZonedConversion" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREENHANCEDDAT2, "FeatureEnhancedDAT2" },
|
||||
{ SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE, "FeatureLoadAndZeroRightmostByte" },
|
||||
{ SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, "FeatureLoadStoreOnCond2" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST5, "FeatureMessageSecurityAssist5" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, "FeatureDFPPackedConversion" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREVECTOR, "FeatureVector" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, "FeatureMiscellaneousExtensions2" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, "FeatureGuardedStorage" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST7, "FeatureMessageSecurityAssist7" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST8, "FeatureMessageSecurityAssist8" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, "FeatureVectorEnhancements1" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, "FeatureVectorPackedDecimal" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREINSERTREFERENCEBITSMULTIPLE, "FeatureInsertReferenceBitsMultiple" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, "FeatureMiscellaneousExtensions3" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST9, "FeatureMessageSecurityAssist9" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, "FeatureVectorEnhancements2" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT, "FeatureVectorPackedDecimalEnhancement" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREENHANCEDSORT, "FeatureEnhancedSort" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREDEFLATECONVERSION, "FeatureDeflateConversion" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, "FeatureVectorPackedDecimalEnhancement2" },
|
||||
{ SYSTEMZ_FEATURE_FEATURENNPASSIST, "FeatureNNPAssist" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT, "FeatureBEAREnhancement" },
|
||||
{ SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, "FeatureResetDATProtection" },
|
||||
{ SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION, "FeatureProcessorActivityInstrumentation" },
|
||||
+24272
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,34 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
SystemZ_OP_GROUP_Operand = 0,
|
||||
SystemZ_OP_GROUP_BDXAddrOperand = 1,
|
||||
SystemZ_OP_GROUP_S32ImmOperand = 2,
|
||||
SystemZ_OP_GROUP_S16ImmOperand = 3,
|
||||
SystemZ_OP_GROUP_BDAddrOperand = 4,
|
||||
SystemZ_OP_GROUP_U32ImmOperand = 5,
|
||||
SystemZ_OP_GROUP_U16ImmOperand = 6,
|
||||
SystemZ_OP_GROUP_S8ImmOperand = 7,
|
||||
SystemZ_OP_GROUP_Cond4Operand = 8,
|
||||
SystemZ_OP_GROUP_U8ImmOperand = 9,
|
||||
SystemZ_OP_GROUP_PCRelOperand = 10,
|
||||
SystemZ_OP_GROUP_U4ImmOperand = 11,
|
||||
SystemZ_OP_GROUP_BDLAddrOperand = 12,
|
||||
SystemZ_OP_GROUP_PCRelTLSOperand = 13,
|
||||
SystemZ_OP_GROUP_U48ImmOperand = 14,
|
||||
SystemZ_OP_GROUP_BDRAddrOperand = 15,
|
||||
SystemZ_OP_GROUP_U12ImmOperand = 16,
|
||||
SystemZ_OP_GROUP_BDVAddrOperand = 17,
|
||||
SystemZ_OP_GROUP_U2ImmOperand = 18,
|
||||
SystemZ_OP_GROUP_U1ImmOperand = 19,
|
||||
SystemZ_OP_GROUP_U3ImmOperand = 20,
|
||||
File diff suppressed because it is too large
Load Diff
+7172
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,953 @@
|
||||
#ifdef GET_REGINFO_ENUM
|
||||
#undef GET_REGINFO_ENUM
|
||||
|
||||
enum {
|
||||
SystemZ_NoRegister,
|
||||
SystemZ_CC = 1,
|
||||
SystemZ_FPC = 2,
|
||||
SystemZ_A0 = 3,
|
||||
SystemZ_A1 = 4,
|
||||
SystemZ_A2 = 5,
|
||||
SystemZ_A3 = 6,
|
||||
SystemZ_A4 = 7,
|
||||
SystemZ_A5 = 8,
|
||||
SystemZ_A6 = 9,
|
||||
SystemZ_A7 = 10,
|
||||
SystemZ_A8 = 11,
|
||||
SystemZ_A9 = 12,
|
||||
SystemZ_A10 = 13,
|
||||
SystemZ_A11 = 14,
|
||||
SystemZ_A12 = 15,
|
||||
SystemZ_A13 = 16,
|
||||
SystemZ_A14 = 17,
|
||||
SystemZ_A15 = 18,
|
||||
SystemZ_C0 = 19,
|
||||
SystemZ_C1 = 20,
|
||||
SystemZ_C2 = 21,
|
||||
SystemZ_C3 = 22,
|
||||
SystemZ_C4 = 23,
|
||||
SystemZ_C5 = 24,
|
||||
SystemZ_C6 = 25,
|
||||
SystemZ_C7 = 26,
|
||||
SystemZ_C8 = 27,
|
||||
SystemZ_C9 = 28,
|
||||
SystemZ_C10 = 29,
|
||||
SystemZ_C11 = 30,
|
||||
SystemZ_C12 = 31,
|
||||
SystemZ_C13 = 32,
|
||||
SystemZ_C14 = 33,
|
||||
SystemZ_C15 = 34,
|
||||
SystemZ_V0 = 35,
|
||||
SystemZ_V1 = 36,
|
||||
SystemZ_V2 = 37,
|
||||
SystemZ_V3 = 38,
|
||||
SystemZ_V4 = 39,
|
||||
SystemZ_V5 = 40,
|
||||
SystemZ_V6 = 41,
|
||||
SystemZ_V7 = 42,
|
||||
SystemZ_V8 = 43,
|
||||
SystemZ_V9 = 44,
|
||||
SystemZ_V10 = 45,
|
||||
SystemZ_V11 = 46,
|
||||
SystemZ_V12 = 47,
|
||||
SystemZ_V13 = 48,
|
||||
SystemZ_V14 = 49,
|
||||
SystemZ_V15 = 50,
|
||||
SystemZ_V16 = 51,
|
||||
SystemZ_V17 = 52,
|
||||
SystemZ_V18 = 53,
|
||||
SystemZ_V19 = 54,
|
||||
SystemZ_V20 = 55,
|
||||
SystemZ_V21 = 56,
|
||||
SystemZ_V22 = 57,
|
||||
SystemZ_V23 = 58,
|
||||
SystemZ_V24 = 59,
|
||||
SystemZ_V25 = 60,
|
||||
SystemZ_V26 = 61,
|
||||
SystemZ_V27 = 62,
|
||||
SystemZ_V28 = 63,
|
||||
SystemZ_V29 = 64,
|
||||
SystemZ_V30 = 65,
|
||||
SystemZ_V31 = 66,
|
||||
SystemZ_F0D = 67,
|
||||
SystemZ_F1D = 68,
|
||||
SystemZ_F2D = 69,
|
||||
SystemZ_F3D = 70,
|
||||
SystemZ_F4D = 71,
|
||||
SystemZ_F5D = 72,
|
||||
SystemZ_F6D = 73,
|
||||
SystemZ_F7D = 74,
|
||||
SystemZ_F8D = 75,
|
||||
SystemZ_F9D = 76,
|
||||
SystemZ_F10D = 77,
|
||||
SystemZ_F11D = 78,
|
||||
SystemZ_F12D = 79,
|
||||
SystemZ_F13D = 80,
|
||||
SystemZ_F14D = 81,
|
||||
SystemZ_F15D = 82,
|
||||
SystemZ_F16D = 83,
|
||||
SystemZ_F17D = 84,
|
||||
SystemZ_F18D = 85,
|
||||
SystemZ_F19D = 86,
|
||||
SystemZ_F20D = 87,
|
||||
SystemZ_F21D = 88,
|
||||
SystemZ_F22D = 89,
|
||||
SystemZ_F23D = 90,
|
||||
SystemZ_F24D = 91,
|
||||
SystemZ_F25D = 92,
|
||||
SystemZ_F26D = 93,
|
||||
SystemZ_F27D = 94,
|
||||
SystemZ_F28D = 95,
|
||||
SystemZ_F29D = 96,
|
||||
SystemZ_F30D = 97,
|
||||
SystemZ_F31D = 98,
|
||||
SystemZ_F0Q = 99,
|
||||
SystemZ_F1Q = 100,
|
||||
SystemZ_F4Q = 101,
|
||||
SystemZ_F5Q = 102,
|
||||
SystemZ_F8Q = 103,
|
||||
SystemZ_F9Q = 104,
|
||||
SystemZ_F12Q = 105,
|
||||
SystemZ_F13Q = 106,
|
||||
SystemZ_F0S = 107,
|
||||
SystemZ_F1S = 108,
|
||||
SystemZ_F2S = 109,
|
||||
SystemZ_F3S = 110,
|
||||
SystemZ_F4S = 111,
|
||||
SystemZ_F5S = 112,
|
||||
SystemZ_F6S = 113,
|
||||
SystemZ_F7S = 114,
|
||||
SystemZ_F8S = 115,
|
||||
SystemZ_F9S = 116,
|
||||
SystemZ_F10S = 117,
|
||||
SystemZ_F11S = 118,
|
||||
SystemZ_F12S = 119,
|
||||
SystemZ_F13S = 120,
|
||||
SystemZ_F14S = 121,
|
||||
SystemZ_F15S = 122,
|
||||
SystemZ_F16S = 123,
|
||||
SystemZ_F17S = 124,
|
||||
SystemZ_F18S = 125,
|
||||
SystemZ_F19S = 126,
|
||||
SystemZ_F20S = 127,
|
||||
SystemZ_F21S = 128,
|
||||
SystemZ_F22S = 129,
|
||||
SystemZ_F23S = 130,
|
||||
SystemZ_F24S = 131,
|
||||
SystemZ_F25S = 132,
|
||||
SystemZ_F26S = 133,
|
||||
SystemZ_F27S = 134,
|
||||
SystemZ_F28S = 135,
|
||||
SystemZ_F29S = 136,
|
||||
SystemZ_F30S = 137,
|
||||
SystemZ_F31S = 138,
|
||||
SystemZ_R0D = 139,
|
||||
SystemZ_R1D = 140,
|
||||
SystemZ_R2D = 141,
|
||||
SystemZ_R3D = 142,
|
||||
SystemZ_R4D = 143,
|
||||
SystemZ_R5D = 144,
|
||||
SystemZ_R6D = 145,
|
||||
SystemZ_R7D = 146,
|
||||
SystemZ_R8D = 147,
|
||||
SystemZ_R9D = 148,
|
||||
SystemZ_R10D = 149,
|
||||
SystemZ_R11D = 150,
|
||||
SystemZ_R12D = 151,
|
||||
SystemZ_R13D = 152,
|
||||
SystemZ_R14D = 153,
|
||||
SystemZ_R15D = 154,
|
||||
SystemZ_R0H = 155,
|
||||
SystemZ_R1H = 156,
|
||||
SystemZ_R2H = 157,
|
||||
SystemZ_R3H = 158,
|
||||
SystemZ_R4H = 159,
|
||||
SystemZ_R5H = 160,
|
||||
SystemZ_R6H = 161,
|
||||
SystemZ_R7H = 162,
|
||||
SystemZ_R8H = 163,
|
||||
SystemZ_R9H = 164,
|
||||
SystemZ_R10H = 165,
|
||||
SystemZ_R11H = 166,
|
||||
SystemZ_R12H = 167,
|
||||
SystemZ_R13H = 168,
|
||||
SystemZ_R14H = 169,
|
||||
SystemZ_R15H = 170,
|
||||
SystemZ_R0L = 171,
|
||||
SystemZ_R1L = 172,
|
||||
SystemZ_R2L = 173,
|
||||
SystemZ_R3L = 174,
|
||||
SystemZ_R4L = 175,
|
||||
SystemZ_R5L = 176,
|
||||
SystemZ_R6L = 177,
|
||||
SystemZ_R7L = 178,
|
||||
SystemZ_R8L = 179,
|
||||
SystemZ_R9L = 180,
|
||||
SystemZ_R10L = 181,
|
||||
SystemZ_R11L = 182,
|
||||
SystemZ_R12L = 183,
|
||||
SystemZ_R13L = 184,
|
||||
SystemZ_R14L = 185,
|
||||
SystemZ_R15L = 186,
|
||||
SystemZ_R0Q = 187,
|
||||
SystemZ_R2Q = 188,
|
||||
SystemZ_R4Q = 189,
|
||||
SystemZ_R6Q = 190,
|
||||
SystemZ_R8Q = 191,
|
||||
SystemZ_R10Q = 192,
|
||||
SystemZ_R12Q = 193,
|
||||
SystemZ_R14Q = 194,
|
||||
NUM_TARGET_REGS // 195
|
||||
};
|
||||
|
||||
// Register classes
|
||||
|
||||
enum {
|
||||
SystemZ_GRX32BitRegClassID = 0,
|
||||
SystemZ_VR32BitRegClassID = 1,
|
||||
SystemZ_AR32BitRegClassID = 2,
|
||||
SystemZ_FP32BitRegClassID = 3,
|
||||
SystemZ_GR32BitRegClassID = 4,
|
||||
SystemZ_GRH32BitRegClassID = 5,
|
||||
SystemZ_ADDR32BitRegClassID = 6,
|
||||
SystemZ_CCRRegClassID = 7,
|
||||
SystemZ_FPCRegsRegClassID = 8,
|
||||
SystemZ_AnyRegBitRegClassID = 9,
|
||||
SystemZ_AnyRegBit_with_subreg_h32_in_FP32BitRegClassID = 10,
|
||||
SystemZ_VR64BitRegClassID = 11,
|
||||
SystemZ_AnyRegBit_with_subreg_h64RegClassID = 12,
|
||||
SystemZ_CR64BitRegClassID = 13,
|
||||
SystemZ_FP64BitRegClassID = 14,
|
||||
SystemZ_GR64BitRegClassID = 15,
|
||||
SystemZ_ADDR64BitRegClassID = 16,
|
||||
SystemZ_VR128BitRegClassID = 17,
|
||||
SystemZ_VF128BitRegClassID = 18,
|
||||
SystemZ_FP128BitRegClassID = 19,
|
||||
SystemZ_GR128BitRegClassID = 20,
|
||||
SystemZ_ADDR128BitRegClassID = 21,
|
||||
|
||||
};
|
||||
|
||||
// Subregister indices
|
||||
|
||||
enum {
|
||||
SystemZ_NoSubRegister,
|
||||
SystemZ_subreg_h32, // 1
|
||||
SystemZ_subreg_h64, // 2
|
||||
SystemZ_subreg_l32, // 3
|
||||
SystemZ_subreg_l64, // 4
|
||||
SystemZ_subreg_lh32, // 5
|
||||
SystemZ_subreg_ll32, // 6
|
||||
SystemZ_NUM_TARGET_SUBREGS
|
||||
};
|
||||
#endif // GET_REGINFO_ENUM
|
||||
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static const MCPhysReg SystemZRegDiffLists[] = {
|
||||
/* 0 */ -40, -32, 0,
|
||||
/* 3 */ -48, 32, -16, -15, 32, -16, 0,
|
||||
/* 10 */ -47, 32, -16, -15, 32, -16, 0,
|
||||
/* 17 */ -46, 32, -16, -15, 32, -16, 0,
|
||||
/* 24 */ -45, 32, -16, -15, 32, -16, 0,
|
||||
/* 31 */ -44, 32, -16, -15, 32, -16, 0,
|
||||
/* 38 */ -43, 32, -16, -15, 32, -16, 0,
|
||||
/* 45 */ -42, 32, -16, -15, 32, -16, 0,
|
||||
/* 52 */ -41, 32, -16, -15, 32, -16, 0,
|
||||
/* 59 */ 1, 1, 1, 0,
|
||||
/* 63 */ 2, 0,
|
||||
/* 65 */ -32, 40, -38, 40, 0,
|
||||
/* 70 */ -30, 40, -38, 40, 0,
|
||||
/* 75 */ -28, 40, -38, 40, 0,
|
||||
/* 80 */ -26, 40, -38, 40, 0,
|
||||
/* 85 */ -32, 40, 0,
|
||||
/* 88 */ -16, 40, 0,
|
||||
/* 91 */ 32, 40, 0,
|
||||
/* 94 */ -32, 41, 0,
|
||||
/* 97 */ -16, 41, 0,
|
||||
/* 100 */ -32, 42, 0,
|
||||
/* 103 */ -16, 42, 0,
|
||||
/* 106 */ -32, 43, 0,
|
||||
/* 109 */ -16, 43, 0,
|
||||
/* 112 */ -32, 44, 0,
|
||||
/* 115 */ -16, 44, 0,
|
||||
/* 118 */ -32, 45, 0,
|
||||
/* 121 */ -16, 45, 0,
|
||||
/* 124 */ -32, 46, 0,
|
||||
/* 127 */ -16, 46, 0,
|
||||
/* 130 */ -32, 47, 0,
|
||||
/* 133 */ -16, 47, 0,
|
||||
/* 136 */ -32, 48, 0,
|
||||
/* 139 */ -16, 48, 0,
|
||||
/* 142 */ -40, -32, 56, 0,
|
||||
/* 146 */ -40, -32, 58, 0,
|
||||
/* 150 */ -40, -32, 60, 0,
|
||||
/* 154 */ -40, -32, 62, 0,
|
||||
/* 158 */ -40, -32, 64, 0,
|
||||
};
|
||||
|
||||
static const uint16_t SystemZSubRegIdxLists[] = {
|
||||
/* 0 */ 2, 1, 0,
|
||||
/* 3 */ 3, 1, 0,
|
||||
/* 6 */ 2, 1, 4, 5, 0,
|
||||
/* 11 */ 2, 3, 1, 4, 6, 5, 0,
|
||||
};
|
||||
|
||||
static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
|
||||
{ 3, 0, 0, 0, 0, 0 },
|
||||
{ 226, 2, 2, 2, 8192, 11 },
|
||||
{ 229, 2, 2, 2, 8193, 11 },
|
||||
{ 20, 2, 2, 2, 8194, 11 },
|
||||
{ 49, 2, 2, 2, 8195, 11 },
|
||||
{ 74, 2, 2, 2, 8196, 11 },
|
||||
{ 99, 2, 2, 2, 8197, 11 },
|
||||
{ 124, 2, 2, 2, 8198, 11 },
|
||||
{ 149, 2, 2, 2, 8199, 11 },
|
||||
{ 166, 2, 2, 2, 8200, 11 },
|
||||
{ 183, 2, 2, 2, 8201, 11 },
|
||||
{ 200, 2, 2, 2, 8202, 11 },
|
||||
{ 217, 2, 2, 2, 8203, 11 },
|
||||
{ 0, 2, 2, 2, 8204, 11 },
|
||||
{ 29, 2, 2, 2, 8205, 11 },
|
||||
{ 58, 2, 2, 2, 8206, 11 },
|
||||
{ 83, 2, 2, 2, 8207, 11 },
|
||||
{ 108, 2, 2, 2, 8208, 11 },
|
||||
{ 133, 2, 2, 2, 8209, 11 },
|
||||
{ 23, 2, 2, 2, 8210, 11 },
|
||||
{ 52, 2, 2, 2, 8211, 11 },
|
||||
{ 77, 2, 2, 2, 8212, 11 },
|
||||
{ 102, 2, 2, 2, 8213, 11 },
|
||||
{ 127, 2, 2, 2, 8214, 11 },
|
||||
{ 152, 2, 2, 2, 8215, 11 },
|
||||
{ 169, 2, 2, 2, 8216, 11 },
|
||||
{ 186, 2, 2, 2, 8217, 11 },
|
||||
{ 203, 2, 2, 2, 8218, 11 },
|
||||
{ 220, 2, 2, 2, 8219, 11 },
|
||||
{ 4, 2, 2, 2, 8220, 11 },
|
||||
{ 33, 2, 2, 2, 8221, 11 },
|
||||
{ 62, 2, 2, 2, 8222, 11 },
|
||||
{ 87, 2, 2, 2, 8223, 11 },
|
||||
{ 112, 2, 2, 2, 8224, 11 },
|
||||
{ 137, 2, 2, 2, 8225, 11 },
|
||||
{ 26, 91, 2, 0, 8226, 1 },
|
||||
{ 55, 91, 2, 0, 8227, 1 },
|
||||
{ 80, 91, 2, 0, 8228, 1 },
|
||||
{ 105, 91, 2, 0, 8229, 1 },
|
||||
{ 130, 91, 2, 0, 8230, 1 },
|
||||
{ 155, 91, 2, 0, 8231, 1 },
|
||||
{ 172, 91, 2, 0, 8232, 1 },
|
||||
{ 189, 91, 2, 0, 8233, 1 },
|
||||
{ 206, 91, 2, 0, 8234, 1 },
|
||||
{ 223, 91, 2, 0, 8235, 1 },
|
||||
{ 8, 91, 2, 0, 8236, 1 },
|
||||
{ 37, 91, 2, 0, 8237, 1 },
|
||||
{ 66, 91, 2, 0, 8238, 1 },
|
||||
{ 91, 91, 2, 0, 8239, 1 },
|
||||
{ 116, 91, 2, 0, 8240, 1 },
|
||||
{ 141, 91, 2, 0, 8241, 1 },
|
||||
{ 158, 91, 2, 0, 8242, 1 },
|
||||
{ 175, 91, 2, 0, 8243, 1 },
|
||||
{ 192, 91, 2, 0, 8244, 1 },
|
||||
{ 209, 91, 2, 0, 8245, 1 },
|
||||
{ 12, 91, 2, 0, 8246, 1 },
|
||||
{ 41, 91, 2, 0, 8247, 1 },
|
||||
{ 70, 91, 2, 0, 8248, 1 },
|
||||
{ 95, 91, 2, 0, 8249, 1 },
|
||||
{ 120, 91, 2, 0, 8250, 1 },
|
||||
{ 145, 91, 2, 0, 8251, 1 },
|
||||
{ 162, 91, 2, 0, 8252, 1 },
|
||||
{ 179, 91, 2, 0, 8253, 1 },
|
||||
{ 196, 91, 2, 0, 8254, 1 },
|
||||
{ 213, 91, 2, 0, 8255, 1 },
|
||||
{ 16, 91, 2, 0, 8256, 1 },
|
||||
{ 45, 91, 2, 0, 8257, 1 },
|
||||
{ 253, 68, 159, 1, 8226, 1 },
|
||||
{ 281, 68, 159, 1, 8227, 1 },
|
||||
{ 304, 68, 155, 1, 8228, 1 },
|
||||
{ 327, 68, 155, 1, 8229, 1 },
|
||||
{ 350, 68, 155, 1, 8230, 1 },
|
||||
{ 373, 68, 155, 1, 8231, 1 },
|
||||
{ 391, 68, 151, 1, 8232, 1 },
|
||||
{ 409, 68, 151, 1, 8233, 1 },
|
||||
{ 427, 68, 151, 1, 8234, 1 },
|
||||
{ 445, 68, 151, 1, 8235, 1 },
|
||||
{ 233, 68, 147, 1, 8236, 1 },
|
||||
{ 261, 68, 147, 1, 8237, 1 },
|
||||
{ 289, 68, 147, 1, 8238, 1 },
|
||||
{ 312, 68, 147, 1, 8239, 1 },
|
||||
{ 335, 68, 143, 1, 8240, 1 },
|
||||
{ 358, 68, 143, 1, 8241, 1 },
|
||||
{ 381, 68, 1, 1, 8242, 1 },
|
||||
{ 399, 68, 1, 1, 8243, 1 },
|
||||
{ 417, 68, 1, 1, 8244, 1 },
|
||||
{ 435, 68, 1, 1, 8245, 1 },
|
||||
{ 243, 68, 1, 1, 8246, 1 },
|
||||
{ 271, 68, 1, 1, 8247, 1 },
|
||||
{ 299, 68, 1, 1, 8248, 1 },
|
||||
{ 322, 68, 1, 1, 8249, 1 },
|
||||
{ 345, 68, 1, 1, 8250, 1 },
|
||||
{ 368, 68, 1, 1, 8251, 1 },
|
||||
{ 386, 68, 1, 1, 8252, 1 },
|
||||
{ 404, 68, 1, 1, 8253, 1 },
|
||||
{ 422, 68, 1, 1, 8254, 1 },
|
||||
{ 440, 68, 1, 1, 8255, 1 },
|
||||
{ 248, 68, 1, 1, 8256, 1 },
|
||||
{ 276, 68, 1, 1, 8257, 1 },
|
||||
{ 598, 65, 2, 6, 258082, 3 },
|
||||
{ 606, 65, 2, 6, 258083, 3 },
|
||||
{ 634, 70, 2, 6, 258086, 3 },
|
||||
{ 642, 70, 2, 6, 258087, 3 },
|
||||
{ 650, 75, 2, 6, 258090, 3 },
|
||||
{ 658, 75, 2, 6, 258091, 3 },
|
||||
{ 610, 80, 2, 6, 258094, 3 },
|
||||
{ 624, 80, 2, 6, 258095, 3 },
|
||||
{ 677, 2, 158, 2, 8226, 11 },
|
||||
{ 696, 2, 158, 2, 8227, 11 },
|
||||
{ 710, 2, 154, 2, 8228, 11 },
|
||||
{ 724, 2, 154, 2, 8229, 11 },
|
||||
{ 738, 2, 154, 2, 8230, 11 },
|
||||
{ 752, 2, 154, 2, 8231, 11 },
|
||||
{ 766, 2, 150, 2, 8232, 11 },
|
||||
{ 780, 2, 150, 2, 8233, 11 },
|
||||
{ 794, 2, 150, 2, 8234, 11 },
|
||||
{ 808, 2, 150, 2, 8235, 11 },
|
||||
{ 662, 2, 146, 2, 8236, 11 },
|
||||
{ 681, 2, 146, 2, 8237, 11 },
|
||||
{ 700, 2, 146, 2, 8238, 11 },
|
||||
{ 714, 2, 146, 2, 8239, 11 },
|
||||
{ 728, 2, 142, 2, 8240, 11 },
|
||||
{ 742, 2, 142, 2, 8241, 11 },
|
||||
{ 756, 2, 0, 2, 8242, 11 },
|
||||
{ 770, 2, 0, 2, 8243, 11 },
|
||||
{ 784, 2, 0, 2, 8244, 11 },
|
||||
{ 798, 2, 0, 2, 8245, 11 },
|
||||
{ 667, 2, 0, 2, 8246, 11 },
|
||||
{ 686, 2, 0, 2, 8247, 11 },
|
||||
{ 705, 2, 0, 2, 8248, 11 },
|
||||
{ 719, 2, 0, 2, 8249, 11 },
|
||||
{ 733, 2, 0, 2, 8250, 11 },
|
||||
{ 747, 2, 0, 2, 8251, 11 },
|
||||
{ 761, 2, 0, 2, 8252, 11 },
|
||||
{ 775, 2, 0, 2, 8253, 11 },
|
||||
{ 789, 2, 0, 2, 8254, 11 },
|
||||
{ 803, 2, 0, 2, 8255, 11 },
|
||||
{ 672, 2, 0, 2, 8256, 11 },
|
||||
{ 691, 2, 0, 2, 8257, 11 },
|
||||
{ 257, 7, 137, 3, 249922, 0 },
|
||||
{ 285, 7, 131, 3, 249924, 0 },
|
||||
{ 308, 7, 131, 3, 249926, 0 },
|
||||
{ 331, 7, 125, 3, 249928, 0 },
|
||||
{ 354, 7, 125, 3, 249930, 0 },
|
||||
{ 377, 7, 119, 3, 249932, 0 },
|
||||
{ 395, 7, 119, 3, 249934, 0 },
|
||||
{ 413, 7, 113, 3, 249936, 0 },
|
||||
{ 431, 7, 113, 3, 249938, 0 },
|
||||
{ 449, 7, 107, 3, 249940, 0 },
|
||||
{ 238, 7, 107, 3, 249942, 0 },
|
||||
{ 266, 7, 101, 3, 249944, 0 },
|
||||
{ 294, 7, 101, 3, 249946, 0 },
|
||||
{ 317, 7, 95, 3, 249948, 0 },
|
||||
{ 340, 7, 95, 3, 249950, 0 },
|
||||
{ 363, 7, 68, 3, 249952, 0 },
|
||||
{ 458, 2, 139, 2, 8259, 11 },
|
||||
{ 467, 2, 133, 2, 8261, 11 },
|
||||
{ 476, 2, 133, 2, 8263, 11 },
|
||||
{ 485, 2, 127, 2, 8265, 11 },
|
||||
{ 494, 2, 127, 2, 8267, 11 },
|
||||
{ 503, 2, 121, 2, 8269, 11 },
|
||||
{ 507, 2, 121, 2, 8271, 11 },
|
||||
{ 511, 2, 115, 2, 8273, 11 },
|
||||
{ 515, 2, 115, 2, 8275, 11 },
|
||||
{ 519, 2, 109, 2, 8277, 11 },
|
||||
{ 453, 2, 109, 2, 8279, 11 },
|
||||
{ 462, 2, 103, 2, 8281, 11 },
|
||||
{ 471, 2, 103, 2, 8283, 11 },
|
||||
{ 480, 2, 97, 2, 8285, 11 },
|
||||
{ 489, 2, 97, 2, 8287, 11 },
|
||||
{ 498, 2, 88, 2, 8289, 11 },
|
||||
{ 528, 2, 136, 2, 8258, 11 },
|
||||
{ 537, 2, 130, 2, 8260, 11 },
|
||||
{ 546, 2, 130, 2, 8262, 11 },
|
||||
{ 555, 2, 124, 2, 8264, 11 },
|
||||
{ 564, 2, 124, 2, 8266, 11 },
|
||||
{ 573, 2, 118, 2, 8268, 11 },
|
||||
{ 577, 2, 118, 2, 8270, 11 },
|
||||
{ 581, 2, 112, 2, 8272, 11 },
|
||||
{ 585, 2, 112, 2, 8274, 11 },
|
||||
{ 589, 2, 106, 2, 8276, 11 },
|
||||
{ 523, 2, 106, 2, 8278, 11 },
|
||||
{ 532, 2, 100, 2, 8280, 11 },
|
||||
{ 541, 2, 100, 2, 8282, 11 },
|
||||
{ 550, 2, 94, 2, 8284, 11 },
|
||||
{ 559, 2, 94, 2, 8286, 11 },
|
||||
{ 568, 2, 85, 2, 8288, 11 },
|
||||
{ 602, 3, 2, 11, 241730, 6 },
|
||||
{ 620, 10, 2, 11, 241734, 6 },
|
||||
{ 638, 17, 2, 11, 241738, 6 },
|
||||
{ 646, 24, 2, 11, 241742, 6 },
|
||||
{ 654, 31, 2, 11, 241746, 6 },
|
||||
{ 593, 38, 2, 11, 241750, 6 },
|
||||
{ 615, 45, 2, 11, 241754, 6 },
|
||||
{ 629, 52, 2, 11, 241758, 6 },
|
||||
};
|
||||
|
||||
// GRX32Bit Register Class...
|
||||
static const MCPhysReg GRX32Bit[] = {
|
||||
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H,
|
||||
};
|
||||
|
||||
// GRX32Bit Bit set.
|
||||
static const uint8_t GRX32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// VR32Bit Register Class...
|
||||
static const MCPhysReg VR32Bit[] = {
|
||||
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
|
||||
};
|
||||
|
||||
// VR32Bit Bit set.
|
||||
static const uint8_t VR32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// AR32Bit Register Class...
|
||||
static const MCPhysReg AR32Bit[] = {
|
||||
SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15,
|
||||
};
|
||||
|
||||
// AR32Bit Bit set.
|
||||
static const uint8_t AR32BitBits[] = {
|
||||
0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// FP32Bit Register Class...
|
||||
static const MCPhysReg FP32Bit[] = {
|
||||
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
|
||||
};
|
||||
|
||||
// FP32Bit Bit set.
|
||||
static const uint8_t FP32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// GR32Bit Register Class...
|
||||
static const MCPhysReg GR32Bit[] = {
|
||||
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
|
||||
};
|
||||
|
||||
// GR32Bit Bit set.
|
||||
static const uint8_t GR32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// GRH32Bit Register Class...
|
||||
static const MCPhysReg GRH32Bit[] = {
|
||||
SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H,
|
||||
};
|
||||
|
||||
// GRH32Bit Bit set.
|
||||
static const uint8_t GRH32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// ADDR32Bit Register Class...
|
||||
static const MCPhysReg ADDR32Bit[] = {
|
||||
SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
|
||||
};
|
||||
|
||||
// ADDR32Bit Bit set.
|
||||
static const uint8_t ADDR32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// CCR Register Class...
|
||||
static const MCPhysReg CCR[] = {
|
||||
SystemZ_CC,
|
||||
};
|
||||
|
||||
// CCR Bit set.
|
||||
static const uint8_t CCRBits[] = {
|
||||
0x02,
|
||||
};
|
||||
|
||||
// FPCRegs Register Class...
|
||||
static const MCPhysReg FPCRegs[] = {
|
||||
SystemZ_FPC,
|
||||
};
|
||||
|
||||
// FPCRegs Bit set.
|
||||
static const uint8_t FPCRegsBits[] = {
|
||||
0x04,
|
||||
};
|
||||
|
||||
// AnyRegBit Register Class...
|
||||
static const MCPhysReg AnyRegBit[] = {
|
||||
SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
||||
};
|
||||
|
||||
// AnyRegBit Bit set.
|
||||
static const uint8_t AnyRegBitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// AnyRegBit_with_subreg_h32_in_FP32Bit Register Class...
|
||||
static const MCPhysReg AnyRegBit_with_subreg_h32_in_FP32Bit[] = {
|
||||
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
||||
};
|
||||
|
||||
// AnyRegBit_with_subreg_h32_in_FP32Bit Bit set.
|
||||
static const uint8_t AnyRegBit_with_subreg_h32_in_FP32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// VR64Bit Register Class...
|
||||
static const MCPhysReg VR64Bit[] = {
|
||||
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
|
||||
};
|
||||
|
||||
// VR64Bit Bit set.
|
||||
static const uint8_t VR64BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// AnyRegBit_with_subreg_h64 Register Class...
|
||||
static const MCPhysReg AnyRegBit_with_subreg_h64[] = {
|
||||
SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
||||
};
|
||||
|
||||
// AnyRegBit_with_subreg_h64 Bit set.
|
||||
static const uint8_t AnyRegBit_with_subreg_h64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// CR64Bit Register Class...
|
||||
static const MCPhysReg CR64Bit[] = {
|
||||
SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15,
|
||||
};
|
||||
|
||||
// CR64Bit Bit set.
|
||||
static const uint8_t CR64BitBits[] = {
|
||||
0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// FP64Bit Register Class...
|
||||
static const MCPhysReg FP64Bit[] = {
|
||||
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
|
||||
};
|
||||
|
||||
// FP64Bit Bit set.
|
||||
static const uint8_t FP64BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// GR64Bit Register Class...
|
||||
static const MCPhysReg GR64Bit[] = {
|
||||
SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
|
||||
};
|
||||
|
||||
// GR64Bit Bit set.
|
||||
static const uint8_t GR64BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// ADDR64Bit Register Class...
|
||||
static const MCPhysReg ADDR64Bit[] = {
|
||||
SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
|
||||
};
|
||||
|
||||
// ADDR64Bit Bit set.
|
||||
static const uint8_t ADDR64BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// VR128Bit Register Class...
|
||||
static const MCPhysReg VR128Bit[] = {
|
||||
SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
||||
};
|
||||
|
||||
// VR128Bit Bit set.
|
||||
static const uint8_t VR128BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// VF128Bit Register Class...
|
||||
static const MCPhysReg VF128Bit[] = {
|
||||
SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
||||
};
|
||||
|
||||
// VF128Bit Bit set.
|
||||
static const uint8_t VF128BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// FP128Bit Register Class...
|
||||
static const MCPhysReg FP128Bit[] = {
|
||||
SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q,
|
||||
};
|
||||
|
||||
// FP128Bit Bit set.
|
||||
static const uint8_t FP128BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
||||
};
|
||||
|
||||
// GR128Bit Register Class...
|
||||
static const MCPhysReg GR128Bit[] = {
|
||||
SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
|
||||
};
|
||||
|
||||
// GR128Bit Bit set.
|
||||
static const uint8_t GR128BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
||||
};
|
||||
|
||||
// ADDR128Bit Register Class...
|
||||
static const MCPhysReg ADDR128Bit[] = {
|
||||
SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
|
||||
};
|
||||
|
||||
// ADDR128Bit Bit set.
|
||||
static const uint8_t ADDR128BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
|
||||
};
|
||||
|
||||
static const MCRegisterClass SystemZMCRegisterClasses[] = {
|
||||
{ GRX32Bit, GRX32BitBits, sizeof(GRX32BitBits) },
|
||||
{ VR32Bit, VR32BitBits, sizeof(VR32BitBits) },
|
||||
{ AR32Bit, AR32BitBits, sizeof(AR32BitBits) },
|
||||
{ FP32Bit, FP32BitBits, sizeof(FP32BitBits) },
|
||||
{ GR32Bit, GR32BitBits, sizeof(GR32BitBits) },
|
||||
{ GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits) },
|
||||
{ ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits) },
|
||||
{ CCR, CCRBits, sizeof(CCRBits) },
|
||||
{ FPCRegs, FPCRegsBits, sizeof(FPCRegsBits) },
|
||||
{ AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits) },
|
||||
{ AnyRegBit_with_subreg_h32_in_FP32Bit, AnyRegBit_with_subreg_h32_in_FP32BitBits, sizeof(AnyRegBit_with_subreg_h32_in_FP32BitBits) },
|
||||
{ VR64Bit, VR64BitBits, sizeof(VR64BitBits) },
|
||||
{ AnyRegBit_with_subreg_h64, AnyRegBit_with_subreg_h64Bits, sizeof(AnyRegBit_with_subreg_h64Bits) },
|
||||
{ CR64Bit, CR64BitBits, sizeof(CR64BitBits) },
|
||||
{ FP64Bit, FP64BitBits, sizeof(FP64BitBits) },
|
||||
{ GR64Bit, GR64BitBits, sizeof(GR64BitBits) },
|
||||
{ ADDR64Bit, ADDR64BitBits, sizeof(ADDR64BitBits) },
|
||||
{ VR128Bit, VR128BitBits, sizeof(VR128BitBits) },
|
||||
{ VF128Bit, VF128BitBits, sizeof(VF128BitBits) },
|
||||
{ FP128Bit, FP128BitBits, sizeof(FP128BitBits) },
|
||||
{ GR128Bit, GR128BitBits, sizeof(GR128BitBits) },
|
||||
{ ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits) },
|
||||
};
|
||||
|
||||
static const uint16_t SystemZRegEncodingTable[] = {
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
31,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
31,
|
||||
0,
|
||||
1,
|
||||
4,
|
||||
5,
|
||||
8,
|
||||
9,
|
||||
12,
|
||||
13,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
31,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
0,
|
||||
2,
|
||||
4,
|
||||
6,
|
||||
8,
|
||||
10,
|
||||
12,
|
||||
14,
|
||||
};
|
||||
#endif // GET_REGINFO_MC_DESC
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,65 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
#ifdef GET_SUBTARGETINFO_ENUM
|
||||
#undef GET_SUBTARGETINFO_ENUM
|
||||
|
||||
enum {
|
||||
SystemZ_FeatureBEAREnhancement = 0,
|
||||
SystemZ_FeatureBackChain = 1,
|
||||
SystemZ_FeatureDFPPackedConversion = 2,
|
||||
SystemZ_FeatureDFPZonedConversion = 3,
|
||||
SystemZ_FeatureDeflateConversion = 4,
|
||||
SystemZ_FeatureDistinctOps = 5,
|
||||
SystemZ_FeatureEnhancedDAT2 = 6,
|
||||
SystemZ_FeatureEnhancedSort = 7,
|
||||
SystemZ_FeatureExecutionHint = 8,
|
||||
SystemZ_FeatureFPExtension = 9,
|
||||
SystemZ_FeatureFastSerialization = 10,
|
||||
SystemZ_FeatureGuardedStorage = 11,
|
||||
SystemZ_FeatureHighWord = 12,
|
||||
SystemZ_FeatureInsertReferenceBitsMultiple = 13,
|
||||
SystemZ_FeatureInterlockedAccess1 = 14,
|
||||
SystemZ_FeatureLoadAndTrap = 15,
|
||||
SystemZ_FeatureLoadAndZeroRightmostByte = 16,
|
||||
SystemZ_FeatureLoadStoreOnCond = 17,
|
||||
SystemZ_FeatureLoadStoreOnCond2 = 18,
|
||||
SystemZ_FeatureMessageSecurityAssist3 = 19,
|
||||
SystemZ_FeatureMessageSecurityAssist4 = 20,
|
||||
SystemZ_FeatureMessageSecurityAssist5 = 21,
|
||||
SystemZ_FeatureMessageSecurityAssist7 = 22,
|
||||
SystemZ_FeatureMessageSecurityAssist8 = 23,
|
||||
SystemZ_FeatureMessageSecurityAssist9 = 24,
|
||||
SystemZ_FeatureMiscellaneousExtensions = 25,
|
||||
SystemZ_FeatureMiscellaneousExtensions2 = 26,
|
||||
SystemZ_FeatureMiscellaneousExtensions3 = 27,
|
||||
SystemZ_FeatureNNPAssist = 28,
|
||||
SystemZ_FeaturePopulationCount = 29,
|
||||
SystemZ_FeatureProcessorActivityInstrumentation = 30,
|
||||
SystemZ_FeatureProcessorAssist = 31,
|
||||
SystemZ_FeatureResetDATProtection = 32,
|
||||
SystemZ_FeatureResetReferenceBitsMultiple = 33,
|
||||
SystemZ_FeatureSoftFloat = 34,
|
||||
SystemZ_FeatureTransactionalExecution = 35,
|
||||
SystemZ_FeatureVector = 36,
|
||||
SystemZ_FeatureVectorEnhancements1 = 37,
|
||||
SystemZ_FeatureVectorEnhancements2 = 38,
|
||||
SystemZ_FeatureVectorPackedDecimal = 39,
|
||||
SystemZ_FeatureVectorPackedDecimalEnhancement = 40,
|
||||
SystemZ_FeatureVectorPackedDecimalEnhancement2 = 41,
|
||||
SystemZ_NumSubtargetFeatures = 42
|
||||
};
|
||||
#endif // GET_SUBTARGETINFO_ENUM
|
||||
|
||||
|
||||
|
||||
+394
@@ -0,0 +1,394 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//===- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax -===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include <ctype.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <capstone/platform.h>
|
||||
|
||||
#include "../../MathExtras.h"
|
||||
#include "../../MCAsmInfo.h"
|
||||
|
||||
#include "SystemZMapping.h"
|
||||
#include "SystemZInstPrinter.h"
|
||||
|
||||
#define CONCAT(a, b) CONCAT_(a, b)
|
||||
#define CONCAT_(a, b) a##_##b
|
||||
|
||||
static void printAddress(const MCAsmInfo *MAI, MCRegister Base,
|
||||
const MCOperand *DispMO, MCRegister Index, SStream *O);
|
||||
static void printMCOperandMAI(const MCOperand *MO, const MCAsmInfo *MAI,
|
||||
SStream *O);
|
||||
static void printRegName(const MCInst *MI, SStream *O, MCRegister Reg);
|
||||
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
|
||||
SStream *O);
|
||||
static void printOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O);
|
||||
static void printPCRelOperand(MCInst *MI, uint64_t Address, int OpNum,
|
||||
SStream *O);
|
||||
static void printPCRelTLSOperand(MCInst *MI, uint64_t Address, int OpNum,
|
||||
SStream *O);
|
||||
// This forms part of the instruction name rather than the operand list.
|
||||
// Print the mnemonic for a condition-code mask ("ne", "lh", etc.)
|
||||
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O);
|
||||
|
||||
#include "SystemZGenAsmWriter.inc"
|
||||
|
||||
#define DECLARE_printUImmOperand(N) \
|
||||
static void CONCAT(printUImmOperand, N)(MCInst * MI, int OpNum, \
|
||||
SStream *O);
|
||||
DECLARE_printUImmOperand(1);
|
||||
DECLARE_printUImmOperand(2);
|
||||
DECLARE_printUImmOperand(3);
|
||||
DECLARE_printUImmOperand(4);
|
||||
DECLARE_printUImmOperand(8);
|
||||
DECLARE_printUImmOperand(12);
|
||||
DECLARE_printUImmOperand(16);
|
||||
DECLARE_printUImmOperand(32);
|
||||
DECLARE_printUImmOperand(48);
|
||||
|
||||
#define DECLARE_printSImmOperand(N) \
|
||||
static void CONCAT(printSImmOperand, N)(MCInst * MI, int OpNum, \
|
||||
SStream *O);
|
||||
DECLARE_printSImmOperand(8);
|
||||
DECLARE_printSImmOperand(16);
|
||||
DECLARE_printSImmOperand(32);
|
||||
|
||||
static void printAddress(const MCAsmInfo *MAI, MCRegister Base,
|
||||
const MCOperand *DispMO, MCRegister Index, SStream *O)
|
||||
{
|
||||
printMCOperandMAI(DispMO, MAI, O);
|
||||
if (Base || Index) {
|
||||
SStream_concat0(O, "(");
|
||||
|
||||
if (Index) {
|
||||
printFormattedRegName(MAI, Index, O);
|
||||
SStream_concat0(O, ",");
|
||||
}
|
||||
if (Base)
|
||||
printFormattedRegName(MAI, Base, O);
|
||||
else
|
||||
SStream_concat0(O, "0");
|
||||
|
||||
SStream_concat0(O, ")");
|
||||
}
|
||||
}
|
||||
|
||||
static void printMCOperandMAI(const MCOperand *MO, const MCAsmInfo *MAI,
|
||||
SStream *O)
|
||||
{
|
||||
if (MCOperand_isReg(MO)) {
|
||||
if (!MCOperand_getReg(MO))
|
||||
SStream_concat1(O, '0');
|
||||
else
|
||||
printFormattedRegName(MAI, MCOperand_getReg(MO), O);
|
||||
} else if (MCOperand_isImm(MO))
|
||||
printInt64(markup_OS(O, Markup_Immediate),
|
||||
MCOperand_getImm(MO));
|
||||
else if (MCOperand_isExpr(MO))
|
||||
printExpr(O, MCOperand_getExpr(MO));
|
||||
else
|
||||
CS_ASSERT(0 && "Invalid operand");
|
||||
}
|
||||
|
||||
static void printMCOperand(const MCInst *MI, const MCOperand *MO, SStream *O)
|
||||
{
|
||||
if (MCOperand_isReg(MO)) {
|
||||
if (!MCOperand_getReg(MO))
|
||||
SStream_concat0(O, "0");
|
||||
|
||||
else
|
||||
printFormattedRegName(&MI->MAI, MCOperand_getReg(MO),
|
||||
O);
|
||||
} else if (MCOperand_isImm(MO))
|
||||
printInt64(markup_OS(O, Markup_Immediate),
|
||||
MCOperand_getImm(MO));
|
||||
else if (MCOperand_isExpr(MO))
|
||||
printExpr(O, MCOperand_getExpr(MO));
|
||||
else
|
||||
CS_ASSERT_RET(0 && "Invalid operand");
|
||||
}
|
||||
|
||||
void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, SStream *O)
|
||||
{
|
||||
const char *RegName = getRegisterName(Reg);
|
||||
if (MAI->assemblerDialect == SYSTEMZASMDIALECT_AD_ATT) {
|
||||
// Skip register prefix so that only register number is left
|
||||
CS_ASSERT((isalpha(RegName[0]) && isdigit(RegName[1])));
|
||||
SStream_concat0(markup_OS(O, Markup_Register), (RegName + 1));
|
||||
} else
|
||||
SStream_concat1(markup_OS(O, Markup_Register), '%');
|
||||
SStream_concat0(markup_OS(O, Markup_Register), RegName);
|
||||
}
|
||||
|
||||
static void printRegName(const MCInst *MI, SStream *O, MCRegister Reg)
|
||||
{
|
||||
printFormattedRegName(&MI->MAI, Reg, O);
|
||||
}
|
||||
|
||||
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
|
||||
SStream *O)
|
||||
{
|
||||
printInstruction(MI, Address, O);
|
||||
}
|
||||
|
||||
#define DEFINE_printUImmOperand(N) \
|
||||
void CONCAT(printUImmOperand, N)(MCInst * MI, int OpNum, SStream *O) \
|
||||
{ \
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \
|
||||
if (MCOperand_isExpr(MO)) { \
|
||||
printExpr(O, MCOperand_getExpr(MO)); \
|
||||
return; \
|
||||
} \
|
||||
uint64_t Value = (uint64_t)(MCOperand_getImm(MO)); \
|
||||
CS_ASSERT((isUIntN(N, Value) && "Invalid uimm argument")); \
|
||||
printUInt64(markup_OS(O, Markup_Immediate), Value); \
|
||||
}
|
||||
DEFINE_printUImmOperand(1);
|
||||
DEFINE_printUImmOperand(2);
|
||||
DEFINE_printUImmOperand(3);
|
||||
DEFINE_printUImmOperand(4);
|
||||
DEFINE_printUImmOperand(8);
|
||||
DEFINE_printUImmOperand(12);
|
||||
DEFINE_printUImmOperand(16);
|
||||
DEFINE_printUImmOperand(32);
|
||||
DEFINE_printUImmOperand(48);
|
||||
|
||||
#define DEFINE_printSImmOperand(N) \
|
||||
void CONCAT(printSImmOperand, N)(MCInst * MI, int OpNum, SStream *O) \
|
||||
{ \
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \
|
||||
if (MCOperand_isExpr(MO)) { \
|
||||
printExpr(O, MCOperand_getExpr(MO)); \
|
||||
return; \
|
||||
} \
|
||||
int64_t Value = \
|
||||
MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \
|
||||
if (N == 8) \
|
||||
printInt8(markup_OS(O, Markup_Immediate), Value); \
|
||||
else if (N == 16) \
|
||||
printInt16(markup_OS(O, Markup_Immediate), Value); \
|
||||
else if (N == 32) \
|
||||
printInt32(markup_OS(O, Markup_Immediate), Value); \
|
||||
else \
|
||||
CS_ASSERT(0 && "Unreachable"); \
|
||||
}
|
||||
DEFINE_printSImmOperand(8);
|
||||
DEFINE_printSImmOperand(16);
|
||||
DEFINE_printSImmOperand(32);
|
||||
|
||||
static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U1ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 1)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U2ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 2)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U3ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 3)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U4ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 4)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_S8ImmOperand, OpNum);
|
||||
CONCAT(printSImmOperand, 8)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U8ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 8)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U12ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 12)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_S16ImmOperand, OpNum);
|
||||
CONCAT(printSImmOperand, 16)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U16ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 16)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_S32ImmOperand, OpNum);
|
||||
CONCAT(printSImmOperand, 32)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U32ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 32)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U48ImmOperand, OpNum);
|
||||
CONCAT(printUImmOperand, 48)(MI, OpNum, O);
|
||||
}
|
||||
|
||||
static void printPCRelOperand(MCInst *MI, uint64_t Address, int OpNum,
|
||||
SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_PCRelOperand, OpNum);
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
|
||||
if (MCOperand_isImm(MO)) {
|
||||
printInt64(O, MCOperand_getImm(MO));
|
||||
} else
|
||||
printExpr(O, MCOperand_getExpr(MO));
|
||||
}
|
||||
|
||||
static void printPCRelTLSOperand(MCInst *MI, uint64_t Address, int OpNum,
|
||||
SStream *O)
|
||||
{
|
||||
// Output the PC-relative operand.
|
||||
printPCRelOperand(MI, MI->address, OpNum, O);
|
||||
|
||||
// Output the TLS marker if present.
|
||||
if ((unsigned)OpNum + 1 < MCInst_getNumOperands(MI)) {
|
||||
// Expressions not supported
|
||||
}
|
||||
}
|
||||
|
||||
static void printOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_Operand, OpNum);
|
||||
printMCOperand(MI, MCInst_getOperand(MI, (OpNum)), O);
|
||||
}
|
||||
|
||||
static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDAddrOperand, OpNum);
|
||||
printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))),
|
||||
MCInst_getOperand(MI, (OpNum + 1)), 0, O);
|
||||
}
|
||||
|
||||
static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDXAddrOperand, OpNum);
|
||||
printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))),
|
||||
MCInst_getOperand(MI, (OpNum + 1)),
|
||||
MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O);
|
||||
}
|
||||
|
||||
static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDLAddrOperand, OpNum);
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
|
||||
MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1));
|
||||
uint64_t Length = MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 2)));
|
||||
printMCOperandMAI(DispMO, &MI->MAI, O);
|
||||
SStream_concat1(O, '(');
|
||||
printUInt64(O, Length);
|
||||
if (Base) {
|
||||
SStream_concat0(O, ",");
|
||||
printRegName(MI, O, Base);
|
||||
}
|
||||
SStream_concat0(O, ")");
|
||||
}
|
||||
|
||||
static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDRAddrOperand, OpNum);
|
||||
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
|
||||
MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1));
|
||||
unsigned Length = MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2)));
|
||||
printMCOperandMAI(DispMO, &MI->MAI, O);
|
||||
SStream_concat0(O, "(");
|
||||
printRegName(MI, O, Length);
|
||||
if (Base) {
|
||||
SStream_concat0(O, ",");
|
||||
printRegName(MI, O, Base);
|
||||
}
|
||||
SStream_concat0(O, ")");
|
||||
}
|
||||
|
||||
static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDVAddrOperand, OpNum);
|
||||
printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))),
|
||||
MCInst_getOperand(MI, (OpNum + 1)),
|
||||
MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O);
|
||||
}
|
||||
|
||||
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_Cond4Operand, OpNum);
|
||||
static const char *const CondNames[] = { "o", "h", "nle", "l",
|
||||
"nhe", "lh", "ne", "e",
|
||||
"nlh", "he", "nl", "le",
|
||||
"nh", "no" };
|
||||
uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
|
||||
CS_ASSERT((Imm > 0 && Imm < 15 && "Invalid condition"));
|
||||
SStream_concat0(O, CondNames[Imm - 1]);
|
||||
}
|
||||
|
||||
const char *SystemZ_LLVM_getRegisterName(unsigned RegNo)
|
||||
{
|
||||
return getRegisterName(RegNo);
|
||||
}
|
||||
|
||||
void SystemZ_LLVM_printInstruction(MCInst *MI, const char *Annotation,
|
||||
SStream *O)
|
||||
{
|
||||
printInst(MI, MI->address, Annotation, O);
|
||||
}
|
||||
@@ -0,0 +1,51 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//==- SystemZInstPrinter.h - Convert SystemZ MCInst to assembly --*- C++ -*-==//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This class prints a SystemZ MCInst to a .s file.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZINSTPRINTER_H
|
||||
#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZINSTPRINTER_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <capstone/platform.h>
|
||||
|
||||
#include "../../MCInstPrinter.h"
|
||||
#include "../../cs_priv.h"
|
||||
#define CONCAT(a, b) CONCAT_(a, b)
|
||||
#define CONCAT_(a, b) a##_##b
|
||||
|
||||
//
|
||||
// All function declarations are moved for now to the C file to make them static.
|
||||
//
|
||||
void printOperandAsmInfo(const MCOperand *MO, const MCAsmInfo *MAI, SStream *O);
|
||||
void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, SStream *O);
|
||||
|
||||
// Print various types of operand.
|
||||
;
|
||||
|
||||
// end namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZINSTPRINTER_H
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
|
||||
#ifndef CS_SYSTEMZ_LINKAGE_H
|
||||
#define CS_SYSTEMZ_LINKAGE_H
|
||||
|
||||
// Function definitions to call static LLVM functions.
|
||||
|
||||
#include "../../MCDisassembler.h"
|
||||
#include "../../MCInst.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "../../SStream.h"
|
||||
#include "capstone/capstone.h"
|
||||
|
||||
DecodeStatus SystemZ_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
|
||||
size_t ByteLen, MCInst *MI,
|
||||
uint16_t *Size, uint64_t Address,
|
||||
void *Info);
|
||||
const char *SystemZ_LLVM_getRegisterName(unsigned RegNo);
|
||||
void SystemZ_LLVM_printInstruction(MCInst *MI, const char *Annot, SStream *O);
|
||||
|
||||
#endif // CS_SYSTEMZ_LINKAGE_H
|
||||
@@ -0,0 +1,157 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <capstone/platform.h>
|
||||
|
||||
#include "../../MCInst.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "SystemZMCTargetDesc.h"
|
||||
#include "SystemZInstPrinter.h"
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#define ENABLE_INSTR_PREDICATE_VERIFIER
|
||||
#include "SystemZGenInstrInfo.inc"
|
||||
|
||||
#define GET_SUBTARGETINFO_MC_DESC
|
||||
#include "SystemZGenSubtargetInfo.inc"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#include "SystemZGenRegisterInfo.inc"
|
||||
#define CONCAT(a, b) CONCAT_(a, b)
|
||||
#define CONCAT_(a, b) a##_##b
|
||||
|
||||
const unsigned SystemZMC_GR32Regs[16] = {
|
||||
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L,
|
||||
SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L,
|
||||
SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L,
|
||||
SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_GRH32Regs[16] = {
|
||||
SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H,
|
||||
SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H,
|
||||
SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H,
|
||||
SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_GR64Regs[16] = {
|
||||
SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D,
|
||||
SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D,
|
||||
SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D,
|
||||
SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_GR128Regs[16] = { SystemZ_R0Q, 0, SystemZ_R2Q, 0,
|
||||
SystemZ_R4Q, 0, SystemZ_R6Q, 0,
|
||||
SystemZ_R8Q, 0, SystemZ_R10Q, 0,
|
||||
SystemZ_R12Q, 0, SystemZ_R14Q, 0 };
|
||||
|
||||
const unsigned SystemZMC_FP32Regs[16] = {
|
||||
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
|
||||
SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
|
||||
SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
|
||||
SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_FP64Regs[16] = {
|
||||
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
|
||||
SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
|
||||
SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
|
||||
SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_FP128Regs[16] = { SystemZ_F0Q, SystemZ_F1Q, 0, 0,
|
||||
SystemZ_F4Q, SystemZ_F5Q, 0, 0,
|
||||
SystemZ_F8Q, SystemZ_F9Q, 0, 0,
|
||||
SystemZ_F12Q, SystemZ_F13Q, 0, 0 };
|
||||
|
||||
const unsigned SystemZMC_VR32Regs[32] = {
|
||||
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S,
|
||||
SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S,
|
||||
SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S,
|
||||
SystemZ_F15S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S,
|
||||
SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S,
|
||||
SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S,
|
||||
SystemZ_F30S, SystemZ_F31S
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_VR64Regs[32] = {
|
||||
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D,
|
||||
SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D,
|
||||
SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D,
|
||||
SystemZ_F15D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D,
|
||||
SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D,
|
||||
SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D,
|
||||
SystemZ_F30D, SystemZ_F31D
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_VR128Regs[32] = {
|
||||
SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4,
|
||||
SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9,
|
||||
SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14,
|
||||
SystemZ_V15, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19,
|
||||
SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24,
|
||||
SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29,
|
||||
SystemZ_V30, SystemZ_V31
|
||||
};
|
||||
|
||||
const unsigned SystemZMC_AR32Regs[16] = { SystemZ_A0, SystemZ_A1, SystemZ_A2,
|
||||
SystemZ_A3, SystemZ_A4, SystemZ_A5,
|
||||
SystemZ_A6, SystemZ_A7, SystemZ_A8,
|
||||
SystemZ_A9, SystemZ_A10, SystemZ_A11,
|
||||
SystemZ_A12, SystemZ_A13, SystemZ_A14,
|
||||
SystemZ_A15 };
|
||||
|
||||
const unsigned SystemZMC_CR64Regs[16] = { SystemZ_C0, SystemZ_C1, SystemZ_C2,
|
||||
SystemZ_C3, SystemZ_C4, SystemZ_C5,
|
||||
SystemZ_C6, SystemZ_C7, SystemZ_C8,
|
||||
SystemZ_C9, SystemZ_C10, SystemZ_C11,
|
||||
SystemZ_C12, SystemZ_C13, SystemZ_C14,
|
||||
SystemZ_C15 };
|
||||
|
||||
unsigned SystemZMC_getFirstReg(unsigned Reg)
|
||||
{
|
||||
static unsigned Map[NUM_TARGET_REGS];
|
||||
static bool Initialized = false;
|
||||
if (!Initialized) {
|
||||
for (unsigned I = 0; I < 16; ++I) {
|
||||
Map[SystemZMC_GR32Regs[I]] = I;
|
||||
Map[SystemZMC_GRH32Regs[I]] = I;
|
||||
Map[SystemZMC_GR64Regs[I]] = I;
|
||||
Map[SystemZMC_GR128Regs[I]] = I;
|
||||
Map[SystemZMC_FP128Regs[I]] = I;
|
||||
Map[SystemZMC_AR32Regs[I]] = I;
|
||||
}
|
||||
for (unsigned I = 0; I < 32; ++I) {
|
||||
Map[SystemZMC_VR32Regs[I]] = I;
|
||||
Map[SystemZMC_VR64Regs[I]] = I;
|
||||
Map[SystemZMC_VR128Regs[I]] = I;
|
||||
}
|
||||
}
|
||||
CS_ASSERT((Reg < NUM_TARGET_REGS));
|
||||
return Map[Reg];
|
||||
}
|
||||
|
||||
// end namespace
|
||||
@@ -0,0 +1,113 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
|
||||
#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <capstone/platform.h>
|
||||
|
||||
#include "../../MCInstPrinter.h"
|
||||
#include "../../cs_priv.h"
|
||||
#define CONCAT(a, b) CONCAT_(a, b)
|
||||
#define CONCAT_(a, b) a##_##b
|
||||
|
||||
// CS namespace begin: SystemZMC
|
||||
|
||||
// Maps of asm register numbers to LLVM register numbers, with 0 indicating
|
||||
// an invalid register. In principle we could use 32-bit and 64-bit register
|
||||
// classes directly, provided that we relegated the GPR allocation order
|
||||
// in SystemZRegisterInfo.td to an AltOrder and left the default order
|
||||
// as %r0-%r15. It seems better to provide the same interface for
|
||||
// all classes though.
|
||||
extern const unsigned SystemZMC_GR32Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_GRH32Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_GR64Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_GR128Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_FP32Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_FP64Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_FP128Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_VR32Regs[32];
|
||||
|
||||
extern const unsigned SystemZMC_VR64Regs[32];
|
||||
|
||||
extern const unsigned SystemZMC_VR128Regs[32];
|
||||
|
||||
extern const unsigned SystemZMC_AR32Regs[16];
|
||||
|
||||
extern const unsigned SystemZMC_CR64Regs[16];
|
||||
|
||||
// Return the 0-based number of the first architectural register that
|
||||
// contains the given LLVM register. E.g. R1D -> 1.
|
||||
unsigned SystemZMC_getFirstReg(unsigned Reg);
|
||||
|
||||
// Return the given register as a GR64.
|
||||
static inline unsigned SystemZMC_getRegAsGR64(unsigned Reg)
|
||||
{
|
||||
return SystemZMC_GR64Regs[SystemZMC_getFirstReg(Reg)];
|
||||
}
|
||||
|
||||
// Return the given register as a low GR32.
|
||||
static inline unsigned SystemZMC_getRegAsGR32(unsigned Reg)
|
||||
{
|
||||
return SystemZMC_GR32Regs[SystemZMC_getFirstReg(Reg)];
|
||||
}
|
||||
|
||||
// Return the given register as a high GR32.
|
||||
static inline unsigned SystemZMC_getRegAsGRH32(unsigned Reg)
|
||||
{
|
||||
return SystemZMC_GRH32Regs[SystemZMC_getFirstReg(Reg)];
|
||||
}
|
||||
|
||||
// Return the given register as a VR128.
|
||||
static inline unsigned SystemZMC_getRegAsVR128(unsigned Reg)
|
||||
{
|
||||
return SystemZMC_VR128Regs[SystemZMC_getFirstReg(Reg)];
|
||||
}
|
||||
|
||||
// CS namespace end: SystemZMC
|
||||
|
||||
// end namespace SystemZMC
|
||||
|
||||
// Defines symbolic names for SystemZ registers.
|
||||
// This defines a mapping from register name to register number.
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "SystemZGenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the SystemZ instructions.
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#define GET_INSTRINFO_MC_HELPER_DECLS
|
||||
#include "SystemZGenInstrInfo.inc"
|
||||
|
||||
#define GET_SUBTARGETINFO_ENUM
|
||||
#include "SystemZGenSubtargetInfo.inc"
|
||||
|
||||
#endif
|
||||
+376
@@ -0,0 +1,376 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_SYSTEMZ
|
||||
|
||||
#include <stdio.h> // debug
|
||||
#include <string.h>
|
||||
|
||||
#include "../../Mapping.h"
|
||||
#include "../../utils.h"
|
||||
#include "../../cs_simple_types.h"
|
||||
#include <capstone/cs_operand.h>
|
||||
|
||||
#include "SystemZMCTargetDesc.h"
|
||||
#include "SystemZMapping.h"
|
||||
#include "SystemZLinkage.h"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
|
||||
static const char *const insn_name_maps[] = {
|
||||
#include "SystemZGenCSMappingInsnName.inc"
|
||||
};
|
||||
|
||||
static const name_map insn_alias_mnem_map[] = {
|
||||
#include "SystemZGenCSAliasMnemMap.inc"
|
||||
{ SYSTEMZ_INS_ALIAS_END, NULL },
|
||||
};
|
||||
|
||||
static const map_insn_ops insn_operands[] = {
|
||||
#include "SystemZGenCSMappingInsnOp.inc"
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#include "SystemZGenRegisterInfo.inc"
|
||||
|
||||
const insn_map systemz_insns[] = {
|
||||
#include "SystemZGenCSMappingInsn.inc"
|
||||
};
|
||||
|
||||
void SystemZ_set_instr_map_data(MCInst *MI, const uint8_t *Bytes,
|
||||
size_t BytesLen)
|
||||
{
|
||||
map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns));
|
||||
map_implicit_reads(MI, systemz_insns);
|
||||
map_implicit_writes(MI, systemz_insns);
|
||||
map_groups(MI, systemz_insns);
|
||||
const systemz_suppl_info *suppl_info =
|
||||
map_get_suppl_info(MI, systemz_insns);
|
||||
if (suppl_info) {
|
||||
SystemZ_get_detail(MI)->format = suppl_info->form;
|
||||
}
|
||||
}
|
||||
|
||||
void SystemZ_init_mri(MCRegisterInfo *MRI)
|
||||
{
|
||||
MCRegisterInfo_InitMCRegisterInfo(
|
||||
MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0,
|
||||
SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0,
|
||||
0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists,
|
||||
ARR_SIZE(SystemZSubRegIdxLists), 0);
|
||||
}
|
||||
|
||||
const char *SystemZ_reg_name(csh handle, unsigned int reg)
|
||||
{
|
||||
return SystemZ_LLVM_getRegisterName(reg);
|
||||
}
|
||||
|
||||
void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
|
||||
{
|
||||
MI->MRI = (MCRegisterInfo *)info;
|
||||
MI->fillDetailOps = detail_is_set(MI);
|
||||
SystemZ_LLVM_printInstruction(MI, "", O);
|
||||
#ifndef CAPSTONE_DIET
|
||||
map_set_alias_id(MI, O, insn_alias_mnem_map,
|
||||
ARR_SIZE(insn_alias_mnem_map));
|
||||
#endif
|
||||
}
|
||||
|
||||
void SystemZ_init_cs_detail(MCInst *MI)
|
||||
{
|
||||
if (!detail_is_set(MI)) {
|
||||
return;
|
||||
}
|
||||
memset(get_detail(MI), 0, sizeof(cs_detail));
|
||||
if (detail_is_set(MI)) {
|
||||
SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
|
||||
MCInst *MI, uint16_t *size, uint64_t address,
|
||||
void *info)
|
||||
{
|
||||
SystemZ_init_cs_detail(MI);
|
||||
MI->MRI = (MCRegisterInfo *)info;
|
||||
DecodeStatus Result = SystemZ_LLVM_getInstruction(
|
||||
handle, bytes, bytes_len, MI, size, address, info);
|
||||
SystemZ_set_instr_map_data(MI, bytes, bytes_len);
|
||||
if (Result == MCDisassembler_SoftFail) {
|
||||
MCInst_setSoftFail(MI);
|
||||
}
|
||||
return Result != MCDisassembler_Fail;
|
||||
}
|
||||
|
||||
// given internal insn id, return public instruction info
|
||||
void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
||||
{
|
||||
// We do this after Instruction disassembly.
|
||||
}
|
||||
|
||||
const char *SystemZ_insn_name(csh handle, unsigned int id)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) {
|
||||
if (id - SYSTEMZ_INS_ALIAS_BEGIN >=
|
||||
ARR_SIZE(insn_alias_mnem_map))
|
||||
return NULL;
|
||||
|
||||
return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1]
|
||||
.name;
|
||||
}
|
||||
if (id >= SYSTEMZ_INS_ENDING)
|
||||
return NULL;
|
||||
|
||||
if (id < ARR_SIZE(insn_name_maps))
|
||||
return insn_name_maps[id];
|
||||
|
||||
// not found
|
||||
return NULL;
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ SYSTEMZ_GRP_INVALID, NULL },
|
||||
{ SYSTEMZ_GRP_JUMP, "jump" },
|
||||
{ SYSTEMZ_GRP_CALL, "call" },
|
||||
{ SYSTEMZ_GRP_RET, "return" },
|
||||
{ SYSTEMZ_GRP_INT, "int" },
|
||||
{ SYSTEMZ_GRP_IRET, "iret" },
|
||||
{ SYSTEMZ_GRP_PRIVILEGE, "privilege" },
|
||||
{ SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" },
|
||||
|
||||
#include "SystemZGenCSFeatureName.inc"
|
||||
};
|
||||
#endif
|
||||
|
||||
const char *SystemZ_group_name(csh handle, unsigned int id)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
void SystemZ_add_cs_detail_0(MCInst *MI, int /* systemz_op_group */ op_group,
|
||||
size_t op_num)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
|
||||
return;
|
||||
|
||||
switch (op_group) {
|
||||
default:
|
||||
printf("Operand group %d not handled\n", op_group);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_Operand: {
|
||||
cs_op_type secondary_op_type = map_get_op_type(MI, op_num) &
|
||||
~(CS_OP_MEM | CS_OP_BOUND);
|
||||
if (secondary_op_type == CS_OP_IMM) {
|
||||
SystemZ_set_detail_op_imm(
|
||||
MI, op_num, MCInst_getOpVal(MI, op_num), 0);
|
||||
} else if (secondary_op_type == CS_OP_REG) {
|
||||
SystemZ_set_detail_op_reg(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num));
|
||||
} else {
|
||||
CS_ASSERT_RET(0 && "Op type not handled.");
|
||||
}
|
||||
break;
|
||||
}
|
||||
case SystemZ_OP_GROUP_Cond4Operand: {
|
||||
systemz_cc cc = MCInst_getOpVal(MI, op_num);
|
||||
SystemZ_get_detail(MI)->cc = cc;
|
||||
break;
|
||||
}
|
||||
case SystemZ_OP_GROUP_BDAddrOperand:
|
||||
CS_ASSERT_RET(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
|
||||
CS_ASSERT_RET(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
|
||||
CS_ASSERT_RET(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
|
||||
CS_ASSERT_RET(
|
||||
MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
|
||||
SystemZ_set_detail_op_mem(MI, op_num,
|
||||
MCInst_getOpVal(MI, (op_num)),
|
||||
MCInst_getOpVal(MI, (op_num + 1)), 0,
|
||||
0, SYSTEMZ_AM_BD);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_BDVAddrOperand:
|
||||
case SystemZ_OP_GROUP_BDXAddrOperand: {
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
|
||||
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
|
||||
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
|
||||
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
|
||||
SystemZ_set_detail_op_mem(
|
||||
MI, op_num, MCInst_getOpVal(MI, (op_num)),
|
||||
MCInst_getOpVal(MI, (op_num + 1)), 0,
|
||||
MCInst_getOpVal(MI, (op_num + 2)),
|
||||
(op_group == SystemZ_OP_GROUP_BDXAddrOperand ?
|
||||
SYSTEMZ_AM_BDX :
|
||||
SYSTEMZ_AM_BDV));
|
||||
break;
|
||||
}
|
||||
case SystemZ_OP_GROUP_BDLAddrOperand:
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
|
||||
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
|
||||
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
|
||||
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2))));
|
||||
SystemZ_set_detail_op_mem(MI, op_num,
|
||||
MCInst_getOpVal(MI, (op_num)),
|
||||
MCInst_getOpVal(MI, (op_num + 1)),
|
||||
MCInst_getOpVal(MI, (op_num + 2)), 0,
|
||||
SYSTEMZ_AM_BDL);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_BDRAddrOperand:
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
|
||||
CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
|
||||
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
|
||||
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
|
||||
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
|
||||
SystemZ_set_detail_op_mem(MI, op_num,
|
||||
MCInst_getOpVal(MI, (op_num)),
|
||||
MCInst_getOpVal(MI, (op_num + 1)),
|
||||
MCInst_getOpVal(MI, (op_num + 2)), 0,
|
||||
SYSTEMZ_AM_BDL);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_PCRelOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 0);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U1ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 1);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U2ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 2);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U3ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 3);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U4ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 4);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U8ImmOperand:
|
||||
case SystemZ_OP_GROUP_S8ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 8);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U12ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 12);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U16ImmOperand:
|
||||
case SystemZ_OP_GROUP_S16ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 16);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U32ImmOperand:
|
||||
case SystemZ_OP_GROUP_S32ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 32);
|
||||
break;
|
||||
case SystemZ_OP_GROUP_U48ImmOperand:
|
||||
SystemZ_set_detail_op_imm(MI, op_num,
|
||||
MCInst_getOpVal(MI, op_num), 48);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
|
||||
void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm,
|
||||
size_t width)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
return;
|
||||
CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM);
|
||||
|
||||
SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
|
||||
SystemZ_get_detail_op(MI, 0)->imm = Imm;
|
||||
SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
|
||||
SystemZ_get_detail_op(MI, 0)->imm_width = width;
|
||||
SystemZ_inc_op_count(MI);
|
||||
}
|
||||
|
||||
void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
return;
|
||||
CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG);
|
||||
if (Reg == SYSTEMZ_REG_INVALID) {
|
||||
// This case is legal. The ISA says:
|
||||
// "
|
||||
// When the R1 field is not zero, bits 8-15 of the instruction designated
|
||||
// by the second-operand address are ORed with bits 56-63 of
|
||||
// general register R1. [...] When the R1 field is zero, no ORing takes place
|
||||
// "
|
||||
// This means we just save the neutral element for ORing, so 0.
|
||||
SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
|
||||
SystemZ_get_detail_op(MI, 0)->imm = 0;
|
||||
SystemZ_get_detail_op(MI, 0)->access =
|
||||
map_get_op_access(MI, op_num);
|
||||
SystemZ_get_detail_op(MI, 0)->imm_width = 0;
|
||||
SystemZ_inc_op_count(MI);
|
||||
return;
|
||||
}
|
||||
|
||||
SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG;
|
||||
SystemZ_get_detail_op(MI, 0)->reg = Reg;
|
||||
SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
|
||||
SystemZ_inc_op_count(MI);
|
||||
}
|
||||
|
||||
void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base,
|
||||
int64_t disp, uint64_t length, systemz_reg index,
|
||||
systemz_addr_mode am)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
return;
|
||||
SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM;
|
||||
SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
|
||||
SystemZ_get_detail_op(MI, 0)->mem.am = am;
|
||||
switch (am) {
|
||||
default:
|
||||
CS_ASSERT(0 && "Address mode not handled\n");
|
||||
break;
|
||||
case SYSTEMZ_AM_BD:
|
||||
SystemZ_get_detail_op(MI, 0)->mem.base = base;
|
||||
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
|
||||
break;
|
||||
case SYSTEMZ_AM_BDX:
|
||||
case SYSTEMZ_AM_BDV:
|
||||
SystemZ_get_detail_op(MI, 0)->mem.base = base;
|
||||
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
|
||||
SystemZ_get_detail_op(MI, 0)->mem.index = index;
|
||||
break;
|
||||
case SYSTEMZ_AM_BDL:
|
||||
SystemZ_get_detail_op(MI, 0)->mem.base = base;
|
||||
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
|
||||
SystemZ_get_detail_op(MI, 0)->mem.length = length;
|
||||
break;
|
||||
case SYSTEMZ_AM_BDR:
|
||||
SystemZ_get_detail_op(MI, 0)->mem.base = base;
|
||||
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
|
||||
SystemZ_get_detail_op(MI, 0)->mem.length = length;
|
||||
break;
|
||||
}
|
||||
SystemZ_inc_op_count(MI);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
+42
@@ -0,0 +1,42 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
|
||||
#ifndef CS_SYSTEMZ_MAP_H
|
||||
#define CS_SYSTEMZ_MAP_H
|
||||
|
||||
#include <capstone/capstone.h>
|
||||
|
||||
#include "../../Mapping.h"
|
||||
#include "../../cs_priv.h"
|
||||
|
||||
typedef enum {
|
||||
#include "SystemZGenCSOpGroup.inc"
|
||||
} systemz_op_group;
|
||||
|
||||
// return name of register in friendly string
|
||||
const char *SystemZ_reg_name(csh handle, unsigned int reg);
|
||||
|
||||
// given internal insn id, return public instruction info
|
||||
void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
|
||||
|
||||
const char *SystemZ_insn_name(csh handle, unsigned int id);
|
||||
|
||||
const char *SystemZ_group_name(csh handle, unsigned int id);
|
||||
|
||||
void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
|
||||
bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
|
||||
MCInst *MI, uint16_t *size, uint64_t address,
|
||||
void *info);
|
||||
void SystemZ_init_mri(MCRegisterInfo *MRI);
|
||||
void SystemZ_init_cs_detail(MCInst *MI);
|
||||
|
||||
void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg);
|
||||
void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm,
|
||||
size_t width);
|
||||
void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base,
|
||||
int64_t disp, uint64_t length, systemz_reg index,
|
||||
systemz_addr_mode am);
|
||||
void SystemZ_add_cs_detail_0(MCInst *MI, int /* systemz_op_group */ op_group,
|
||||
size_t op_num);
|
||||
|
||||
#endif // CS_SYSTEMZ_MAP_H
|
||||
+44
@@ -0,0 +1,44 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_SYSTEMZ
|
||||
|
||||
#include "../../utils.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "SystemZMapping.h"
|
||||
#include "SystemZModule.h"
|
||||
|
||||
cs_err SystemZ_global_init(cs_struct *ud)
|
||||
{
|
||||
MCRegisterInfo *mri;
|
||||
mri = cs_mem_malloc(sizeof(*mri));
|
||||
if (!mri)
|
||||
return CS_ERR_MEM;
|
||||
|
||||
SystemZ_init_mri(mri);
|
||||
ud->printer = SystemZ_printer;
|
||||
ud->printer_info = mri;
|
||||
ud->getinsn_info = mri;
|
||||
ud->disasm = SystemZ_getInstruction;
|
||||
ud->post_printer = NULL;
|
||||
|
||||
ud->reg_name = SystemZ_reg_name;
|
||||
ud->insn_id = SystemZ_get_insn_id;
|
||||
ud->insn_name = SystemZ_insn_name;
|
||||
ud->group_name = SystemZ_group_name;
|
||||
|
||||
return CS_ERR_OK;
|
||||
}
|
||||
|
||||
cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value)
|
||||
{
|
||||
if (type == CS_OPT_SYNTAX) {
|
||||
handle->syntax = (int)value;
|
||||
} else if (type == CS_OPT_MODE) {
|
||||
handle->mode |= (cs_mode)value;
|
||||
}
|
||||
|
||||
return CS_ERR_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
|
||||
|
||||
#ifndef CS_SYSTEMZ_MODULE_H
|
||||
#define CS_SYSTEMZ_MODULE_H
|
||||
|
||||
#include "../../utils.h"
|
||||
|
||||
cs_err SystemZ_global_init(cs_struct *ud);
|
||||
cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user