weeemu/weee
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'

Browse Source
This commit is contained in:
iris
2026-05-11 11:55:07 +02:00
parent ef8e742694 802798ce3c
commit c0de07465b
3968 changed files with 2967598 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
external/capstone/suite/MC/RISCV/XCValu_valid_riscv32_riscv_xcvalu_syntax_no_alias_text.txt.cs
Vendored
+73
View File
@@ -0,0 +1,73 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVALU", None
0xab,0x32,0x73,0x86 == cv.addurnr t0, t1, t2
0x2b,0xb5,0xc5,0x86 == cv.addurnr a0, a1, a2
0xab,0x32,0x73,0x5c == cv.maxu t0, t1, t2
0x2b,0xb5,0xc5,0x5c == cv.maxu a0, a1, a2
0xab,0x32,0x73,0x8c == cv.subrnr t0, t1, t2
0x2b,0xb5,0xc5,0x8c == cv.subrnr a0, a1, a2
0xab,0x32,0x73,0x52 == cv.slet t0, t1, t2
0x2b,0xb5,0xc5,0x52 == cv.slet a0, a1, a2
0xdb,0x32,0x73,0x80 == cv.subrn t0, t1, t2, 0
0xdb,0x32,0x73,0xa0 == cv.subrn t0, t1, t2, 16
0x5b,0xb5,0x05,0xbe == cv.subrn a0, a1, zero, 31
0xab,0x32,0x73,0x88 == cv.subnr t0, t1, t2
0x2b,0xb5,0xc5,0x88 == cv.subnr a0, a1, a2
0xab,0x32,0x73,0x82 == cv.addunr t0, t1, t2
0x2b,0xb5,0xc5,0x82 == cv.addunr a0, a1, a2
0xdb,0x22,0x73,0xc0 == cv.addurn t0, t1, t2, 0
0xdb,0x22,0x73,0xe0 == cv.addurn t0, t1, t2, 16
0x5b,0xa5,0x05,0xfe == cv.addurn a0, a1, zero, 31
0xdb,0x22,0x73,0x40 == cv.addun t0, t1, t2, 0
0xdb,0x22,0x73,0x60 == cv.addun t0, t1, t2, 16
0x5b,0xa5,0x05,0x7e == cv.addun a0, a1, zero, 31
0xab,0x32,0x03,0x72 == cv.clipu t0, t1, 0
0xab,0x32,0x03,0x73 == cv.clipu t0, t1, 16
0x2b,0x35,0xf0,0x73 == cv.clipu a0, zero, 31
0xab,0x32,0x03,0x70 == cv.clip t0, t1, 0
0xab,0x32,0x03,0x71 == cv.clip t0, t1, 16
0x2b,0x35,0xf0,0x71 == cv.clip a0, zero, 31
0xab,0x32,0x03,0x62 == cv.exthz t0, t1
0x2b,0xb5,0x05,0x62 == cv.exthz a0, a1
0xab,0x32,0x73,0x5a == cv.max t0, t1, t2
0x2b,0xb5,0xc5,0x5a == cv.max a0, a1, a2
0xab,0x32,0x73,0x74 == cv.clipr t0, t1, t2
0x2b,0xb5,0xc5,0x74 == cv.clipr a0, a1, a2
0xdb,0x32,0x73,0x00 == cv.subn t0, t1, t2, 0
0xdb,0x32,0x73,0x20 == cv.subn t0, t1, t2, 16
0x5b,0xb5,0x05,0x3e == cv.subn a0, a1, zero, 31
0xab,0x32,0x03,0x66 == cv.extbz t0, t1
0x2b,0xb5,0x05,0x66 == cv.extbz a0, a1
0xab,0x32,0x03,0x50 == cv.abs t0, t1
0x2b,0xb5,0x05,0x50 == cv.abs a0, a1
0xab,0x32,0x73,0x76 == cv.clipur t0, t1, t2
0x2b,0xb5,0xc5,0x76 == cv.clipur a0, a1, a2
0xab,0x32,0x73,0x58 == cv.minu t0, t1, t2
0x2b,0xb5,0xc5,0x58 == cv.minu a0, a1, a2
0xdb,0x22,0x73,0x00 == cv.addn t0, t1, t2, 0
0xdb,0x22,0x73,0x20 == cv.addn t0, t1, t2, 16
0x5b,0xa5,0x05,0x3e == cv.addn a0, a1, zero, 31
0xab,0x32,0x73,0x8a == cv.subunr t0, t1, t2
0x2b,0xb5,0xc5,0x8a == cv.subunr a0, a1, a2
0xab,0x32,0x03,0x64 == cv.extbs t0, t1
0x2b,0xb5,0x05,0x64 == cv.extbs a0, a1
0xab,0x32,0x73,0x54 == cv.sletu t0, t1, t2
0x2b,0xb5,0xc5,0x54 == cv.sletu a0, a1, a2
0xab,0x32,0x73,0x56 == cv.min t0, t1, t2
0x2b,0xb5,0xc5,0x56 == cv.min a0, a1, a2
0xab,0x32,0x73,0x8e == cv.suburnr t0, t1, t2
0x2b,0xb5,0xc5,0x8e == cv.suburnr a0, a1, a2
0xab,0x32,0x73,0x84 == cv.addrnr t0, t1, t2
0x2b,0xb5,0xc5,0x84 == cv.addrnr a0, a1, a2
0xab,0x32,0x03,0x60 == cv.exths t0, t1
0x2b,0xb5,0x05,0x60 == cv.exths a0, a1
0xdb,0x22,0x73,0x80 == cv.addrn t0, t1, t2, 0
0xdb,0x22,0x73,0xa0 == cv.addrn t0, t1, t2, 16
0x5b,0xa5,0x05,0xbe == cv.addrn a0, a1, zero, 31
0xdb,0x32,0x73,0xc0 == cv.suburn t0, t1, t2, 0
0xdb,0x32,0x73,0xe0 == cv.suburn t0, t1, t2, 16
0x5b,0xb5,0x05,0xfe == cv.suburn a0, a1, zero, 31
0xab,0x32,0x73,0x80 == cv.addnr t0, t1, t2
0x2b,0xb5,0xc5,0x80 == cv.addnr a0, a1, a2
0xdb,0x32,0x73,0x40 == cv.subun t0, t1, t2, 0
0xdb,0x32,0x73,0x60 == cv.subun t0, t1, t2, 16
0x5b,0xb5,0x05,0x7e == cv.subun a0, a1, zero, 31
external/capstone/suite/MC/RISCV/XCVbi_riscv32_riscv_xcvbi.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVBI", None
0x0b,0xe0,0x02,0x00 == cv.beqimm t0, 0, 0
0x0b,0x65,0x55,0x02 == cv.beqimm a0, 5, 42
0x0b,0xf0,0x02,0x00 == cv.bneimm t0, 0, 0
0x0b,0x75,0x55,0x02 == cv.bneimm a0, 5, 42
external/capstone/suite/MC/RISCV/XCVbitmanip_riscv32_riscv_xcvbitmanip.txt.cs
Vendored
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVBITMANIP", None
0xdb,0x02,0x13,0x00 == cv.extract t0, t1, 0, 1
0x5b,0x85,0x25,0x23 == cv.extract a0, a1, 17, 18
0x5b,0x84,0xf4,0x3d == cv.extract s0, s1, 30, 31
0xdb,0x02,0x13,0x40 == cv.extractu t0, t1, 0, 1
0x5b,0x85,0x25,0x63 == cv.extractu a0, a1, 17, 18
0x5b,0x84,0xf4,0x7d == cv.extractu s0, s1, 30, 31
0xdb,0x02,0x13,0x80 == cv.insert t0, t1, 0, 1
0x5b,0x85,0x25,0xa3 == cv.insert a0, a1, 17, 18
0x5b,0x84,0xf4,0xbd == cv.insert s0, s1, 30, 31
0xdb,0x12,0x13,0x00 == cv.bclr t0, t1, 0, 1
0x5b,0x95,0x25,0x23 == cv.bclr a0, a1, 17, 18
0x5b,0x94,0xf4,0x3d == cv.bclr s0, s1, 30, 31
0xdb,0x12,0x13,0x40 == cv.bset t0, t1, 0, 1
0x5b,0x95,0x25,0x63 == cv.bset a0, a1, 17, 18
0x5b,0x94,0xf4,0x7d == cv.bset s0, s1, 30, 31
0xdb,0x12,0x13,0xc0 == cv.bitrev t0, t1, 0, 1
0x5b,0x95,0x25,0xc3 == cv.bitrev a0, a1, 1, 18
0x5b,0x94,0xf4,0xc5 == cv.bitrev s0, s1, 2, 31
0xab,0x32,0x73,0x30 == cv.extractr t0, t1, t2
0x2b,0xb5,0xc5,0x30 == cv.extractr a0, a1, a2
0x2b,0xb4,0x24,0x31 == cv.extractr s0, s1, s2
0xab,0x32,0x73,0x32 == cv.extractur t0, t1, t2
0x2b,0xb5,0xc5,0x32 == cv.extractur a0, a1, a2
0x2b,0xb4,0x24,0x33 == cv.extractur s0, s1, s2
0xab,0x32,0x73,0x34 == cv.insertr t0, t1, t2
0x2b,0xb5,0xc5,0x34 == cv.insertr a0, a1, a2
0x2b,0xb4,0x24,0x35 == cv.insertr s0, s1, s2
0xab,0x32,0x73,0x38 == cv.bclrr t0, t1, t2
0x2b,0xb5,0xc5,0x38 == cv.bclrr a0, a1, a2
0x2b,0xb4,0x24,0x39 == cv.bclrr s0, s1, s2
0xab,0x32,0x73,0x3a == cv.bsetr t0, t1, t2
0x2b,0xb5,0xc5,0x3a == cv.bsetr a0, a1, a2
0x2b,0xb4,0x24,0x3b == cv.bsetr s0, s1, s2
0xab,0x32,0x73,0x40 == cv.ror t0, t1, t2
0x2b,0xb5,0xc5,0x40 == cv.ror a0, a1, a2
0x2b,0xb4,0x24,0x41 == cv.ror s0, s1, s2
0xab,0x32,0x03,0x42 == cv.ff1 t0, t1
0x2b,0xb5,0x05,0x42 == cv.ff1 a0, a1
0x2b,0xb4,0x04,0x42 == cv.ff1 s0, s1
0xab,0x32,0x03,0x44 == cv.fl1 t0, t1
0x2b,0xb5,0x05,0x44 == cv.fl1 a0, a1
0x2b,0xb4,0x04,0x44 == cv.fl1 s0, s1
0xab,0x32,0x03,0x46 == cv.clb t0, t1
0x2b,0xb5,0x05,0x46 == cv.clb a0, a1
0x2b,0xb4,0x04,0x46 == cv.clb s0, s1
0xab,0x32,0x03,0x48 == cv.cnt t0, t1
0x2b,0xb5,0x05,0x48 == cv.cnt a0, a1
0x2b,0xb4,0x04,0x48 == cv.cnt s0, s1
external/capstone/suite/MC/RISCV/XCVelw_valid_riscv32_riscv_xcvelw.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVELW", None
0x0b,0x35,0x05,0x40 == cv.elw a0, 1024(a0)
0x8b,0xb5,0x15,0x00 == cv.elw a1, 1(a1)
0x0b,0xb6,0x06,0xc0 == cv.elw a2, -1024(a3)
external/capstone/suite/MC/RISCV/XCVmac_valid_riscv32_riscv_xcvmac_syntax_no_alias_text.txt.cs
Vendored
+57
View File
@@ -0,0 +1,57 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVMAC", None
0xab,0x32,0x73,0x90 == cv.mac t0, t1, t2
0xab,0x32,0x03,0x90 == cv.mac t0, t1, zero
0xdb,0x62,0x73,0x40 == cv.machhsn t0, t1, t2, 0
0xdb,0x62,0x03,0x60 == cv.machhsn t0, t1, zero, 16
0xdb,0x62,0x03,0x7e == cv.machhsn t0, t1, zero, 31
0xdb,0x62,0x73,0xc0 == cv.machhsrn t0, t1, t2, 0
0xdb,0x62,0x03,0xe0 == cv.machhsrn t0, t1, zero, 16
0xdb,0x62,0x03,0xfe == cv.machhsrn t0, t1, zero, 31
0xdb,0x72,0x73,0x40 == cv.machhun t0, t1, t2, 0
0xdb,0x72,0x03,0x60 == cv.machhun t0, t1, zero, 16
0xdb,0x72,0x03,0x7e == cv.machhun t0, t1, zero, 31
0xdb,0x72,0x73,0xc0 == cv.machhurn t0, t1, t2, 0
0xdb,0x72,0x03,0xe0 == cv.machhurn t0, t1, zero, 16
0xdb,0x72,0x03,0xfe == cv.machhurn t0, t1, zero, 31
0xdb,0x62,0x73,0x00 == cv.macsn t0, t1, t2, 0
0xdb,0x62,0x03,0x20 == cv.macsn t0, t1, zero, 16
0xdb,0x62,0x03,0x3e == cv.macsn t0, t1, zero, 31
0xdb,0x62,0x73,0x80 == cv.macsrn t0, t1, t2, 0
0xdb,0x62,0x03,0xa0 == cv.macsrn t0, t1, zero, 16
0xdb,0x62,0x03,0xbe == cv.macsrn t0, t1, zero, 31
0xdb,0x72,0x73,0x00 == cv.macun t0, t1, t2, 0
0xdb,0x72,0x03,0x20 == cv.macun t0, t1, zero, 16
0xdb,0x72,0x03,0x3e == cv.macun t0, t1, zero, 31
0xdb,0x72,0x73,0x80 == cv.macurn t0, t1, t2, 0
0xdb,0x72,0x03,0xa0 == cv.macurn t0, t1, zero, 16
0xdb,0x72,0x03,0xbe == cv.macurn t0, t1, zero, 31
0xab,0x32,0x73,0x92 == cv.msu t0, t1, t2
0xab,0x32,0x03,0x92 == cv.msu t0, t1, zero
0xdb,0x42,0x73,0x40 == cv.mulhhsn t0, t1, t2, 0
0xdb,0x42,0x03,0x40 == cv.mulhhsn t0, t1, zero, 0
0xdb,0x42,0x03,0x60 == cv.mulhhsn t0, t1, zero, 16
0xdb,0x42,0x03,0x7e == cv.mulhhsn t0, t1, zero, 31
0xdb,0x42,0x73,0xc0 == cv.mulhhsrn t0, t1, t2, 0
0xdb,0x42,0x03,0xe0 == cv.mulhhsrn t0, t1, zero, 16
0xdb,0x42,0x03,0xfe == cv.mulhhsrn t0, t1, zero, 31
0xdb,0x52,0x73,0x40 == cv.mulhhun t0, t1, t2, 0
0xdb,0x52,0x03,0x40 == cv.mulhhun t0, t1, zero, 0
0xdb,0x52,0x03,0x60 == cv.mulhhun t0, t1, zero, 16
0xdb,0x52,0x03,0x7e == cv.mulhhun t0, t1, zero, 31
0xdb,0x52,0x73,0xc0 == cv.mulhhurn t0, t1, t2, 0
0xdb,0x52,0x03,0xe0 == cv.mulhhurn t0, t1, zero, 16
0xdb,0x52,0x03,0xfe == cv.mulhhurn t0, t1, zero, 31
0xdb,0x42,0x73,0x00 == cv.mulsn t0, t1, t2, 0
0xdb,0x42,0x03,0x00 == cv.mulsn t0, t1, zero, 0
0xdb,0x42,0x03,0x20 == cv.mulsn t0, t1, zero, 16
0xdb,0x42,0x03,0x3e == cv.mulsn t0, t1, zero, 31
0xdb,0x42,0x73,0x80 == cv.mulsrn t0, t1, t2, 0
0xdb,0x42,0x03,0xa0 == cv.mulsrn t0, t1, zero, 16
0xdb,0x42,0x03,0xbe == cv.mulsrn t0, t1, zero, 31
0xdb,0x52,0x73,0x00 == cv.mulun t0, t1, t2, 0
0xdb,0x52,0x03,0x00 == cv.mulun t0, t1, zero, 0
0xdb,0x52,0x03,0x20 == cv.mulun t0, t1, zero, 16
0xdb,0x52,0x03,0x3e == cv.mulun t0, t1, zero, 31
0xdb,0x52,0x73,0x80 == cv.mulurn t0, t1, t2, 0
0xdb,0x52,0x03,0xa0 == cv.mulurn t0, t1, zero, 16
0xdb,0x52,0x03,0xbe == cv.mulurn t0, t1, zero, 31
external/capstone/suite/MC/RISCV/XCVmem_valid_riscv32_riscv_xcvmem.txt.cs
Vendored
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVMEM", None
0x8b,0x02,0x03,0x00 == cv.lb t0, (t1), 0
0x0b,0x85,0xf5,0x7f == cv.lb a0, (a1), 2047
0xab,0x32,0x73,0x00 == cv.lb t0, (t1), t2
0x2b,0xb5,0xc5,0x00 == cv.lb a0, (a1), a2
0xab,0x32,0x73,0x08 == cv.lb t0, t2(t1)
0x2b,0xb5,0xc5,0x08 == cv.lb a0, a2(a1)
0x8b,0x42,0x03,0x00 == cv.lbu t0, (t1), 0
0x0b,0xc5,0xf5,0x7f == cv.lbu a0, (a1), 2047
0xab,0x32,0x73,0x10 == cv.lbu t0, (t1), t2
0x2b,0xb5,0xc5,0x10 == cv.lbu a0, (a1), a2
0xab,0x32,0x73,0x18 == cv.lbu t0, t2(t1)
0x2b,0xb5,0xc5,0x18 == cv.lbu a0, a2(a1)
0x8b,0x12,0x03,0x00 == cv.lh t0, (t1), 0
0x0b,0x95,0xf5,0x7f == cv.lh a0, (a1), 2047
0xab,0x32,0x73,0x02 == cv.lh t0, (t1), t2
0x2b,0xb5,0xc5,0x02 == cv.lh a0, (a1), a2
0xab,0x32,0x73,0x0a == cv.lh t0, t2(t1)
0x2b,0xb5,0xc5,0x0a == cv.lh a0, a2(a1)
0x8b,0x52,0x03,0x00 == cv.lhu t0, (t1), 0
0x0b,0xd5,0xf5,0x7f == cv.lhu a0, (a1), 2047
0xab,0x32,0x73,0x12 == cv.lhu t0, (t1), t2
0x2b,0xb5,0xc5,0x12 == cv.lhu a0, (a1), a2
0xab,0x32,0x73,0x1a == cv.lhu t0, t2(t1)
0x2b,0xb5,0xc5,0x1a == cv.lhu a0, a2(a1)
0x8b,0x22,0x03,0x00 == cv.lw t0, (t1), 0
0x0b,0xa5,0xf5,0x7f == cv.lw a0, (a1), 2047
0xab,0x32,0x73,0x04 == cv.lw t0, (t1), t2
0x2b,0xb5,0xc5,0x04 == cv.lw a0, (a1), a2
0xab,0x32,0x73,0x0c == cv.lw t0, t2(t1)
0x2b,0xb5,0xc5,0x0c == cv.lw a0, a2(a1)
0x2b,0x00,0x53,0x00 == cv.sb t0, (t1), 0
0xab,0x8f,0xa5,0x7e == cv.sb a0, (a1), 2047
0xab,0x33,0x53,0x20 == cv.sb t0, (t1), t2
0x2b,0xb6,0xa5,0x20 == cv.sb a0, (a1), a2
0xab,0x33,0x53,0x28 == cv.sb t0, t2(t1)
0x2b,0xb6,0xa5,0x28 == cv.sb a0, a2(a1)
0x2b,0x10,0x53,0x00 == cv.sh t0, (t1), 0
0xab,0x9f,0xa5,0x7e == cv.sh a0, (a1), 2047
0xab,0x33,0x53,0x22 == cv.sh t0, (t1), t2
0x2b,0xb6,0xa5,0x22 == cv.sh a0, (a1), a2
0xab,0x33,0x53,0x2a == cv.sh t0, t2(t1)
0x2b,0xb6,0xa5,0x2a == cv.sh a0, a2(a1)
0x2b,0x20,0x53,0x00 == cv.sw t0, (t1), 0
0xab,0xaf,0xa5,0x7e == cv.sw a0, (a1), 2047
0xab,0x33,0x53,0x24 == cv.sw t0, (t1), t2
0x2b,0xb6,0xa5,0x24 == cv.sw a0, (a1), a2
0xab,0x33,0x53,0x2c == cv.sw t0, t2(t1)
0x2b,0xb6,0xa5,0x2c == cv.sw a0, a2(a1)
external/capstone/suite/MC/RISCV/XCVsimd_riscv32_riscv_xcvsimd.txt.cs
Vendored
+881
View File
@@ -0,0 +1,881 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVSIMD", None
0xfb,0x02,0x73,0x00 == cv.add.h t0, t1, t2
0x7b,0x8e,0xee,0x01 == cv.add.h t3, t4, t5
0x7b,0x85,0xc5,0x00 == cv.add.h a0, a1, a2
0x7b,0x84,0x24,0x01 == cv.add.h s0, s1, s2
0xfb,0x12,0x73,0x00 == cv.add.b t0, t1, t2
0x7b,0x9e,0xee,0x01 == cv.add.b t3, t4, t5
0x7b,0x95,0xc5,0x00 == cv.add.b a0, a1, a2
0x7b,0x94,0x24,0x01 == cv.add.b s0, s1, s2
0xfb,0x42,0x73,0x00 == cv.add.sc.h t0, t1, t2
0x7b,0xce,0xee,0x01 == cv.add.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x00 == cv.add.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x01 == cv.add.sc.h s0, s1, s2
0xfb,0x52,0x73,0x00 == cv.add.sc.b t0, t1, t2
0x7b,0xde,0xee,0x01 == cv.add.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x00 == cv.add.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x01 == cv.add.sc.b s0, s1, s2
0xfb,0x62,0x03,0x00 == cv.add.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x01 == cv.add.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x02 == cv.add.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x03 == cv.add.sci.h s0, s1, -1
0xfb,0x72,0x03,0x00 == cv.add.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x01 == cv.add.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x02 == cv.add.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x03 == cv.add.sci.b s0, s1, -1
0xfb,0x02,0x73,0x08 == cv.sub.h t0, t1, t2
0x7b,0x8e,0xee,0x09 == cv.sub.h t3, t4, t5
0x7b,0x85,0xc5,0x08 == cv.sub.h a0, a1, a2
0x7b,0x84,0x24,0x09 == cv.sub.h s0, s1, s2
0xfb,0x12,0x73,0x08 == cv.sub.b t0, t1, t2
0x7b,0x9e,0xee,0x09 == cv.sub.b t3, t4, t5
0x7b,0x95,0xc5,0x08 == cv.sub.b a0, a1, a2
0x7b,0x94,0x24,0x09 == cv.sub.b s0, s1, s2
0xfb,0x42,0x73,0x08 == cv.sub.sc.h t0, t1, t2
0x7b,0xce,0xee,0x09 == cv.sub.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x08 == cv.sub.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x09 == cv.sub.sc.h s0, s1, s2
0xfb,0x52,0x73,0x08 == cv.sub.sc.b t0, t1, t2
0x7b,0xde,0xee,0x09 == cv.sub.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x08 == cv.sub.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x09 == cv.sub.sc.b s0, s1, s2
0xfb,0x62,0x03,0x08 == cv.sub.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x09 == cv.sub.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x0a == cv.sub.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x0b == cv.sub.sci.h s0, s1, -1
0xfb,0x72,0x03,0x08 == cv.sub.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x09 == cv.sub.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x0a == cv.sub.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x0b == cv.sub.sci.b s0, s1, -1
0xfb,0x02,0x73,0x10 == cv.avg.h t0, t1, t2
0x7b,0x8e,0xee,0x11 == cv.avg.h t3, t4, t5
0x7b,0x85,0xc5,0x10 == cv.avg.h a0, a1, a2
0x7b,0x84,0x24,0x11 == cv.avg.h s0, s1, s2
0xfb,0x12,0x73,0x10 == cv.avg.b t0, t1, t2
0x7b,0x9e,0xee,0x11 == cv.avg.b t3, t4, t5
0x7b,0x95,0xc5,0x10 == cv.avg.b a0, a1, a2
0x7b,0x94,0x24,0x11 == cv.avg.b s0, s1, s2
0xfb,0x42,0x73,0x10 == cv.avg.sc.h t0, t1, t2
0x7b,0xce,0xee,0x11 == cv.avg.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x10 == cv.avg.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x11 == cv.avg.sc.h s0, s1, s2
0xfb,0x52,0x73,0x10 == cv.avg.sc.b t0, t1, t2
0x7b,0xde,0xee,0x11 == cv.avg.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x10 == cv.avg.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x11 == cv.avg.sc.b s0, s1, s2
0xfb,0x62,0x03,0x10 == cv.avg.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x11 == cv.avg.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x12 == cv.avg.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x13 == cv.avg.sci.h s0, s1, -1
0xfb,0x72,0x03,0x10 == cv.avg.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x11 == cv.avg.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x12 == cv.avg.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x13 == cv.avg.sci.b s0, s1, -1
0xfb,0x02,0x73,0x18 == cv.avgu.h t0, t1, t2
0x7b,0x8e,0xee,0x19 == cv.avgu.h t3, t4, t5
0x7b,0x85,0xc5,0x18 == cv.avgu.h a0, a1, a2
0x7b,0x84,0x24,0x19 == cv.avgu.h s0, s1, s2
0xfb,0x12,0x73,0x18 == cv.avgu.b t0, t1, t2
0x7b,0x9e,0xee,0x19 == cv.avgu.b t3, t4, t5
0x7b,0x95,0xc5,0x18 == cv.avgu.b a0, a1, a2
0x7b,0x94,0x24,0x19 == cv.avgu.b s0, s1, s2
0xfb,0x42,0x73,0x18 == cv.avgu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x19 == cv.avgu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x18 == cv.avgu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x19 == cv.avgu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x18 == cv.avgu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x19 == cv.avgu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x18 == cv.avgu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x19 == cv.avgu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x18 == cv.avgu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x19 == cv.avgu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x1a == cv.avgu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x1b == cv.avgu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x18 == cv.avgu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x19 == cv.avgu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x1a == cv.avgu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x1b == cv.avgu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x20 == cv.min.h t0, t1, t2
0x7b,0x8e,0xee,0x21 == cv.min.h t3, t4, t5
0x7b,0x85,0xc5,0x20 == cv.min.h a0, a1, a2
0x7b,0x84,0x24,0x21 == cv.min.h s0, s1, s2
0xfb,0x12,0x73,0x20 == cv.min.b t0, t1, t2
0x7b,0x9e,0xee,0x21 == cv.min.b t3, t4, t5
0x7b,0x95,0xc5,0x20 == cv.min.b a0, a1, a2
0x7b,0x94,0x24,0x21 == cv.min.b s0, s1, s2
0xfb,0x42,0x73,0x20 == cv.min.sc.h t0, t1, t2
0x7b,0xce,0xee,0x21 == cv.min.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x20 == cv.min.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x21 == cv.min.sc.h s0, s1, s2
0xfb,0x52,0x73,0x20 == cv.min.sc.b t0, t1, t2
0x7b,0xde,0xee,0x21 == cv.min.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x20 == cv.min.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x21 == cv.min.sc.b s0, s1, s2
0xfb,0x62,0x03,0x20 == cv.min.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x21 == cv.min.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x22 == cv.min.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x23 == cv.min.sci.h s0, s1, -1
0xfb,0x72,0x03,0x20 == cv.min.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x21 == cv.min.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x22 == cv.min.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x23 == cv.min.sci.b s0, s1, -1
0xfb,0x02,0x73,0x28 == cv.minu.h t0, t1, t2
0x7b,0x8e,0xee,0x29 == cv.minu.h t3, t4, t5
0x7b,0x85,0xc5,0x28 == cv.minu.h a0, a1, a2
0x7b,0x84,0x24,0x29 == cv.minu.h s0, s1, s2
0xfb,0x12,0x73,0x28 == cv.minu.b t0, t1, t2
0x7b,0x9e,0xee,0x29 == cv.minu.b t3, t4, t5
0x7b,0x95,0xc5,0x28 == cv.minu.b a0, a1, a2
0x7b,0x94,0x24,0x29 == cv.minu.b s0, s1, s2
0xfb,0x42,0x73,0x28 == cv.minu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x29 == cv.minu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x28 == cv.minu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x29 == cv.minu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x28 == cv.minu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x29 == cv.minu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x28 == cv.minu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x29 == cv.minu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x28 == cv.minu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x29 == cv.minu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x2a == cv.minu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x2b == cv.minu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x28 == cv.minu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x29 == cv.minu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x2a == cv.minu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x2b == cv.minu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x30 == cv.max.h t0, t1, t2
0x7b,0x8e,0xee,0x31 == cv.max.h t3, t4, t5
0x7b,0x85,0xc5,0x30 == cv.max.h a0, a1, a2
0x7b,0x84,0x24,0x31 == cv.max.h s0, s1, s2
0xfb,0x12,0x73,0x30 == cv.max.b t0, t1, t2
0x7b,0x9e,0xee,0x31 == cv.max.b t3, t4, t5
0x7b,0x95,0xc5,0x30 == cv.max.b a0, a1, a2
0x7b,0x94,0x24,0x31 == cv.max.b s0, s1, s2
0xfb,0x42,0x73,0x30 == cv.max.sc.h t0, t1, t2
0x7b,0xce,0xee,0x31 == cv.max.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x30 == cv.max.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x31 == cv.max.sc.h s0, s1, s2
0xfb,0x52,0x73,0x30 == cv.max.sc.b t0, t1, t2
0x7b,0xde,0xee,0x31 == cv.max.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x30 == cv.max.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x31 == cv.max.sc.b s0, s1, s2
0xfb,0x62,0x03,0x30 == cv.max.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x31 == cv.max.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x32 == cv.max.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x33 == cv.max.sci.h s0, s1, -1
0xfb,0x72,0x03,0x30 == cv.max.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x31 == cv.max.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x32 == cv.max.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x33 == cv.max.sci.b s0, s1, -1
0xfb,0x02,0x73,0x38 == cv.maxu.h t0, t1, t2
0x7b,0x8e,0xee,0x39 == cv.maxu.h t3, t4, t5
0x7b,0x85,0xc5,0x38 == cv.maxu.h a0, a1, a2
0x7b,0x84,0x24,0x39 == cv.maxu.h s0, s1, s2
0xfb,0x12,0x73,0x38 == cv.maxu.b t0, t1, t2
0x7b,0x9e,0xee,0x39 == cv.maxu.b t3, t4, t5
0x7b,0x95,0xc5,0x38 == cv.maxu.b a0, a1, a2
0x7b,0x94,0x24,0x39 == cv.maxu.b s0, s1, s2
0xfb,0x42,0x73,0x38 == cv.maxu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x39 == cv.maxu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x38 == cv.maxu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x39 == cv.maxu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x38 == cv.maxu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x39 == cv.maxu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x38 == cv.maxu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x39 == cv.maxu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x38 == cv.maxu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x39 == cv.maxu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x3a == cv.maxu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x3b == cv.maxu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x38 == cv.maxu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x39 == cv.maxu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x3a == cv.maxu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x3b == cv.maxu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x40 == cv.srl.h t0, t1, t2
0x7b,0x8e,0xee,0x41 == cv.srl.h t3, t4, t5
0x7b,0x85,0xc5,0x40 == cv.srl.h a0, a1, a2
0x7b,0x84,0x24,0x41 == cv.srl.h s0, s1, s2
0xfb,0x12,0x73,0x40 == cv.srl.b t0, t1, t2
0x7b,0x9e,0xee,0x41 == cv.srl.b t3, t4, t5
0x7b,0x95,0xc5,0x40 == cv.srl.b a0, a1, a2
0x7b,0x94,0x24,0x41 == cv.srl.b s0, s1, s2
0xfb,0x42,0x73,0x40 == cv.srl.sc.h t0, t1, t2
0x7b,0xce,0xee,0x41 == cv.srl.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x40 == cv.srl.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x41 == cv.srl.sc.h s0, s1, s2
0xfb,0x52,0x73,0x40 == cv.srl.sc.b t0, t1, t2
0x7b,0xde,0xee,0x41 == cv.srl.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x40 == cv.srl.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x41 == cv.srl.sc.b s0, s1, s2
0xfb,0x62,0x03,0x40 == cv.srl.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x40 == cv.srl.sci.h t3, t4, 0
0x7b,0xe5,0x35,0x42 == cv.srl.sci.h a0, a1, 7
0x7b,0xe4,0x74,0x42 == cv.srl.sci.h s0, s1, 15
0xfb,0x72,0x03,0x40 == cv.srl.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x40 == cv.srl.sci.b t3, t4, 0
0x7b,0xf5,0x35,0x42 == cv.srl.sci.b a0, a1, 7
0x7b,0xf4,0x34,0x42 == cv.srl.sci.b s0, s1, 7
0xfb,0x02,0x73,0x48 == cv.sra.h t0, t1, t2
0x7b,0x8e,0xee,0x49 == cv.sra.h t3, t4, t5
0x7b,0x85,0xc5,0x48 == cv.sra.h a0, a1, a2
0x7b,0x84,0x24,0x49 == cv.sra.h s0, s1, s2
0xfb,0x12,0x73,0x48 == cv.sra.b t0, t1, t2
0x7b,0x9e,0xee,0x49 == cv.sra.b t3, t4, t5
0x7b,0x95,0xc5,0x48 == cv.sra.b a0, a1, a2
0x7b,0x94,0x24,0x49 == cv.sra.b s0, s1, s2
0xfb,0x42,0x73,0x48 == cv.sra.sc.h t0, t1, t2
0x7b,0xce,0xee,0x49 == cv.sra.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x48 == cv.sra.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x49 == cv.sra.sc.h s0, s1, s2
0xfb,0x52,0x73,0x48 == cv.sra.sc.b t0, t1, t2
0x7b,0xde,0xee,0x49 == cv.sra.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x48 == cv.sra.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x49 == cv.sra.sc.b s0, s1, s2
0xfb,0x62,0x03,0x48 == cv.sra.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x48 == cv.sra.sci.h t3, t4, 0
0x7b,0xe5,0x35,0x4a == cv.sra.sci.h a0, a1, 7
0x7b,0xe4,0x74,0x4a == cv.sra.sci.h s0, s1, 15
0xfb,0x72,0x03,0x48 == cv.sra.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x48 == cv.sra.sci.b t3, t4, 0
0x7b,0xf5,0x35,0x4a == cv.sra.sci.b a0, a1, 7
0x7b,0xf4,0x34,0x4a == cv.sra.sci.b s0, s1, 7
0xfb,0x02,0x73,0x50 == cv.sll.h t0, t1, t2
0x7b,0x8e,0xee,0x51 == cv.sll.h t3, t4, t5
0x7b,0x85,0xc5,0x50 == cv.sll.h a0, a1, a2
0x7b,0x84,0x24,0x51 == cv.sll.h s0, s1, s2
0xfb,0x12,0x73,0x50 == cv.sll.b t0, t1, t2
0x7b,0x9e,0xee,0x51 == cv.sll.b t3, t4, t5
0x7b,0x95,0xc5,0x50 == cv.sll.b a0, a1, a2
0x7b,0x94,0x24,0x51 == cv.sll.b s0, s1, s2
0xfb,0x42,0x73,0x50 == cv.sll.sc.h t0, t1, t2
0x7b,0xce,0xee,0x51 == cv.sll.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x50 == cv.sll.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x51 == cv.sll.sc.h s0, s1, s2
0xfb,0x52,0x73,0x50 == cv.sll.sc.b t0, t1, t2
0x7b,0xde,0xee,0x51 == cv.sll.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x50 == cv.sll.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x51 == cv.sll.sc.b s0, s1, s2
0xfb,0x62,0x03,0x50 == cv.sll.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x50 == cv.sll.sci.h t3, t4, 0
0x7b,0xe5,0x35,0x52 == cv.sll.sci.h a0, a1, 7
0x7b,0xe4,0x74,0x52 == cv.sll.sci.h s0, s1, 15
0xfb,0x72,0x03,0x50 == cv.sll.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x50 == cv.sll.sci.b t3, t4, 0
0x7b,0xf5,0x35,0x52 == cv.sll.sci.b a0, a1, 7
0x7b,0xf4,0x34,0x52 == cv.sll.sci.b s0, s1, 7
0xfb,0x02,0x73,0x58 == cv.or.h t0, t1, t2
0x7b,0x8e,0xee,0x59 == cv.or.h t3, t4, t5
0x7b,0x85,0xc5,0x58 == cv.or.h a0, a1, a2
0x7b,0x84,0x24,0x59 == cv.or.h s0, s1, s2
0xfb,0x12,0x73,0x58 == cv.or.b t0, t1, t2
0x7b,0x9e,0xee,0x59 == cv.or.b t3, t4, t5
0x7b,0x95,0xc5,0x58 == cv.or.b a0, a1, a2
0x7b,0x94,0x24,0x59 == cv.or.b s0, s1, s2
0xfb,0x42,0x73,0x58 == cv.or.sc.h t0, t1, t2
0x7b,0xce,0xee,0x59 == cv.or.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x58 == cv.or.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x59 == cv.or.sc.h s0, s1, s2
0xfb,0x52,0x73,0x58 == cv.or.sc.b t0, t1, t2
0x7b,0xde,0xee,0x59 == cv.or.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x58 == cv.or.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x59 == cv.or.sc.b s0, s1, s2
0xfb,0x62,0x03,0x58 == cv.or.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x59 == cv.or.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x5a == cv.or.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x5b == cv.or.sci.h s0, s1, -1
0xfb,0x72,0x03,0x58 == cv.or.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x59 == cv.or.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x5a == cv.or.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x5b == cv.or.sci.b s0, s1, -1
0xfb,0x02,0x73,0x60 == cv.xor.h t0, t1, t2
0x7b,0x8e,0xee,0x61 == cv.xor.h t3, t4, t5
0x7b,0x85,0xc5,0x60 == cv.xor.h a0, a1, a2
0x7b,0x84,0x24,0x61 == cv.xor.h s0, s1, s2
0xfb,0x12,0x73,0x60 == cv.xor.b t0, t1, t2
0x7b,0x9e,0xee,0x61 == cv.xor.b t3, t4, t5
0x7b,0x95,0xc5,0x60 == cv.xor.b a0, a1, a2
0x7b,0x94,0x24,0x61 == cv.xor.b s0, s1, s2
0xfb,0x42,0x73,0x60 == cv.xor.sc.h t0, t1, t2
0x7b,0xce,0xee,0x61 == cv.xor.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x60 == cv.xor.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x61 == cv.xor.sc.h s0, s1, s2
0xfb,0x52,0x73,0x60 == cv.xor.sc.b t0, t1, t2
0x7b,0xde,0xee,0x61 == cv.xor.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x60 == cv.xor.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x61 == cv.xor.sc.b s0, s1, s2
0xfb,0x62,0x03,0x60 == cv.xor.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x61 == cv.xor.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x62 == cv.xor.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x63 == cv.xor.sci.h s0, s1, -1
0xfb,0x72,0x03,0x60 == cv.xor.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x61 == cv.xor.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x62 == cv.xor.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x63 == cv.xor.sci.b s0, s1, -1
0xfb,0x02,0x73,0x68 == cv.and.h t0, t1, t2
0x7b,0x8e,0xee,0x69 == cv.and.h t3, t4, t5
0x7b,0x85,0xc5,0x68 == cv.and.h a0, a1, a2
0x7b,0x84,0x24,0x69 == cv.and.h s0, s1, s2
0xfb,0x12,0x73,0x68 == cv.and.b t0, t1, t2
0x7b,0x9e,0xee,0x69 == cv.and.b t3, t4, t5
0x7b,0x95,0xc5,0x68 == cv.and.b a0, a1, a2
0x7b,0x94,0x24,0x69 == cv.and.b s0, s1, s2
0xfb,0x42,0x73,0x68 == cv.and.sc.h t0, t1, t2
0x7b,0xce,0xee,0x69 == cv.and.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x68 == cv.and.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x69 == cv.and.sc.h s0, s1, s2
0xfb,0x52,0x73,0x68 == cv.and.sc.b t0, t1, t2
0x7b,0xde,0xee,0x69 == cv.and.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x68 == cv.and.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x69 == cv.and.sc.b s0, s1, s2
0xfb,0x62,0x03,0x68 == cv.and.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x69 == cv.and.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x6a == cv.and.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x6b == cv.and.sci.h s0, s1, -1
0xfb,0x72,0x03,0x68 == cv.and.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x69 == cv.and.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x6a == cv.and.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x6b == cv.and.sci.b s0, s1, -1
0xfb,0x02,0x03,0x70 == cv.abs.h t0, t1
0x7b,0x8e,0x0e,0x70 == cv.abs.h t3, t4
0x7b,0x85,0x05,0x70 == cv.abs.h a0, a1
0x7b,0x84,0x04,0x70 == cv.abs.h s0, s1
0xfb,0x12,0x03,0x70 == cv.abs.b t0, t1
0x7b,0x9e,0x0e,0x70 == cv.abs.b t3, t4
0x7b,0x95,0x05,0x70 == cv.abs.b a0, a1
0x7b,0x94,0x04,0x70 == cv.abs.b s0, s1
0xfb,0x02,0x73,0x80 == cv.dotup.h t0, t1, t2
0x7b,0x8e,0xee,0x81 == cv.dotup.h t3, t4, t5
0x7b,0x85,0xc5,0x80 == cv.dotup.h a0, a1, a2
0x7b,0x84,0x24,0x81 == cv.dotup.h s0, s1, s2
0xfb,0x12,0x73,0x80 == cv.dotup.b t0, t1, t2
0x7b,0x9e,0xee,0x81 == cv.dotup.b t3, t4, t5
0x7b,0x95,0xc5,0x80 == cv.dotup.b a0, a1, a2
0x7b,0x94,0x24,0x81 == cv.dotup.b s0, s1, s2
0xfb,0x42,0x73,0x80 == cv.dotup.sc.h t0, t1, t2
0x7b,0xce,0xee,0x81 == cv.dotup.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x80 == cv.dotup.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x81 == cv.dotup.sc.h s0, s1, s2
0xfb,0x52,0x73,0x80 == cv.dotup.sc.b t0, t1, t2
0x7b,0xde,0xee,0x81 == cv.dotup.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x80 == cv.dotup.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x81 == cv.dotup.sc.b s0, s1, s2
0xfb,0x62,0x03,0x80 == cv.dotup.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x81 == cv.dotup.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x82 == cv.dotup.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x83 == cv.dotup.sci.h s0, s1, 63
0xfb,0x72,0x03,0x80 == cv.dotup.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x81 == cv.dotup.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x82 == cv.dotup.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x83 == cv.dotup.sci.b s0, s1, 63
0xfb,0x02,0x73,0x88 == cv.dotusp.h t0, t1, t2
0x7b,0x8e,0xee,0x89 == cv.dotusp.h t3, t4, t5
0x7b,0x85,0xc5,0x88 == cv.dotusp.h a0, a1, a2
0x7b,0x84,0x24,0x89 == cv.dotusp.h s0, s1, s2
0xfb,0x12,0x73,0x88 == cv.dotusp.b t0, t1, t2
0x7b,0x9e,0xee,0x89 == cv.dotusp.b t3, t4, t5
0x7b,0x95,0xc5,0x88 == cv.dotusp.b a0, a1, a2
0x7b,0x94,0x24,0x89 == cv.dotusp.b s0, s1, s2
0xfb,0x42,0x73,0x88 == cv.dotusp.sc.h t0, t1, t2
0x7b,0xce,0xee,0x89 == cv.dotusp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x88 == cv.dotusp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x89 == cv.dotusp.sc.h s0, s1, s2
0xfb,0x52,0x73,0x88 == cv.dotusp.sc.b t0, t1, t2
0x7b,0xde,0xee,0x89 == cv.dotusp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x88 == cv.dotusp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x89 == cv.dotusp.sc.b s0, s1, s2
0xfb,0x62,0x03,0x88 == cv.dotusp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x89 == cv.dotusp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x8a == cv.dotusp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x8b == cv.dotusp.sci.h s0, s1, -1
0xfb,0x72,0x03,0x88 == cv.dotusp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x89 == cv.dotusp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x8a == cv.dotusp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x8b == cv.dotusp.sci.b s0, s1, -1
0xfb,0x02,0x73,0x90 == cv.dotsp.h t0, t1, t2
0x7b,0x8e,0xee,0x91 == cv.dotsp.h t3, t4, t5
0x7b,0x85,0xc5,0x90 == cv.dotsp.h a0, a1, a2
0x7b,0x84,0x24,0x91 == cv.dotsp.h s0, s1, s2
0xfb,0x12,0x73,0x90 == cv.dotsp.b t0, t1, t2
0x7b,0x9e,0xee,0x91 == cv.dotsp.b t3, t4, t5
0x7b,0x95,0xc5,0x90 == cv.dotsp.b a0, a1, a2
0x7b,0x94,0x24,0x91 == cv.dotsp.b s0, s1, s2
0xfb,0x42,0x73,0x90 == cv.dotsp.sc.h t0, t1, t2
0x7b,0xce,0xee,0x91 == cv.dotsp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x90 == cv.dotsp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x91 == cv.dotsp.sc.h s0, s1, s2
0xfb,0x52,0x73,0x90 == cv.dotsp.sc.b t0, t1, t2
0x7b,0xde,0xee,0x91 == cv.dotsp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x90 == cv.dotsp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x91 == cv.dotsp.sc.b s0, s1, s2
0xfb,0x62,0x03,0x90 == cv.dotsp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x91 == cv.dotsp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x92 == cv.dotsp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x93 == cv.dotsp.sci.h s0, s1, -1
0xfb,0x72,0x03,0x90 == cv.dotsp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x91 == cv.dotsp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x92 == cv.dotsp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x93 == cv.dotsp.sci.b s0, s1, -1
0xfb,0x02,0x73,0x98 == cv.sdotup.h t0, t1, t2
0x7b,0x8e,0xee,0x99 == cv.sdotup.h t3, t4, t5
0x7b,0x85,0xc5,0x98 == cv.sdotup.h a0, a1, a2
0x7b,0x84,0x24,0x99 == cv.sdotup.h s0, s1, s2
0xfb,0x12,0x73,0x98 == cv.sdotup.b t0, t1, t2
0x7b,0x9e,0xee,0x99 == cv.sdotup.b t3, t4, t5
0x7b,0x95,0xc5,0x98 == cv.sdotup.b a0, a1, a2
0x7b,0x94,0x24,0x99 == cv.sdotup.b s0, s1, s2
0xfb,0x42,0x73,0x98 == cv.sdotup.sc.h t0, t1, t2
0x7b,0xce,0xee,0x99 == cv.sdotup.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x98 == cv.sdotup.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x99 == cv.sdotup.sc.h s0, s1, s2
0xfb,0x52,0x73,0x98 == cv.sdotup.sc.b t0, t1, t2
0x7b,0xde,0xee,0x99 == cv.sdotup.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x98 == cv.sdotup.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x99 == cv.sdotup.sc.b s0, s1, s2
0xfb,0x62,0x03,0x98 == cv.sdotup.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x99 == cv.sdotup.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x9a == cv.sdotup.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x9b == cv.sdotup.sci.h s0, s1, 63
0xfb,0x72,0x03,0x98 == cv.sdotup.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x99 == cv.sdotup.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x9a == cv.sdotup.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x9b == cv.sdotup.sci.b s0, s1, 63
0xfb,0x02,0x73,0xa0 == cv.sdotusp.h t0, t1, t2
0x7b,0x8e,0xee,0xa1 == cv.sdotusp.h t3, t4, t5
0x7b,0x85,0xc5,0xa0 == cv.sdotusp.h a0, a1, a2
0x7b,0x84,0x24,0xa1 == cv.sdotusp.h s0, s1, s2
0xfb,0x12,0x73,0xa0 == cv.sdotusp.b t0, t1, t2
0x7b,0x9e,0xee,0xa1 == cv.sdotusp.b t3, t4, t5
0x7b,0x95,0xc5,0xa0 == cv.sdotusp.b a0, a1, a2
0x7b,0x94,0x24,0xa1 == cv.sdotusp.b s0, s1, s2
0xfb,0x42,0x73,0xa0 == cv.sdotusp.sc.h t0, t1, t2
0x7b,0xce,0xee,0xa1 == cv.sdotusp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0xa0 == cv.sdotusp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0xa1 == cv.sdotusp.sc.h s0, s1, s2
0xfb,0x52,0x73,0xa0 == cv.sdotusp.sc.b t0, t1, t2
0x7b,0xde,0xee,0xa1 == cv.sdotusp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0xa0 == cv.sdotusp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0xa1 == cv.sdotusp.sc.b s0, s1, s2
0xfb,0x62,0x03,0xa0 == cv.sdotusp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0xa1 == cv.sdotusp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0xa2 == cv.sdotusp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0xa3 == cv.sdotusp.sci.h s0, s1, -1
0xfb,0x72,0x03,0xa0 == cv.sdotusp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xa1 == cv.sdotusp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0xa2 == cv.sdotusp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xa3 == cv.sdotusp.sci.b s0, s1, -1
0xfb,0x02,0x73,0xa8 == cv.sdotsp.h t0, t1, t2
0x7b,0x8e,0xee,0xa9 == cv.sdotsp.h t3, t4, t5
0x7b,0x85,0xc5,0xa8 == cv.sdotsp.h a0, a1, a2
0x7b,0x84,0x24,0xa9 == cv.sdotsp.h s0, s1, s2
0xfb,0x12,0x73,0xa8 == cv.sdotsp.b t0, t1, t2
0x7b,0x9e,0xee,0xa9 == cv.sdotsp.b t3, t4, t5
0x7b,0x95,0xc5,0xa8 == cv.sdotsp.b a0, a1, a2
0x7b,0x94,0x24,0xa9 == cv.sdotsp.b s0, s1, s2
0xfb,0x42,0x73,0xa8 == cv.sdotsp.sc.h t0, t1, t2
0x7b,0xce,0xee,0xa9 == cv.sdotsp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0xa8 == cv.sdotsp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0xa9 == cv.sdotsp.sc.h s0, s1, s2
0xfb,0x52,0x73,0xa8 == cv.sdotsp.sc.b t0, t1, t2
0x7b,0xde,0xee,0xa9 == cv.sdotsp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0xa8 == cv.sdotsp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0xa9 == cv.sdotsp.sc.b s0, s1, s2
0xfb,0x62,0x03,0xa8 == cv.sdotsp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0xa9 == cv.sdotsp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0xaa == cv.sdotsp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0xab == cv.sdotsp.sci.h s0, s1, -1
0xfb,0x72,0x03,0xa8 == cv.sdotsp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xa9 == cv.sdotsp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0xaa == cv.sdotsp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xab == cv.sdotsp.sci.b s0, s1, -1
0xfb,0x02,0x03,0xb8 == cv.extract.h t0, t1, 0
0x7b,0x8e,0x0e,0xb9 == cv.extract.h t3, t4, 32
0x7b,0x85,0x35,0xba == cv.extract.h a0, a1, 7
0x7b,0x84,0xf4,0xbb == cv.extract.h s0, s1, 63
0xfb,0x12,0x03,0xb8 == cv.extract.b t0, t1, 0
0x7b,0x9e,0x0e,0xb9 == cv.extract.b t3, t4, 32
0x7b,0x95,0x35,0xba == cv.extract.b a0, a1, 7
0x7b,0x94,0xf4,0xbb == cv.extract.b s0, s1, 63
0xfb,0x22,0x03,0xb8 == cv.extractu.h t0, t1, 0
0x7b,0xae,0x0e,0xb9 == cv.extractu.h t3, t4, 32
0x7b,0xa5,0x35,0xba == cv.extractu.h a0, a1, 7
0x7b,0xa4,0xf4,0xbb == cv.extractu.h s0, s1, 63
0xfb,0x32,0x03,0xb8 == cv.extractu.b t0, t1, 0
0x7b,0xbe,0x0e,0xb9 == cv.extractu.b t3, t4, 32
0x7b,0xb5,0x35,0xba == cv.extractu.b a0, a1, 7
0x7b,0xb4,0xf4,0xbb == cv.extractu.b s0, s1, 63
0xfb,0x42,0x03,0xb8 == cv.insert.h t0, t1, 0
0x7b,0xce,0x0e,0xb9 == cv.insert.h t3, t4, 32
0x7b,0xc5,0x35,0xba == cv.insert.h a0, a1, 7
0x7b,0xc4,0xf4,0xbb == cv.insert.h s0, s1, 63
0xfb,0x52,0x03,0xb8 == cv.insert.b t0, t1, 0
0x7b,0xde,0x0e,0xb9 == cv.insert.b t3, t4, 32
0x7b,0xd5,0x35,0xba == cv.insert.b a0, a1, 7
0x7b,0xd4,0xf4,0xbb == cv.insert.b s0, s1, 63
0xfb,0x02,0x73,0xc0 == cv.shuffle.h t0, t1, t2
0x7b,0x8e,0xee,0xc1 == cv.shuffle.h t3, t4, t5
0x7b,0x85,0xc5,0xc0 == cv.shuffle.h a0, a1, a2
0x7b,0x84,0x24,0xc1 == cv.shuffle.h s0, s1, s2
0xfb,0x12,0x73,0xc0 == cv.shuffle.b t0, t1, t2
0x7b,0x9e,0xee,0xc1 == cv.shuffle.b t3, t4, t5
0x7b,0x95,0xc5,0xc0 == cv.shuffle.b a0, a1, a2
0x7b,0x94,0x24,0xc1 == cv.shuffle.b s0, s1, s2
0xfb,0x62,0x03,0xc0 == cv.shuffle.sci.h t0, t1, 0
0x7b,0xee,0x0e,0xc1 == cv.shuffle.sci.h t3, t4, 32
0x7b,0xe5,0x35,0xc2 == cv.shuffle.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0xc3 == cv.shuffle.sci.h s0, s1, 63
0xfb,0x72,0x03,0xc0 == cv.shufflei0.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xc1 == cv.shufflei0.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xc2 == cv.shufflei0.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xc3 == cv.shufflei0.sci.b s0, s1, 63
0xfb,0x72,0x03,0xc8 == cv.shufflei1.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xc9 == cv.shufflei1.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xca == cv.shufflei1.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xcb == cv.shufflei1.sci.b s0, s1, 63
0xfb,0x72,0x03,0xd0 == cv.shufflei2.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xd1 == cv.shufflei2.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xd2 == cv.shufflei2.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xd3 == cv.shufflei2.sci.b s0, s1, 63
0xfb,0x72,0x03,0xd8 == cv.shufflei3.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xd9 == cv.shufflei3.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xda == cv.shufflei3.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xdb == cv.shufflei3.sci.b s0, s1, 63
0xfb,0x02,0x73,0xe0 == cv.shuffle2.h t0, t1, t2
0x7b,0x8e,0xee,0xe1 == cv.shuffle2.h t3, t4, t5
0x7b,0x85,0xc5,0xe0 == cv.shuffle2.h a0, a1, a2
0x7b,0x84,0x24,0xe1 == cv.shuffle2.h s0, s1, s2
0xfb,0x12,0x73,0xe0 == cv.shuffle2.b t0, t1, t2
0x7b,0x9e,0xee,0xe1 == cv.shuffle2.b t3, t4, t5
0x7b,0x95,0xc5,0xe0 == cv.shuffle2.b a0, a1, a2
0x7b,0x94,0x24,0xe1 == cv.shuffle2.b s0, s1, s2
0xfb,0x02,0x73,0xf0 == cv.pack t0, t1, t2
0x7b,0x8e,0xee,0xf1 == cv.pack t3, t4, t5
0x7b,0x85,0xc5,0xf0 == cv.pack a0, a1, a2
0x7b,0x84,0x24,0xf1 == cv.pack s0, s1, s2
0xfb,0x02,0x73,0xf2 == cv.pack.h t0, t1, t2
0x7b,0x8e,0xee,0xf3 == cv.pack.h t3, t4, t5
0x7b,0x85,0xc5,0xf2 == cv.pack.h a0, a1, a2
0x7b,0x84,0x24,0xf3 == cv.pack.h s0, s1, s2
0xfb,0x12,0x73,0xfa == cv.packhi.b t0, t1, t2
0x7b,0x9e,0xee,0xfb == cv.packhi.b t3, t4, t5
0x7b,0x95,0xc5,0xfa == cv.packhi.b a0, a1, a2
0x7b,0x94,0x24,0xfb == cv.packhi.b s0, s1, s2
0xfb,0x12,0x73,0xf8 == cv.packlo.b t0, t1, t2
0x7b,0x9e,0xee,0xf9 == cv.packlo.b t3, t4, t5
0x7b,0x95,0xc5,0xf8 == cv.packlo.b a0, a1, a2
0x7b,0x94,0x24,0xf9 == cv.packlo.b s0, s1, s2
0xfb,0x02,0x73,0x04 == cv.cmpeq.h t0, t1, t2
0x7b,0x8e,0xee,0x05 == cv.cmpeq.h t3, t4, t5
0x7b,0x85,0xc5,0x04 == cv.cmpeq.h a0, a1, a2
0x7b,0x84,0x24,0x05 == cv.cmpeq.h s0, s1, s2
0xfb,0x12,0x73,0x04 == cv.cmpeq.b t0, t1, t2
0x7b,0x9e,0xee,0x05 == cv.cmpeq.b t3, t4, t5
0x7b,0x95,0xc5,0x04 == cv.cmpeq.b a0, a1, a2
0x7b,0x94,0x24,0x05 == cv.cmpeq.b s0, s1, s2
0xfb,0x42,0x73,0x04 == cv.cmpeq.sc.h t0, t1, t2
0x7b,0xce,0xee,0x05 == cv.cmpeq.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x04 == cv.cmpeq.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x05 == cv.cmpeq.sc.h s0, s1, s2
0xfb,0x52,0x73,0x04 == cv.cmpeq.sc.b t0, t1, t2
0x7b,0xde,0xee,0x05 == cv.cmpeq.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x04 == cv.cmpeq.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x05 == cv.cmpeq.sc.b s0, s1, s2
0xfb,0x62,0x03,0x04 == cv.cmpeq.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x05 == cv.cmpeq.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x06 == cv.cmpeq.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x07 == cv.cmpeq.sci.h s0, s1, -1
0xfb,0x72,0x03,0x04 == cv.cmpeq.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x05 == cv.cmpeq.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x06 == cv.cmpeq.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x07 == cv.cmpeq.sci.b s0, s1, -1
0xfb,0x02,0x73,0x0c == cv.cmpne.h t0, t1, t2
0x7b,0x8e,0xee,0x0d == cv.cmpne.h t3, t4, t5
0x7b,0x85,0xc5,0x0c == cv.cmpne.h a0, a1, a2
0x7b,0x84,0x24,0x0d == cv.cmpne.h s0, s1, s2
0xfb,0x12,0x73,0x0c == cv.cmpne.b t0, t1, t2
0x7b,0x9e,0xee,0x0d == cv.cmpne.b t3, t4, t5
0x7b,0x95,0xc5,0x0c == cv.cmpne.b a0, a1, a2
0x7b,0x94,0x24,0x0d == cv.cmpne.b s0, s1, s2
0xfb,0x42,0x73,0x0c == cv.cmpne.sc.h t0, t1, t2
0x7b,0xce,0xee,0x0d == cv.cmpne.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x0c == cv.cmpne.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x0d == cv.cmpne.sc.h s0, s1, s2
0xfb,0x52,0x73,0x0c == cv.cmpne.sc.b t0, t1, t2
0x7b,0xde,0xee,0x0d == cv.cmpne.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x0c == cv.cmpne.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x0d == cv.cmpne.sc.b s0, s1, s2
0xfb,0x62,0x03,0x0c == cv.cmpne.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x0d == cv.cmpne.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x0e == cv.cmpne.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x0f == cv.cmpne.sci.h s0, s1, -1
0xfb,0x72,0x03,0x0c == cv.cmpne.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x0d == cv.cmpne.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x0e == cv.cmpne.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x0f == cv.cmpne.sci.b s0, s1, -1
0xfb,0x02,0x73,0x14 == cv.cmpgt.h t0, t1, t2
0x7b,0x8e,0xee,0x15 == cv.cmpgt.h t3, t4, t5
0x7b,0x85,0xc5,0x14 == cv.cmpgt.h a0, a1, a2
0x7b,0x84,0x24,0x15 == cv.cmpgt.h s0, s1, s2
0xfb,0x12,0x73,0x14 == cv.cmpgt.b t0, t1, t2
0x7b,0x9e,0xee,0x15 == cv.cmpgt.b t3, t4, t5
0x7b,0x95,0xc5,0x14 == cv.cmpgt.b a0, a1, a2
0x7b,0x94,0x24,0x15 == cv.cmpgt.b s0, s1, s2
0xfb,0x42,0x73,0x14 == cv.cmpgt.sc.h t0, t1, t2
0x7b,0xce,0xee,0x15 == cv.cmpgt.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x14 == cv.cmpgt.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x15 == cv.cmpgt.sc.h s0, s1, s2
0xfb,0x52,0x73,0x14 == cv.cmpgt.sc.b t0, t1, t2
0x7b,0xde,0xee,0x15 == cv.cmpgt.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x14 == cv.cmpgt.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x15 == cv.cmpgt.sc.b s0, s1, s2
0xfb,0x62,0x03,0x14 == cv.cmpgt.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x15 == cv.cmpgt.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x16 == cv.cmpgt.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x17 == cv.cmpgt.sci.h s0, s1, -1
0xfb,0x72,0x03,0x14 == cv.cmpgt.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x15 == cv.cmpgt.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x16 == cv.cmpgt.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x17 == cv.cmpgt.sci.b s0, s1, -1
0xfb,0x02,0x73,0x1c == cv.cmpge.h t0, t1, t2
0x7b,0x8e,0xee,0x1d == cv.cmpge.h t3, t4, t5
0x7b,0x85,0xc5,0x1c == cv.cmpge.h a0, a1, a2
0x7b,0x84,0x24,0x1d == cv.cmpge.h s0, s1, s2
0xfb,0x12,0x73,0x1c == cv.cmpge.b t0, t1, t2
0x7b,0x9e,0xee,0x1d == cv.cmpge.b t3, t4, t5
0x7b,0x95,0xc5,0x1c == cv.cmpge.b a0, a1, a2
0x7b,0x94,0x24,0x1d == cv.cmpge.b s0, s1, s2
0xfb,0x42,0x73,0x1c == cv.cmpge.sc.h t0, t1, t2
0x7b,0xce,0xee,0x1d == cv.cmpge.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x1c == cv.cmpge.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x1d == cv.cmpge.sc.h s0, s1, s2
0xfb,0x52,0x73,0x1c == cv.cmpge.sc.b t0, t1, t2
0x7b,0xde,0xee,0x1d == cv.cmpge.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x1c == cv.cmpge.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x1d == cv.cmpge.sc.b s0, s1, s2
0xfb,0x62,0x03,0x1c == cv.cmpge.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x1d == cv.cmpge.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x1e == cv.cmpge.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x1f == cv.cmpge.sci.h s0, s1, -1
0xfb,0x72,0x03,0x1c == cv.cmpge.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x1d == cv.cmpge.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x1e == cv.cmpge.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x1f == cv.cmpge.sci.b s0, s1, -1
0xfb,0x02,0x73,0x24 == cv.cmplt.h t0, t1, t2
0x7b,0x8e,0xee,0x25 == cv.cmplt.h t3, t4, t5
0x7b,0x85,0xc5,0x24 == cv.cmplt.h a0, a1, a2
0x7b,0x84,0x24,0x25 == cv.cmplt.h s0, s1, s2
0xfb,0x12,0x73,0x24 == cv.cmplt.b t0, t1, t2
0x7b,0x9e,0xee,0x25 == cv.cmplt.b t3, t4, t5
0x7b,0x95,0xc5,0x24 == cv.cmplt.b a0, a1, a2
0x7b,0x94,0x24,0x25 == cv.cmplt.b s0, s1, s2
0xfb,0x42,0x73,0x24 == cv.cmplt.sc.h t0, t1, t2
0x7b,0xce,0xee,0x25 == cv.cmplt.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x24 == cv.cmplt.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x25 == cv.cmplt.sc.h s0, s1, s2
0xfb,0x52,0x73,0x24 == cv.cmplt.sc.b t0, t1, t2
0x7b,0xde,0xee,0x25 == cv.cmplt.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x24 == cv.cmplt.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x25 == cv.cmplt.sc.b s0, s1, s2
0xfb,0x62,0x03,0x24 == cv.cmplt.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x25 == cv.cmplt.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x26 == cv.cmplt.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x27 == cv.cmplt.sci.h s0, s1, -1
0xfb,0x72,0x03,0x24 == cv.cmplt.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x25 == cv.cmplt.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x26 == cv.cmplt.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x27 == cv.cmplt.sci.b s0, s1, -1
0xfb,0x02,0x73,0x2c == cv.cmple.h t0, t1, t2
0x7b,0x8e,0xee,0x2d == cv.cmple.h t3, t4, t5
0x7b,0x85,0xc5,0x2c == cv.cmple.h a0, a1, a2
0x7b,0x84,0x24,0x2d == cv.cmple.h s0, s1, s2
0xfb,0x12,0x73,0x2c == cv.cmple.b t0, t1, t2
0x7b,0x9e,0xee,0x2d == cv.cmple.b t3, t4, t5
0x7b,0x95,0xc5,0x2c == cv.cmple.b a0, a1, a2
0x7b,0x94,0x24,0x2d == cv.cmple.b s0, s1, s2
0xfb,0x42,0x73,0x2c == cv.cmple.sc.h t0, t1, t2
0x7b,0xce,0xee,0x2d == cv.cmple.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x2c == cv.cmple.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x2d == cv.cmple.sc.h s0, s1, s2
0xfb,0x52,0x73,0x2c == cv.cmple.sc.b t0, t1, t2
0x7b,0xde,0xee,0x2d == cv.cmple.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x2c == cv.cmple.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x2d == cv.cmple.sc.b s0, s1, s2
0xfb,0x62,0x03,0x2c == cv.cmple.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x2d == cv.cmple.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x2e == cv.cmple.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x2f == cv.cmple.sci.h s0, s1, -1
0xfb,0x72,0x03,0x2c == cv.cmple.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x2d == cv.cmple.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x2e == cv.cmple.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x2f == cv.cmple.sci.b s0, s1, -1
0xfb,0x02,0x73,0x34 == cv.cmpgtu.h t0, t1, t2
0x7b,0x8e,0xee,0x35 == cv.cmpgtu.h t3, t4, t5
0x7b,0x85,0xc5,0x34 == cv.cmpgtu.h a0, a1, a2
0x7b,0x84,0x24,0x35 == cv.cmpgtu.h s0, s1, s2
0xfb,0x12,0x73,0x34 == cv.cmpgtu.b t0, t1, t2
0x7b,0x9e,0xee,0x35 == cv.cmpgtu.b t3, t4, t5
0x7b,0x95,0xc5,0x34 == cv.cmpgtu.b a0, a1, a2
0x7b,0x94,0x24,0x35 == cv.cmpgtu.b s0, s1, s2
0xfb,0x42,0x73,0x34 == cv.cmpgtu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x35 == cv.cmpgtu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x34 == cv.cmpgtu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x35 == cv.cmpgtu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x34 == cv.cmpgtu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x35 == cv.cmpgtu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x34 == cv.cmpgtu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x35 == cv.cmpgtu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x34 == cv.cmpgtu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x35 == cv.cmpgtu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x36 == cv.cmpgtu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x37 == cv.cmpgtu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x34 == cv.cmpgtu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x35 == cv.cmpgtu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x36 == cv.cmpgtu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x37 == cv.cmpgtu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x3c == cv.cmpgeu.h t0, t1, t2
0x7b,0x8e,0xee,0x3d == cv.cmpgeu.h t3, t4, t5
0x7b,0x85,0xc5,0x3c == cv.cmpgeu.h a0, a1, a2
0x7b,0x84,0x24,0x3d == cv.cmpgeu.h s0, s1, s2
0xfb,0x12,0x73,0x3c == cv.cmpgeu.b t0, t1, t2
0x7b,0x9e,0xee,0x3d == cv.cmpgeu.b t3, t4, t5
0x7b,0x95,0xc5,0x3c == cv.cmpgeu.b a0, a1, a2
0x7b,0x94,0x24,0x3d == cv.cmpgeu.b s0, s1, s2
0xfb,0x42,0x73,0x3c == cv.cmpgeu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x3d == cv.cmpgeu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x3c == cv.cmpgeu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x3d == cv.cmpgeu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x3c == cv.cmpgeu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x3d == cv.cmpgeu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x3c == cv.cmpgeu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x3d == cv.cmpgeu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x3c == cv.cmpgeu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x3d == cv.cmpgeu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x3e == cv.cmpgeu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x3f == cv.cmpgeu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x3c == cv.cmpgeu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x3d == cv.cmpgeu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x3e == cv.cmpgeu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x3f == cv.cmpgeu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x44 == cv.cmpltu.h t0, t1, t2
0x7b,0x8e,0xee,0x45 == cv.cmpltu.h t3, t4, t5
0x7b,0x85,0xc5,0x44 == cv.cmpltu.h a0, a1, a2
0x7b,0x84,0x24,0x45 == cv.cmpltu.h s0, s1, s2
0xfb,0x12,0x73,0x44 == cv.cmpltu.b t0, t1, t2
0x7b,0x9e,0xee,0x45 == cv.cmpltu.b t3, t4, t5
0x7b,0x95,0xc5,0x44 == cv.cmpltu.b a0, a1, a2
0x7b,0x94,0x24,0x45 == cv.cmpltu.b s0, s1, s2
0xfb,0x42,0x73,0x44 == cv.cmpltu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x45 == cv.cmpltu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x44 == cv.cmpltu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x45 == cv.cmpltu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x44 == cv.cmpltu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x45 == cv.cmpltu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x44 == cv.cmpltu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x45 == cv.cmpltu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x44 == cv.cmpltu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x45 == cv.cmpltu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x46 == cv.cmpltu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x47 == cv.cmpltu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x44 == cv.cmpltu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x45 == cv.cmpltu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x46 == cv.cmpltu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x47 == cv.cmpltu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x4c == cv.cmpleu.h t0, t1, t2
0x7b,0x8e,0xee,0x4d == cv.cmpleu.h t3, t4, t5
0x7b,0x85,0xc5,0x4c == cv.cmpleu.h a0, a1, a2
0x7b,0x84,0x24,0x4d == cv.cmpleu.h s0, s1, s2
0xfb,0x12,0x73,0x4c == cv.cmpleu.b t0, t1, t2
0x7b,0x9e,0xee,0x4d == cv.cmpleu.b t3, t4, t5
0x7b,0x95,0xc5,0x4c == cv.cmpleu.b a0, a1, a2
0x7b,0x94,0x24,0x4d == cv.cmpleu.b s0, s1, s2
0xfb,0x42,0x73,0x4c == cv.cmpleu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x4d == cv.cmpleu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x4c == cv.cmpleu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x4d == cv.cmpleu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x4c == cv.cmpleu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x4d == cv.cmpleu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x4c == cv.cmpleu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x4d == cv.cmpleu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x4c == cv.cmpleu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x4d == cv.cmpleu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x4e == cv.cmpleu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x4f == cv.cmpleu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x4c == cv.cmpleu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x4d == cv.cmpleu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x4e == cv.cmpleu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x4f == cv.cmpleu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x54 == cv.cplxmul.r t0, t1, t2
0x7b,0x8e,0xee,0x55 == cv.cplxmul.r t3, t4, t5
0x7b,0x85,0xc5,0x54 == cv.cplxmul.r a0, a1, a2
0x7b,0x84,0x24,0x55 == cv.cplxmul.r s0, s1, s2
0xfb,0x02,0x73,0x56 == cv.cplxmul.i t0, t1, t2
0x7b,0x8e,0xee,0x57 == cv.cplxmul.i t3, t4, t5
0x7b,0x85,0xc5,0x56 == cv.cplxmul.i a0, a1, a2
0x7b,0x84,0x24,0x57 == cv.cplxmul.i s0, s1, s2
0xfb,0x22,0x73,0x54 == cv.cplxmul.r.div2 t0, t1, t2
0x7b,0xae,0xee,0x55 == cv.cplxmul.r.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x54 == cv.cplxmul.r.div2 a0, a1, a2
0x7b,0xa4,0x24,0x55 == cv.cplxmul.r.div2 s0, s1, s2
0xfb,0x22,0x73,0x56 == cv.cplxmul.i.div2 t0, t1, t2
0x7b,0xae,0xee,0x57 == cv.cplxmul.i.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x56 == cv.cplxmul.i.div2 a0, a1, a2
0x7b,0xa4,0x24,0x57 == cv.cplxmul.i.div2 s0, s1, s2
0xfb,0x42,0x73,0x54 == cv.cplxmul.r.div4 t0, t1, t2
0x7b,0xce,0xee,0x55 == cv.cplxmul.r.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x54 == cv.cplxmul.r.div4 a0, a1, a2
0x7b,0xc4,0x24,0x55 == cv.cplxmul.r.div4 s0, s1, s2
0xfb,0x42,0x73,0x56 == cv.cplxmul.i.div4 t0, t1, t2
0x7b,0xce,0xee,0x57 == cv.cplxmul.i.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x56 == cv.cplxmul.i.div4 a0, a1, a2
0x7b,0xc4,0x24,0x57 == cv.cplxmul.i.div4 s0, s1, s2
0xfb,0x62,0x73,0x54 == cv.cplxmul.r.div8 t0, t1, t2
0x7b,0xee,0xee,0x55 == cv.cplxmul.r.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x54 == cv.cplxmul.r.div8 a0, a1, a2
0x7b,0xe4,0x24,0x55 == cv.cplxmul.r.div8 s0, s1, s2
0xfb,0x62,0x73,0x56 == cv.cplxmul.i.div8 t0, t1, t2
0x7b,0xee,0xee,0x57 == cv.cplxmul.i.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x56 == cv.cplxmul.i.div8 a0, a1, a2
0x7b,0xe4,0x24,0x57 == cv.cplxmul.i.div8 s0, s1, s2
0xfb,0x02,0x03,0x5c == cv.cplxconj t0, t1
0x7b,0x8e,0x0e,0x5c == cv.cplxconj t3, t4
0x7b,0x85,0x05,0x5c == cv.cplxconj a0, a1
0x7b,0x84,0x04,0x5c == cv.cplxconj s0, s1
0xfb,0x02,0x73,0x64 == cv.subrotmj t0, t1, t2
0x7b,0x8e,0xee,0x65 == cv.subrotmj t3, t4, t5
0x7b,0x85,0xc5,0x64 == cv.subrotmj a0, a1, a2
0x7b,0x84,0x24,0x65 == cv.subrotmj s0, s1, s2
0xfb,0x22,0x73,0x64 == cv.subrotmj.div2 t0, t1, t2
0x7b,0xae,0xee,0x65 == cv.subrotmj.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x64 == cv.subrotmj.div2 a0, a1, a2
0x7b,0xa4,0x24,0x65 == cv.subrotmj.div2 s0, s1, s2
0xfb,0x42,0x73,0x64 == cv.subrotmj.div4 t0, t1, t2
0x7b,0xce,0xee,0x65 == cv.subrotmj.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x64 == cv.subrotmj.div4 a0, a1, a2
0x7b,0xc4,0x24,0x65 == cv.subrotmj.div4 s0, s1, s2
0xfb,0x62,0x73,0x64 == cv.subrotmj.div8 t0, t1, t2
0x7b,0xee,0xee,0x65 == cv.subrotmj.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x64 == cv.subrotmj.div8 a0, a1, a2
0x7b,0xe4,0x24,0x65 == cv.subrotmj.div8 s0, s1, s2
0xfb,0x22,0x73,0x6c == cv.add.div2 t0, t1, t2
0x7b,0xae,0xee,0x6d == cv.add.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x6c == cv.add.div2 a0, a1, a2
0x7b,0xa4,0x24,0x6d == cv.add.div2 s0, s1, s2
0xfb,0x42,0x73,0x6c == cv.add.div4 t0, t1, t2
0x7b,0xce,0xee,0x6d == cv.add.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x6c == cv.add.div4 a0, a1, a2
0x7b,0xc4,0x24,0x6d == cv.add.div4 s0, s1, s2
0xfb,0x62,0x73,0x6c == cv.add.div8 t0, t1, t2
0x7b,0xee,0xee,0x6d == cv.add.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x6c == cv.add.div8 a0, a1, a2
0x7b,0xe4,0x24,0x6d == cv.add.div8 s0, s1, s2
0xfb,0x22,0x73,0x74 == cv.sub.div2 t0, t1, t2
0x7b,0xae,0xee,0x75 == cv.sub.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x74 == cv.sub.div2 a0, a1, a2
0x7b,0xa4,0x24,0x75 == cv.sub.div2 s0, s1, s2
0xfb,0x42,0x73,0x74 == cv.sub.div4 t0, t1, t2
0x7b,0xce,0xee,0x75 == cv.sub.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x74 == cv.sub.div4 a0, a1, a2
0x7b,0xc4,0x24,0x75 == cv.sub.div4 s0, s1, s2
0xfb,0x62,0x73,0x74 == cv.sub.div8 t0, t1, t2
0x7b,0xee,0xee,0x75 == cv.sub.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x74 == cv.sub.div8 a0, a1, a2
0x7b,0xe4,0x24,0x75 == cv.sub.div8 s0, s1, s2
external/capstone/suite/MC/RISCV/XTHeadBa_valid_riscv32_riscv_xtheadba.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADBA", None
0x8b,0x12,0x73,0x00 == th.addsl t0, t1, t2, 0
0x8b,0x12,0x73,0x02 == th.addsl t0, t1, t2, 1
0x8b,0x12,0x73,0x04 == th.addsl t0, t1, t2, 2
0x8b,0x12,0x73,0x06 == th.addsl t0, t1, t2, 3
external/capstone/suite/MC/RISCV/XTHeadVdot_valid_riscv64_riscv_xtheadvdot.txt.cs
Vendored
+15
View File
@@ -0,0 +1,15 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_XTHEADVDOT", None
0x0b,0x64,0x4a,0x88 == th.vmaqau.vv v8, v20, v4, v0.t
0x0b,0x64,0x4a,0x8a == th.vmaqau.vv v8, v20, v4
0x0b,0x64,0x45,0x8c == th.vmaqau.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x8e == th.vmaqau.vx v8, a0, v4
0x0b,0x64,0x4a,0x80 == th.vmaqa.vv v8, v20, v4, v0.t
0x0b,0x64,0x4a,0x82 == th.vmaqa.vv v8, v20, v4
0x0b,0x64,0x45,0x84 == th.vmaqa.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x86 == th.vmaqa.vx v8, a0, v4
0x0b,0x64,0x4a,0x90 == th.vmaqasu.vv v8, v20, v4, v0.t
0x0b,0x64,0x4a,0x92 == th.vmaqasu.vv v8, v20, v4
0x0b,0x64,0x45,0x94 == th.vmaqasu.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x96 == th.vmaqasu.vx v8, a0, v4
0x0b,0x64,0x45,0x9c == th.vmaqaus.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x9e == th.vmaqaus.vx v8, a0, v4
external/capstone/suite/MC/RISCV/XVentanaCondOps_valid_riscv64_xventanacondops_syntax_no_alias_text.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64", None
0x7b,0x60,0x00,0x00 == vt.maskc zero, zero, zero
0x7b,0x70,0x00,0x00 == vt.maskcn zero, zero, zero
0xfb,0x60,0x31,0x00 == vt.maskc ra, sp, gp
0xfb,0x70,0x31,0x00 == vt.maskcn ra, sp, gp
external/capstone/suite/MC/RISCV/Zawrs_valid_riscv32_zawrs_syntax_no_alias_text.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x00,0xd0,0x00 == wrs.nto
0x73,0x00,0xd0,0x01 == wrs.sto
external/capstone/suite/MC/RISCV/add_riscv64_riscv_v.txt.cs
Vendored
+60
View File
@@ -0,0 +1,60 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x00 == vadd.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x02 == vadd.vv v8, v4, v20
0x57,0x44,0x45,0x00 == vadd.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x02 == vadd.vx v8, v4, a0
0x57,0xb4,0x47,0x00 == vadd.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x02 == vadd.vi v8, v4, 15
0x57,0x24,0x4a,0xc0 == vwaddu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xc2 == vwaddu.vv v8, v4, v20
0x57,0x64,0x45,0xc0 == vwaddu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xc2 == vwaddu.vx v8, v4, a0
0x57,0x24,0x4a,0xc4 == vwadd.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xc6 == vwadd.vv v8, v4, v20
0x57,0x64,0x45,0xc4 == vwadd.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xc6 == vwadd.vx v8, v4, a0
0x57,0x24,0x4a,0xd0 == vwaddu.wv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xd2 == vwaddu.wv v8, v4, v20
0x57,0x64,0x45,0xd0 == vwaddu.wx v8, v4, a0, v0.t
0x57,0x64,0x45,0xd2 == vwaddu.wx v8, v4, a0
0x57,0x24,0x4a,0xd4 == vwadd.wv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xd6 == vwadd.wv v8, v4, v20
0x57,0x64,0x45,0xd4 == vwadd.wx v8, v4, a0, v0.t
0x57,0x64,0x45,0xd6 == vwadd.wx v8, v4, a0
0x57,0x04,0x4a,0x40 == vadc.vvm v8, v4, v20, v0
0x57,0x02,0x4a,0x40 == vadc.vvm v4, v4, v20, v0
0x57,0x04,0x44,0x40 == vadc.vvm v8, v4, v8, v0
0x57,0x44,0x45,0x40 == vadc.vxm v8, v4, a0, v0
0x57,0xb4,0x47,0x40 == vadc.vim v8, v4, 15, v0
0x57,0x04,0x4a,0x44 == vmadc.vvm v8, v4, v20, v0
0x57,0x02,0x4a,0x44 == vmadc.vvm v4, v4, v20, v0
0x57,0x04,0x44,0x44 == vmadc.vvm v8, v4, v8, v0
0x57,0x44,0x45,0x44 == vmadc.vxm v8, v4, a0, v0
0x57,0xb4,0x47,0x44 == vmadc.vim v8, v4, 15, v0
0x57,0x04,0x4a,0x46 == vmadc.vv v8, v4, v20
0x57,0x44,0x45,0x46 == vmadc.vx v8, v4, a0
0x57,0xb4,0x47,0x46 == vmadc.vi v8, v4, 15
0x57,0x04,0x4a,0x80 == vsaddu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x82 == vsaddu.vv v8, v4, v20
0x57,0x44,0x45,0x80 == vsaddu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x82 == vsaddu.vx v8, v4, a0
0x57,0xb4,0x47,0x80 == vsaddu.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x82 == vsaddu.vi v8, v4, 15
0x57,0x04,0x4a,0x84 == vsadd.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x86 == vsadd.vv v8, v4, v20
0x57,0x44,0x45,0x84 == vsadd.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x86 == vsadd.vx v8, v4, a0
0x57,0xb4,0x47,0x84 == vsadd.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x86 == vsadd.vi v8, v4, 15
0x57,0x24,0x4a,0x24 == vaadd.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x26 == vaadd.vv v8, v4, v20
0x57,0x64,0x45,0x24 == vaadd.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x26 == vaadd.vx v8, v4, a0
0x57,0x24,0x4a,0x20 == vaaddu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x22 == vaaddu.vv v8, v4, v20
0x57,0x64,0x45,0x20 == vaaddu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x22 == vaaddu.vx v8, v4, a0
0x57,0x64,0x40,0xc4 == vwcvt.x.x.v v8, v4, v0.t
0x57,0x64,0x40,0xc6 == vwcvt.x.x.v v8, v4
0x57,0x64,0x40,0xc0 == vwcvtu.x.x.v v8, v4, v0.t
0x57,0x64,0x40,0xc2 == vwcvtu.x.x.v v8, v4
external/capstone/suite/MC/RISCV/and_riscv64_riscv_v.txt.cs
Vendored
+7
View File
@@ -0,0 +1,7 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x24 == vand.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x26 == vand.vv v8, v4, v20
0x57,0x44,0x45,0x24 == vand.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x26 == vand.vx v8, v4, a0
0x57,0xb4,0x47,0x24 == vand.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x26 == vand.vi v8, v4, 15
external/capstone/suite/MC/RISCV/clip_riscv64_riscv_v.txt.cs
Vendored
+13
View File
@@ -0,0 +1,13 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0xb8 == vnclipu.wv v8, v4, v20, v0.t
0x57,0x04,0x4a,0xba == vnclipu.wv v8, v4, v20
0x57,0x44,0x45,0xb8 == vnclipu.wx v8, v4, a0, v0.t
0x57,0x44,0x45,0xba == vnclipu.wx v8, v4, a0
0x57,0xb4,0x4f,0xb8 == vnclipu.wi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0xba == vnclipu.wi v8, v4, 31
0x57,0x04,0x4a,0xbc == vnclip.wv v8, v4, v20, v0.t
0x57,0x04,0x4a,0xbe == vnclip.wv v8, v4, v20
0x57,0x44,0x45,0xbc == vnclip.wx v8, v4, a0, v0.t
0x57,0x44,0x45,0xbe == vnclip.wx v8, v4, a0
0x57,0xb4,0x4f,0xbc == vnclip.wi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0xbe == vnclip.wi v8, v4, 31
external/capstone/suite/MC/RISCV/compare_riscv64_riscv_v.txt.cs
Vendored
+58
View File
@@ -0,0 +1,58 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x00,0x4a,0x6c == vmslt.vv v0, v4, v20, v0.t
0x57,0x04,0x4a,0x60 == vmseq.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x62 == vmseq.vv v8, v4, v20
0x57,0x44,0x45,0x60 == vmseq.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x62 == vmseq.vx v8, v4, a0
0x57,0xb4,0x47,0x60 == vmseq.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x62 == vmseq.vi v8, v4, 15
0x57,0x04,0x4a,0x64 == vmsne.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x66 == vmsne.vv v8, v4, v20
0x57,0x44,0x45,0x64 == vmsne.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x66 == vmsne.vx v8, v4, a0
0x57,0xb4,0x47,0x64 == vmsne.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x66 == vmsne.vi v8, v4, 15
0x57,0x04,0x4a,0x68 == vmsltu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x6a == vmsltu.vv v8, v4, v20
0x57,0x44,0x45,0x68 == vmsltu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x6a == vmsltu.vx v8, v4, a0
0x57,0x04,0x4a,0x6c == vmslt.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x6e == vmslt.vv v8, v4, v20
0x57,0x44,0x45,0x6c == vmslt.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x6e == vmslt.vx v8, v4, a0
0x57,0x04,0x4a,0x70 == vmsleu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x72 == vmsleu.vv v8, v4, v20
0x57,0x44,0x45,0x70 == vmsleu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x72 == vmsleu.vx v8, v4, a0
0x57,0xb4,0x47,0x70 == vmsleu.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x72 == vmsleu.vi v8, v4, 15
0x57,0x04,0x4a,0x74 == vmsle.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x76 == vmsle.vv v8, v4, v20
0x57,0x44,0x45,0x74 == vmsle.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x76 == vmsle.vx v8, v4, a0
0x57,0xb4,0x47,0x74 == vmsle.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x76 == vmsle.vi v8, v4, 15
0x57,0x44,0x45,0x78 == vmsgtu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x7a == vmsgtu.vx v8, v4, a0
0x57,0xb4,0x47,0x78 == vmsgtu.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x7a == vmsgtu.vi v8, v4, 15
0x57,0x44,0x45,0x7c == vmsgt.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x7e == vmsgt.vx v8, v4, a0
0x57,0xb4,0x47,0x7c == vmsgt.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x7e == vmsgt.vi v8, v4, 15
0x57,0x04,0x42,0x64 == vmsne.vv v8, v4, v4, v0.t
0x57,0x04,0x42,0x66 == vmsne.vv v8, v4, v4
0x57,0x04,0x42,0x60 == vmseq.vv v8, v4, v4, v0.t
0x57,0x04,0x42,0x62 == vmseq.vv v8, v4, v4
0x57,0x24,0x84,0x76 == vmnot.m v8, v8
0x57,0x40,0x45,0x6e == vmslt.vx v0, v4, a0
0x57,0x20,0x00,0x76 == vmnot.m v0, v0
0x57,0x24,0x80,0x6e == vmxor.mm v8, v8, v0
0x57,0x41,0x45,0x6a == vmsltu.vx v2, v4, a0
0x57,0x20,0x01,0x62 == vmandn.mm v0, v0, v2
0x57,0x41,0x45,0x6e == vmslt.vx v2, v4, a0
0x57,0x21,0x01,0x62 == vmandn.mm v2, v0, v2
0xd7,0x24,0x90,0x62 == vmandn.mm v9, v9, v0
0xd7,0xa4,0x24,0x6a == vmor.mm v9, v2, v9
0x57,0x24,0x80,0x62 == vmandn.mm v8, v8, v0
0x57,0x24,0x24,0x6a == vmor.mm v8, v2, v8
external/capstone/suite/MC/RISCV/compress_cjal_riscv32_riscv_c.txt.cs
Vendored
+2
View File
@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0xfd,0x2f == jal 2046
external/capstone/suite/MC/RISCV/compress_rv32d_riscv32_riscv_c_riscv_d.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C"|"CS_MODE_RISCV_D", None
0x06,0x20 == fld ft0, 64(sp)
0x82,0xa0 == fsd ft0, 64(sp)
0x60,0x3c == fld fs0, 248(s0)
0x60,0xbc == fsd fs0, 248(s0)
external/capstone/suite/MC/RISCV/compress_rv32f_riscv32_riscv_c_riscv_f.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C"|"CS_MODE_RISCV_F", None
0x76,0x70 == flw ft0, 124(sp)
0x82,0xfe == fsw ft0, 124(sp)
0x60,0x7c == flw fs0, 124(s0)
0x60,0xfc == fsw fs0, 124(s0)
external/capstone/suite/MC/RISCV/compress_rv32i_riscv32_riscv_c.txt.cs
Vendored
+30
View File
@@ -0,0 +1,30 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0x2e,0x85 == mv a0, a1
0xe0,0x1f == addi s0, sp, 1020
0xe0,0x5f == lw s0, 124(a5)
0xe0,0xdf == sw s0, 124(a5)
0x01,0x00 == nop
0x81,0x10 == addi ra, ra, -32
0x85,0x50 == li ra, -31
0x39,0x71 == addi sp, sp, -64
0xfd,0x61 == lui gp, 31
0x7d,0x80 == srli s0, s0, 31
0x7d,0x84 == srai s0, s0, 31
0x7d,0x88 == andi s0, s0, 31
0x1d,0x8c == sub s0, s0, a5
0x3d,0x8c == xor s0, s0, a5
0x5d,0x8c == or s0, s0, a5
0x45,0x8c == or s0, s0, s1
0x7d,0x8c == and s0, s0, a5
0x01,0xb0 == j -2048
0x01,0xd0 == beqz s0, -256
0x7d,0xec == bnez s0, 254
0x7e,0x04 == slli s0, s0, 31
0xfe,0x50 == lw ra, 252(sp)
0x82,0x80 == ret
0x92,0x80 == mv ra, tp
0x02,0x90 == ebreak
0x02,0x94 == jalr s0
0x3e,0x94 == add s0, s0, a5
0x82,0xdf == sw zero, 252(sp)
0x00,0x00 == unimp
external/capstone/suite/MC/RISCV/compress_rv64i_riscv64_riscv_c.txt.cs
Vendored
+8
View File
@@ -0,0 +1,8 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_C", None
0xe0,0x7f == ld s0, 248(a5)
0xa0,0xe3 == sd s0, 64(a5)
0x7d,0x22 == addiw tp, tp, 31
0x1d,0x9c == subw s0, s0, a5
0x3d,0x9c == addw s0, s0, a5
0xee,0x70 == ld ra, 248(sp)
0xa2,0xe0 == sd s0, 64(sp)
external/capstone/suite/MC/RISCV/compressed_zicfiss_riscv32_riscv_experimental_zicfiss__experimental_zcmop_syntax_no_alias_text.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_EXPERIMENTAL_ZICFISS", None
0x81,0x62 == c.sspopchk t0
0x81,0x60 == c.sspush ra
external/capstone/suite/MC/RISCV/convert_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+44
View File
@@ -0,0 +1,44 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x40,0x48 == vfcvt.xu.f.v v8, v4, v0.t
0x57,0x14,0x40,0x4a == vfcvt.xu.f.v v8, v4
0x57,0x94,0x40,0x48 == vfcvt.x.f.v v8, v4, v0.t
0x57,0x94,0x40,0x4a == vfcvt.x.f.v v8, v4
0x57,0x14,0x41,0x48 == vfcvt.f.xu.v v8, v4, v0.t
0x57,0x14,0x41,0x4a == vfcvt.f.xu.v v8, v4
0x57,0x94,0x41,0x48 == vfcvt.f.x.v v8, v4, v0.t
0x57,0x94,0x41,0x4a == vfcvt.f.x.v v8, v4
0x57,0x14,0x43,0x48 == vfcvt.rtz.xu.f.v v8, v4, v0.t
0x57,0x14,0x43,0x4a == vfcvt.rtz.xu.f.v v8, v4
0x57,0x94,0x43,0x48 == vfcvt.rtz.x.f.v v8, v4, v0.t
0x57,0x94,0x43,0x4a == vfcvt.rtz.x.f.v v8, v4
0x57,0x14,0x44,0x48 == vfwcvt.xu.f.v v8, v4, v0.t
0x57,0x14,0x44,0x4a == vfwcvt.xu.f.v v8, v4
0x57,0x94,0x44,0x48 == vfwcvt.x.f.v v8, v4, v0.t
0x57,0x94,0x44,0x4a == vfwcvt.x.f.v v8, v4
0x57,0x14,0x45,0x48 == vfwcvt.f.xu.v v8, v4, v0.t
0x57,0x14,0x45,0x4a == vfwcvt.f.xu.v v8, v4
0x57,0x94,0x45,0x48 == vfwcvt.f.x.v v8, v4, v0.t
0x57,0x94,0x45,0x4a == vfwcvt.f.x.v v8, v4
0x57,0x14,0x46,0x48 == vfwcvt.f.f.v v8, v4, v0.t
0x57,0x14,0x46,0x4a == vfwcvt.f.f.v v8, v4
0x57,0x14,0x47,0x48 == vfwcvt.rtz.xu.f.v v8, v4, v0.t
0x57,0x14,0x47,0x4a == vfwcvt.rtz.xu.f.v v8, v4
0x57,0x94,0x47,0x48 == vfwcvt.rtz.x.f.v v8, v4, v0.t
0x57,0x94,0x47,0x4a == vfwcvt.rtz.x.f.v v8, v4
0x57,0x14,0x48,0x48 == vfncvt.xu.f.w v8, v4, v0.t
0x57,0x12,0x48,0x48 == vfncvt.xu.f.w v4, v4, v0.t
0x57,0x14,0x48,0x4a == vfncvt.xu.f.w v8, v4
0x57,0x94,0x48,0x48 == vfncvt.x.f.w v8, v4, v0.t
0x57,0x94,0x48,0x4a == vfncvt.x.f.w v8, v4
0x57,0x14,0x49,0x48 == vfncvt.f.xu.w v8, v4, v0.t
0x57,0x14,0x49,0x4a == vfncvt.f.xu.w v8, v4
0x57,0x94,0x49,0x48 == vfncvt.f.x.w v8, v4, v0.t
0x57,0x94,0x49,0x4a == vfncvt.f.x.w v8, v4
0x57,0x14,0x4a,0x48 == vfncvt.f.f.w v8, v4, v0.t
0x57,0x14,0x4a,0x4a == vfncvt.f.f.w v8, v4
0x57,0x94,0x4a,0x48 == vfncvt.rod.f.f.w v8, v4, v0.t
0x57,0x94,0x4a,0x4a == vfncvt.rod.f.f.w v8, v4
0x57,0x14,0x4b,0x48 == vfncvt.rtz.xu.f.w v8, v4, v0.t
0x57,0x14,0x4b,0x4a == vfncvt.rtz.xu.f.w v8, v4
0x57,0x94,0x4b,0x48 == vfncvt.rtz.x.f.w v8, v4, v0.t
0x57,0x94,0x4b,0x4a == vfncvt.rtz.x.f.w v8, v4
external/capstone/suite/MC/RISCV/debug_valid_riscv32_syntax_no_alias_text.txt.cs
Vendored
+2
View File
@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x00,0x20,0x7b == dret
external/capstone/suite/MC/RISCV/deprecated_csr_names_riscv32_syntax_no_alias_text.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x10,0x30,0x14 == csrrw zero, stval, zero
0x73,0x10,0x30,0x34 == csrrw zero, mtval, zero
0x73,0x10,0x00,0x18 == csrrw zero, satp, zero
external/capstone/suite/MC/RISCV/div_riscv64_riscv_v.txt.cs
Vendored
+17
View File
@@ -0,0 +1,17 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x80 == vdivu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x82 == vdivu.vv v8, v4, v20
0x57,0x64,0x45,0x80 == vdivu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x82 == vdivu.vx v8, v4, a0
0x57,0x24,0x4a,0x84 == vdiv.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x86 == vdiv.vv v8, v4, v20
0x57,0x64,0x45,0x84 == vdiv.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x86 == vdiv.vx v8, v4, a0
0x57,0x24,0x4a,0x88 == vremu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x8a == vremu.vv v8, v4, v20
0x57,0x64,0x45,0x88 == vremu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x8a == vremu.vx v8, v4, a0
0x57,0x24,0x4a,0x8c == vrem.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x8e == vrem.vv v8, v4, v20
0x57,0x64,0x45,0x8c == vrem.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x8e == vrem.vx v8, v4, a0
external/capstone/suite/MC/RISCV/ext_riscv64_riscv_v.txt.cs
Vendored
+13
View File
@@ -0,0 +1,13 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x43,0x48 == vzext.vf2 v8, v4, v0.t
0x57,0x24,0x43,0x4a == vzext.vf2 v8, v4
0x57,0xa4,0x43,0x48 == vsext.vf2 v8, v4, v0.t
0x57,0xa4,0x43,0x4a == vsext.vf2 v8, v4
0x57,0x24,0x42,0x48 == vzext.vf4 v8, v4, v0.t
0x57,0x24,0x42,0x4a == vzext.vf4 v8, v4
0x57,0xa4,0x42,0x48 == vsext.vf4 v8, v4, v0.t
0x57,0xa4,0x42,0x4a == vsext.vf4 v8, v4
0x57,0x24,0x41,0x48 == vzext.vf8 v8, v4, v0.t
0x57,0x24,0x41,0x4a == vzext.vf8 v8, v4
0x57,0xa4,0x41,0x48 == vsext.vf8 v8, v4, v0.t
0x57,0xa4,0x41,0x4a == vsext.vf8 v8, v4
external/capstone/suite/MC/RISCV/fadd_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+13
View File
@@ -0,0 +1,13 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x00 == vfadd.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x02 == vfadd.vv v8, v4, v20
0x57,0x54,0x45,0x00 == vfadd.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x02 == vfadd.vf v8, v4, fa0
0x57,0x14,0x4a,0xc0 == vfwadd.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xc2 == vfwadd.vv v8, v4, v20
0x57,0x54,0x45,0xc0 == vfwadd.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xc2 == vfwadd.vf v8, v4, fa0
0x57,0x14,0x4a,0xd0 == vfwadd.wv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xd2 == vfwadd.wv v8, v4, v20
0x57,0x54,0x45,0xd0 == vfwadd.wf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xd2 == vfwadd.wf v8, v4, fa0
external/capstone/suite/MC/RISCV/fcompare_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+22
View File
@@ -0,0 +1,22 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x60 == vmfeq.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x62 == vmfeq.vv v8, v4, v20
0x57,0x54,0x45,0x60 == vmfeq.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x62 == vmfeq.vf v8, v4, fa0
0x57,0x14,0x4a,0x70 == vmfne.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x72 == vmfne.vv v8, v4, v20
0x57,0x54,0x45,0x70 == vmfne.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x72 == vmfne.vf v8, v4, fa0
0x57,0x14,0x4a,0x6c == vmflt.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x6e == vmflt.vv v8, v4, v20
0x57,0x54,0x45,0x6c == vmflt.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x6e == vmflt.vf v8, v4, fa0
0x57,0x14,0x4a,0x64 == vmfle.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x66 == vmfle.vv v8, v4, v20
0x57,0x54,0x45,0x64 == vmfle.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x66 == vmfle.vf v8, v4, fa0
0x57,0x54,0x45,0x74 == vmfgt.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x76 == vmfgt.vf v8, v4, fa0
0x57,0x54,0x45,0x7c == vmfge.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x7e == vmfge.vf v8, v4, fa0
0x57,0x10,0x4a,0x60 == vmfeq.vv v0, v4, v20, v0.t
external/capstone/suite/MC/RISCV/fdiv_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+7
View File
@@ -0,0 +1,7 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x80 == vfdiv.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x82 == vfdiv.vv v8, v4, v20
0x57,0x54,0x45,0x80 == vfdiv.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x82 == vfdiv.vf v8, v4, fa0
0x57,0x54,0x45,0x84 == vfrdiv.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x86 == vfrdiv.vf v8, v4, fa0
external/capstone/suite/MC/RISCV/fixups_compressed_riscv32_riscv_c.txt.cs
Vendored
+2
View File
@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0x01,0x00 == nop
external/capstone/suite/MC/RISCV/fixups_riscv32_syntax_no_alias_text.txt.cs
Vendored
+2
View File
@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x13,0x00,0x00,0x00 == addi zero, zero, 0
external/capstone/suite/MC/RISCV/fmacc_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0xb0 == vfmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xb2 == vfmacc.vv v8, v20, v4
0x57,0x54,0x45,0xb0 == vfmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xb2 == vfmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xb4 == vfnmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xb6 == vfnmacc.vv v8, v20, v4
0x57,0x54,0x45,0xb4 == vfnmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xb6 == vfnmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xb8 == vfmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xba == vfmsac.vv v8, v20, v4
0x57,0x54,0x45,0xb8 == vfmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xba == vfmsac.vf v8, fa0, v4
0x57,0x14,0x4a,0xbc == vfnmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xbe == vfnmsac.vv v8, v20, v4
0x57,0x54,0x45,0xbc == vfnmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xbe == vfnmsac.vf v8, fa0, v4
0x57,0x14,0x4a,0xa0 == vfmadd.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xa2 == vfmadd.vv v8, v20, v4
0x57,0x54,0x45,0xa0 == vfmadd.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xa2 == vfmadd.vf v8, fa0, v4
0x57,0x14,0x4a,0xa4 == vfnmadd.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xa6 == vfnmadd.vv v8, v20, v4
0x57,0x54,0x45,0xa4 == vfnmadd.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xa6 == vfnmadd.vf v8, fa0, v4
0x57,0x14,0x4a,0xa8 == vfmsub.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xaa == vfmsub.vv v8, v20, v4
0x57,0x54,0x45,0xa8 == vfmsub.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xaa == vfmsub.vf v8, fa0, v4
0x57,0x14,0x4a,0xac == vfnmsub.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xae == vfnmsub.vv v8, v20, v4
0x57,0x54,0x45,0xac == vfnmsub.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xae == vfnmsub.vf v8, fa0, v4
0x57,0x14,0x4a,0xf0 == vfwmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xf2 == vfwmacc.vv v8, v20, v4
0x57,0x54,0x45,0xf0 == vfwmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xf2 == vfwmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xf4 == vfwnmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xf6 == vfwnmacc.vv v8, v20, v4
0x57,0x54,0x45,0xf4 == vfwnmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xf6 == vfwnmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xf8 == vfwmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xfa == vfwmsac.vv v8, v20, v4
0x57,0x54,0x45,0xf8 == vfwmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xfa == vfwmsac.vf v8, fa0, v4
0x57,0x14,0x4a,0xfc == vfwnmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xfe == vfwnmsac.vv v8, v20, v4
0x57,0x54,0x45,0xfc == vfwnmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xfe == vfwnmsac.vf v8, fa0, v4
external/capstone/suite/MC/RISCV/fminmax_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+9
View File
@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x10 == vfmin.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x12 == vfmin.vv v8, v4, v20
0x57,0x54,0x45,0x10 == vfmin.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x12 == vfmin.vf v8, v4, fa0
0x57,0x14,0x4a,0x18 == vfmax.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x1a == vfmax.vv v8, v4, v20
0x57,0x54,0x45,0x18 == vfmax.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x1a == vfmax.vf v8, v4, fa0
external/capstone/suite/MC/RISCV/fmul_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+9
View File
@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x90 == vfmul.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x92 == vfmul.vv v8, v4, v20
0x57,0x54,0x45,0x90 == vfmul.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x92 == vfmul.vf v8, v4, fa0
0x57,0x14,0x4a,0xe0 == vfwmul.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xe2 == vfwmul.vv v8, v4, v20
0x57,0x54,0x45,0xe0 == vfwmul.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xe2 == vfwmul.vf v8, v4, fa0
external/capstone/suite/MC/RISCV/fmv_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x54,0x05,0x5e == vfmv.v.f v8, fa0
0x57,0x15,0x40,0x42 == vfmv.f.s fa0, v4
0x57,0x54,0x05,0x42 == vfmv.s.f v8, fa0
external/capstone/suite/MC/RISCV/fothers_riscv64_riscv_v_riscv_f_syntax_no_alias_text.txt.cs
Vendored
+14
View File
@@ -0,0 +1,14 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x40,0x4c == vfsqrt.v v8, v4, v0.t
0x57,0x14,0x40,0x4e == vfsqrt.v v8, v4
0x57,0x14,0x42,0x4c == vfrsqrt7.v v8, v4, v0.t
0x57,0x14,0x42,0x4e == vfrsqrt7.v v8, v4
0x57,0x94,0x42,0x4c == vfrec7.v v8, v4, v0.t
0x57,0x94,0x42,0x4e == vfrec7.v v8, v4
0x57,0x14,0x48,0x4c == vfclass.v v8, v4, v0.t
0x57,0x14,0x48,0x4e == vfclass.v v8, v4
0x57,0x54,0x45,0x5c == vfmerge.vfm v8, v4, fa0, v0
0x57,0x54,0x45,0x38 == vfslide1up.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x3a == vfslide1up.vf v8, v4, fa0
0x57,0x54,0x45,0x3c == vfslide1down.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x3e == vfslide1down.vf v8, v4, fa0
external/capstone/suite/MC/RISCV/freduction_riscv64_riscv_v_riscv_f_syntax_no_alias_text.txt.cs
Vendored
+14
View File
@@ -0,0 +1,14 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x0c == vfredosum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x0e == vfredosum.vs v8, v4, v20
0x57,0x14,0x4a,0x04 == vfredusum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x06 == vfredusum.vs v8, v4, v20
0x57,0x14,0x4a,0x1c == vfredmax.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x1e == vfredmax.vs v8, v4, v20
0x57,0x14,0x4a,0x14 == vfredmin.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x16 == vfredmin.vs v8, v4, v20
0x57,0x14,0x4a,0xcc == vfwredosum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0xce == vfwredosum.vs v8, v4, v20
0x57,0x14,0x4a,0xc4 == vfwredusum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0xc6 == vfwredusum.vs v8, v4, v20
0x57,0x10,0x4a,0x0c == vfredosum.vs v0, v4, v20, v0.t
external/capstone/suite/MC/RISCV/fsub_riscv64_riscv_v_riscv_f.txt.cs
Vendored
+15
View File
@@ -0,0 +1,15 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x08 == vfsub.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x0a == vfsub.vv v8, v4, v20
0x57,0x54,0x45,0x08 == vfsub.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x0a == vfsub.vf v8, v4, fa0
0x57,0x54,0x45,0x9c == vfrsub.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x9e == vfrsub.vf v8, v4, fa0
0x57,0x14,0x4a,0xc8 == vfwsub.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xca == vfwsub.vv v8, v4, v20
0x57,0x54,0x45,0xc8 == vfwsub.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xca == vfwsub.vf v8, v4, fa0
0x57,0x14,0x4a,0xd8 == vfwsub.wv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xda == vfwsub.wv v8, v4, v20
0x57,0x54,0x45,0xd8 == vfwsub.wf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xda == vfwsub.wf v8, v4, fa0
external/capstone/suite/MC/RISCV/hypervisor_csr_names_riscv32_syntax_no_alias_text.txt.cs
Vendored
+75
View File
@@ -0,0 +1,75 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0x00,0x60 == csrrs t1, hstatus, zero
0xf3,0x23,0x00,0x60 == csrrs t2, hstatus, zero
0x73,0x23,0x20,0x60 == csrrs t1, hedeleg, zero
0xf3,0x23,0x20,0x60 == csrrs t2, hedeleg, zero
0x73,0x23,0x30,0x60 == csrrs t1, hideleg, zero
0xf3,0x23,0x30,0x60 == csrrs t2, hideleg, zero
0x73,0x23,0x40,0x60 == csrrs t1, hie, zero
0xf3,0x23,0x40,0x60 == csrrs t2, hie, zero
0x73,0x23,0x60,0x60 == csrrs t1, hcounteren, zero
0xf3,0x23,0x60,0x60 == csrrs t2, hcounteren, zero
0x73,0x23,0x70,0x60 == csrrs t1, hgeie, zero
0xf3,0x23,0x70,0x60 == csrrs t2, hgeie, zero
0x73,0x23,0x30,0x64 == csrrs t1, htval, zero
0xf3,0x23,0x30,0x64 == csrrs t2, htval, zero
0x73,0x23,0x40,0x64 == csrrs t1, hip, zero
0xf3,0x23,0x40,0x64 == csrrs t2, hip, zero
0x73,0x23,0x50,0x64 == csrrs t1, hvip, zero
0xf3,0x23,0x50,0x64 == csrrs t2, hvip, zero
0x73,0x23,0xa0,0x64 == csrrs t1, htinst, zero
0xf3,0x23,0xa0,0x64 == csrrs t2, htinst, zero
0x73,0x23,0x20,0xe1 == csrrs t1, hgeip, zero
0xf3,0x23,0x20,0xe1 == csrrs t2, hgeip, zero
0x73,0x23,0xa0,0x60 == csrrs t1, henvcfg, zero
0xf3,0x23,0xa0,0x60 == csrrs t2, henvcfg, zero
0x73,0x23,0x00,0x68 == csrrs t1, hgatp, zero
0xf3,0x23,0x00,0x68 == csrrs t2, hgatp, zero
0x73,0x23,0x80,0x6a == csrrs t1, hcontext, zero
0xf3,0x23,0x80,0x6a == csrrs t2, hcontext, zero
0x73,0x23,0x50,0x60 == csrrs t1, htimedelta, zero
0xf3,0x23,0x50,0x60 == csrrs t2, htimedelta, zero
0x73,0x23,0x00,0x20 == csrrs t1, vsstatus, zero
0xf3,0x23,0x00,0x20 == csrrs t2, vsstatus, zero
0x73,0x23,0x40,0x20 == csrrs t1, vsie, zero
0xf3,0x23,0x40,0x20 == csrrs t2, vsie, zero
0x73,0x23,0x50,0x20 == csrrs t1, vstvec, zero
0xf3,0x23,0x50,0x20 == csrrs t2, vstvec, zero
0x73,0x23,0x00,0x24 == csrrs t1, vsscratch, zero
0xf3,0x23,0x00,0x24 == csrrs t2, vsscratch, zero
0x73,0x23,0x10,0x24 == csrrs t1, vsepc, zero
0xf3,0x23,0x10,0x24 == csrrs t2, vsepc, zero
0x73,0x23,0x20,0x24 == csrrs t1, vscause, zero
0xf3,0x23,0x20,0x24 == csrrs t2, vscause, zero
0x73,0x23,0x30,0x24 == csrrs t1, vstval, zero
0xf3,0x23,0x30,0x24 == csrrs t2, vstval, zero
0x73,0x23,0x40,0x24 == csrrs t1, vsip, zero
0xf3,0x23,0x40,0x24 == csrrs t2, vsip, zero
0x73,0x23,0xd0,0x24 == csrrs t1, vstimecmp, zero
0xf3,0x23,0xd0,0x24 == csrrs t2, vstimecmp, zero
0x73,0x23,0x00,0x28 == csrrs t1, vsatp, zero
0xf3,0x23,0x00,0x28 == csrrs t2, vsatp, zero
0x73,0x23,0xc0,0x60 == csrrs t1, hstateen0, zero
0xf3,0x23,0xc0,0x60 == csrrs t2, hstateen0, zero
0x73,0x23,0xd0,0x60 == csrrs t1, hstateen1, zero
0xf3,0x23,0xd0,0x60 == csrrs t2, hstateen1, zero
0x73,0x23,0xe0,0x60 == csrrs t1, hstateen2, zero
0xf3,0x23,0xe0,0x60 == csrrs t2, hstateen2, zero
0x73,0x23,0xf0,0x60 == csrrs t1, hstateen3, zero
0xf3,0x23,0xf0,0x60 == csrrs t2, hstateen3, zero
0x73,0x23,0x80,0x60 == csrrs t1, hvien, zero
0xf3,0x23,0x80,0x60 == csrrs t2, hvien, zero
0x73,0x23,0x90,0x60 == csrrs t1, hvictl, zero
0xf3,0x23,0x90,0x60 == csrrs t2, hvictl, zero
0x73,0x23,0x60,0x64 == csrrs t1, hviprio1, zero
0xf3,0x23,0x60,0x64 == csrrs t2, hviprio1, zero
0x73,0x23,0x70,0x64 == csrrs t1, hviprio2, zero
0xf3,0x23,0x70,0x64 == csrrs t2, hviprio2, zero
0x73,0x23,0x00,0x25 == csrrs t1, vsiselect, zero
0xf3,0x23,0x00,0x25 == csrrs t2, vsiselect, zero
0x73,0x23,0x10,0x25 == csrrs t1, vsireg, zero
0xf3,0x23,0x10,0x25 == csrrs t2, vsireg, zero
0x73,0x23,0xc0,0x25 == csrrs t1, vstopei, zero
0xf3,0x23,0xc0,0x25 == csrrs t2, vstopei, zero
0x73,0x23,0x00,0xeb == csrrs t1, vstopi, zero
0xf3,0x23,0x00,0xeb == csrrs t2, vstopi, zero
external/capstone/suite/MC/RISCV/insn-riscv32.s.cs
Vendored
+13
View File
@@ -0,0 +1,13 @@
# CS_ARCH_RISCV, CS_MODE_RISCV32, None
0x37,0x34,0x00,0x00 = lui s0, 3
0x97,0x82,0x00,0x00 = auipc t0, 8
0x2f,0xae,0xaa,0x0a = amoswap.w.rl t3, a0, (s5)
0xe3,0x1f,0x31,0x5e = bne sp, gp, 0xdfe
0x73,0x00,0x00,0x00 = ecall
0x33,0x00,0x31,0x02 = mul zero, sp, gp
0x53,0x00,0x31,0x28 = fmin.s ft0, ft2, ft3
0x53,0x10,0x31,0x2a = fmax.d ft0, ft2, ft3
0x27,0xaa,0x6a,0x00 = fsw ft6, 0x14(s5)
// issues
0xef,0xf0,0x1f,0xff = jal -0x10
external/capstone/suite/MC/RISCV/insn-riscv64.s.cs
Vendored
+8
View File
@@ -0,0 +1,8 @@
# CS_ARCH_RISCV, CS_MODE_RISCV64, None
0x13,0x04,0xa8,0x7a = addi s0, a6, 0x7aa
0x1b,0x8e,0xaa,0x2a = addiw t3, s5, 0x2aa
0x2f,0xbe,0xaa,0x0a = amoswap.d.rl t3, a0, (s5)
0x3b,0x00,0x31,0x02 = mulw zero, sp, gp
0x53,0xa0,0x31,0xd0 = fcvt.s.lu ft0, gp, rdn
0x53,0x81,0x01,0xf2 = fmv.d.x ft2, gp
external/capstone/suite/MC/RISCV/load_riscv64_riscv_v_syntax_no_alias_text.txt.cs
Vendored
+59
View File
@@ -0,0 +1,59 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x07,0x00,0xb5,0x02 == vlm.v v0, (a0)
0x07,0x04,0xb5,0x02 == vlm.v v8, (a0)
0x07,0x04,0x05,0x00 == vle8.v v8, (a0), v0.t
0x07,0x04,0x05,0x02 == vle8.v v8, (a0)
0x07,0x54,0x05,0x00 == vle16.v v8, (a0), v0.t
0x07,0x54,0x05,0x02 == vle16.v v8, (a0)
0x07,0x64,0x05,0x00 == vle32.v v8, (a0), v0.t
0x07,0x64,0x05,0x02 == vle32.v v8, (a0)
0x07,0x74,0x05,0x00 == vle64.v v8, (a0), v0.t
0x07,0x74,0x05,0x02 == vle64.v v8, (a0)
0x07,0x04,0x05,0x01 == vle8ff.v v8, (a0), v0.t
0x07,0x04,0x05,0x03 == vle8ff.v v8, (a0)
0x07,0x54,0x05,0x01 == vle16ff.v v8, (a0), v0.t
0x07,0x54,0x05,0x03 == vle16ff.v v8, (a0)
0x07,0x64,0x05,0x01 == vle32ff.v v8, (a0), v0.t
0x07,0x64,0x05,0x03 == vle32ff.v v8, (a0)
0x07,0x74,0x05,0x01 == vle64ff.v v8, (a0), v0.t
0x07,0x74,0x05,0x03 == vle64ff.v v8, (a0)
0x07,0x04,0xb5,0x08 == vlse8.v v8, (a0), a1, v0.t
0x07,0x04,0xb5,0x0a == vlse8.v v8, (a0), a1
0x07,0x54,0xb5,0x08 == vlse16.v v8, (a0), a1, v0.t
0x07,0x54,0xb5,0x0a == vlse16.v v8, (a0), a1
0x07,0x64,0xb5,0x08 == vlse32.v v8, (a0), a1, v0.t
0x07,0x64,0xb5,0x0a == vlse32.v v8, (a0), a1
0x07,0x74,0xb5,0x08 == vlse64.v v8, (a0), a1, v0.t
0x07,0x74,0xb5,0x0a == vlse64.v v8, (a0), a1
0x07,0x04,0x45,0x04 == vluxei8.v v8, (a0), v4, v0.t
0x07,0x04,0x45,0x06 == vluxei8.v v8, (a0), v4
0x07,0x54,0x45,0x04 == vluxei16.v v8, (a0), v4, v0.t
0x07,0x54,0x45,0x06 == vluxei16.v v8, (a0), v4
0x07,0x64,0x45,0x04 == vluxei32.v v8, (a0), v4, v0.t
0x07,0x64,0x45,0x06 == vluxei32.v v8, (a0), v4
0x07,0x74,0x45,0x04 == vluxei64.v v8, (a0), v4, v0.t
0x07,0x74,0x45,0x06 == vluxei64.v v8, (a0), v4
0x07,0x04,0x45,0x0c == vloxei8.v v8, (a0), v4, v0.t
0x07,0x04,0x45,0x0e == vloxei8.v v8, (a0), v4
0x07,0x54,0x45,0x0c == vloxei16.v v8, (a0), v4, v0.t
0x07,0x54,0x45,0x0e == vloxei16.v v8, (a0), v4
0x07,0x64,0x45,0x0c == vloxei32.v v8, (a0), v4, v0.t
0x07,0x64,0x45,0x0e == vloxei32.v v8, (a0), v4
0x07,0x74,0x45,0x0c == vloxei64.v v8, (a0), v4, v0.t
0x07,0x74,0x45,0x0e == vloxei64.v v8, (a0), v4
0x07,0x04,0x85,0x02 == vl1re8.v v8, (a0)
0x07,0x54,0x85,0x02 == vl1re16.v v8, (a0)
0x07,0x64,0x85,0x02 == vl1re32.v v8, (a0)
0x07,0x74,0x85,0x02 == vl1re64.v v8, (a0)
0x07,0x04,0x85,0x22 == vl2re8.v v8, (a0)
0x07,0x54,0x85,0x22 == vl2re16.v v8, (a0)
0x07,0x64,0x85,0x22 == vl2re32.v v8, (a0)
0x07,0x74,0x85,0x22 == vl2re64.v v8, (a0)
0x07,0x04,0x85,0x62 == vl4re8.v v8, (a0)
0x07,0x54,0x85,0x62 == vl4re16.v v8, (a0)
0x07,0x64,0x85,0x62 == vl4re32.v v8, (a0)
0x07,0x74,0x85,0x62 == vl4re64.v v8, (a0)
0x07,0x04,0x85,0xe2 == vl8re8.v v8, (a0)
0x07,0x54,0x85,0xe2 == vl8re16.v v8, (a0)
0x07,0x64,0x85,0xe2 == vl8re32.v v8, (a0)
0x07,0x74,0x85,0xe2 == vl8re64.v v8, (a0)
external/capstone/suite/MC/RISCV/macc_riscv64_riscv_v.txt.cs
Vendored
+31
View File
@@ -0,0 +1,31 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0xb4 == vmacc.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xb6 == vmacc.vv v8, v20, v4
0x57,0x64,0x45,0xb4 == vmacc.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xb6 == vmacc.vx v8, a0, v4
0x57,0x24,0x4a,0xbc == vnmsac.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xbe == vnmsac.vv v8, v20, v4
0x57,0x64,0x45,0xbc == vnmsac.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xbe == vnmsac.vx v8, a0, v4
0x57,0x24,0x4a,0xa4 == vmadd.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xa6 == vmadd.vv v8, v20, v4
0x57,0x64,0x45,0xa4 == vmadd.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xa6 == vmadd.vx v8, a0, v4
0x57,0x24,0x4a,0xac == vnmsub.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xae == vnmsub.vv v8, v20, v4
0x57,0x64,0x45,0xac == vnmsub.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xae == vnmsub.vx v8, a0, v4
0x57,0x24,0x4a,0xf0 == vwmaccu.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xf2 == vwmaccu.vv v8, v20, v4
0x57,0x64,0x45,0xf0 == vwmaccu.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xf2 == vwmaccu.vx v8, a0, v4
0x57,0x24,0x4a,0xf4 == vwmacc.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xf6 == vwmacc.vv v8, v20, v4
0x57,0x64,0x45,0xf4 == vwmacc.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xf6 == vwmacc.vx v8, a0, v4
0x57,0x24,0x4a,0xfc == vwmaccsu.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xfe == vwmaccsu.vv v8, v20, v4
0x57,0x64,0x45,0xfc == vwmaccsu.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xfe == vwmaccsu.vx v8, a0, v4
0x57,0x64,0x45,0xf8 == vwmaccus.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xfa == vwmaccus.vx v8, a0, v4
external/capstone/suite/MC/RISCV/machine_csr_names_riscv32_syntax_no_alias_text.txt.cs
Vendored
+347
View File
@@ -0,0 +1,347 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0x10,0xf1 == csrrs t1, mvendorid, zero
0xf3,0x23,0x10,0xf1 == csrrs t2, mvendorid, zero
0x73,0x23,0x20,0xf1 == csrrs t1, marchid, zero
0xf3,0x23,0x20,0xf1 == csrrs t2, marchid, zero
0x73,0x23,0x30,0xf1 == csrrs t1, mimpid, zero
0xf3,0x23,0x30,0xf1 == csrrs t2, mimpid, zero
0x73,0x23,0x40,0xf1 == csrrs t1, mhartid, zero
0xf3,0x23,0x40,0xf1 == csrrs t2, mhartid, zero
0x73,0x23,0x50,0xf1 == csrrs t1, mconfigptr, zero
0xf3,0x23,0x50,0xf1 == csrrs t2, mconfigptr, zero
0x73,0x23,0x00,0x30 == csrrs t1, mstatus, zero
0xf3,0x23,0x00,0x30 == csrrs t2, mstatus, zero
0x73,0x23,0x10,0x30 == csrrs t1, misa, zero
0xf3,0x23,0x10,0x30 == csrrs t2, misa, zero
0x73,0x23,0x20,0x30 == csrrs t1, medeleg, zero
0xf3,0x23,0x20,0x30 == csrrs t2, medeleg, zero
0x73,0x23,0x30,0x30 == csrrs t1, mideleg, zero
0xf3,0x23,0x30,0x30 == csrrs t2, mideleg, zero
0x73,0x23,0x40,0x30 == csrrs t1, mie, zero
0xf3,0x23,0x40,0x30 == csrrs t2, mie, zero
0x73,0x23,0x50,0x30 == csrrs t1, mtvec, zero
0xf3,0x23,0x50,0x30 == csrrs t2, mtvec, zero
0x73,0x23,0x60,0x30 == csrrs t1, mcounteren, zero
0xf3,0x23,0x60,0x30 == csrrs t2, mcounteren, zero
0x73,0x23,0x00,0x34 == csrrs t1, mscratch, zero
0xf3,0x23,0x00,0x34 == csrrs t2, mscratch, zero
0x73,0x23,0x10,0x34 == csrrs t1, mepc, zero
0xf3,0x23,0x10,0x34 == csrrs t2, mepc, zero
0x73,0x23,0x20,0x34 == csrrs t1, mcause, zero
0xf3,0x23,0x20,0x34 == csrrs t2, mcause, zero
0x73,0x23,0x30,0x34 == csrrs t1, mtval, zero
0xf3,0x23,0x30,0x34 == csrrs t2, mtval, zero
0x73,0x23,0x40,0x34 == csrrs t1, mip, zero
0xf3,0x23,0x40,0x34 == csrrs t2, mip, zero
0x73,0x23,0xa0,0x34 == csrrs t1, mtinst, zero
0xf3,0x23,0xa0,0x34 == csrrs t2, mtinst, zero
0x73,0x23,0xb0,0x34 == csrrs t1, mtval2, zero
0xf3,0x23,0xb0,0x34 == csrrs t2, mtval2, zero
0x73,0x23,0xa0,0x30 == csrrs t1, menvcfg, zero
0xf3,0x23,0xa0,0x30 == csrrs t2, menvcfg, zero
0x73,0x23,0x70,0x74 == csrrs t1, mseccfg, zero
0xf3,0x23,0x70,0x74 == csrrs t2, mseccfg, zero
0x73,0x23,0x00,0x3a == csrrs t1, pmpcfg0, zero
0xf3,0x23,0x00,0x3a == csrrs t2, pmpcfg0, zero
0x73,0x23,0x20,0x3a == csrrs t1, pmpcfg2, zero
0xf3,0x23,0x20,0x3a == csrrs t2, pmpcfg2, zero
0x73,0x23,0x40,0x3a == csrrs t1, pmpcfg4, zero
0xf3,0x23,0x40,0x3a == csrrs t2, pmpcfg4, zero
0x73,0x23,0x60,0x3a == csrrs t1, pmpcfg6, zero
0xf3,0x23,0x60,0x3a == csrrs t2, pmpcfg6, zero
0x73,0x23,0x80,0x3a == csrrs t1, pmpcfg8, zero
0xf3,0x23,0x80,0x3a == csrrs t2, pmpcfg8, zero
0x73,0x23,0xa0,0x3a == csrrs t1, pmpcfg10, zero
0xf3,0x23,0xa0,0x3a == csrrs t2, pmpcfg10, zero
0x73,0x23,0xc0,0x3a == csrrs t1, pmpcfg12, zero
0xf3,0x23,0xc0,0x3a == csrrs t2, pmpcfg12, zero
0x73,0x23,0xe0,0x3a == csrrs t1, pmpcfg14, zero
0xf3,0x23,0xe0,0x3a == csrrs t2, pmpcfg14, zero
0x73,0x23,0x00,0x3b == csrrs t1, pmpaddr0, zero
0xf3,0x23,0x00,0x3b == csrrs t2, pmpaddr0, zero
0x73,0x23,0x10,0x3b == csrrs t1, pmpaddr1, zero
0xf3,0x23,0x10,0x3b == csrrs t2, pmpaddr1, zero
0x73,0x23,0x20,0x3b == csrrs t1, pmpaddr2, zero
0xf3,0x23,0x20,0x3b == csrrs t2, pmpaddr2, zero
0x73,0x23,0x30,0x3b == csrrs t1, pmpaddr3, zero
0xf3,0x23,0x30,0x3b == csrrs t2, pmpaddr3, zero
0x73,0x23,0x40,0x3b == csrrs t1, pmpaddr4, zero
0xf3,0x23,0x40,0x3b == csrrs t2, pmpaddr4, zero
0x73,0x23,0x50,0x3b == csrrs t1, pmpaddr5, zero
0xf3,0x23,0x50,0x3b == csrrs t2, pmpaddr5, zero
0x73,0x23,0x60,0x3b == csrrs t1, pmpaddr6, zero
0xf3,0x23,0x60,0x3b == csrrs t2, pmpaddr6, zero
0x73,0x23,0x70,0x3b == csrrs t1, pmpaddr7, zero
0xf3,0x23,0x70,0x3b == csrrs t2, pmpaddr7, zero
0x73,0x23,0x80,0x3b == csrrs t1, pmpaddr8, zero
0xf3,0x23,0x80,0x3b == csrrs t2, pmpaddr8, zero
0x73,0x23,0x90,0x3b == csrrs t1, pmpaddr9, zero
0xf3,0x23,0x90,0x3b == csrrs t2, pmpaddr9, zero
0x73,0x23,0xa0,0x3b == csrrs t1, pmpaddr10, zero
0xf3,0x23,0xa0,0x3b == csrrs t2, pmpaddr10, zero
0x73,0x23,0xb0,0x3b == csrrs t1, pmpaddr11, zero
0xf3,0x23,0xb0,0x3b == csrrs t2, pmpaddr11, zero
0x73,0x23,0xc0,0x3b == csrrs t1, pmpaddr12, zero
0xf3,0x23,0xc0,0x3b == csrrs t2, pmpaddr12, zero
0x73,0x23,0xd0,0x3b == csrrs t1, pmpaddr13, zero
0xf3,0x23,0xd0,0x3b == csrrs t2, pmpaddr13, zero
0x73,0x23,0xe0,0x3b == csrrs t1, pmpaddr14, zero
0xf3,0x23,0xe0,0x3b == csrrs t2, pmpaddr14, zero
0x73,0x23,0xf0,0x3b == csrrs t1, pmpaddr15, zero
0xf3,0x23,0xf0,0x3b == csrrs t2, pmpaddr15, zero
0x73,0x23,0x00,0x3c == csrrs t1, pmpaddr16, zero
0xf3,0x23,0x00,0x3c == csrrs t2, pmpaddr16, zero
0x73,0x23,0x10,0x3c == csrrs t1, pmpaddr17, zero
0xf3,0x23,0x10,0x3c == csrrs t2, pmpaddr17, zero
0x73,0x23,0x20,0x3c == csrrs t1, pmpaddr18, zero
0xf3,0x23,0x20,0x3c == csrrs t2, pmpaddr18, zero
0x73,0x23,0x30,0x3c == csrrs t1, pmpaddr19, zero
0xf3,0x23,0x30,0x3c == csrrs t2, pmpaddr19, zero
0x73,0x23,0x40,0x3c == csrrs t1, pmpaddr20, zero
0xf3,0x23,0x40,0x3c == csrrs t2, pmpaddr20, zero
0x73,0x23,0x50,0x3c == csrrs t1, pmpaddr21, zero
0xf3,0x23,0x50,0x3c == csrrs t2, pmpaddr21, zero
0x73,0x23,0x60,0x3c == csrrs t1, pmpaddr22, zero
0xf3,0x23,0x60,0x3c == csrrs t2, pmpaddr22, zero
0x73,0x23,0x70,0x3c == csrrs t1, pmpaddr23, zero
0xf3,0x23,0x70,0x3c == csrrs t2, pmpaddr23, zero
0x73,0x23,0x80,0x3c == csrrs t1, pmpaddr24, zero
0xf3,0x23,0x80,0x3c == csrrs t2, pmpaddr24, zero
0x73,0x23,0x90,0x3c == csrrs t1, pmpaddr25, zero
0xf3,0x23,0x90,0x3c == csrrs t2, pmpaddr25, zero
0x73,0x23,0xa0,0x3c == csrrs t1, pmpaddr26, zero
0xf3,0x23,0xa0,0x3c == csrrs t2, pmpaddr26, zero
0x73,0x23,0xb0,0x3c == csrrs t1, pmpaddr27, zero
0xf3,0x23,0xb0,0x3c == csrrs t2, pmpaddr27, zero
0x73,0x23,0xc0,0x3c == csrrs t1, pmpaddr28, zero
0xf3,0x23,0xc0,0x3c == csrrs t2, pmpaddr28, zero
0x73,0x23,0xd0,0x3c == csrrs t1, pmpaddr29, zero
0xf3,0x23,0xd0,0x3c == csrrs t2, pmpaddr29, zero
0x73,0x23,0xe0,0x3c == csrrs t1, pmpaddr30, zero
0xf3,0x23,0xe0,0x3c == csrrs t2, pmpaddr30, zero
0x73,0x23,0xf0,0x3c == csrrs t1, pmpaddr31, zero
0xf3,0x23,0xf0,0x3c == csrrs t2, pmpaddr31, zero
0x73,0x23,0x00,0x3d == csrrs t1, pmpaddr32, zero
0xf3,0x23,0x00,0x3d == csrrs t2, pmpaddr32, zero
0x73,0x23,0x10,0x3d == csrrs t1, pmpaddr33, zero
0xf3,0x23,0x10,0x3d == csrrs t2, pmpaddr33, zero
0x73,0x23,0x20,0x3d == csrrs t1, pmpaddr34, zero
0xf3,0x23,0x20,0x3d == csrrs t2, pmpaddr34, zero
0x73,0x23,0x30,0x3d == csrrs t1, pmpaddr35, zero
0xf3,0x23,0x30,0x3d == csrrs t2, pmpaddr35, zero
0x73,0x23,0x40,0x3d == csrrs t1, pmpaddr36, zero
0xf3,0x23,0x40,0x3d == csrrs t2, pmpaddr36, zero
0x73,0x23,0x50,0x3d == csrrs t1, pmpaddr37, zero
0xf3,0x23,0x50,0x3d == csrrs t2, pmpaddr37, zero
0x73,0x23,0x60,0x3d == csrrs t1, pmpaddr38, zero
0xf3,0x23,0x60,0x3d == csrrs t2, pmpaddr38, zero
0x73,0x23,0x70,0x3d == csrrs t1, pmpaddr39, zero
0xf3,0x23,0x70,0x3d == csrrs t2, pmpaddr39, zero
0x73,0x23,0x80,0x3d == csrrs t1, pmpaddr40, zero
0xf3,0x23,0x80,0x3d == csrrs t2, pmpaddr40, zero
0x73,0x23,0x90,0x3d == csrrs t1, pmpaddr41, zero
0xf3,0x23,0x90,0x3d == csrrs t2, pmpaddr41, zero
0x73,0x23,0xa0,0x3d == csrrs t1, pmpaddr42, zero
0xf3,0x23,0xa0,0x3d == csrrs t2, pmpaddr42, zero
0x73,0x23,0xb0,0x3d == csrrs t1, pmpaddr43, zero
0xf3,0x23,0xb0,0x3d == csrrs t2, pmpaddr43, zero
0x73,0x23,0xc0,0x3d == csrrs t1, pmpaddr44, zero
0xf3,0x23,0xc0,0x3d == csrrs t2, pmpaddr44, zero
0x73,0x23,0xd0,0x3d == csrrs t1, pmpaddr45, zero
0xf3,0x23,0xd0,0x3d == csrrs t2, pmpaddr45, zero
0x73,0x23,0xe0,0x3d == csrrs t1, pmpaddr46, zero
0xf3,0x23,0xe0,0x3d == csrrs t2, pmpaddr46, zero
0x73,0x23,0xf0,0x3d == csrrs t1, pmpaddr47, zero
0xf3,0x23,0xf0,0x3d == csrrs t2, pmpaddr47, zero
0x73,0x23,0x00,0x3e == csrrs t1, pmpaddr48, zero
0xf3,0x23,0x00,0x3e == csrrs t2, pmpaddr48, zero
0x73,0x23,0x10,0x3e == csrrs t1, pmpaddr49, zero
0xf3,0x23,0x10,0x3e == csrrs t2, pmpaddr49, zero
0x73,0x23,0x20,0x3e == csrrs t1, pmpaddr50, zero
0xf3,0x23,0x20,0x3e == csrrs t2, pmpaddr50, zero
0x73,0x23,0x30,0x3e == csrrs t1, pmpaddr51, zero
0xf3,0x23,0x30,0x3e == csrrs t2, pmpaddr51, zero
0x73,0x23,0x40,0x3e == csrrs t1, pmpaddr52, zero
0xf3,0x23,0x40,0x3e == csrrs t2, pmpaddr52, zero
0x73,0x23,0x50,0x3e == csrrs t1, pmpaddr53, zero
0xf3,0x23,0x50,0x3e == csrrs t2, pmpaddr53, zero
0x73,0x23,0x60,0x3e == csrrs t1, pmpaddr54, zero
0xf3,0x23,0x60,0x3e == csrrs t2, pmpaddr54, zero
0x73,0x23,0x70,0x3e == csrrs t1, pmpaddr55, zero
0xf3,0x23,0x70,0x3e == csrrs t2, pmpaddr55, zero
0x73,0x23,0x80,0x3e == csrrs t1, pmpaddr56, zero
0xf3,0x23,0x80,0x3e == csrrs t2, pmpaddr56, zero
0x73,0x23,0x90,0x3e == csrrs t1, pmpaddr57, zero
0xf3,0x23,0x90,0x3e == csrrs t2, pmpaddr57, zero
0x73,0x23,0xa0,0x3e == csrrs t1, pmpaddr58, zero
0xf3,0x23,0xa0,0x3e == csrrs t2, pmpaddr58, zero
0x73,0x23,0xb0,0x3e == csrrs t1, pmpaddr59, zero
0xf3,0x23,0xb0,0x3e == csrrs t2, pmpaddr59, zero
0x73,0x23,0xc0,0x3e == csrrs t1, pmpaddr60, zero
0xf3,0x23,0xc0,0x3e == csrrs t2, pmpaddr60, zero
0x73,0x23,0xd0,0x3e == csrrs t1, pmpaddr61, zero
0xf3,0x23,0xd0,0x3e == csrrs t2, pmpaddr61, zero
0x73,0x23,0xe0,0x3e == csrrs t1, pmpaddr62, zero
0xf3,0x23,0xe0,0x3e == csrrs t2, pmpaddr62, zero
0x73,0x23,0xf0,0x3e == csrrs t1, pmpaddr63, zero
0xf3,0x23,0xf0,0x3e == csrrs t2, pmpaddr63, zero
0x73,0x23,0x00,0xb0 == csrrs t1, mcycle, zero
0xf3,0x23,0x00,0xb0 == csrrs t2, mcycle, zero
0x73,0x23,0x20,0xb0 == csrrs t1, minstret, zero
0xf3,0x23,0x20,0xb0 == csrrs t2, minstret, zero
0x73,0x23,0x00,0x7a == csrrs t1, tselect, zero
0xf3,0x23,0x00,0x7a == csrrs t2, tselect, zero
0x73,0x23,0x10,0x7a == csrrs t1, tdata1, zero
0xf3,0x23,0x10,0x7a == csrrs t2, tdata1, zero
0x73,0x23,0x20,0x7a == csrrs t1, tdata2, zero
0xf3,0x23,0x20,0x7a == csrrs t2, tdata2, zero
0x73,0x23,0x30,0x7a == csrrs t1, tdata3, zero
0xf3,0x23,0x30,0x7a == csrrs t2, tdata3, zero
0x73,0x23,0x80,0x7a == csrrs t1, mcontext, zero
0xf3,0x23,0x80,0x7a == csrrs t2, mcontext, zero
0x73,0x23,0x00,0x7b == csrrs t1, dcsr, zero
0xf3,0x23,0x00,0x7b == csrrs t2, dcsr, zero
0x73,0x23,0x10,0x7b == csrrs t1, dpc, zero
0xf3,0x23,0x10,0x7b == csrrs t2, dpc, zero
0x73,0x23,0x20,0x7b == csrrs t1, dscratch0, zero
0xf3,0x23,0x20,0x7b == csrrs t2, dscratch0, zero
0x73,0x23,0x30,0x7b == csrrs t1, dscratch1, zero
0xf3,0x23,0x30,0x7b == csrrs t2, dscratch1, zero
0x73,0x23,0x30,0xb0 == csrrs t1, mhpmcounter3, zero
0xf3,0x23,0x30,0xb0 == csrrs t2, mhpmcounter3, zero
0x73,0x23,0x40,0xb0 == csrrs t1, mhpmcounter4, zero
0xf3,0x23,0x40,0xb0 == csrrs t2, mhpmcounter4, zero
0x73,0x23,0x50,0xb0 == csrrs t1, mhpmcounter5, zero
0xf3,0x23,0x50,0xb0 == csrrs t2, mhpmcounter5, zero
0x73,0x23,0x60,0xb0 == csrrs t1, mhpmcounter6, zero
0xf3,0x23,0x60,0xb0 == csrrs t2, mhpmcounter6, zero
0x73,0x23,0x70,0xb0 == csrrs t1, mhpmcounter7, zero
0xf3,0x23,0x70,0xb0 == csrrs t2, mhpmcounter7, zero
0x73,0x23,0x80,0xb0 == csrrs t1, mhpmcounter8, zero
0xf3,0x23,0x80,0xb0 == csrrs t2, mhpmcounter8, zero
0x73,0x23,0x90,0xb0 == csrrs t1, mhpmcounter9, zero
0xf3,0x23,0x90,0xb0 == csrrs t2, mhpmcounter9, zero
0x73,0x23,0xa0,0xb0 == csrrs t1, mhpmcounter10, zero
0xf3,0x23,0xa0,0xb0 == csrrs t2, mhpmcounter10, zero
0x73,0x23,0xb0,0xb0 == csrrs t1, mhpmcounter11, zero
0xf3,0x23,0xb0,0xb0 == csrrs t2, mhpmcounter11, zero
0x73,0x23,0xc0,0xb0 == csrrs t1, mhpmcounter12, zero
0xf3,0x23,0xc0,0xb0 == csrrs t2, mhpmcounter12, zero
0x73,0x23,0xd0,0xb0 == csrrs t1, mhpmcounter13, zero
0xf3,0x23,0xd0,0xb0 == csrrs t2, mhpmcounter13, zero
0x73,0x23,0xe0,0xb0 == csrrs t1, mhpmcounter14, zero
0xf3,0x23,0xe0,0xb0 == csrrs t2, mhpmcounter14, zero
0x73,0x23,0xf0,0xb0 == csrrs t1, mhpmcounter15, zero
0xf3,0x23,0xf0,0xb0 == csrrs t2, mhpmcounter15, zero
0x73,0x23,0x00,0xb1 == csrrs t1, mhpmcounter16, zero
0xf3,0x23,0x00,0xb1 == csrrs t2, mhpmcounter16, zero
0x73,0x23,0x10,0xb1 == csrrs t1, mhpmcounter17, zero
0xf3,0x23,0x10,0xb1 == csrrs t2, mhpmcounter17, zero
0x73,0x23,0x20,0xb1 == csrrs t1, mhpmcounter18, zero
0xf3,0x23,0x20,0xb1 == csrrs t2, mhpmcounter18, zero
0x73,0x23,0x30,0xb1 == csrrs t1, mhpmcounter19, zero
0xf3,0x23,0x30,0xb1 == csrrs t2, mhpmcounter19, zero
0x73,0x23,0x40,0xb1 == csrrs t1, mhpmcounter20, zero
0xf3,0x23,0x40,0xb1 == csrrs t2, mhpmcounter20, zero
0x73,0x23,0x50,0xb1 == csrrs t1, mhpmcounter21, zero
0xf3,0x23,0x50,0xb1 == csrrs t2, mhpmcounter21, zero
0x73,0x23,0x60,0xb1 == csrrs t1, mhpmcounter22, zero
0xf3,0x23,0x60,0xb1 == csrrs t2, mhpmcounter22, zero
0x73,0x23,0x70,0xb1 == csrrs t1, mhpmcounter23, zero
0xf3,0x23,0x70,0xb1 == csrrs t2, mhpmcounter23, zero
0x73,0x23,0x80,0xb1 == csrrs t1, mhpmcounter24, zero
0xf3,0x23,0x80,0xb1 == csrrs t2, mhpmcounter24, zero
0x73,0x23,0x90,0xb1 == csrrs t1, mhpmcounter25, zero
0xf3,0x23,0x90,0xb1 == csrrs t2, mhpmcounter25, zero
0x73,0x23,0xa0,0xb1 == csrrs t1, mhpmcounter26, zero
0xf3,0x23,0xa0,0xb1 == csrrs t2, mhpmcounter26, zero
0x73,0x23,0xb0,0xb1 == csrrs t1, mhpmcounter27, zero
0xf3,0x23,0xb0,0xb1 == csrrs t2, mhpmcounter27, zero
0x73,0x23,0xc0,0xb1 == csrrs t1, mhpmcounter28, zero
0xf3,0x23,0xc0,0xb1 == csrrs t2, mhpmcounter28, zero
0x73,0x23,0xd0,0xb1 == csrrs t1, mhpmcounter29, zero
0xf3,0x23,0xd0,0xb1 == csrrs t2, mhpmcounter29, zero
0x73,0x23,0xe0,0xb1 == csrrs t1, mhpmcounter30, zero
0xf3,0x23,0xe0,0xb1 == csrrs t2, mhpmcounter30, zero
0x73,0x23,0xf0,0xb1 == csrrs t1, mhpmcounter31, zero
0xf3,0x23,0xf0,0xb1 == csrrs t2, mhpmcounter31, zero
0x73,0x23,0x00,0x32 == csrrs t1, mcountinhibit, zero
0xf3,0x23,0x00,0x32 == csrrs t2, mcountinhibit, zero
0x73,0x23,0x30,0x32 == csrrs t1, mhpmevent3, zero
0xf3,0x23,0x30,0x32 == csrrs t2, mhpmevent3, zero
0x73,0x23,0x40,0x32 == csrrs t1, mhpmevent4, zero
0xf3,0x23,0x40,0x32 == csrrs t2, mhpmevent4, zero
0x73,0x23,0x50,0x32 == csrrs t1, mhpmevent5, zero
0xf3,0x23,0x50,0x32 == csrrs t2, mhpmevent5, zero
0x73,0x23,0x60,0x32 == csrrs t1, mhpmevent6, zero
0xf3,0x23,0x60,0x32 == csrrs t2, mhpmevent6, zero
0x73,0x23,0x70,0x32 == csrrs t1, mhpmevent7, zero
0xf3,0x23,0x70,0x32 == csrrs t2, mhpmevent7, zero
0x73,0x23,0x80,0x32 == csrrs t1, mhpmevent8, zero
0xf3,0x23,0x80,0x32 == csrrs t2, mhpmevent8, zero
0x73,0x23,0x90,0x32 == csrrs t1, mhpmevent9, zero
0xf3,0x23,0x90,0x32 == csrrs t2, mhpmevent9, zero
0x73,0x23,0xa0,0x32 == csrrs t1, mhpmevent10, zero
0xf3,0x23,0xa0,0x32 == csrrs t2, mhpmevent10, zero
0x73,0x23,0xb0,0x32 == csrrs t1, mhpmevent11, zero
0xf3,0x23,0xb0,0x32 == csrrs t2, mhpmevent11, zero
0x73,0x23,0xc0,0x32 == csrrs t1, mhpmevent12, zero
0xf3,0x23,0xc0,0x32 == csrrs t2, mhpmevent12, zero
0x73,0x23,0xd0,0x32 == csrrs t1, mhpmevent13, zero
0xf3,0x23,0xd0,0x32 == csrrs t2, mhpmevent13, zero
0x73,0x23,0xe0,0x32 == csrrs t1, mhpmevent14, zero
0xf3,0x23,0xe0,0x32 == csrrs t2, mhpmevent14, zero
0x73,0x23,0xf0,0x32 == csrrs t1, mhpmevent15, zero
0xf3,0x23,0xf0,0x32 == csrrs t2, mhpmevent15, zero
0x73,0x23,0x00,0x33 == csrrs t1, mhpmevent16, zero
0xf3,0x23,0x00,0x33 == csrrs t2, mhpmevent16, zero
0x73,0x23,0x10,0x33 == csrrs t1, mhpmevent17, zero
0xf3,0x23,0x10,0x33 == csrrs t2, mhpmevent17, zero
0x73,0x23,0x20,0x33 == csrrs t1, mhpmevent18, zero
0xf3,0x23,0x20,0x33 == csrrs t2, mhpmevent18, zero
0x73,0x23,0x30,0x33 == csrrs t1, mhpmevent19, zero
0xf3,0x23,0x30,0x33 == csrrs t2, mhpmevent19, zero
0x73,0x23,0x40,0x33 == csrrs t1, mhpmevent20, zero
0xf3,0x23,0x40,0x33 == csrrs t2, mhpmevent20, zero
0x73,0x23,0x50,0x33 == csrrs t1, mhpmevent21, zero
0xf3,0x23,0x50,0x33 == csrrs t2, mhpmevent21, zero
0x73,0x23,0x60,0x33 == csrrs t1, mhpmevent22, zero
0xf3,0x23,0x60,0x33 == csrrs t2, mhpmevent22, zero
0x73,0x23,0x70,0x33 == csrrs t1, mhpmevent23, zero
0xf3,0x23,0x70,0x33 == csrrs t2, mhpmevent23, zero
0x73,0x23,0x80,0x33 == csrrs t1, mhpmevent24, zero
0xf3,0x23,0x80,0x33 == csrrs t2, mhpmevent24, zero
0x73,0x23,0x90,0x33 == csrrs t1, mhpmevent25, zero
0xf3,0x23,0x90,0x33 == csrrs t2, mhpmevent25, zero
0x73,0x23,0xa0,0x33 == csrrs t1, mhpmevent26, zero
0xf3,0x23,0xa0,0x33 == csrrs t2, mhpmevent26, zero
0x73,0x23,0xb0,0x33 == csrrs t1, mhpmevent27, zero
0xf3,0x23,0xb0,0x33 == csrrs t2, mhpmevent27, zero
0x73,0x23,0xc0,0x33 == csrrs t1, mhpmevent28, zero
0xf3,0x23,0xc0,0x33 == csrrs t2, mhpmevent28, zero
0x73,0x23,0xd0,0x33 == csrrs t1, mhpmevent29, zero
0xf3,0x23,0xd0,0x33 == csrrs t2, mhpmevent29, zero
0x73,0x23,0xe0,0x33 == csrrs t1, mhpmevent30, zero
0xf3,0x23,0xe0,0x33 == csrrs t2, mhpmevent30, zero
0x73,0x23,0xf0,0x33 == csrrs t1, mhpmevent31, zero
0xf3,0x23,0xf0,0x33 == csrrs t2, mhpmevent31, zero
0x73,0x23,0xc0,0x30 == csrrs t1, mstateen0, zero
0xf3,0x23,0xc0,0x30 == csrrs t2, mstateen0, zero
0x73,0x23,0xd0,0x30 == csrrs t1, mstateen1, zero
0xf3,0x23,0xd0,0x30 == csrrs t2, mstateen1, zero
0x73,0x23,0xe0,0x30 == csrrs t1, mstateen2, zero
0xf3,0x23,0xe0,0x30 == csrrs t2, mstateen2, zero
0x73,0x23,0xf0,0x30 == csrrs t1, mstateen3, zero
0xf3,0x23,0xf0,0x30 == csrrs t2, mstateen3, zero
0x73,0x23,0x00,0x35 == csrrs t1, miselect, zero
0xf3,0x23,0x00,0x35 == csrrs t2, miselect, zero
0x73,0x23,0x10,0x35 == csrrs t1, mireg, zero
0xf3,0x23,0x10,0x35 == csrrs t2, mireg, zero
0x73,0x23,0xc0,0x35 == csrrs t1, mtopei, zero
0xf3,0x23,0xc0,0x35 == csrrs t2, mtopei, zero
0x73,0x23,0x00,0xfb == csrrs t1, mtopi, zero
0xf3,0x23,0x00,0xfb == csrrs t2, mtopi, zero
0x73,0x23,0x80,0x30 == csrrs t1, mvien, zero
0xf3,0x23,0x80,0x30 == csrrs t2, mvien, zero
0x73,0x23,0x90,0x30 == csrrs t1, mvip, zero
0xf3,0x23,0x90,0x30 == csrrs t2, mvip, zero
external/capstone/suite/MC/RISCV/mask_riscv64_riscv_v.txt.cs
Vendored
+27
View File
@@ -0,0 +1,27 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x66 == vmand.mm v8, v4, v20
0x57,0x24,0x4a,0x76 == vmnand.mm v8, v4, v20
0x57,0x24,0x4a,0x62 == vmandn.mm v8, v4, v20
0x57,0x24,0x4a,0x6e == vmxor.mm v8, v4, v20
0x57,0x24,0x4a,0x6a == vmor.mm v8, v4, v20
0x57,0x24,0x4a,0x7a == vmnor.mm v8, v4, v20
0x57,0x24,0x4a,0x72 == vmorn.mm v8, v4, v20
0x57,0x24,0x4a,0x7e == vmxnor.mm v8, v4, v20
0x57,0x26,0x48,0x40 == vcpop.m a2, v4, v0.t
0x57,0x26,0x48,0x42 == vcpop.m a2, v4
0x57,0xa6,0x48,0x40 == vfirst.m a2, v4, v0.t
0x57,0xa6,0x48,0x42 == vfirst.m a2, v4
0x57,0xa4,0x40,0x50 == vmsbf.m v8, v4, v0.t
0x57,0xa4,0x40,0x52 == vmsbf.m v8, v4
0x57,0xa4,0x41,0x50 == vmsif.m v8, v4, v0.t
0x57,0xa4,0x41,0x52 == vmsif.m v8, v4
0x57,0x24,0x41,0x50 == vmsof.m v8, v4, v0.t
0x57,0x24,0x41,0x52 == vmsof.m v8, v4
0x57,0x24,0x48,0x50 == viota.m v8, v4, v0.t
0x57,0x24,0x48,0x52 == viota.m v8, v4
0x57,0xa4,0x08,0x50 == vid.v v8, v0.t
0x57,0xa4,0x08,0x52 == vid.v v8
0x57,0x24,0x42,0x66 == vmmv.m v8, v4
0x57,0x24,0x84,0x6e == vmclr.m v8
0x57,0x24,0x84,0x7e == vmset.m v8
0x57,0x24,0x42,0x76 == vmnot.m v8, v4
external/capstone/suite/MC/RISCV/minmax_riscv64_riscv_v.txt.cs
Vendored
+17
View File
@@ -0,0 +1,17 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x10 == vminu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x12 == vminu.vv v8, v4, v20
0x57,0x44,0x45,0x10 == vminu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x12 == vminu.vx v8, v4, a0
0x57,0x04,0x4a,0x14 == vmin.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x16 == vmin.vv v8, v4, v20
0x57,0x44,0x45,0x14 == vmin.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x16 == vmin.vx v8, v4, a0
0x57,0x04,0x4a,0x18 == vmaxu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x1a == vmaxu.vv v8, v4, v20
0x57,0x44,0x45,0x18 == vmaxu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x1a == vmaxu.vx v8, v4, a0
0x57,0x04,0x4a,0x1c == vmax.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x1e == vmax.vv v8, v4, v20
0x57,0x44,0x45,0x1c == vmax.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x1e == vmax.vx v8, v4, a0
external/capstone/suite/MC/RISCV/mul_riscv64_riscv_v.txt.cs
Vendored
+33
View File
@@ -0,0 +1,33 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x94 == vmul.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x96 == vmul.vv v8, v4, v20
0x57,0x64,0x45,0x94 == vmul.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x96 == vmul.vx v8, v4, a0
0x57,0x24,0x4a,0x9c == vmulh.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x9e == vmulh.vv v8, v4, v20
0x57,0x64,0x45,0x9c == vmulh.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x9e == vmulh.vx v8, v4, a0
0x57,0x24,0x4a,0x90 == vmulhu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x92 == vmulhu.vv v8, v4, v20
0x57,0x64,0x45,0x90 == vmulhu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x92 == vmulhu.vx v8, v4, a0
0x57,0x24,0x4a,0x98 == vmulhsu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x9a == vmulhsu.vv v8, v4, v20
0x57,0x64,0x45,0x98 == vmulhsu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x9a == vmulhsu.vx v8, v4, a0
0x57,0x24,0x4a,0xec == vwmul.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xee == vwmul.vv v8, v4, v20
0x57,0x64,0x45,0xec == vwmul.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xee == vwmul.vx v8, v4, a0
0x57,0x24,0x4a,0xe0 == vwmulu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xe2 == vwmulu.vv v8, v4, v20
0x57,0x64,0x45,0xe0 == vwmulu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xe2 == vwmulu.vx v8, v4, a0
0x57,0x24,0x4a,0xe8 == vwmulsu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xea == vwmulsu.vv v8, v4, v20
0x57,0x64,0x45,0xe8 == vwmulsu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xea == vwmulsu.vx v8, v4, a0
0x57,0x04,0x4a,0x9c == vsmul.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x9e == vsmul.vv v8, v4, v20
0x57,0x44,0x45,0x9c == vsmul.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x9e == vsmul.vx v8, v4, a0
external/capstone/suite/MC/RISCV/mv_riscv64_riscv_v.txt.cs
Vendored
+10
View File
@@ -0,0 +1,10 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x0a,0x5e == vmv.v.v v8, v20
0x57,0x44,0x05,0x5e == vmv.v.x v8, a0
0x57,0xb4,0x07,0x5e == vmv.v.i v8, 15
0x57,0x26,0x40,0x42 == vmv.x.s a2, v4
0x57,0x64,0x05,0x42 == vmv.s.x v8, a0
0x57,0x34,0x40,0x9e == vmv1r.v v8, v4
0x57,0xb4,0x40,0x9e == vmv2r.v v8, v4
0x57,0xb4,0x41,0x9e == vmv4r.v v8, v4
0x57,0xb4,0x83,0x9f == vmv8r.v v8, v24
external/capstone/suite/MC/RISCV/option_arch_riscv32.txt.cs
Vendored
+10
View File
@@ -0,0 +1,10 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x13,0x85,0x05,0x00 == mv a0, a1
0x13,0x04,0xc1,0x3f == addi s0, sp, 1020
0x2e,0x85 == mv a0, a1
0xe0,0x1f == addi s0, sp, 1020
0x07,0x20,0xc5,0x00 == flw ft0, 12(a0)
0x33,0x87,0x80,0x02 == mul a4, ra, s0
0xaf,0x22,0x03,0x10 == lr.w t0, (t1)
0xb3,0x22,0x73,0x20 == sh1add t0, t1, t2
0x08,0x61 == flw fa0, 0(a0)
external/capstone/suite/MC/RISCV/option_rvc_riscv32.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x13,0x85,0x05,0x00 == mv a0, a1
0x13,0x04,0xc1,0x3f == addi s0, sp, 1020
0x2e,0x85 == mv a0, a1
0xe0,0x1f == addi s0, sp, 1020
external/capstone/suite/MC/RISCV/or_riscv64_riscv_v.txt.cs
Vendored
+7
View File
@@ -0,0 +1,7 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x28 == vor.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x2a == vor.vv v8, v4, v20
0x57,0x44,0x45,0x28 == vor.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x2a == vor.vx v8, v4, a0
0x57,0xb4,0x47,0x28 == vor.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x2a == vor.vi v8, v4, 15
external/capstone/suite/MC/RISCV/others_riscv64_riscv_v_syntax_no_alias_text.txt.cs
Vendored
+25
View File
@@ -0,0 +1,25 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x5c == vmerge.vvm v8, v4, v20, v0
0x57,0x44,0x45,0x5c == vmerge.vxm v8, v4, a0, v0
0x57,0xb4,0x47,0x5c == vmerge.vim v8, v4, 15, v0
0x57,0x44,0x45,0x38 == vslideup.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x3a == vslideup.vx v8, v4, a0
0x57,0xb4,0x4f,0x38 == vslideup.vi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0x3a == vslideup.vi v8, v4, 31
0x57,0x44,0x45,0x3c == vslidedown.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x3e == vslidedown.vx v8, v4, a0
0x57,0xb4,0x4f,0x3c == vslidedown.vi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0x3e == vslidedown.vi v8, v4, 31
0x57,0x64,0x45,0x38 == vslide1up.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x3a == vslide1up.vx v8, v4, a0
0x57,0x64,0x45,0x3c == vslide1down.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x3e == vslide1down.vx v8, v4, a0
0x57,0x04,0x4a,0x30 == vrgather.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x32 == vrgather.vv v8, v4, v20
0x57,0x44,0x45,0x30 == vrgather.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x32 == vrgather.vx v8, v4, a0
0x57,0xb4,0x4f,0x30 == vrgather.vi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0x32 == vrgather.vi v8, v4, 31
0x57,0x04,0x4a,0x38 == vrgatherei16.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x3a == vrgatherei16.vv v8, v4, v20
0x57,0x24,0x4a,0x5e == vcompress.vm v8, v4, v20
external/capstone/suite/MC/RISCV/print_imm_hex_riscv32_riscv_v_syntax_no_alias_text.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_V", None
0x63,0x83,0x94,0x06 == beq s1, s1, 102
0x03,0x25,0x16,0x06 == lw a0, 97(a2)
0xf3,0xd2,0xff,0xff == csrrwi t0, 4095, 31
0x57,0x76,0xf5,0x0f == vsetvli a2, a0, 255
external/capstone/suite/MC/RISCV/priv_valid_riscv32_svinval_syntax_no_alias_text.txt.cs
Vendored
+10
View File
@@ -0,0 +1,10 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x00,0x20,0x10 == sret
0x73,0x00,0x20,0x30 == mret
0x73,0x00,0x50,0x10 == wfi
0x73,0x00,0x00,0x12 == sfence.vma zero, zero
0x73,0x00,0xb5,0x12 == sfence.vma a0, a1
0x73,0x00,0x00,0x16 == sinval.vma zero, zero
0x73,0x00,0xb5,0x16 == sinval.vma a0, a1
0x73,0x00,0x00,0x18 == sfence.w.inval
0x73,0x00,0x10,0x18 == sfence.inval.ir
external/capstone/suite/MC/RISCV/reduction_riscv64_riscv_v.txt.cs
Vendored
+22
View File
@@ -0,0 +1,22 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x00 == vredsum.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x02 == vredsum.vs v8, v4, v20
0x57,0x24,0x4a,0x18 == vredmaxu.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x1a == vredmaxu.vs v8, v4, v20
0x57,0x24,0x4a,0x1c == vredmax.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x1e == vredmax.vs v8, v4, v20
0x57,0x24,0x4a,0x10 == vredminu.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x12 == vredminu.vs v8, v4, v20
0x57,0x24,0x4a,0x14 == vredmin.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x16 == vredmin.vs v8, v4, v20
0x57,0x24,0x4a,0x04 == vredand.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x06 == vredand.vs v8, v4, v20
0x57,0x24,0x4a,0x08 == vredor.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x0a == vredor.vs v8, v4, v20
0x57,0x24,0x4a,0x0c == vredxor.vs v8, v4, v20, v0.t
0x57,0x24,0x4a,0x0e == vredxor.vs v8, v4, v20
0x57,0x04,0x4a,0xc0 == vwredsumu.vs v8, v4, v20, v0.t
0x57,0x04,0x4a,0xc2 == vwredsumu.vs v8, v4, v20
0x57,0x04,0x4a,0xc4 == vwredsum.vs v8, v4, v20, v0.t
0x57,0x04,0x4a,0xc6 == vwredsum.vs v8, v4, v20
0x57,0x20,0x4a,0x00 == vredsum.vs v0, v4, v20, v0.t
external/capstone/suite/MC/RISCV/rv32_hypervisor_csr_names_riscv32_syntax_no_alias_text.txt.cs
Vendored
+29
View File
@@ -0,0 +1,29 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0xa0,0x61 == csrrs t1, henvcfgh, zero
0xf3,0x23,0xa0,0x61 == csrrs t2, henvcfgh, zero
0x73,0x23,0x50,0x61 == csrrs t1, htimedeltah, zero
0xf3,0x23,0x50,0x61 == csrrs t2, htimedeltah, zero
0x73,0x23,0xd0,0x25 == csrrs t1, vstimecmph, zero
0xf3,0x23,0xd0,0x25 == csrrs t2, vstimecmph, zero
0x73,0x23,0xc0,0x61 == csrrs t1, hstateen0h, zero
0xf3,0x23,0xc0,0x61 == csrrs t2, hstateen0h, zero
0x73,0x23,0xd0,0x61 == csrrs t1, hstateen1h, zero
0xf3,0x23,0xd0,0x61 == csrrs t2, hstateen1h, zero
0x73,0x23,0xe0,0x61 == csrrs t1, hstateen2h, zero
0xf3,0x23,0xe0,0x61 == csrrs t2, hstateen2h, zero
0x73,0x23,0xf0,0x61 == csrrs t1, hstateen3h, zero
0xf3,0x23,0xf0,0x61 == csrrs t2, hstateen3h, zero
0x73,0x23,0x30,0x61 == csrrs t1, hidelegh, zero
0xf3,0x23,0x30,0x61 == csrrs t2, hidelegh, zero
0x73,0x23,0x80,0x61 == csrrs t1, hvienh, zero
0xf3,0x23,0x80,0x61 == csrrs t2, hvienh, zero
0x73,0x23,0x50,0x65 == csrrs t1, hviph, zero
0xf3,0x23,0x50,0x65 == csrrs t2, hviph, zero
0x73,0x23,0x60,0x65 == csrrs t1, hviprio1h, zero
0xf3,0x23,0x60,0x65 == csrrs t2, hviprio1h, zero
0x73,0x23,0x70,0x65 == csrrs t1, hviprio2h, zero
0xf3,0x23,0x70,0x65 == csrrs t2, hviprio2h, zero
0x73,0x23,0x40,0x21 == csrrs t1, vsieh, zero
0xf3,0x23,0x40,0x21 == csrrs t2, vsieh, zero
0x73,0x23,0x40,0x25 == csrrs t1, vsiph, zero
0xf3,0x23,0x40,0x25 == csrrs t2, vsiph, zero
external/capstone/suite/MC/RISCV/rv32_immediate_riscv32_riscv_v.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_V", None
0x57,0x34,0x48,0x02 == vadd.vi v8, v4, -16
0x57,0x34,0x48,0x72 == vmsleu.vi v8, v4, -16
external/capstone/suite/MC/RISCV/rv32_machine_csr_names_riscv32_syntax_no_alias_text.txt.cs
Vendored
+161
View File
@@ -0,0 +1,161 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0x00,0x31 == csrrs t1, mstatush, zero
0xf3,0x23,0x00,0x31 == csrrs t2, mstatush, zero
0x73,0x23,0xa0,0x31 == csrrs t1, menvcfgh, zero
0xf3,0x23,0xa0,0x31 == csrrs t2, menvcfgh, zero
0x73,0x23,0x70,0x75 == csrrs t1, mseccfgh, zero
0xf3,0x23,0x70,0x75 == csrrs t2, mseccfgh, zero
0x73,0x23,0x10,0x3a == csrrs t1, pmpcfg1, zero
0xf3,0x23,0x10,0x3a == csrrs t2, pmpcfg1, zero
0x73,0x23,0x30,0x3a == csrrs t1, pmpcfg3, zero
0xf3,0x23,0x30,0x3a == csrrs t2, pmpcfg3, zero
0x73,0x23,0x50,0x3a == csrrs t1, pmpcfg5, zero
0xf3,0x23,0x50,0x3a == csrrs t2, pmpcfg5, zero
0x73,0x23,0x70,0x3a == csrrs t1, pmpcfg7, zero
0xf3,0x23,0x70,0x3a == csrrs t2, pmpcfg7, zero
0x73,0x23,0x90,0x3a == csrrs t1, pmpcfg9, zero
0xf3,0x23,0x90,0x3a == csrrs t2, pmpcfg9, zero
0x73,0x23,0xb0,0x3a == csrrs t1, pmpcfg11, zero
0xf3,0x23,0xb0,0x3a == csrrs t2, pmpcfg11, zero
0x73,0x23,0xd0,0x3a == csrrs t1, pmpcfg13, zero
0xf3,0x23,0xd0,0x3a == csrrs t2, pmpcfg13, zero
0x73,0x23,0xf0,0x3a == csrrs t1, pmpcfg15, zero
0xf3,0x23,0xf0,0x3a == csrrs t2, pmpcfg15, zero
0x73,0x23,0x00,0xb8 == csrrs t1, mcycleh, zero
0xf3,0x23,0x00,0xb8 == csrrs t2, mcycleh, zero
0x73,0x23,0x20,0xb8 == csrrs t1, minstreth, zero
0xf3,0x23,0x20,0xb8 == csrrs t2, minstreth, zero
0x73,0x23,0x30,0xb8 == csrrs t1, mhpmcounter3h, zero
0xf3,0x23,0x30,0xb8 == csrrs t2, mhpmcounter3h, zero
0x73,0x23,0x40,0xb8 == csrrs t1, mhpmcounter4h, zero
0xf3,0x23,0x40,0xb8 == csrrs t2, mhpmcounter4h, zero
0x73,0x23,0x50,0xb8 == csrrs t1, mhpmcounter5h, zero
0xf3,0x23,0x50,0xb8 == csrrs t2, mhpmcounter5h, zero
0x73,0x23,0x60,0xb8 == csrrs t1, mhpmcounter6h, zero
0xf3,0x23,0x60,0xb8 == csrrs t2, mhpmcounter6h, zero
0x73,0x23,0x70,0xb8 == csrrs t1, mhpmcounter7h, zero
0xf3,0x23,0x70,0xb8 == csrrs t2, mhpmcounter7h, zero
0x73,0x23,0x80,0xb8 == csrrs t1, mhpmcounter8h, zero
0xf3,0x23,0x80,0xb8 == csrrs t2, mhpmcounter8h, zero
0x73,0x23,0x90,0xb8 == csrrs t1, mhpmcounter9h, zero
0xf3,0x23,0x90,0xb8 == csrrs t2, mhpmcounter9h, zero
0x73,0x23,0xa0,0xb8 == csrrs t1, mhpmcounter10h, zero
0xf3,0x23,0xa0,0xb8 == csrrs t2, mhpmcounter10h, zero
0x73,0x23,0xb0,0xb8 == csrrs t1, mhpmcounter11h, zero
0xf3,0x23,0xb0,0xb8 == csrrs t2, mhpmcounter11h, zero
0x73,0x23,0xc0,0xb8 == csrrs t1, mhpmcounter12h, zero
0xf3,0x23,0xc0,0xb8 == csrrs t2, mhpmcounter12h, zero
0x73,0x23,0xd0,0xb8 == csrrs t1, mhpmcounter13h, zero
0xf3,0x23,0xd0,0xb8 == csrrs t2, mhpmcounter13h, zero
0x73,0x23,0xe0,0xb8 == csrrs t1, mhpmcounter14h, zero
0xf3,0x23,0xe0,0xb8 == csrrs t2, mhpmcounter14h, zero
0x73,0x23,0xf0,0xb8 == csrrs t1, mhpmcounter15h, zero
0xf3,0x23,0xf0,0xb8 == csrrs t2, mhpmcounter15h, zero
0x73,0x23,0x00,0xb9 == csrrs t1, mhpmcounter16h, zero
0xf3,0x23,0x00,0xb9 == csrrs t2, mhpmcounter16h, zero
0x73,0x23,0x10,0xb9 == csrrs t1, mhpmcounter17h, zero
0xf3,0x23,0x10,0xb9 == csrrs t2, mhpmcounter17h, zero
0x73,0x23,0x20,0xb9 == csrrs t1, mhpmcounter18h, zero
0xf3,0x23,0x20,0xb9 == csrrs t2, mhpmcounter18h, zero
0x73,0x23,0x30,0xb9 == csrrs t1, mhpmcounter19h, zero
0xf3,0x23,0x30,0xb9 == csrrs t2, mhpmcounter19h, zero
0x73,0x23,0x40,0xb9 == csrrs t1, mhpmcounter20h, zero
0xf3,0x23,0x40,0xb9 == csrrs t2, mhpmcounter20h, zero
0x73,0x23,0x50,0xb9 == csrrs t1, mhpmcounter21h, zero
0xf3,0x23,0x50,0xb9 == csrrs t2, mhpmcounter21h, zero
0x73,0x23,0x60,0xb9 == csrrs t1, mhpmcounter22h, zero
0xf3,0x23,0x60,0xb9 == csrrs t2, mhpmcounter22h, zero
0x73,0x23,0x70,0xb9 == csrrs t1, mhpmcounter23h, zero
0xf3,0x23,0x70,0xb9 == csrrs t2, mhpmcounter23h, zero
0x73,0x23,0x80,0xb9 == csrrs t1, mhpmcounter24h, zero
0xf3,0x23,0x80,0xb9 == csrrs t2, mhpmcounter24h, zero
0x73,0x23,0x90,0xb9 == csrrs t1, mhpmcounter25h, zero
0xf3,0x23,0x90,0xb9 == csrrs t2, mhpmcounter25h, zero
0x73,0x23,0xa0,0xb9 == csrrs t1, mhpmcounter26h, zero
0xf3,0x23,0xa0,0xb9 == csrrs t2, mhpmcounter26h, zero
0x73,0x23,0xb0,0xb9 == csrrs t1, mhpmcounter27h, zero
0xf3,0x23,0xb0,0xb9 == csrrs t2, mhpmcounter27h, zero
0x73,0x23,0xc0,0xb9 == csrrs t1, mhpmcounter28h, zero
0xf3,0x23,0xc0,0xb9 == csrrs t2, mhpmcounter28h, zero
0x73,0x23,0xd0,0xb9 == csrrs t1, mhpmcounter29h, zero
0xf3,0x23,0xd0,0xb9 == csrrs t2, mhpmcounter29h, zero
0x73,0x23,0xe0,0xb9 == csrrs t1, mhpmcounter30h, zero
0xf3,0x23,0xe0,0xb9 == csrrs t2, mhpmcounter30h, zero
0x73,0x23,0xf0,0xb9 == csrrs t1, mhpmcounter31h, zero
0xf3,0x23,0xf0,0xb9 == csrrs t2, mhpmcounter31h, zero
0x73,0x23,0x30,0x72 == csrrs t1, mhpmevent3h, zero
0xf3,0x23,0x30,0x72 == csrrs t2, mhpmevent3h, zero
0x73,0x23,0x40,0x72 == csrrs t1, mhpmevent4h, zero
0xf3,0x23,0x40,0x72 == csrrs t2, mhpmevent4h, zero
0x73,0x23,0x50,0x72 == csrrs t1, mhpmevent5h, zero
0xf3,0x23,0x50,0x72 == csrrs t2, mhpmevent5h, zero
0x73,0x23,0x60,0x72 == csrrs t1, mhpmevent6h, zero
0xf3,0x23,0x60,0x72 == csrrs t2, mhpmevent6h, zero
0x73,0x23,0x70,0x72 == csrrs t1, mhpmevent7h, zero
0xf3,0x23,0x70,0x72 == csrrs t2, mhpmevent7h, zero
0x73,0x23,0x80,0x72 == csrrs t1, mhpmevent8h, zero
0xf3,0x23,0x80,0x72 == csrrs t2, mhpmevent8h, zero
0x73,0x23,0x90,0x72 == csrrs t1, mhpmevent9h, zero
0xf3,0x23,0x90,0x72 == csrrs t2, mhpmevent9h, zero
0x73,0x23,0xa0,0x72 == csrrs t1, mhpmevent10h, zero
0xf3,0x23,0xa0,0x72 == csrrs t2, mhpmevent10h, zero
0x73,0x23,0xb0,0x72 == csrrs t1, mhpmevent11h, zero
0xf3,0x23,0xb0,0x72 == csrrs t2, mhpmevent11h, zero
0x73,0x23,0xc0,0x72 == csrrs t1, mhpmevent12h, zero
0xf3,0x23,0xc0,0x72 == csrrs t2, mhpmevent12h, zero
0x73,0x23,0xd0,0x72 == csrrs t1, mhpmevent13h, zero
0xf3,0x23,0xd0,0x72 == csrrs t2, mhpmevent13h, zero
0x73,0x23,0xe0,0x72 == csrrs t1, mhpmevent14h, zero
0xf3,0x23,0xe0,0x72 == csrrs t2, mhpmevent14h, zero
0x73,0x23,0xf0,0x72 == csrrs t1, mhpmevent15h, zero
0xf3,0x23,0xf0,0x72 == csrrs t2, mhpmevent15h, zero
0x73,0x23,0x00,0x73 == csrrs t1, mhpmevent16h, zero
0xf3,0x23,0x00,0x73 == csrrs t2, mhpmevent16h, zero
0x73,0x23,0x10,0x73 == csrrs t1, mhpmevent17h, zero
0xf3,0x23,0x10,0x73 == csrrs t2, mhpmevent17h, zero
0x73,0x23,0x20,0x73 == csrrs t1, mhpmevent18h, zero
0xf3,0x23,0x20,0x73 == csrrs t2, mhpmevent18h, zero
0x73,0x23,0x30,0x73 == csrrs t1, mhpmevent19h, zero
0xf3,0x23,0x30,0x73 == csrrs t2, mhpmevent19h, zero
0x73,0x23,0x40,0x73 == csrrs t1, mhpmevent20h, zero
0xf3,0x23,0x40,0x73 == csrrs t2, mhpmevent20h, zero
0x73,0x23,0x50,0x73 == csrrs t1, mhpmevent21h, zero
0xf3,0x23,0x50,0x73 == csrrs t2, mhpmevent21h, zero
0x73,0x23,0x60,0x73 == csrrs t1, mhpmevent22h, zero
0xf3,0x23,0x60,0x73 == csrrs t2, mhpmevent22h, zero
0x73,0x23,0x70,0x73 == csrrs t1, mhpmevent23h, zero
0xf3,0x23,0x70,0x73 == csrrs t2, mhpmevent23h, zero
0x73,0x23,0x80,0x73 == csrrs t1, mhpmevent24h, zero
0xf3,0x23,0x80,0x73 == csrrs t2, mhpmevent24h, zero
0x73,0x23,0x90,0x73 == csrrs t1, mhpmevent25h, zero
0xf3,0x23,0x90,0x73 == csrrs t2, mhpmevent25h, zero
0x73,0x23,0xa0,0x73 == csrrs t1, mhpmevent26h, zero
0xf3,0x23,0xa0,0x73 == csrrs t2, mhpmevent26h, zero
0x73,0x23,0xb0,0x73 == csrrs t1, mhpmevent27h, zero
0xf3,0x23,0xb0,0x73 == csrrs t2, mhpmevent27h, zero
0x73,0x23,0xc0,0x73 == csrrs t1, mhpmevent28h, zero
0xf3,0x23,0xc0,0x73 == csrrs t2, mhpmevent28h, zero
0x73,0x23,0xd0,0x73 == csrrs t1, mhpmevent29h, zero
0xf3,0x23,0xd0,0x73 == csrrs t2, mhpmevent29h, zero
0x73,0x23,0xe0,0x73 == csrrs t1, mhpmevent30h, zero
0xf3,0x23,0xe0,0x73 == csrrs t2, mhpmevent30h, zero
0x73,0x23,0xf0,0x73 == csrrs t1, mhpmevent31h, zero
0xf3,0x23,0xf0,0x73 == csrrs t2, mhpmevent31h, zero
0x73,0x23,0xc0,0x31 == csrrs t1, mstateen0h, zero
0xf3,0x23,0xc0,0x31 == csrrs t2, mstateen0h, zero
0x73,0x23,0xd0,0x31 == csrrs t1, mstateen1h, zero
0xf3,0x23,0xd0,0x31 == csrrs t2, mstateen1h, zero
0x73,0x23,0xe0,0x31 == csrrs t1, mstateen2h, zero
0xf3,0x23,0xe0,0x31 == csrrs t2, mstateen2h, zero
0x73,0x23,0xf0,0x31 == csrrs t1, mstateen3h, zero
0xf3,0x23,0xf0,0x31 == csrrs t2, mstateen3h, zero
0x73,0x23,0x30,0x31 == csrrs t1, midelegh, zero
0xf3,0x23,0x30,0x31 == csrrs t2, midelegh, zero
0x73,0x23,0x40,0x31 == csrrs t1, mieh, zero
0xf3,0x23,0x40,0x31 == csrrs t2, mieh, zero
0x73,0x23,0x80,0x31 == csrrs t1, mvienh, zero
0xf3,0x23,0x80,0x31 == csrrs t2, mvienh, zero
0x73,0x23,0x90,0x31 == csrrs t1, mviph, zero
0xf3,0x23,0x90,0x31 == csrrs t2, mviph, zero
0x73,0x23,0x40,0x35 == csrrs t1, miph, zero
0xf3,0x23,0x40,0x35 == csrrs t2, miph, zero
external/capstone/suite/MC/RISCV/rv32_supervisor_csr_names_riscv32_syntax_no_alias_text.txt.cs
Vendored
+7
View File
@@ -0,0 +1,7 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0xd0,0x15 == csrrs t1, stimecmph, zero
0xf3,0x23,0xd0,0x15 == csrrs t2, stimecmph, zero
0x73,0x23,0x40,0x11 == csrrs t1, sieh, zero
0xf3,0x23,0x40,0x11 == csrrs t2, sieh, zero
0x73,0x23,0x40,0x15 == csrrs t1, siph, zero
0xf3,0x23,0x40,0x15 == csrrs t2, siph, zero
external/capstone/suite/MC/RISCV/rv32_user_csr_names_riscv32_syntax_no_alias_text.txt.cs
Vendored
+65
View File
@@ -0,0 +1,65 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0x00,0xc8 == csrrs t1, cycleh, zero
0xf3,0x23,0x00,0xc8 == csrrs t2, cycleh, zero
0x73,0x23,0x10,0xc8 == csrrs t1, timeh, zero
0xf3,0x23,0x10,0xc8 == csrrs t2, timeh, zero
0x73,0x23,0x20,0xc8 == csrrs t1, instreth, zero
0xf3,0x23,0x20,0xc8 == csrrs t2, instreth, zero
0x73,0x23,0x30,0xc8 == csrrs t1, hpmcounter3h, zero
0xf3,0x23,0x30,0xc8 == csrrs t2, hpmcounter3h, zero
0x73,0x23,0x40,0xc8 == csrrs t1, hpmcounter4h, zero
0xf3,0x23,0x40,0xc8 == csrrs t2, hpmcounter4h, zero
0x73,0x23,0x50,0xc8 == csrrs t1, hpmcounter5h, zero
0xf3,0x23,0x50,0xc8 == csrrs t2, hpmcounter5h, zero
0x73,0x23,0x60,0xc8 == csrrs t1, hpmcounter6h, zero
0xf3,0x23,0x60,0xc8 == csrrs t2, hpmcounter6h, zero
0x73,0x23,0x70,0xc8 == csrrs t1, hpmcounter7h, zero
0xf3,0x23,0x70,0xc8 == csrrs t2, hpmcounter7h, zero
0x73,0x23,0x80,0xc8 == csrrs t1, hpmcounter8h, zero
0xf3,0x23,0x80,0xc8 == csrrs t2, hpmcounter8h, zero
0x73,0x23,0x90,0xc8 == csrrs t1, hpmcounter9h, zero
0xf3,0x23,0x90,0xc8 == csrrs t2, hpmcounter9h, zero
0x73,0x23,0xa0,0xc8 == csrrs t1, hpmcounter10h, zero
0xf3,0x23,0xa0,0xc8 == csrrs t2, hpmcounter10h, zero
0x73,0x23,0xb0,0xc8 == csrrs t1, hpmcounter11h, zero
0xf3,0x23,0xb0,0xc8 == csrrs t2, hpmcounter11h, zero
0x73,0x23,0xc0,0xc8 == csrrs t1, hpmcounter12h, zero
0xf3,0x23,0xc0,0xc8 == csrrs t2, hpmcounter12h, zero
0x73,0x23,0xd0,0xc8 == csrrs t1, hpmcounter13h, zero
0xf3,0x23,0xd0,0xc8 == csrrs t2, hpmcounter13h, zero
0x73,0x23,0xe0,0xc8 == csrrs t1, hpmcounter14h, zero
0xf3,0x23,0xe0,0xc8 == csrrs t2, hpmcounter14h, zero
0x73,0x23,0xf0,0xc8 == csrrs t1, hpmcounter15h, zero
0xf3,0x23,0xf0,0xc8 == csrrs t2, hpmcounter15h, zero
0x73,0x23,0x00,0xc9 == csrrs t1, hpmcounter16h, zero
0xf3,0x23,0x00,0xc9 == csrrs t2, hpmcounter16h, zero
0x73,0x23,0x10,0xc9 == csrrs t1, hpmcounter17h, zero
0xf3,0x23,0x10,0xc9 == csrrs t2, hpmcounter17h, zero
0x73,0x23,0x20,0xc9 == csrrs t1, hpmcounter18h, zero
0xf3,0x23,0x20,0xc9 == csrrs t2, hpmcounter18h, zero
0x73,0x23,0x30,0xc9 == csrrs t1, hpmcounter19h, zero
0xf3,0x23,0x30,0xc9 == csrrs t2, hpmcounter19h, zero
0x73,0x23,0x40,0xc9 == csrrs t1, hpmcounter20h, zero
0xf3,0x23,0x40,0xc9 == csrrs t2, hpmcounter20h, zero
0x73,0x23,0x50,0xc9 == csrrs t1, hpmcounter21h, zero
0xf3,0x23,0x50,0xc9 == csrrs t2, hpmcounter21h, zero
0x73,0x23,0x60,0xc9 == csrrs t1, hpmcounter22h, zero
0xf3,0x23,0x60,0xc9 == csrrs t2, hpmcounter22h, zero
0x73,0x23,0x70,0xc9 == csrrs t1, hpmcounter23h, zero
0xf3,0x23,0x70,0xc9 == csrrs t2, hpmcounter23h, zero
0x73,0x23,0x80,0xc9 == csrrs t1, hpmcounter24h, zero
0xf3,0x23,0x80,0xc9 == csrrs t2, hpmcounter24h, zero
0x73,0x23,0x90,0xc9 == csrrs t1, hpmcounter25h, zero
0xf3,0x23,0x90,0xc9 == csrrs t2, hpmcounter25h, zero
0x73,0x23,0xa0,0xc9 == csrrs t1, hpmcounter26h, zero
0xf3,0x23,0xa0,0xc9 == csrrs t2, hpmcounter26h, zero
0x73,0x23,0xb0,0xc9 == csrrs t1, hpmcounter27h, zero
0xf3,0x23,0xb0,0xc9 == csrrs t2, hpmcounter27h, zero
0x73,0x23,0xc0,0xc9 == csrrs t1, hpmcounter28h, zero
0xf3,0x23,0xc0,0xc9 == csrrs t2, hpmcounter28h, zero
0x73,0x23,0xd0,0xc9 == csrrs t1, hpmcounter29h, zero
0xf3,0x23,0xd0,0xc9 == csrrs t2, hpmcounter29h, zero
0x73,0x23,0xe0,0xc9 == csrrs t1, hpmcounter30h, zero
0xf3,0x23,0xe0,0xc9 == csrrs t2, hpmcounter30h, zero
0x73,0x23,0xf0,0xc9 == csrrs t1, hpmcounter31h, zero
0xf3,0x23,0xf0,0xc9 == csrrs t2, hpmcounter31h, zero
external/capstone/suite/MC/RISCV/rv32c_only_valid_riscv32_riscv_c_syntax_no_alias_text.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0xfd,0x2f == c.jal 2046
0xfd,0x15 == c.addi a1, -1
external/capstone/suite/MC/RISCV/rv32c_valid_riscv32_riscv_c_syntax_no_alias_text.txt.cs
Vendored
+36
View File
@@ -0,0 +1,36 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0x82,0x40 == c.lwsp ra, 0(sp)
0x86,0xdf == c.swsp ra, 252(sp)
0x10,0x41 == c.lw a2, 0(a0)
0xfc,0xde == c.sw a5, 124(a3)
0x02,0x44 == c.lwsp s0, 0(sp)
0x22,0xc0 == c.swsp s0, 0(sp)
0x80,0x40 == c.lw s0, 0(s1)
0x80,0xc0 == c.sw s0, 0(s1)
0x01,0xb0 == c.j -2048
0x82,0x88 == c.jr a7
0x82,0x95 == c.jalr a1
0x81,0xd2 == c.beqz a3, -256
0xfd,0xef == c.bnez a5, 254
0xfd,0x48 == c.li a7, 31
0x81,0x16 == c.addi a3, -32
0x01,0x71 == c.addi16sp sp, -512
0x7d,0x61 == c.addi16sp sp, 496
0xf4,0x1f == c.addi4spn a3, sp, 1020
0x54,0x00 == c.addi4spn a3, sp, 4
0x86,0x05 == c.slli a1, 1
0xfd,0x82 == c.srli a3, 31
0x09,0x87 == c.srai a4, 2
0xbd,0x8b == c.andi a5, 15
0xa2,0x88 == c.mv a7, s0
0xf1,0x8d == c.and a1, a2
0x55,0x8e == c.or a2, a3
0xb9,0x8e == c.xor a3, a4
0x1d,0x8f == c.sub a4, a5
0x01,0x00 == c.nop
0x02,0x90 == c.ebreak
0x05,0x64 == c.lui s0, 1
0x7d,0x64 == c.lui s0, 31
0x01,0x74 == c.lui s0, 1048544
0x7d,0x74 == c.lui s0, 1048575
0x00,0x00 == c.unimp
external/capstone/suite/MC/RISCV/rv32d_valid_riscv32_riscv_d_syntax_no_alias_text.txt.cs
Vendored
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_D", None
0x53,0xfd,0xcd,0x01 == fadd.s fs10, fs11, ft8, dyn
0x07,0x30,0xc5,0x00 == fld ft0, 12(a0)
0x87,0xb0,0x40,0x00 == fld ft1, 4(ra)
0x07,0xb1,0x06,0x80 == fld ft2, -2048(a3)
0x87,0xb1,0x04,0x80 == fld ft3, -2048(s1)
0x07,0x32,0xf9,0x7f == fld ft4, 2047(s2)
0x87,0xb2,0x09,0x00 == fld ft5, 0(s3)
0xa7,0x3f,0x6a,0x7e == fsd ft6, 2047(s4)
0x27,0xb0,0x7a,0x80 == fsd ft7, -2048(s5)
0x27,0x30,0x8b,0x80 == fsd fs0, -2048(s6)
0xa7,0xb3,0x9b,0x3e == fsd fs1, 999(s7)
0x43,0xf5,0xc5,0x6a == fmadd.d fa0, fa1, fa2, fa3, dyn
0x47,0xf7,0x07,0x8b == fmsub.d fa4, fa5, fa6, fa7, dyn
0x4b,0xf9,0x49,0xab == fnmsub.d fs2, fs3, fs4, fs5, dyn
0x4f,0xfb,0x8b,0xcb == fnmadd.d fs6, fs7, fs8, fs9, dyn
0x53,0xfd,0xcd,0x03 == fadd.d fs10, fs11, ft8, dyn
0xd3,0x7e,0xff,0x0b == fsub.d ft9, ft10, ft11, dyn
0x53,0xf0,0x20,0x12 == fmul.d ft0, ft1, ft2, dyn
0xd3,0x71,0x52,0x1a == fdiv.d ft3, ft4, ft5, dyn
0x53,0xf3,0x03,0x5a == fsqrt.d ft6, ft7, dyn
0xd3,0x04,0xb5,0x22 == fsgnj.d fs1, fa0, fa1
0xd3,0x95,0xe6,0x22 == fsgnjn.d fa1, fa3, fa4
0xd3,0x26,0xb6,0x22 == fsgnjx.d fa3, fa2, fa1
0xd3,0x07,0x18,0x2b == fmin.d fa5, fa6, fa7
0x53,0x99,0x49,0x2b == fmax.d fs2, fs3, fs4
0xd3,0x7a,0x1b,0x40 == fcvt.s.d fs5, fs6, dyn
0xd3,0x0b,0x0c,0x42 == fcvt.d.s fs7, fs8
0xd3,0x3b,0x0c,0x42 == fcvt.d.s fs7, fs8, rup
0xd3,0x25,0x9c,0xa3 == feq.d a1, fs8, fs9
0x53,0x16,0xbd,0xa3 == flt.d a2, fs10, fs11
0xd3,0x06,0xde,0xa3 == fle.d a3, ft8, ft9
0xd3,0x16,0x0f,0xe2 == fclass.d a3, ft10
0x53,0xf7,0x0f,0xc2 == fcvt.w.d a4, ft11, dyn
0x53,0x80,0x07,0xd2 == fcvt.d.w ft0, a5
0x53,0xb0,0x07,0xd2 == fcvt.d.w ft0, a5, rup
0xd3,0x00,0x18,0xd2 == fcvt.d.wu ft1, a6
0xd3,0x30,0x18,0xd2 == fcvt.d.wu ft1, a6, rup
0x43,0x85,0xc5,0x6a == fmadd.d fa0, fa1, fa2, fa3, rne
0x47,0x97,0x07,0x8b == fmsub.d fa4, fa5, fa6, fa7, rtz
0x4b,0xa9,0x49,0xab == fnmsub.d fs2, fs3, fs4, fs5, rdn
0x4f,0xbb,0x8b,0xcb == fnmadd.d fs6, fs7, fs8, fs9, rup
0x53,0xcd,0xcd,0x03 == fadd.d fs10, fs11, ft8, rmm
0x53,0x80,0x20,0x12 == fmul.d ft0, ft1, ft2, rne
0xd3,0x11,0x52,0x1a == fdiv.d ft3, ft4, ft5, rtz
0x53,0xa3,0x03,0x5a == fsqrt.d ft6, ft7, rdn
0xd3,0x3a,0x1b,0x40 == fcvt.s.d fs5, fs6, rup
0x53,0xc7,0x0f,0xc2 == fcvt.w.d a4, ft11, rmm
0xd3,0x77,0x1f,0xc2 == fcvt.wu.d a5, ft10, dyn
external/capstone/suite/MC/RISCV/rv32dc_valid_riscv32_riscv_c_riscv_d_syntax_no_alias_text.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C"|"CS_MODE_RISCV_D", None
0x7e,0x34 == c.fldsp fs0, 504(sp)
0xc6,0xbf == c.fsdsp fa7, 504(sp)
0xf4,0x3f == c.fld fa3, 248(a5)
0xf0,0xbd == c.fsd fa2, 248(a1)
external/capstone/suite/MC/RISCV/rv32e_valid_riscv32_riscv_e_syntax_no_alias_text.txt.cs
Vendored
+50
View File
@@ -0,0 +1,50 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_E", None
0x37,0x10,0x00,0x00 == lui zero, 1
0x97,0x20,0x00,0x00 == auipc ra, 2
0x6f,0x01,0x40,0x00 == jal sp, 4
0xe7,0x81,0x41,0x00 == jalr gp, 4(gp)
0x63,0x04,0x52,0x00 == beq tp, t0, 8
0x63,0x16,0x73,0x00 == bne t1, t2, 12
0x63,0x48,0x94,0x00 == blt s0, s1, 16
0x63,0x5a,0xb5,0x00 == bge a0, a1, 20
0x63,0x7c,0xd6,0x00 == bgeu a2, a3, 24
0x03,0x87,0x97,0x01 == lb a4, 25(a5)
0x03,0x90,0xa0,0x01 == lh zero, 26(ra)
0x03,0xa1,0xc1,0x01 == lw sp, 28(gp)
0x03,0xc2,0xd2,0x01 == lbu tp, 29(t0)
0x03,0xd3,0xe3,0x01 == lhu t1, 30(t2)
0xa3,0x8f,0x84,0x00 == sb s0, 31(s1)
0x23,0x90,0xa5,0x02 == sh a0, 32(a1)
0x23,0xa2,0xc6,0x02 == sw a2, 36(a3)
0x13,0x87,0x57,0x02 == addi a4, a5, 37
0x13,0x25,0xc6,0xfe == slti a0, a2, -20
0x13,0x42,0xd3,0xf9 == xori tp, t1, -99
0x13,0xe5,0x05,0x80 == ori a0, a1, -2048
0x93,0x70,0xf1,0x7f == andi ra, sp, 2047
0x13,0x13,0xf3,0x01 == slli t1, t1, 31
0x13,0x55,0x07,0x00 == srli a0, a4, 0
0x93,0x55,0xf1,0x40 == srai a1, sp, 15
0x93,0x12,0xd3,0x00 == slli t0, t1, 13
0xb3,0x00,0x00,0x00 == add ra, zero, zero
0xb3,0x82,0x63,0x40 == sub t0, t2, t1
0xb3,0x17,0xd7,0x00 == sll a5, a4, a3
0x33,0x24,0x84,0x00 == slt s0, s0, s0
0xb3,0x31,0xb5,0x00 == sltu gp, a0, a1
0xb3,0x44,0x94,0x00 == xor s1, s0, s1
0x33,0x55,0x54,0x00 == srl a0, s0, t0
0xb3,0xd2,0x06,0x40 == sra t0, a3, zero
0xb3,0x67,0x13,0x00 == or a5, t1, ra
0x33,0xf5,0xd4,0x00 == and a0, s1, a3
0x0f,0x00,0xf0,0x0f == fence iorw, iorw
0x0f,0x00,0x30,0x83 == fence.tso
0x0f,0x10,0x00,0x00 == fence.i
0x73,0x00,0x00,0x00 == ecall
0x73,0x00,0x10,0x00 == ebreak
0x73,0x10,0x00,0xc0 == unimp
0xf3,0x12,0xf3,0xff == csrrw t0, 4095, t1
0x73,0x24,0x00,0xc0 == csrrs s0, cycle, zero
0x73,0xa4,0x17,0x00 == csrrs s0, fflags, a5
0x73,0xb1,0x00,0x00 == csrrc sp, 0, ra
0xf3,0x57,0x00,0x00 == csrrwi a5, 0, 0
0xf3,0xe3,0xff,0xff == csrrsi t2, 4095, 31
0x73,0xf3,0x02,0x14 == csrrci t1, sscratch, 5
external/capstone/suite/MC/RISCV/rv32f_valid_riscv32_riscv_f_syntax_no_alias_text.txt.cs
Vendored
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_F", None
0x07,0x20,0xc5,0x00 == flw ft0, 12(a0)
0x87,0xa0,0x40,0x00 == flw ft1, 4(ra)
0x07,0xa1,0x06,0x80 == flw ft2, -2048(a3)
0x87,0xa1,0x04,0x80 == flw ft3, -2048(s1)
0x07,0x22,0xf9,0x7f == flw ft4, 2047(s2)
0x87,0xa2,0x09,0x00 == flw ft5, 0(s3)
0xa7,0x2f,0x6a,0x7e == fsw ft6, 2047(s4)
0x27,0xa0,0x7a,0x80 == fsw ft7, -2048(s5)
0x27,0x20,0x8b,0x80 == fsw fs0, -2048(s6)
0xa7,0xa3,0x9b,0x3e == fsw fs1, 999(s7)
0x43,0xf5,0xc5,0x68 == fmadd.s fa0, fa1, fa2, fa3, dyn
0x47,0xf7,0x07,0x89 == fmsub.s fa4, fa5, fa6, fa7, dyn
0x4b,0xf9,0x49,0xa9 == fnmsub.s fs2, fs3, fs4, fs5, dyn
0x4f,0xfb,0x8b,0xc9 == fnmadd.s fs6, fs7, fs8, fs9, dyn
0x53,0xfd,0xcd,0x01 == fadd.s fs10, fs11, ft8, dyn
0xd3,0x7e,0xff,0x09 == fsub.s ft9, ft10, ft11, dyn
0x53,0xf0,0x20,0x10 == fmul.s ft0, ft1, ft2, dyn
0xd3,0x71,0x52,0x18 == fdiv.s ft3, ft4, ft5, dyn
0x53,0xf3,0x03,0x58 == fsqrt.s ft6, ft7, dyn
0xd3,0x04,0xb5,0x20 == fsgnj.s fs1, fa0, fa1
0xd3,0x95,0xe6,0x20 == fsgnjn.s fa1, fa3, fa4
0x53,0xa7,0xc6,0x20 == fsgnjx.s fa4, fa3, fa2
0xd3,0x07,0x18,0x29 == fmin.s fa5, fa6, fa7
0x53,0x99,0x49,0x29 == fmax.s fs2, fs3, fs4
0x53,0xf5,0x0a,0xc0 == fcvt.w.s a0, fs5, dyn
0xd3,0x75,0x1b,0xc0 == fcvt.wu.s a1, fs6, dyn
0x53,0x86,0x0b,0xe0 == fmv.x.w a2, fs7
0xd3,0x25,0x9c,0xa1 == feq.s a1, fs8, fs9
0x53,0x16,0xbd,0xa1 == flt.s a2, fs10, fs11
0xd3,0x06,0xde,0xa1 == fle.s a3, ft8, ft9
0xd3,0x16,0x0f,0xe0 == fclass.s a3, ft10
0xd3,0x7f,0x07,0xd0 == fcvt.s.w ft11, a4, dyn
0x53,0xf0,0x17,0xd0 == fcvt.s.wu ft0, a5, dyn
0xd3,0x00,0x08,0xf0 == fmv.w.x ft1, a6
0x43,0x85,0xc5,0x68 == fmadd.s fa0, fa1, fa2, fa3, rne
0x47,0x97,0x07,0x89 == fmsub.s fa4, fa5, fa6, fa7, rtz
0x4b,0xa9,0x49,0xa9 == fnmsub.s fs2, fs3, fs4, fs5, rdn
0x4f,0xbb,0x8b,0xc9 == fnmadd.s fs6, fs7, fs8, fs9, rup
0x43,0xc5,0xc5,0x68 == fmadd.s fa0, fa1, fa2, fa3, rmm
0x53,0x8d,0xcd,0x01 == fadd.s fs10, fs11, ft8, rne
0xd3,0x1e,0xff,0x09 == fsub.s ft9, ft10, ft11, rtz
0x53,0xa0,0x20,0x10 == fmul.s ft0, ft1, ft2, rdn
0xd3,0x31,0x52,0x18 == fdiv.s ft3, ft4, ft5, rup
0x53,0xc3,0x03,0x58 == fsqrt.s ft6, ft7, rmm
0x53,0xb5,0x0a,0xc0 == fcvt.w.s a0, fs5, rup
0xd3,0x25,0x1b,0xc0 == fcvt.wu.s a1, fs6, rdn
0xd3,0x1f,0x07,0xd0 == fcvt.s.w ft11, a4, rtz
0x53,0x80,0x17,0xd0 == fcvt.s.wu ft0, a5, rne
external/capstone/suite/MC/RISCV/rv32fc_valid_riscv32_riscv_c_riscv_f_syntax_no_alias_text.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C"|"CS_MODE_RISCV_F", None
0x7e,0x74 == c.flwsp fs0, 252(sp)
0xc6,0xff == c.fswsp fa7, 252(sp)
0xf4,0x7f == c.flw fa3, 124(a5)
0xf0,0xfd == c.fsw fa2, 124(a1)
external/capstone/suite/MC/RISCV/rv32i_only_valid_riscv32_syntax_no_alias_text.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x13,0x85,0xf5,0xff == addi a0, a1, -1
0x13,0xe6,0x06,0x80 == ori a2, a3, -2048
0x83,0x25,0xb6,0x9a == lw a1, -1621(a2)
0x23,0x2c,0xb6,0xfe == sw a1, -8(a2)
external/capstone/suite/MC/RISCV/rv32i_valid_riscv32_syntax_no_alias_text.txt.cs
Vendored
+86
View File
@@ -0,0 +1,86 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x37,0x25,0x00,0x00 == lui a0, 2
0xb7,0x0d,0x00,0x87 == lui s11, 552960
0x37,0x05,0x00,0x00 == lui a0, 0
0xb7,0xf2,0xff,0xff == lui t0, 1048575
0xb7,0x01,0x00,0x00 == lui gp, 0
0x37,0xe5,0x01,0x00 == lui a0, 30
0x37,0xf5,0x01,0x00 == lui a0, 31
0x17,0x25,0x00,0x00 == auipc a0, 2
0x97,0x0d,0x00,0x87 == auipc s11, 552960
0x97,0xf2,0xff,0xff == auipc t0, 1048575
0x97,0x01,0x00,0x00 == auipc gp, 0
0x17,0xe5,0x01,0x00 == auipc a0, 30
0x6f,0xf6,0xff,0x7f == jal a2, 1048574
0xef,0x06,0x00,0x10 == jal a3, 256
0x6f,0x05,0xe0,0x01 == jal a0, 30
0x6f,0x04,0x00,0x00 == jal s0, 0
0x6f,0x04,0xc0,0x09 == jal s0, 156
0x67,0x85,0x05,0x80 == jalr a0, -2048(a1)
0xe7,0x03,0xf3,0x7f == jalr t2, 2047(t1)
0x67,0x01,0x00,0x10 == jalr sp, 256(zero)
0xe7,0x05,0xe6,0x01 == jalr a1, 30(a2)
0x63,0x83,0x94,0x06 == beq s1, s1, 102
0x63,0x10,0xf7,0x80 == bne a4, a5, -4096
0xe3,0x4f,0x31,0x7e == blt sp, gp, 4094
0xe3,0x50,0x19,0xf2 == bge s2, ra, -224
0x63,0x60,0x00,0x00 == bltu zero, zero, 0
0x63,0x70,0x2c,0x20 == bgeu s8, sp, 512
0x63,0xff,0x62,0x00 == bgeu t0, t1, 30
0x83,0x89,0x40,0x00 == lb s3, 4(ra)
0x03,0x13,0x00,0x80 == lh t1, -2048(zero)
0x03,0x13,0x00,0x00 == lh t1, 0(zero)
0x03,0x11,0xf5,0x7f == lh sp, 2047(a0)
0x03,0x25,0x16,0x06 == lw a0, 97(a2)
0x83,0x02,0xe3,0x01 == lb t0, 30(t1)
0x03,0x84,0x04,0x00 == lb s0, 0(s1)
0x03,0x84,0xc4,0x09 == lb s0, 156(s1)
0xa3,0x0f,0xa6,0x7e == sb a0, 2047(a2)
0x23,0x10,0xcf,0x81 == sh t3, -2048(t5)
0x23,0x10,0xcf,0x01 == sh t3, 0(t5)
0xa3,0x23,0x10,0x3e == sw ra, 999(zero)
0x23,0xaf,0xa2,0x00 == sw a0, 30(t0)
0x23,0xa0,0x84,0x00 == sw s0, 0(s1)
0x23,0xae,0x84,0x08 == sw s0, 156(s1)
0x93,0x00,0x21,0x00 == addi ra, sp, 2
0x93,0x00,0xe1,0x01 == addi ra, sp, 30
0x93,0x00,0x01,0x00 == addi ra, sp, 0
0x93,0x00,0xc1,0x09 == addi ra, sp, 156
0x13,0x25,0xc6,0xfe == slti a0, a2, -20
0x13,0xb9,0x09,0x05 == sltiu s2, s3, 80
0x13,0x42,0xd3,0xf9 == xori tp, t1, -99
0x13,0xe5,0x05,0x80 == ori a0, a1, -2048
0x13,0xe5,0x05,0x00 == ori a0, a1, 0
0x93,0x70,0xf1,0x7f == andi ra, sp, 2047
0x13,0x1e,0xfe,0x01 == slli t3, t3, 31
0x13,0x55,0x07,0x00 == srli a0, a4, 0
0x13,0x56,0xf1,0x40 == srai a2, sp, 15
0x13,0x1e,0xee,0x01 == slli t3, t3, 30
0xb3,0x00,0x00,0x00 == add ra, zero, zero
0xb3,0x82,0x63,0x40 == sub t0, t2, t1
0xb3,0x17,0xd7,0x00 == sll a5, a4, a3
0x33,0x24,0x84,0x00 == slt s0, s0, s0
0xb3,0x31,0xb5,0x00 == sltu gp, a0, a1
0x33,0x49,0x89,0x01 == xor s2, s2, s8
0x33,0x55,0x54,0x00 == srl a0, s0, t0
0xb3,0x52,0x09,0x40 == sra t0, s2, zero
0x33,0x6d,0x13,0x00 == or s10, t1, ra
0x33,0x75,0x39,0x01 == and a0, s2, s3
0x0f,0x00,0xf0,0x0f == fence iorw, iorw
0x0f,0x00,0x30,0x0c == fence io, rw
0x0f,0x00,0x10,0x02 == fence r, w
0x0f,0x00,0xa0,0x01 == fence w, ir
0x0f,0x00,0x30,0x83 == fence.tso
0x0f,0x10,0x00,0x00 == fence.i
0x73,0x00,0x00,0x00 == ecall
0x73,0x00,0x10,0x00 == ebreak
0x73,0x10,0x00,0xc0 == unimp
0xf3,0x12,0xf3,0xff == csrrw t0, 4095, t1
0x73,0x94,0xf4,0xff == csrrw s0, 4095, s1
0x73,0x94,0x14,0x00 == csrrw s0, fflags, s1
0x73,0x24,0x00,0xc0 == csrrs s0, cycle, zero
0xf3,0xa9,0x1a,0x00 == csrrs s3, fflags, s5
0x73,0xb1,0x00,0x00 == csrrc sp, 0, ra
0xf3,0x57,0x00,0x00 == csrrwi a5, 0, 0
0xf3,0xe3,0xff,0xff == csrrsi t2, 4095, 31
0x73,0xf3,0x02,0x14 == csrrci t1, sscratch, 5
external/capstone/suite/MC/RISCV/rv32ih_aliases_valid_riscv32_h_syntax_no_alias_text.txt.cs
Vendored
+15
View File
@@ -0,0 +1,15 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x00,0x00,0x62 == hfence.gvma zero, zero
0x73,0x00,0x05,0x62 == hfence.gvma a0, zero
0x73,0x00,0x00,0x22 == hfence.vvma zero, zero
0x73,0x00,0x05,0x22 == hfence.vvma a0, zero
0x73,0xc5,0x05,0x60 == hlv.b a0, (a1)
0x73,0xc5,0x15,0x60 == hlv.bu a0, (a1)
0xf3,0x45,0x06,0x64 == hlv.h a1, (a2)
0xf3,0xc5,0x15,0x64 == hlv.hu a1, (a1)
0xf3,0x45,0x36,0x64 == hlvx.hu a1, (a2)
0x73,0x46,0x06,0x68 == hlv.w a2, (a2)
0x73,0xc6,0x36,0x68 == hlvx.wu a2, (a3)
0x73,0xc0,0xa5,0x62 == hsv.b a0, (a1)
0x73,0xc0,0xa5,0x66 == hsv.h a0, (a1)
0x73,0xc0,0xa5,0x6a == hsv.w a0, (a1)
external/capstone/suite/MC/RISCV/rv32ih_valid_riscv32_h_syntax_no_alias_text.txt.cs
Vendored
+15
View File
@@ -0,0 +1,15 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x00,0x00,0x22 == hfence.vvma zero, zero
0x73,0x00,0xb5,0x22 == hfence.vvma a0, a1
0x73,0x00,0x00,0x62 == hfence.gvma zero, zero
0x73,0x00,0xb5,0x62 == hfence.gvma a0, a1
0x73,0xc5,0x05,0x60 == hlv.b a0, (a1)
0x73,0xc5,0x15,0x60 == hlv.bu a0, (a1)
0xf3,0x45,0x06,0x64 == hlv.h a1, (a2)
0xf3,0xc5,0x15,0x64 == hlv.hu a1, (a1)
0xf3,0x45,0x36,0x64 == hlvx.hu a1, (a2)
0x73,0x46,0x06,0x68 == hlv.w a2, (a2)
0x73,0xc6,0x36,0x68 == hlvx.wu a2, (a3)
0x73,0xc0,0xa5,0x62 == hsv.b a0, (a1)
0x73,0xc0,0xa5,0x66 == hsv.h a0, (a1)
0x73,0xc0,0xa5,0x6a == hsv.w a0, (a1)
external/capstone/suite/MC/RISCV/rv32m_valid_riscv32_m_syntax_no_alias_text.txt.cs
Vendored
+9
View File
@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x33,0x87,0x80,0x02 == mul a4, ra, s0
0xb3,0x10,0x00,0x02 == mulh ra, zero, zero
0xb3,0xa2,0x63,0x02 == mulhsu t0, t2, t1
0xb3,0x37,0xd7,0x02 == mulhu a5, a4, a3
0x33,0x44,0x84,0x02 == div s0, s0, s0
0xb3,0x51,0xb5,0x02 == divu gp, a0, a1
0x33,0x69,0x89,0x03 == rem s2, s2, s8
0x33,0x79,0x89,0x03 == remu s2, s2, s8
external/capstone/suite/MC/RISCV/rv32xtheadbs_valid_riscv32_riscv_xtheadbs.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADBS", None
0x8b,0x12,0x13,0x88 == th.tst t0, t1, 1
0x8b,0x12,0xf3,0x89 == th.tst t0, t1, 31
external/capstone/suite/MC/RISCV/rv32xtheadfmemidx_valid_riscv32_riscv_d_riscv_xtheadfmemidx.txt.cs
Vendored
+9
View File
@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_D"|"CS_MODE_RISCV_XTHEADFMEMIDX", None
0x0b,0xe5,0xc5,0x60 == th.flrd fa0, a1, a2, 0
0x0b,0xe5,0xc5,0x66 == th.flrd fa0, a1, a2, 3
0x0b,0xe5,0xc5,0x40 == th.flrw fa0, a1, a2, 0
0x0b,0xe5,0xc5,0x46 == th.flrw fa0, a1, a2, 3
0x0b,0xf5,0xc5,0x60 == th.fsrd fa0, a1, a2, 0
0x0b,0xf5,0xc5,0x66 == th.fsrd fa0, a1, a2, 3
0x0b,0xf5,0xc5,0x40 == th.fsrw fa0, a1, a2, 0
0x0b,0xf5,0xc5,0x46 == th.fsrw fa0, a1, a2, 3
external/capstone/suite/MC/RISCV/rv32xtheadmac_valid_riscv32_riscv_xtheadmac.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADMAC", None
0x0b,0x95,0xc5,0x20 == th.mula a0, a1, a2
0x0b,0x95,0xc5,0x28 == th.mulah a0, a1, a2
0x0b,0x95,0xc5,0x22 == th.muls a0, a1, a2
0x0b,0x95,0xc5,0x2a == th.mulsh a0, a1, a2
external/capstone/suite/MC/RISCV/rv32xtheadmemidx_valid_riscv32_riscv_xtheadmemidx.txt.cs
Vendored
+33
View File
@@ -0,0 +1,33 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADMEMIDX", None
0x0b,0xc5,0x05,0x5c == th.lwia a0, (a1), 0, 2
0x0b,0xc5,0x05,0x4f == th.lwib a0, (a1), -16, 3
0x0b,0xc5,0x05,0x3c == th.lhia a0, (a1), 0, 2
0x0b,0xc5,0x05,0x2f == th.lhib a0, (a1), -16, 3
0x0b,0xc5,0x05,0xb8 == th.lhuia a0, (a1), 0, 0
0x0b,0xc5,0xf5,0xaa == th.lhuib a0, (a1), 15, 1
0x0b,0xc5,0x05,0x1c == th.lbia a0, (a1), 0, 2
0x0b,0xc5,0x05,0x0f == th.lbib a0, (a1), -16, 3
0x0b,0xc5,0x05,0x98 == th.lbuia a0, (a1), 0, 0
0x0b,0xc5,0xf5,0x8a == th.lbuib a0, (a1), 15, 1
0x0b,0xd5,0x05,0x5c == th.swia a0, (a1), 0, 2
0x0b,0xd5,0x15,0x4e == th.swib a0, (a1), 1, 3
0x0b,0xd5,0x45,0x38 == th.shia a0, (a1), 4, 0
0x0b,0xd5,0xd5,0x2a == th.shib a0, (a1), 13, 1
0x0b,0xd5,0xe5,0x1c == th.sbia a0, (a1), 14, 2
0x0b,0xd5,0xf5,0x0e == th.sbib a0, (a1), 15, 3
0x0b,0xc5,0xc5,0x42 == th.lrw a0, a1, a2, 1
0x0b,0xc5,0xc5,0x26 == th.lrh a0, a1, a2, 3
0x0b,0xc5,0xc5,0xa0 == th.lrhu a0, a1, a2, 0
0x0b,0xc5,0xc5,0x02 == th.lrb a0, a1, a2, 1
0x0b,0xc5,0xc5,0x84 == th.lrbu a0, a1, a2, 2
0x0b,0xd5,0xc5,0x40 == th.srw a0, a1, a2, 0
0x0b,0xd5,0xc5,0x22 == th.srh a0, a1, a2, 1
0x0b,0xd5,0xc5,0x04 == th.srb a0, a1, a2, 2
0x0b,0xc5,0xc5,0x52 == th.lurw a0, a1, a2, 1
0x0b,0xc5,0xc5,0x36 == th.lurh a0, a1, a2, 3
0x0b,0xc5,0xc5,0xb0 == th.lurhu a0, a1, a2, 0
0x0b,0xc5,0xc5,0x12 == th.lurb a0, a1, a2, 1
0x0b,0xc5,0xc5,0x94 == th.lurbu a0, a1, a2, 2
0x0b,0xd5,0xc5,0x50 == th.surw a0, a1, a2, 0
0x0b,0xd5,0xc5,0x32 == th.surh a0, a1, a2, 1
0x0b,0xd5,0xc5,0x14 == th.surb a0, a1, a2, 2
external/capstone/suite/MC/RISCV/rv32xtheadmempair_valid_riscv32_riscv_xtheadmempair.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADMEMPAIR", None
0x0b,0x45,0xb6,0xe2 == th.lwd a0, a1, (a2), 1, 3
0x0b,0x45,0xb6,0xf4 == th.lwud a0, a1, (a2), 2, 3
0x0b,0x55,0xb6,0xe0 == th.swd a0, a1, (a2), 0, 3
external/capstone/suite/MC/RISCV/rv32zaamo_valid_riscv32_riscv_a_syntax_no_alias_text.txt.cs
Vendored
+37
View File
@@ -0,0 +1,37 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_A", None
0x2f,0x27,0x14,0x08 == amoswap.w a4, ra, (s0)
0xaf,0xa5,0xc6,0x00 == amoadd.w a1, a2, (a3)
0x2f,0x26,0xd7,0x20 == amoxor.w a2, a3, (a4)
0xaf,0xa6,0xe7,0x60 == amoand.w a3, a4, (a5)
0x2f,0x27,0xf8,0x40 == amoor.w a4, a5, (a6)
0xaf,0xa7,0x08,0x81 == amomin.w a5, a6, (a7)
0xaf,0xab,0x6a,0xa1 == amomax.w s7, s6, (s5)
0x2f,0x2b,0x5a,0xc1 == amominu.w s6, s5, (s4)
0xaf,0xaa,0x49,0xe1 == amomaxu.w s5, s4, (s3)
0x2f,0x27,0x14,0x0c == amoswap.w.aq a4, ra, (s0)
0xaf,0xa5,0xc6,0x04 == amoadd.w.aq a1, a2, (a3)
0x2f,0x26,0xd7,0x24 == amoxor.w.aq a2, a3, (a4)
0xaf,0xa6,0xe7,0x64 == amoand.w.aq a3, a4, (a5)
0x2f,0x27,0xf8,0x44 == amoor.w.aq a4, a5, (a6)
0xaf,0xa7,0x08,0x85 == amomin.w.aq a5, a6, (a7)
0xaf,0xab,0x6a,0xa5 == amomax.w.aq s7, s6, (s5)
0x2f,0x2b,0x5a,0xc5 == amominu.w.aq s6, s5, (s4)
0xaf,0xaa,0x49,0xe5 == amomaxu.w.aq s5, s4, (s3)
0x2f,0x27,0x14,0x0a == amoswap.w.rl a4, ra, (s0)
0xaf,0xa5,0xc6,0x02 == amoadd.w.rl a1, a2, (a3)
0x2f,0x26,0xd7,0x22 == amoxor.w.rl a2, a3, (a4)
0xaf,0xa6,0xe7,0x62 == amoand.w.rl a3, a4, (a5)
0x2f,0x27,0xf8,0x42 == amoor.w.rl a4, a5, (a6)
0xaf,0xa7,0x08,0x83 == amomin.w.rl a5, a6, (a7)
0xaf,0xab,0x6a,0xa3 == amomax.w.rl s7, s6, (s5)
0x2f,0x2b,0x5a,0xc3 == amominu.w.rl s6, s5, (s4)
0xaf,0xaa,0x49,0xe3 == amomaxu.w.rl s5, s4, (s3)
0x2f,0x27,0x14,0x0e == amoswap.w.aqrl a4, ra, (s0)
0xaf,0xa5,0xc6,0x06 == amoadd.w.aqrl a1, a2, (a3)
0x2f,0x26,0xd7,0x26 == amoxor.w.aqrl a2, a3, (a4)
0xaf,0xa6,0xe7,0x66 == amoand.w.aqrl a3, a4, (a5)
0x2f,0x27,0xf8,0x46 == amoor.w.aqrl a4, a5, (a6)
0xaf,0xa7,0x08,0x87 == amomin.w.aqrl a5, a6, (a7)
0xaf,0xab,0x6a,0xa7 == amomax.w.aqrl s7, s6, (s5)
0x2f,0x2b,0x5a,0xc7 == amominu.w.aqrl s6, s5, (s4)
0xaf,0xaa,0x49,0xe7 == amomaxu.w.aqrl s5, s4, (s3)
external/capstone/suite/MC/RISCV/rv32zacas_valid_riscv32_experimental_zacas_syntax_no_alias_text.txt.cs
Vendored
+11
View File
@@ -0,0 +1,11 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0xaf,0xa5,0xd7,0x28 == amocas.w a1, a3, (a5)
0x2f,0xa0,0x07,0x28 == amocas.w zero, zero, (a5)
0x2f,0xa0,0x07,0x2c == amocas.w.aq zero, zero, (a5)
0x2f,0xa0,0x07,0x2a == amocas.w.rl zero, zero, (a5)
0x2f,0xa0,0x07,0x2e == amocas.w.aqrl zero, zero, (a5)
0x2f,0xb5,0xc5,0x28 == amocas.d a0, a2, (a1)
0x2f,0xb0,0x05,0x28 == amocas.d zero, zero, (a1)
0x2f,0xb0,0x05,0x2c == amocas.d.aq zero, zero, (a1)
0x2f,0xb0,0x05,0x2a == amocas.d.rl zero, zero, (a1)
0x2f,0xb0,0x05,0x2e == amocas.d.aqrl zero, zero, (a1)
external/capstone/suite/MC/RISCV/rv32zalrsc_valid_riscv32_riscv_a_syntax_no_alias_text.txt.cs
Vendored
+9
View File
@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_A", None
0xaf,0x22,0x03,0x10 == lr.w t0, (t1)
0x2f,0xa3,0x03,0x14 == lr.w.aq t1, (t2)
0xaf,0x23,0x0e,0x12 == lr.w.rl t2, (t3)
0x2f,0xae,0x0e,0x16 == lr.w.aqrl t3, (t4)
0xaf,0xaf,0xee,0x19 == sc.w t6, t5, (t4)
0x2f,0x2f,0xde,0x1d == sc.w.aq t5, t4, (t3)
0xaf,0xae,0xc3,0x1b == sc.w.rl t4, t3, (t2)
0x2f,0x2e,0x73,0x1e == sc.w.aqrl t3, t2, (t1)
external/capstone/suite/MC/RISCV/rv32zba_valid_riscv32_riscv_zba.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBA", None
0xb3,0x22,0x73,0x20 == sh1add t0, t1, t2
0xb3,0x42,0x73,0x20 == sh2add t0, t1, t2
0xb3,0x62,0x73,0x20 == sh3add t0, t1, t2
external/capstone/suite/MC/RISCV/rv32zbb_only_valid_riscv32_riscv_zbb_syntax_no_alias_text.txt.cs
Vendored
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBB", None
0xb3,0x42,0x03,0x08 == zext.h t0, t1
0x93,0x52,0xf3,0x61 == rori t0, t1, 31
0x93,0x52,0x03,0x60 == rori t0, t1, 0
0x93,0x52,0x83,0x69 == rev8 t0, t1
external/capstone/suite/MC/RISCV/rv32zbb_valid_riscv32_riscv_zbb_syntax_no_alias_text.txt.cs
Vendored
+16
View File
@@ -0,0 +1,16 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBB", None
0x93,0x12,0x03,0x60 == clz t0, t1
0x93,0x12,0x13,0x60 == ctz t0, t1
0x93,0x12,0x23,0x60 == cpop t0, t1
0x93,0x12,0x43,0x60 == sext.b t0, t1
0x93,0x12,0x53,0x60 == sext.h t0, t1
0xb3,0x42,0x73,0x0a == min t0, t1, t2
0xb3,0x52,0x73,0x0a == minu t0, t1, t2
0xb3,0x62,0x73,0x0a == max t0, t1, t2
0xb3,0x72,0x73,0x0a == maxu t0, t1, t2
0xb3,0x72,0x73,0x40 == andn t0, t1, t2
0xb3,0x62,0x73,0x40 == orn t0, t1, t2
0xb3,0x42,0x73,0x40 == xnor t0, t1, t2
0xb3,0x12,0x73,0x60 == rol t0, t1, t2
0xb3,0x52,0x73,0x60 == ror t0, t1, t2
0x93,0x52,0x73,0x28 == orc.b t0, t1
external/capstone/suite/MC/RISCV/rv32zbc_valid_riscv32_riscv_zbc.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBC", None
0xb3,0x12,0x73,0x0a == clmul t0, t1, t2
0xb3,0x22,0x73,0x0a == clmulr t0, t1, t2
0xb3,0x32,0x73,0x0a == clmulh t0, t1, t2
external/capstone/suite/MC/RISCV/rv32zbkb_only_valid_riscv32_riscv_zbkb.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBKB", None
0x93,0x52,0x83,0x69 == rev8 t0, t1
0x93,0x12,0xf3,0x08 == zip t0, t1
0x93,0x52,0xf3,0x08 == unzip t0, t1
external/capstone/suite/MC/RISCV/rv32zbkb_valid_riscv32_riscv_zbkb.txt.cs
Vendored
+12
View File
@@ -0,0 +1,12 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBKB", None
0xb3,0x52,0x73,0x60 == ror t0, t1, t2
0xb3,0x12,0x73,0x60 == rol t0, t1, t2
0x93,0x52,0xf3,0x61 == rori t0, t1, 31
0x93,0x52,0x03,0x60 == rori t0, t1, 0
0xb3,0x72,0x73,0x40 == andn t0, t1, t2
0xb3,0x62,0x73,0x40 == orn t0, t1, t2
0xb3,0x42,0x73,0x40 == xnor t0, t1, t2
0xb3,0x42,0x73,0x08 == pack t0, t1, t2
0xb3,0x42,0x03,0x08 == pack t0, t1, zero
0xb3,0x72,0x73,0x08 == packh t0, t1, t2
0x93,0x52,0x73,0x68 == brev8 t0, t1
external/capstone/suite/MC/RISCV/rv32zbkc_valid_riscv32_riscv_zbkc.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBKC", None
0xb3,0x12,0x73,0x0a == clmul t0, t1, t2
0xb3,0x32,0x73,0x0a == clmulh t0, t1, t2
external/capstone/suite/MC/RISCV/rv32zbkx_valid_riscv32_riscv_zbkx.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBKX", None
0xb3,0x42,0x73,0x28 == xperm8 t0, t1, t2
0xb3,0x22,0x73,0x28 == xperm4 t0, t1, t2
external/capstone/suite/MC/RISCV/rv32zbs_valid_riscv32_riscv_zbs.txt.cs
Vendored
+9
View File
@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBS", None
0xb3,0x12,0x73,0x48 == bclr t0, t1, t2
0xb3,0x12,0x73,0x28 == bset t0, t1, t2
0xb3,0x12,0x73,0x68 == binv t0, t1, t2
0xb3,0x52,0x73,0x48 == bext t0, t1, t2
0x93,0x12,0x13,0x48 == bclri t0, t1, 1
0x93,0x12,0x13,0x28 == bseti t0, t1, 1
0x93,0x12,0x13,0x68 == binvi t0, t1, 1
0x93,0x52,0x13,0x48 == bexti t0, t1, 1
external/capstone/suite/MC/RISCV/rv32zcb_valid_riscv32_m_riscv_zbb_riscv_zba__zcb_syntax_no_alias_text.txt.cs
Vendored
+17
View File
@@ -0,0 +1,17 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZBB"|"CS_MODE_RISCV_ZBA", None
0x61,0x9c == c.zext.b s0
0x65,0x9c == c.sext.b s0
0x69,0x9c == c.zext.h s0
0x6d,0x9c == c.sext.h s0
0x75,0x9c == c.not s0
0x45,0x9c == c.mul s0, s1
0x3c,0x83 == c.lbu a5, 2(a4)
0x3c,0x87 == c.lhu a5, 2(a4)
0x7c,0x87 == c.lh a5, 2(a4)
0x3c,0x8b == c.sb a5, 2(a4)
0x3c,0x8f == c.sh a5, 2(a4)
0x80,0x80 == c.lbu s0, 0(s1)
0x80,0x84 == c.lhu s0, 0(s1)
0xc0,0x84 == c.lh s0, 0(s1)
0x80,0x88 == c.sb s0, 0(s1)
0x80,0x8c == c.sh s0, 0(s1)
external/capstone/suite/MC/RISCV/rv32zcmp_valid_riscv32_riscv_zcmp_syntax_no_alias_text.txt.cs
Vendored
+38
View File
@@ -0,0 +1,38 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZCMP", None
0xa2,0xac == cm.mvsa01 s1, s0
0xe2,0xac == cm.mva01s s1, s0
0x62,0xac == cm.mva01s s0, s0
0x42,0xbe == cm.popret {ra}, 16
0x46,0xbe == cm.popret {ra}, 32
0x5e,0xbe == cm.popret {ra, s0}, 64
0x62,0xbe == cm.popret {ra, s0-s1}, 16
0x76,0xbe == cm.popret {ra, s0-s2}, 32
0x82,0xbe == cm.popret {ra, s0-s3}, 32
0xa2,0xbe == cm.popret {ra, s0-s5}, 32
0xc2,0xbe == cm.popret {ra, s0-s7}, 48
0xfe,0xbe == cm.popret {ra, s0-s11}, 112
0x42,0xbc == cm.popretz {ra}, 16
0x46,0xbc == cm.popretz {ra}, 32
0x5e,0xbc == cm.popretz {ra, s0}, 64
0x62,0xbc == cm.popretz {ra, s0-s1}, 16
0x76,0xbc == cm.popretz {ra, s0-s2}, 32
0x82,0xbc == cm.popretz {ra, s0-s3}, 32
0xa2,0xbc == cm.popretz {ra, s0-s5}, 32
0xc2,0xbc == cm.popretz {ra, s0-s7}, 48
0xfe,0xbc == cm.popretz {ra, s0-s11}, 112
0x42,0xba == cm.pop {ra}, 16
0x46,0xba == cm.pop {ra}, 32
0x52,0xba == cm.pop {ra, s0}, 16
0x66,0xba == cm.pop {ra, s0-s1}, 32
0x76,0xba == cm.pop {ra, s0-s2}, 32
0xa2,0xba == cm.pop {ra, s0-s5}, 32
0xc2,0xba == cm.pop {ra, s0-s7}, 48
0xf2,0xba == cm.pop {ra, s0-s11}, 64
0x42,0xb8 == cm.push {ra}, -16
0x56,0xb8 == cm.push {ra, s0}, -32
0x62,0xb8 == cm.push {ra, s0-s1}, -16
0x82,0xb8 == cm.push {ra, s0-s3}, -32
0xc2,0xb8 == cm.push {ra, s0-s7}, -48
0xc6,0xb8 == cm.push {ra, s0-s7}, -64
0xf6,0xb8 == cm.push {ra, s0-s11}, -80
0xfe,0xb8 == cm.push {ra, s0-s11}, -112
external/capstone/suite/MC/RISCV/rv32zcmt_valid_riscv32_riscv_zcmt_syntax_no_alias_text.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZCMT", None
0x06,0xa0 == cm.jt 1
0x82,0xa0 == cm.jalt 32
external/capstone/suite/MC/RISCV/rv32zdinx_valid_riscv32_riscv_zdinx_syntax_no_alias_text.txt.cs
Vendored
+38
View File
@@ -0,0 +1,38 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZDINX", None
0x43,0x75,0xe6,0x82 == fmadd.d a0, a2, a4, a6, dyn
0x47,0x75,0xe6,0x82 == fmsub.d a0, a2, a4, a6, dyn
0x4b,0x75,0xe6,0x82 == fnmsub.d a0, a2, a4, a6, dyn
0x4f,0x75,0xe6,0x82 == fnmadd.d a0, a2, a4, a6, dyn
0x53,0x7d,0xee,0x03 == fadd.d s10, t3, t5, dyn
0x53,0x7d,0xee,0x0b == fsub.d s10, t3, t5, dyn
0x53,0x7d,0xee,0x13 == fmul.d s10, t3, t5, dyn
0x53,0x7d,0xee,0x1b == fdiv.d s10, t3, t5, dyn
0x53,0x7a,0x0b,0x5a == fsqrt.d s4, s6, dyn
0x53,0x0d,0xee,0x23 == fsgnj.d s10, t3, t5
0x53,0x1d,0xee,0x23 == fsgnjn.d s10, t3, t5
0x53,0x2d,0xee,0x23 == fsgnjx.d s10, t3, t5
0x53,0x0d,0xee,0x2b == fmin.d s10, t3, t5
0x53,0x1d,0xee,0x2b == fmax.d s10, t3, t5
0x53,0x7d,0x1e,0x40 == fcvt.s.d s10, t3, dyn
0x53,0x0d,0x0e,0x42 == fcvt.d.s s10, t3
0x53,0x3d,0x0e,0x42 == fcvt.d.s s10, t3, rup
0x53,0x2d,0xee,0xa3 == feq.d s10, t3, t5
0x53,0x1d,0xee,0xa3 == flt.d s10, t3, t5
0x53,0x0d,0xee,0xa3 == fle.d s10, t3, t5
0x53,0x1d,0x0e,0xe2 == fclass.d s10, t3
0x53,0x7a,0x0b,0xc2 == fcvt.w.d s4, s6, dyn
0x53,0x0d,0x0e,0xd2 == fcvt.d.w s10, t3
0x53,0x3d,0x0e,0xd2 == fcvt.d.w s10, t3, rup
0x53,0x0d,0x1e,0xd2 == fcvt.d.wu s10, t3
0x53,0x3d,0x1e,0xd2 == fcvt.d.wu s10, t3, rup
0x43,0x05,0xe6,0x82 == fmadd.d a0, a2, a4, a6, rne
0x47,0x15,0xe6,0x82 == fmsub.d a0, a2, a4, a6, rtz
0x4b,0x25,0xe6,0x82 == fnmsub.d a0, a2, a4, a6, rdn
0x4f,0x35,0xe6,0x82 == fnmadd.d a0, a2, a4, a6, rup
0x53,0x4d,0xee,0x03 == fadd.d s10, t3, t5, rmm
0x53,0x0d,0xee,0x13 == fmul.d s10, t3, t5, rne
0x53,0x1d,0xee,0x1b == fdiv.d s10, t3, t5, rtz
0x53,0x2a,0x0b,0x5a == fsqrt.d s4, s6, rdn
0x53,0x3a,0x1b,0x40 == fcvt.s.d s4, s6, rup
0x53,0x4a,0x0b,0xc2 == fcvt.w.d s4, s6, rmm
0x53,0x7a,0x1b,0xc2 == fcvt.wu.d s4, s6, dyn
external/capstone/suite/MC/RISCV/rv32zfa_only_valid_riscv32_zfa_riscv_d__zfh_syntax_no_alias_text.txt.cs
Vendored
+3
View File
@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_D", None
0xd3,0x85,0x14,0xe2 == fmvh.x.d a1, fs1
0xd3,0x84,0xc5,0xb2 == fmvp.d.x fs1, a1, a2
external/capstone/suite/MC/RISCV/rv32zfbfmin_valid_riscv32_experimental_zfbfmin_syntax_no_alias_text.txt.cs
Vendored
+15
View File
@@ -0,0 +1,15 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x07,0x10,0xc5,0x00 == flh ft0, 12(a0)
0x87,0x90,0x40,0x00 == flh ft1, 4(ra)
0x07,0x91,0x06,0x80 == flh ft2, -2048(a3)
0x87,0x91,0x04,0x80 == flh ft3, -2048(s1)
0x07,0x12,0xf9,0x7f == flh ft4, 2047(s2)
0x87,0x92,0x09,0x00 == flh ft5, 0(s3)
0xa7,0x1f,0x6a,0x7e == fsh ft6, 2047(s4)
0x27,0x90,0x7a,0x80 == fsh ft7, -2048(s5)
0x27,0x10,0x8b,0x80 == fsh fs0, -2048(s6)
0xa7,0x93,0x9b,0x3e == fsh fs1, 999(s7)
0x53,0x86,0x0b,0xe4 == fmv.x.h a2, fs7
0xd3,0x00,0x08,0xf4 == fmv.h.x ft1, a6
0x53,0x75,0x60,0x40 == fcvt.s.bf16 fa0, ft0, dyn
0x53,0x71,0x86,0x44 == fcvt.bf16.s ft2, fa2, dyn
external/capstone/suite/MC/RISCV/rv32zfh_valid_riscv32_zfh_syntax_no_alias_text.txt.cs
Vendored
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x07,0x10,0xc5,0x00 == flh ft0, 12(a0)
0x87,0x90,0x40,0x00 == flh ft1, 4(ra)
0x07,0x91,0x06,0x80 == flh ft2, -2048(a3)
0x87,0x91,0x04,0x80 == flh ft3, -2048(s1)
0x07,0x12,0xf9,0x7f == flh ft4, 2047(s2)
0x87,0x92,0x09,0x00 == flh ft5, 0(s3)
0xa7,0x1f,0x6a,0x7e == fsh ft6, 2047(s4)
0x27,0x90,0x7a,0x80 == fsh ft7, -2048(s5)
0x27,0x10,0x8b,0x80 == fsh fs0, -2048(s6)
0xa7,0x93,0x9b,0x3e == fsh fs1, 999(s7)
0x43,0xf5,0xc5,0x6c == fmadd.h fa0, fa1, fa2, fa3, dyn
0x47,0xf7,0x07,0x8d == fmsub.h fa4, fa5, fa6, fa7, dyn
0x4b,0xf9,0x49,0xad == fnmsub.h fs2, fs3, fs4, fs5, dyn
0x4f,0xfb,0x8b,0xcd == fnmadd.h fs6, fs7, fs8, fs9, dyn
0x53,0xfd,0xcd,0x05 == fadd.h fs10, fs11, ft8, dyn
0xd3,0x7e,0xff,0x0d == fsub.h ft9, ft10, ft11, dyn
0x53,0xf0,0x20,0x14 == fmul.h ft0, ft1, ft2, dyn
0xd3,0x71,0x52,0x1c == fdiv.h ft3, ft4, ft5, dyn
0x53,0xf3,0x03,0x5c == fsqrt.h ft6, ft7, dyn
0xd3,0x04,0xb5,0x24 == fsgnj.h fs1, fa0, fa1
0xd3,0x95,0xe6,0x24 == fsgnjn.h fa1, fa3, fa4
0x53,0xa7,0xc6,0x24 == fsgnjx.h fa4, fa3, fa2
0xd3,0x07,0x18,0x2d == fmin.h fa5, fa6, fa7
0x53,0x99,0x49,0x2d == fmax.h fs2, fs3, fs4
0x53,0xf5,0x0a,0xc4 == fcvt.w.h a0, fs5, dyn
0xd3,0x75,0x1b,0xc4 == fcvt.wu.h a1, fs6, dyn
0x53,0x86,0x0b,0xe4 == fmv.x.h a2, fs7
0xd3,0x25,0x9c,0xa5 == feq.h a1, fs8, fs9
0x53,0x16,0xbd,0xa5 == flt.h a2, fs10, fs11
0xd3,0x06,0xde,0xa5 == fle.h a3, ft8, ft9
0xd3,0x16,0x0f,0xe4 == fclass.h a3, ft10
0xd3,0x7f,0x07,0xd4 == fcvt.h.w ft11, a4, dyn
0x53,0xf0,0x17,0xd4 == fcvt.h.wu ft0, a5, dyn
0xd3,0x00,0x08,0xf4 == fmv.h.x ft1, a6
0x43,0x85,0xc5,0x6c == fmadd.h fa0, fa1, fa2, fa3, rne
0x47,0x97,0x07,0x8d == fmsub.h fa4, fa5, fa6, fa7, rtz
0x4b,0xa9,0x49,0xad == fnmsub.h fs2, fs3, fs4, fs5, rdn
0x4f,0xbb,0x8b,0xcd == fnmadd.h fs6, fs7, fs8, fs9, rup
0x43,0xc5,0xc5,0x6c == fmadd.h fa0, fa1, fa2, fa3, rmm
0x53,0x8d,0xcd,0x05 == fadd.h fs10, fs11, ft8, rne
0xd3,0x1e,0xff,0x0d == fsub.h ft9, ft10, ft11, rtz
0x53,0xa0,0x20,0x14 == fmul.h ft0, ft1, ft2, rdn
0xd3,0x31,0x52,0x1c == fdiv.h ft3, ft4, ft5, rup
0x53,0xc3,0x03,0x5c == fsqrt.h ft6, ft7, rmm
0x53,0xb5,0x0a,0xc4 == fcvt.w.h a0, fs5, rup
0xd3,0x25,0x1b,0xc4 == fcvt.wu.h a1, fs6, rdn
0xd3,0x1f,0x07,0xd4 == fcvt.h.w ft11, a4, rtz
0x53,0x80,0x17,0xd4 == fcvt.h.wu ft0, a5, rne
external/capstone/suite/MC/RISCV/rv32zfhmin_valid_riscv32_zfhmin_riscv_d_syntax_no_alias_text.txt.cs
Vendored
+19
View File
@@ -0,0 +1,19 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_D", None
0x07,0x10,0xc5,0x00 == flh ft0, 12(a0)
0x87,0x90,0x40,0x00 == flh ft1, 4(ra)
0x07,0x91,0x06,0x80 == flh ft2, -2048(a3)
0x87,0x91,0x04,0x80 == flh ft3, -2048(s1)
0x07,0x12,0xf9,0x7f == flh ft4, 2047(s2)
0x87,0x92,0x09,0x00 == flh ft5, 0(s3)
0xa7,0x1f,0x6a,0x7e == fsh ft6, 2047(s4)
0x27,0x90,0x7a,0x80 == fsh ft7, -2048(s5)
0x27,0x10,0x8b,0x80 == fsh fs0, -2048(s6)
0xa7,0x93,0x9b,0x3e == fsh fs1, 999(s7)
0x53,0x86,0x0b,0xe4 == fmv.x.h a2, fs7
0xd3,0x00,0x08,0xf4 == fmv.h.x ft1, a6
0x53,0x05,0x20,0x40 == fcvt.s.h fa0, ft0
0x53,0x35,0x20,0x40 == fcvt.s.h fa0, ft0, rup
0x53,0x71,0x06,0x44 == fcvt.h.s ft2, fa2, dyn
0x53,0x05,0x20,0x42 == fcvt.d.h fa0, ft0
0x53,0x35,0x20,0x42 == fcvt.d.h fa0, ft0, rup
0x53,0x71,0x16,0x44 == fcvt.h.d ft2, fa2, dyn
external/capstone/suite/MC/RISCV/rv32zfinx_valid_riscv32_riscv_zfinx_syntax_no_alias_text.txt.cs
Vendored
+37
View File
@@ -0,0 +1,37 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZFINX", None
0x43,0xf5,0xc5,0x68 == fmadd.s a0, a1, a2, a3, dyn
0x47,0xf7,0x07,0x89 == fmsub.s a4, a5, a6, a7, dyn
0x4b,0xf9,0x49,0xa9 == fnmsub.s s2, s3, s4, s5, dyn
0x4f,0xfb,0x8b,0xc9 == fnmadd.s s6, s7, s8, s9, dyn
0x53,0xfd,0xcd,0x01 == fadd.s s10, s11, t3, dyn
0xd3,0x7e,0xff,0x09 == fsub.s t4, t5, t6, dyn
0x53,0xf4,0x24,0x11 == fmul.s s0, s1, s2, dyn
0xd3,0x79,0x5a,0x19 == fdiv.s s3, s4, s5, dyn
0x53,0xf3,0x03,0x58 == fsqrt.s t1, t2, dyn
0xd3,0x04,0xb5,0x20 == fsgnj.s s1, a0, a1
0xd3,0x95,0xe6,0x20 == fsgnjn.s a1, a3, a4
0x53,0xa7,0xc6,0x20 == fsgnjx.s a4, a3, a2
0xd3,0x07,0x18,0x29 == fmin.s a5, a6, a7
0x53,0x99,0x49,0x29 == fmax.s s2, s3, s4
0x53,0xf5,0x0a,0xc0 == fcvt.w.s a0, s5, dyn
0xd3,0x75,0x1b,0xc0 == fcvt.wu.s a1, s6, dyn
0xd3,0x25,0x9c,0xa1 == feq.s a1, s8, s9
0x53,0x16,0xbd,0xa1 == flt.s a2, s10, s11
0xd3,0x06,0xde,0xa1 == fle.s a3, t3, t4
0xd3,0x16,0x0f,0xe0 == fclass.s a3, t5
0xd3,0x7f,0x07,0xd0 == fcvt.s.w t6, a4, dyn
0x53,0xf4,0x17,0xd0 == fcvt.s.wu s0, a5, dyn
0x43,0x85,0xc5,0x68 == fmadd.s a0, a1, a2, a3, rne
0x47,0x97,0x07,0x89 == fmsub.s a4, a5, a6, a7, rtz
0x4b,0xa9,0x49,0xa9 == fnmsub.s s2, s3, s4, s5, rdn
0x4f,0xbb,0x8b,0xc9 == fnmadd.s s6, s7, s8, s9, rup
0x43,0xc5,0xc5,0x68 == fmadd.s a0, a1, a2, a3, rmm
0x53,0x8d,0xcd,0x01 == fadd.s s10, s11, t3, rne
0xd3,0x1e,0xff,0x09 == fsub.s t4, t5, t6, rtz
0x53,0xa4,0x24,0x11 == fmul.s s0, s1, s2, rdn
0xd3,0x39,0x5a,0x19 == fdiv.s s3, s4, s5, rup
0x53,0xc3,0x03,0x58 == fsqrt.s t1, t2, rmm
0x53,0xb5,0x0a,0xc0 == fcvt.w.s a0, s5, rup
0xd3,0x25,0x1b,0xc0 == fcvt.wu.s a1, s6, rdn
0xd3,0x1f,0x07,0xd0 == fcvt.s.w t6, a4, rtz
0x53,0x84,0x17,0xd0 == fcvt.s.wu s0, a5, rne
external/capstone/suite/MC/RISCV/rv32zhinx_valid_riscv32_riscv_zfinx_syntax_no_alias_text.txt.cs
Vendored
+37
View File
@@ -0,0 +1,37 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZFINX", None
0x43,0xf5,0xc5,0x6c == fmadd.h a0, a1, a2, a3, dyn
0x47,0xf7,0x07,0x8d == fmsub.h a4, a5, a6, a7, dyn
0x4b,0xf9,0x49,0xad == fnmsub.h s2, s3, s4, s5, dyn
0x4f,0xfb,0x8b,0xcd == fnmadd.h s6, s7, s8, s9, dyn
0x53,0xfd,0xcd,0x05 == fadd.h s10, s11, t3, dyn
0xd3,0x7e,0xff,0x0d == fsub.h t4, t5, t6, dyn
0x53,0xf4,0x24,0x15 == fmul.h s0, s1, s2, dyn
0xd3,0x79,0x5a,0x1d == fdiv.h s3, s4, s5, dyn
0x53,0xfb,0x0b,0x5c == fsqrt.h s6, s7, dyn
0xd3,0x04,0xb5,0x24 == fsgnj.h s1, a0, a1
0xd3,0x95,0xe6,0x24 == fsgnjn.h a1, a3, a4
0x53,0xa7,0xc6,0x24 == fsgnjx.h a4, a3, a2
0xd3,0x07,0x18,0x2d == fmin.h a5, a6, a7
0x53,0x99,0x49,0x2d == fmax.h s2, s3, s4
0x53,0xf5,0x0a,0xc4 == fcvt.w.h a0, s5, dyn
0xd3,0x75,0x1b,0xc4 == fcvt.wu.h a1, s6, dyn
0xd3,0x25,0x9c,0xa5 == feq.h a1, s8, s9
0x53,0x16,0xbd,0xa5 == flt.h a2, s10, s11
0xd3,0x06,0xde,0xa5 == fle.h a3, t3, t4
0xd3,0x16,0x0f,0xe4 == fclass.h a3, t5
0xd3,0x7f,0x07,0xd4 == fcvt.h.w t6, a4, dyn
0x53,0xf4,0x17,0xd4 == fcvt.h.wu s0, a5, dyn
0x43,0x85,0xc5,0x6c == fmadd.h a0, a1, a2, a3, rne
0x47,0x97,0x07,0x8d == fmsub.h a4, a5, a6, a7, rtz
0x4b,0xa9,0x49,0xad == fnmsub.h s2, s3, s4, s5, rdn
0x4f,0xbb,0x8b,0xcd == fnmadd.h s6, s7, s8, s9, rup
0x43,0xc5,0xc5,0x6c == fmadd.h a0, a1, a2, a3, rmm
0x53,0x8d,0xcd,0x05 == fadd.h s10, s11, t3, rne
0xd3,0x1e,0xff,0x0d == fsub.h t4, t5, t6, rtz
0x53,0xa4,0x24,0x15 == fmul.h s0, s1, s2, rdn
0xd3,0x39,0x5a,0x1d == fdiv.h s3, s4, s5, rup
0x53,0xcb,0x0b,0x5c == fsqrt.h s6, s7, rmm
0x53,0xb5,0x0a,0xc4 == fcvt.w.h a0, s5, rup
0xd3,0x25,0x1b,0xc4 == fcvt.wu.h a1, s6, rdn
0xd3,0x1f,0x07,0xd4 == fcvt.h.w t6, a4, rtz
0x53,0x84,0x17,0xd4 == fcvt.h.wu s0, a5, rne
external/capstone/suite/MC/RISCV/rv32zhinxmin_valid_riscv32_riscv_zfinx_syntax_no_alias_text.txt.cs
Vendored
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_ZFINX", None
0x53,0x85,0x25,0x40 == fcvt.s.h a0, a1
0x53,0xb5,0x25,0x40 == fcvt.s.h a0, a1, rup
0x53,0xf5,0x05,0x44 == fcvt.h.s a0, a1, dyn

Some files were not shown because too many files have changed in this diff Show More