weeemu/weee
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'

Browse Source
This commit is contained in:
iris
2026-05-11 11:55:07 +02:00
parent ef8e742694 802798ce3c
commit c0de07465b
3968 changed files with 2967598 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
external/capstone/tests/MC/AArch64/SVE/sqdecp.s.yaml
Vendored
+320
View File
@@ -0,0 +1,320 @@
test_cases:
-
input:
bytes: [ 0x00, 0x8c, 0x2a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.b"
-
input:
bytes: [ 0x00, 0x8c, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.h"
-
input:
bytes: [ 0x00, 0x8c, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.s"
-
input:
bytes: [ 0x00, 0x8c, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.d"
-
input:
bytes: [ 0xff, 0x89, 0x2a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.b, wzr"
-
input:
bytes: [ 0xff, 0x89, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.h, wzr"
-
input:
bytes: [ 0xff, 0x89, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.s, wzr"
-
input:
bytes: [ 0xff, 0x89, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.d, wzr"
-
input:
bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp z0.h, p0.h"
-
input:
bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp z0.h, p0.h"
-
input:
bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp z0.s, p0.s"
-
input:
bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp z0.s, p0.s"
-
input:
bytes: [ 0x00, 0x80, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp z0.d, p0.d"
-
input:
bytes: [ 0x00, 0x80, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp z0.d, p0.d"
-
input:
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "movprfx z0, z7"
-
input:
bytes: [ 0x00, 0x80, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ]
expected:
insns:
-
asm_text: "sqdecp z0.d, p0.d"
-
input:
bytes: [ 0x00, 0x8c, 0x2a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.b"
-
input:
bytes: [ 0x00, 0x8c, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.h"
-
input:
bytes: [ 0x00, 0x8c, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.s"
-
input:
bytes: [ 0x00, 0x8c, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp x0, p0.d"
-
input:
bytes: [ 0xff, 0x89, 0x2a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.b, wzr"
-
input:
bytes: [ 0xff, 0x89, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.h, wzr"
-
input:
bytes: [ 0xff, 0x89, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.s, wzr"
-
input:
bytes: [ 0xff, 0x89, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp xzr, p15.d, wzr"
-
input:
bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp z0.h, p0.h"
-
input:
bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp z0.h, p0.h"
-
input:
bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp z0.s, p0.s"
-
input:
bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp z0.s, p0.s"
-
input:
bytes: [ 0x00, 0x80, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp z0.d, p0.d"
-
input:
bytes: [ 0x00, 0x80, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp z0.d, p0.d"
-
input:
bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "movprfx z0, z7"
-
input:
bytes: [ 0x00, 0x80, 0xea, 0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme" ]
expected:
insns:
-
asm_text: "sqdecp z0.d, p0.d"