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Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'

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iris
2026-05-11 11:55:07 +02:00
parent ef8e742694 802798ce3c
commit c0de07465b
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external/capstone/tests/MC/RISCV/minmax_riscv64_riscv_v.txt.yaml
Vendored
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test_cases:
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x10 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vminu.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x12 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vminu.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x10 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vminu.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x12 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vminu.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x14 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmin.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x16 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmin.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x14 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmin.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x16 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmin.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x18 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmaxu.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x1a ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmaxu.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x18 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmaxu.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x1a ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmaxu.vx v8, v4, a0"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x1c ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmax.vv v8, v4, v20, v0.t"
-
input:
bytes: [ 0x57, 0x04, 0x4a, 0x1e ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmax.vv v8, v4, v20"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x1c ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmax.vx v8, v4, a0, v0.t"
-
input:
bytes: [ 0x57, 0x44, 0x45, 0x1e ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_V" ]
expected:
insns:
-
asm_text: "vmax.vx v8, v4, a0"