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Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'

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iris
2026-05-11 11:55:07 +02:00
parent ef8e742694 802798ce3c
commit c0de07465b
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external/capstone/tests/MC/RISCV/zvfbfwma_riscv32_experimental_zvfbfwma.txt.yaml
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test_cases:
-
input:
bytes: [ 0x57, 0x14, 0x4a, 0xec ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "vfwmaccbf16.vv v8, v20, v4, v0.t"
-
input:
bytes: [ 0x57, 0x14, 0x4a, 0xee ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "vfwmaccbf16.vv v8, v20, v4"
-
input:
bytes: [ 0x57, 0x54, 0x45, 0xec ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "vfwmaccbf16.vf v8, fa0, v4, v0.t"
-
input:
bytes: [ 0x57, 0x54, 0x45, 0xee ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "vfwmaccbf16.vf v8, fa0, v4"
-
input:
bytes: [ 0x07, 0x10, 0xc5, 0x00 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "flh ft0, 12(a0)"
-
input:
bytes: [ 0xa7, 0x1f, 0x6a, 0x7e ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "fsh ft6, 2047(s4)"
-
input:
bytes: [ 0x53, 0x86, 0x0b, 0xe4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "fmv.x.h a2, fs7"
-
input:
bytes: [ 0xd3, 0x00, 0x08, 0xf4 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV32", "experimental-zvfbfwma" ]
expected:
insns:
-
asm_text: "fmv.h.x ft1, a6"