# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADSYNC", None
0x0b,0x00,0xb5,0x04 == th.sfence.vmas a0, a1
0x0b,0x00,0x80,0x01 == th.sync
0x0b,0x00,0xa0,0x01 == th.sync.i
0x0b,0x00,0xb0,0x01 == th.sync.is
0x0b,0x00,0x90,0x01 == th.sync.s