/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

  RISCV_OP_GROUP_Operand = 0,
  RISCV_OP_GROUP_BranchOperand = 1,
  RISCV_OP_GROUP_VMaskReg = 2,
  RISCV_OP_GROUP_VTypeI = 3,
  RISCV_OP_GROUP_ZeroOffsetMemOp = 4,
  RISCV_OP_GROUP_Rlist = 5,
  RISCV_OP_GROUP_Spimm = 6,
  RISCV_OP_GROUP_CSRSystemRegister = 7,
  RISCV_OP_GROUP_RegReg = 8,
  RISCV_OP_GROUP_FRMArg = 9,
  RISCV_OP_GROUP_FRMArgLegacy = 10,
  RISCV_OP_GROUP_FenceArg = 11,
  RISCV_OP_GROUP_FPImmOperand = 12,