144 lines
3.8 KiB
C
144 lines
3.8 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISC-V target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "RISCVBaseInfo.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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typedef struct {
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unsigned value;
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bool isFractional;
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} VLMULDecodeResult;
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VLMULDecodeResult decodeVLMUL(RISCVII_VLMUL VLMUL)
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{
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switch (VLMUL) {
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default:
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CS_ASSERT(0 && "Unexpected LMUL value!");
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break;
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case RISCVII_LMUL_1:
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case RISCVII_LMUL_2:
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case RISCVII_LMUL_4:
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case RISCVII_LMUL_8: {
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VLMULDecodeResult result = { .value = 1 << (unsigned)(VLMUL),
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.isFractional = false };
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return result;
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}
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case RISCVII_LMUL_F2:
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case RISCVII_LMUL_F4:
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case RISCVII_LMUL_F8: {
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VLMULDecodeResult result = { .value = 1 << (8 -
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(unsigned)(VLMUL)),
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.isFractional = true };
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return result;
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}
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}
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VLMULDecodeResult result = { .value = 0, .isFractional = false };
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return result;
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}
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void printVType(unsigned VType, SStream *OS)
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{
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unsigned Sew = RISCVVType_getSEW(VType);
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SStream_concat(OS, "%s", "e");
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printUInt64(OS, Sew);
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unsigned LMul;
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bool Fractional;
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VLMULDecodeResult result = decodeVLMUL(RISCVVType_getVLMUL(VType));
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LMul = result.value;
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Fractional = result.isFractional;
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if (Fractional)
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SStream_concat0(OS, ", mf");
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else
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SStream_concat0(OS, ", m");
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printUInt64(OS, LMul);
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if (RISCVVType_isTailAgnostic(VType))
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SStream_concat0(OS, ", ta");
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else
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SStream_concat0(OS, ", tu");
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if (RISCVVType_isMaskAgnostic(VType))
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SStream_concat0(OS, ", ma");
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else
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SStream_concat0(OS, ", mu");
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}
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typedef struct {
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uint8_t first;
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uint8_t second;
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} LoadFP32ImmArrElement;
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// Lookup table for fli.s for entries 2-31.
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static const LoadFP32ImmArrElement LoadFP32ImmArr[] = {
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{ 0x6f, 0x00 }, { 0x70, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 },
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{ 0x7b, 0x00 }, { 0x7c, 0x00 }, { 0x7d, 0x00 }, { 0x7d, 0x01 },
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{ 0x7d, 0x02 }, { 0x7d, 0x03 }, { 0x7e, 0x00 }, { 0x7e, 0x01 },
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{ 0x7e, 0x02 }, { 0x7e, 0x03 }, { 0x7f, 0x00 }, { 0x7f, 0x01 },
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{ 0x7f, 0x02 }, { 0x7f, 0x03 }, { 0x80, 0x00 }, { 0x80, 0x01 },
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{ 0x80, 0x02 }, { 0x81, 0x00 }, { 0x82, 0x00 }, { 0x83, 0x00 },
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{ 0x86, 0x00 }, { 0x87, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 },
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{ 0xff, 0x00 }, { 0xff, 0x02 },
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};
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float getFPImm(unsigned Imm)
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{
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CS_ASSERT(Imm != 1 && Imm != 30 && Imm != 31 &&
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"Unsupported immediate");
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CS_ASSERT((Imm == 0 || (Imm >= 2 && Imm < 30)) &&
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"Unsupported immediate");
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// Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
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uint32_t Sign = 0;
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if (Imm == 0) {
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Sign = 0x01;
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Imm = 16;
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}
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uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
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uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
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uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
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float result;
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memcpy(&result, &I, sizeof(float));
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return result;
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}
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void RISCVZC_printSpimm(int64_t Spimm, SStream *OS)
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{
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printInt32(OS, Spimm);
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}
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// namespace llvm
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