299 lines
7.8 KiB
C
299 lines
7.8 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISC-V target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../utils.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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// CS namespace begin: RISCVII
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// RISC-V Specific Machine Operand Flags
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enum {
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RISCVII_MO_None = 0,
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RISCVII_MO_CALL = 1,
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RISCVII_MO_LO = 3,
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RISCVII_MO_HI = 4,
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RISCVII_MO_PCREL_LO = 5,
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RISCVII_MO_PCREL_HI = 6,
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RISCVII_MO_GOT_HI = 7,
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RISCVII_MO_TPREL_LO = 8,
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RISCVII_MO_TPREL_HI = 9,
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RISCVII_MO_TPREL_ADD = 10,
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RISCVII_MO_TLS_GOT_HI = 11,
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RISCVII_MO_TLS_GD_HI = 12,
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RISCVII_MO_TLSDESC_HI = 13,
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RISCVII_MO_TLSDESC_LOAD_LO = 14,
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RISCVII_MO_TLSDESC_ADD_LO = 15,
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RISCVII_MO_TLSDESC_CALL = 16,
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// Used to differentiate between target-specific "direct" flags and "bitmask"
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// flags. A machine operand can only have one "direct" flag, but can have
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// multiple "bitmask" flags.
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RISCVII_MO_DIRECT_FLAG_MASK = 31
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};
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typedef enum OperandType {
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RISCVOp_OPERAND_FIRST_RISCV_IMM = MCOI_OPERAND_FIRST_TARGET,
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RISCVOp_OPERAND_UIMM1 = RISCVOp_OPERAND_FIRST_RISCV_IMM,
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RISCVOp_OPERAND_UIMM2,
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RISCVOp_OPERAND_UIMM2_LSB0,
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RISCVOp_OPERAND_UIMM3,
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RISCVOp_OPERAND_UIMM4,
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RISCVOp_OPERAND_UIMM5,
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RISCVOp_OPERAND_UIMM6,
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RISCVOp_OPERAND_UIMM7,
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RISCVOp_OPERAND_UIMM7_LSB00,
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RISCVOp_OPERAND_UIMM8_LSB00,
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RISCVOp_OPERAND_UIMM8,
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RISCVOp_OPERAND_UIMM8_LSB000,
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RISCVOp_OPERAND_UIMM8_GE32,
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RISCVOp_OPERAND_UIMM9_LSB000,
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RISCVOp_OPERAND_UIMM10_LSB00_NONZERO,
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RISCVOp_OPERAND_UIMM12,
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RISCVOp_OPERAND_ZERO,
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RISCVOp_OPERAND_SIMM5,
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RISCVOp_OPERAND_SIMM5_PLUS1,
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RISCVOp_OPERAND_SIMM6,
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RISCVOp_OPERAND_SIMM6_NONZERO,
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RISCVOp_OPERAND_SIMM10_LSB0000_NONZERO,
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RISCVOp_OPERAND_SIMM12,
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RISCVOp_OPERAND_SIMM12_LSB00000,
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RISCVOp_OPERAND_UIMM20,
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RISCVOp_OPERAND_UIMMLOG2XLEN,
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RISCVOp_OPERAND_UIMMLOG2XLEN_NONZERO,
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RISCVOp_OPERAND_CLUI_IMM,
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RISCVOp_OPERAND_VTYPEI10,
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RISCVOp_OPERAND_VTYPEI11,
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RISCVOp_OPERAND_RVKRNUM,
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RISCVOp_OPERAND_RVKRNUM_0_7,
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RISCVOp_OPERAND_RVKRNUM_1_10,
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RISCVOp_OPERAND_RVKRNUM_2_14,
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OPERAND_LAST_RISCV_IMM = RISCVOp_OPERAND_RVKRNUM_2_14,
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// Operand is either a register or uimm5, this is used by V extension pseudo
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// instructions to represent a value that be passed as AVL to either vsetvli
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// or vsetivli.
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RISCVOp_OPERAND_AVL,
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} RISCVOp_OperandType;
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// Describes the predecessor/successor bits used in the FENCE instruction.
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typedef enum FenceField {
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RISCVFenceField_I = 8,
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RISCVFenceField_O = 4,
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RISCVFenceField_R = 2,
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RISCVFenceField_W = 1
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} RISCVFenceField_FenceField;
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// Describes the supported floating point rounding mode encodings.
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typedef enum RoundingMode {
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RISCVFPRndMode_RNE = 0,
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RISCVFPRndMode_RTZ = 1,
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RISCVFPRndMode_RDN = 2,
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RISCVFPRndMode_RUP = 3,
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RISCVFPRndMode_RMM = 4,
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RISCVFPRndMode_DYN = 7,
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RISCVFPRndMode_Invalid
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} RISCVFPRndMode_RoundingMode;
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inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode)
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{
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switch (Mode) {
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default:
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return false;
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case RISCVFPRndMode_RNE:
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case RISCVFPRndMode_RTZ:
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case RISCVFPRndMode_RDN:
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case RISCVFPRndMode_RUP:
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case RISCVFPRndMode_RMM:
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case RISCVFPRndMode_DYN:
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return true;
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}
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}
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inline static const char *RISCVFPRndMode_roundingModeToString(unsigned RndMode)
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{
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switch (RndMode) {
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default:
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CS_ASSERT(0 && "Unknown floating point rounding mode");
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case RISCVFPRndMode_RNE:
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return "rne";
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case RISCVFPRndMode_RTZ:
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return "rtz";
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case RISCVFPRndMode_RDN:
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return "rdn";
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case RISCVFPRndMode_RUP:
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return "rup";
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case RISCVFPRndMode_RMM:
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return "rmm";
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case RISCVFPRndMode_DYN:
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return "dyn";
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}
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}
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inline static bool RISCVVType_isTailAgnostic(unsigned VType)
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{
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return VType & 0x40;
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}
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inline static bool RISCVVType_isMaskAgnostic(unsigned VType)
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{
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return VType & 0x80;
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}
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typedef enum RLISTENCODE {
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RISCVZC_RLISTENCODE_RA = 4,
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RISCVZC_RLISTENCODE_RA_S0,
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RISCVZC_RLISTENCODE_RA_S0_S1,
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RISCVZC_RLISTENCODE_RA_S0_S2,
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RISCVZC_RLISTENCODE_RA_S0_S3,
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RISCVZC_RLISTENCODE_RA_S0_S4,
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RISCVZC_RLISTENCODE_RA_S0_S5,
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RISCVZC_RLISTENCODE_RA_S0_S6,
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RISCVZC_RLISTENCODE_RA_S0_S7,
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RISCVZC_RLISTENCODE_RA_S0_S8,
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RISCVZC_RLISTENCODE_RA_S0_S9,
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// note - to include s10, s11 must also be included
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RISCVZC_RLISTENCODE_RA_S0_S11,
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RISCVZC_RLISTENCODE_INVALID_RLIST,
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} RISCVZC_RLISTENCODE;
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inline static unsigned RISCVZC_getStackAdjBase(unsigned RlistVal, bool IsRV64,
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bool IsEABI)
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{
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CS_ASSERT(RlistVal != RISCVZC_RLISTENCODE_INVALID_RLIST &&
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"{ra, s0-s10} is not supported, s11 must be included.");
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if (IsEABI)
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return 16;
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if (!IsRV64) {
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switch (RlistVal) {
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case RISCVZC_RLISTENCODE_RA:
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case RISCVZC_RLISTENCODE_RA_S0:
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case RISCVZC_RLISTENCODE_RA_S0_S1:
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case RISCVZC_RLISTENCODE_RA_S0_S2:
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return 16;
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case RISCVZC_RLISTENCODE_RA_S0_S3:
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case RISCVZC_RLISTENCODE_RA_S0_S4:
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case RISCVZC_RLISTENCODE_RA_S0_S5:
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case RISCVZC_RLISTENCODE_RA_S0_S6:
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return 32;
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case RISCVZC_RLISTENCODE_RA_S0_S7:
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case RISCVZC_RLISTENCODE_RA_S0_S8:
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case RISCVZC_RLISTENCODE_RA_S0_S9:
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return 48;
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case RISCVZC_RLISTENCODE_RA_S0_S11:
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return 64;
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}
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} else {
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switch (RlistVal) {
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case RISCVZC_RLISTENCODE_RA:
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case RISCVZC_RLISTENCODE_RA_S0:
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return 16;
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case RISCVZC_RLISTENCODE_RA_S0_S1:
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case RISCVZC_RLISTENCODE_RA_S0_S2:
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return 32;
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case RISCVZC_RLISTENCODE_RA_S0_S3:
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case RISCVZC_RLISTENCODE_RA_S0_S4:
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return 48;
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case RISCVZC_RLISTENCODE_RA_S0_S5:
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case RISCVZC_RLISTENCODE_RA_S0_S6:
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return 64;
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case RISCVZC_RLISTENCODE_RA_S0_S7:
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case RISCVZC_RLISTENCODE_RA_S0_S8:
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return 80;
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case RISCVZC_RLISTENCODE_RA_S0_S9:
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return 96;
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case RISCVZC_RLISTENCODE_RA_S0_S11:
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return 112;
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}
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}
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CS_ASSERT(0 && "Unexpected RlistVal");
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return 0; // unreachable
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}
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typedef enum VLMUL {
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RISCVII_LMUL_1 = 0,
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RISCVII_LMUL_2,
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RISCVII_LMUL_4,
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RISCVII_LMUL_8,
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RISCVII_LMUL_RESERVED,
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RISCVII_LMUL_F8,
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RISCVII_LMUL_F4,
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RISCVII_LMUL_F2
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} RISCVII_VLMUL;
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inline static RISCVII_VLMUL RISCVVType_getVLMUL(unsigned VType)
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{
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unsigned VLMUL = VType & 0x7;
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return (RISCVII_VLMUL)(VLMUL);
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}
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inline static unsigned RISCVVType_decodeVSEW(unsigned VSEW)
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{
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CS_ASSERT(VSEW < 8 && "Unexpected VSEW value");
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return 1 << (VSEW + 3);
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}
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inline static unsigned RISCVVType_getSEW(unsigned VType)
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{
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unsigned VSEW = (VType >> 3) & 0x7;
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return RISCVVType_decodeVSEW(VSEW);
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}
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typedef struct {
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unsigned raw_val;
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} RegVal;
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typedef struct SysReg {
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const char *Name;
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RegVal val1;
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const char *AltName;
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RegVal val2;
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const char *DeprecatedName;
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unsigned Encoding;
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unsigned DummyFeatureArray[1];
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bool isRV32Only;
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} RISCV_SysReg;
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void printVType(unsigned VType, SStream *OS);
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float getFPImm(unsigned Imm);
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void RISCVZC_printSpimm(int64_t Spimm, SStream *OS);
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#endif
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