103 lines
3.1 KiB
Python
103 lines
3.1 KiB
Python
import unittest
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from capstone import *
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from capstone.riscv import *
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import unittest
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class TestRiscvRegAccess(unittest.TestCase):
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def setUp(self):
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self.cs = Cs(CS_ARCH_RISCV, CS_MODE_RISCV64)
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self.cs.option(CS_OPT_DETAIL, CS_OPT_DETAIL_REAL | CS_OPT_ON)
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def test_addi(self):
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# addi a0, a1, 10
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code = b"\x13\x85\xa5\x00"
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insns = list(self.cs.disasm(code, 0))
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self.assertEqual(len(insns), 1)
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insn = insns[0]
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read, write = insn.regs_access()
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# a1 = RISCV_REG_X11, a0 = RISCV_REG_X10
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self.assertIn(RISCV_REG_X11, read)
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self.assertIn(RISCV_REG_X10, write)
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self.assertEqual(len(read), 1)
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self.assertEqual(len(write), 1)
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def test_jalr(self):
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# jalr ra, a1, 0 -> 0x000580e7 (rd=x1=ra, rs1=x11=a1, imm=0)
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code = b"\xe7\x80\x05\x00"
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insns = list(self.cs.disasm(code, 0))
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self.assertEqual(len(insns), 1)
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insn = insns[0]
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read, write = insn.regs_access()
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# ra = RISCV_REG_X1
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self.assertIn(RISCV_REG_X11, read)
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self.assertIn(RISCV_REG_X1, write)
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self.assertEqual(len(read), 1)
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self.assertEqual(len(write), 1)
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def test_lb(self):
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# lb a0, 0(sp)
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code = b"\x03\x05\x01\x00"
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insns = list(self.cs.disasm(code, 0))
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self.assertEqual(len(insns), 1)
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insn = insns[0]
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read, write = insn.regs_access()
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# sp = RISCV_REG_X2
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self.assertIn(RISCV_REG_X2, read)
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self.assertIn(RISCV_REG_X10, write)
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self.assertEqual(len(read), 1)
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self.assertEqual(len(write), 1)
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def test_caddi(self):
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# c.addi a0, 10 (0x0529)
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code = b"\x29\x05"
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insns = list(self.cs.disasm(code, 0))
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self.assertEqual(len(insns), 1)
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insn = insns[0]
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read, write = insn.regs_access()
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# x10 is both read and written
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self.assertIn(RISCV_REG_X10, read)
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self.assertIn(RISCV_REG_X10, write)
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self.assertEqual(len(read), 1)
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self.assertEqual(len(write), 1)
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def test_ecall(self):
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# ecall
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code = b"\x73\x00\x00\x00"
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insns = list(self.cs.disasm(code, 0))
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self.assertEqual(len(insns), 1)
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insn = insns[0]
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read, write = insn.regs_access()
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self.assertEqual(len(read), 0)
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self.assertEqual(len(write), 0)
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def test_csrrw(self):
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# csrrw a0, sstatus, a1
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code = b"\x73\x95\x05\x10"
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insns = list(self.cs.disasm(code, 0))
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self.assertEqual(len(insns), 1)
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insn = insns[0]
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read, write = insn.regs_access()
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# CSRs should NOT be in the reg_access list
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self.assertIn(RISCV_REG_X11, read)
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self.assertIn(RISCV_REG_X10, write)
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self.assertEqual(len(read), 1)
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self.assertEqual(len(write), 1)
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def test():
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loader = unittest.TestLoader()
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suite = loader.loadTestsFromTestCase(TestRiscvRegAccess)
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runner = unittest.TextTestRunner(verbosity=2)
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return runner.run(suite).failures
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def main():
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unittest.main()
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if __name__ == '__main__':
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main()
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