iris
802798ce3c
git-subtree-dir: external/capstone git-subtree-split: e46f64fadb351e9ecd05264fab26f2772feb0994
481 lines
10 KiB
YAML
481 lines
10 KiB
YAML
test_cases:
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input:
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bytes: [ 0x8b, 0x02, 0x03, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lb t0, (t1), 0"
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-
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input:
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bytes: [ 0x0b, 0x85, 0xf5, 0x7f ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lb a0, (a1), 2047"
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-
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lb t0, (t1), t2"
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lb a0, (a1), a2"
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x08 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lb t0, t2(t1)"
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-
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x08 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lb a0, a2(a1)"
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-
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input:
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bytes: [ 0x8b, 0x42, 0x03, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lbu t0, (t1), 0"
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-
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input:
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bytes: [ 0x0b, 0xc5, 0xf5, 0x7f ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lbu a0, (a1), 2047"
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x10 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lbu t0, (t1), t2"
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-
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x10 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lbu a0, (a1), a2"
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-
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x18 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lbu t0, t2(t1)"
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x18 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lbu a0, a2(a1)"
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input:
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bytes: [ 0x8b, 0x12, 0x03, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lh t0, (t1), 0"
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-
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input:
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bytes: [ 0x0b, 0x95, 0xf5, 0x7f ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lh a0, (a1), 2047"
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x02 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lh t0, (t1), t2"
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x02 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lh a0, (a1), a2"
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-
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x0a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lh t0, t2(t1)"
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-
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x0a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lh a0, a2(a1)"
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input:
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bytes: [ 0x8b, 0x52, 0x03, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lhu t0, (t1), 0"
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-
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input:
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bytes: [ 0x0b, 0xd5, 0xf5, 0x7f ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lhu a0, (a1), 2047"
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-
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x12 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lhu t0, (t1), t2"
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-
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x12 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lhu a0, (a1), a2"
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-
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x1a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lhu t0, t2(t1)"
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-
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x1a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lhu a0, a2(a1)"
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-
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input:
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bytes: [ 0x8b, 0x22, 0x03, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lw t0, (t1), 0"
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-
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input:
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bytes: [ 0x0b, 0xa5, 0xf5, 0x7f ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lw a0, (a1), 2047"
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-
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x04 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lw t0, (t1), t2"
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-
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x04 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lw a0, (a1), a2"
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-
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input:
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bytes: [ 0xab, 0x32, 0x73, 0x0c ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lw t0, t2(t1)"
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-
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input:
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bytes: [ 0x2b, 0xb5, 0xc5, 0x0c ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.lw a0, a2(a1)"
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-
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input:
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bytes: [ 0x2b, 0x00, 0x53, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sb t0, (t1), 0"
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-
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input:
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bytes: [ 0xab, 0x8f, 0xa5, 0x7e ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sb a0, (a1), 2047"
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-
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input:
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bytes: [ 0xab, 0x33, 0x53, 0x20 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sb t0, (t1), t2"
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-
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input:
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bytes: [ 0x2b, 0xb6, 0xa5, 0x20 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sb a0, (a1), a2"
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-
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input:
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bytes: [ 0xab, 0x33, 0x53, 0x28 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sb t0, t2(t1)"
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-
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input:
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bytes: [ 0x2b, 0xb6, 0xa5, 0x28 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sb a0, a2(a1)"
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-
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input:
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bytes: [ 0x2b, 0x10, 0x53, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sh t0, (t1), 0"
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-
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input:
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bytes: [ 0xab, 0x9f, 0xa5, 0x7e ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sh a0, (a1), 2047"
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-
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input:
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bytes: [ 0xab, 0x33, 0x53, 0x22 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sh t0, (t1), t2"
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-
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input:
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bytes: [ 0x2b, 0xb6, 0xa5, 0x22 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sh a0, (a1), a2"
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-
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input:
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bytes: [ 0xab, 0x33, 0x53, 0x2a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sh t0, t2(t1)"
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-
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input:
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bytes: [ 0x2b, 0xb6, 0xa5, 0x2a ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sh a0, a2(a1)"
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-
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input:
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bytes: [ 0x2b, 0x20, 0x53, 0x00 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sw t0, (t1), 0"
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-
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input:
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bytes: [ 0xab, 0xaf, 0xa5, 0x7e ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sw a0, (a1), 2047"
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-
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input:
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bytes: [ 0xab, 0x33, 0x53, 0x24 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sw t0, (t1), t2"
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-
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input:
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bytes: [ 0x2b, 0xb6, 0xa5, 0x24 ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sw a0, (a1), a2"
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-
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input:
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bytes: [ 0xab, 0x33, 0x53, 0x2c ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sw t0, t2(t1)"
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-
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input:
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bytes: [ 0x2b, 0xb6, 0xa5, 0x2c ]
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arch: "CS_ARCH_RISCV"
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options: [ "CS_MODE_RISCV32", "CS_MODE_RISCV_XCVMEM" ]
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expected:
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insns:
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-
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asm_text: "cv.sw a0, a2(a1)"
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