302 lines
12 KiB
C
302 lines
12 KiB
C
/* Capstone Disassembly Engine */
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/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
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#ifndef CS_M68KDISASSEMBLER_H
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#define CS_M68KDISASSEMBLER_H
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#include "../../MCInst.h"
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/* ======================================================================== */
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/* ============================ GENERAL DEFINES =========================== */
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/* ======================================================================== */
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/* Bit Isolation Functions */
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#define BIT_0(A) ((A) & 0x00000001)
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#define BIT_1(A) ((A) & 0x00000002)
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#define BIT_2(A) ((A) & 0x00000004)
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#define BIT_3(A) ((A) & 0x00000008)
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#define BIT_4(A) ((A) & 0x00000010)
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#define BIT_5(A) ((A) & 0x00000020)
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#define BIT_6(A) ((A) & 0x00000040)
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#define BIT_7(A) ((A) & 0x00000080)
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#define BIT_8(A) ((A) & 0x00000100)
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#define BIT_9(A) ((A) & 0x00000200)
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#define BIT_A(A) ((A) & 0x00000400)
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#define BIT_B(A) ((A) & 0x00000800)
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#define BIT_C(A) ((A) & 0x00001000)
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#define BIT_D(A) ((A) & 0x00002000)
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#define BIT_E(A) ((A) & 0x00004000)
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#define BIT_F(A) ((A) & 0x00008000)
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#define BIT_10(A) ((A) & 0x00010000)
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#define BIT_11(A) ((A) & 0x00020000)
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#define BIT_12(A) ((A) & 0x00040000)
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#define BIT_13(A) ((A) & 0x00080000)
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#define BIT_14(A) ((A) & 0x00100000)
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#define BIT_15(A) ((A) & 0x00200000)
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#define BIT_16(A) ((A) & 0x00400000)
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#define BIT_17(A) ((A) & 0x00800000)
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#define BIT_18(A) ((A) & 0x01000000)
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#define BIT_19(A) ((A) & 0x02000000)
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#define BIT_1A(A) ((A) & 0x04000000)
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#define BIT_1B(A) ((A) & 0x08000000)
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#define BIT_1C(A) ((A) & 0x10000000)
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#define BIT_1D(A) ((A) & 0x20000000)
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#define BIT_1E(A) ((A) & 0x40000000)
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#define BIT_1F(A) ((A) & 0x80000000)
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/* These are the CPU types understood by this disassembler */
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#define TYPE_68000 1
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#define TYPE_68010 2
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#define TYPE_68020 4
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#define TYPE_68030 8
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#define TYPE_68040 16
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#define TYPE_68060 32
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#define TYPE_CPU32 64
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#define M68000_ONLY TYPE_68000
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#define M68010_ONLY TYPE_68010
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#define M68010_LESS (TYPE_68000 | TYPE_68010)
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#define M68010_PLUS \
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(TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68060)
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#define M68020_ONLY TYPE_68020
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#define M68020_LESS (TYPE_68010 | TYPE_68020)
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#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68060)
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#define M68030_ONLY TYPE_68030
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#define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030)
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#define M68030_PLUS (TYPE_68030 | TYPE_68040 | TYPE_68060)
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#define M68040_PLUS (TYPE_68040 | TYPE_68060)
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/* Extension word formats */
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#define EXT_8BIT_DISPLACEMENT(A) ((A) & 0xff)
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#define EXT_FULL(A) BIT_8(A)
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#define EXT_EFFECTIVE_ZERO(A) (((A) & 0xe4) == 0xc4 || ((A) & 0xe2) == 0xc0)
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#define EXT_BASE_REGISTER_PRESENT(A) (!BIT_7(A))
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#define EXT_INDEX_REGISTER_PRESENT(A) (!BIT_6(A))
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#define EXT_INDEX_REGISTER(A) (((A) >> 12) & 7)
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#define EXT_INDEX_PRE_POST(A) (EXT_INDEX_REGISTER_PRESENT(A) && (A) & 3)
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#define EXT_INDEX_PRE(A) \
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(EXT_INDEX_REGISTER_PRESENT(A) && ((A) & 7) < 4 && ((A) & 7) != 0)
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#define EXT_INDEX_POST(A) (EXT_INDEX_REGISTER_PRESENT(A) && ((A) & 7) > 4)
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#define EXT_INDEX_SCALE(A) (((A) >> 9) & 3)
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#define EXT_INDEX_LONG(A) BIT_B(A)
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#define EXT_INDEX_AR(A) BIT_F(A)
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#define EXT_BASE_DISPLACEMENT_PRESENT(A) (((A) & 0x30) > 0x10)
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#define EXT_BASE_DISPLACEMENT_WORD(A) (((A) & 0x30) == 0x20)
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#define EXT_BASE_DISPLACEMENT_LONG(A) (((A) & 0x30) == 0x30)
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/* Outer displacement is present when I/IS[1:0] (bits 1-0) is 2 (word) or 3 (long).
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* This applies regardless of the IS bit (bit 6): when index is suppressed,
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* I/IS values 5-7 mirror 1-3 (just indirect instead of postindexed).
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* The old check ((A) & 0x47) < 0x44 incorrectly excluded IS=1 cases
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* (I/IS=6,7) which DO have outer displacements per the M68K spec.
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*/
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#define EXT_OUTER_DISPLACEMENT_PRESENT(A) (((A) & 3) > 1)
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#define EXT_OUTER_DISPLACEMENT_WORD(A) (((A) & 3) == 2)
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#define EXT_OUTER_DISPLACEMENT_LONG(A) (((A) & 3) == 3)
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#define IS_BITSET(val, b) ((val) & (1 << (b)))
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#define BITFIELD_MASK(sb, eb) (((1 << ((sb) + 1)) - 1) & (~((1 << (eb)) - 1)))
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#define BITFIELD(val, sb, eb) ((BITFIELD_MASK(sb, eb) & (val)) >> (eb))
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/* Bitfield offset/width encoding.
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* Public decode macros (M68K_BF_*) live in <capstone/m68k.h>.
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* Internal aliases kept for brevity within arch code. */
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#define M68K_BITFIELD_REG_FLAG M68K_BF_REG_FLAG
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#define M68K_BITFIELD_IS_REG(v) M68K_BF_IS_REG(v)
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#define M68K_BITFIELD_REG_NUM(v) M68K_BF_REG_NUM(v)
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#define M68K_BITFIELD_ENCODE_REG(regnum) (((regnum) & 7) | M68K_BF_REG_FLAG)
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/* ── Coprocessor ID (CpID) ───────────────────────────────────────────
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* Bits 11:9 of the F-line instruction word select the coprocessor. */
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#define M68K_CPID(info) (((info)->ir >> 9) & 7)
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#define M68K_CPID_MMU 0 /* PMMU (68030/68851) */
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#define M68K_CPID_FPU 1 /* FPU (68881/68882/internal) */
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#define M68K_CPID_CACHE 2 /* Cache ops -- cinvl/cpushl on 68040+ */
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/* ── IR bit-field helpers ────────────────────────────────────────────
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* Extract commonly-used fields from the first instruction word. */
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/* 6-bit coprocessor condition (bits 5:0 of IR). */
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#define M68K_IR_CONDITION(info) ((info)->ir & 0x3f)
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/* cinv/cpush: select cpush(1) vs cinv(0) -- bit 5 of IR. */
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#define M68K_IR_IS_CPUSH(info) (((info)->ir >> 5) & 1)
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/* cinv/cpush: cache scope -- bits 4:3 of IR (0=invalid,1=line,2=page,3=all). */
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#define M68K_IR_CACHE_SCOPE(info) (((info)->ir >> 3) & 3)
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/* cinv/cpush: cache selector -- bits 7:6 of IR (DC/IC/BC). */
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#define M68K_IR_CACHE_SEL(info) (((info)->ir >> 6) & 3)
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/* ── FPU extension-word bit-field helpers ────────────────────────────
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* The FPU command word is the 16-bit extension following the F-line. */
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/* R/M bit (bit 14): 1 = source from EA, 0 = source from FP register. */
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#define M68K_FEXT_RM(ext) (((ext) >> 14) & 1)
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/* Type / command class (bits 15:13). */
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#define M68K_FEXT_TYPE(ext) (((ext) >> 13) & 7)
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/* Source specifier (bits 12:10) -- data format when R/M=1. */
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#define M68K_FEXT_SRC(ext) (((ext) >> 10) & 7)
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/* Destination FP register (bits 9:7). */
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#define M68K_FEXT_DST(ext) (((ext) >> 7) & 7)
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/* Opmode (bits 5:0) -- FPU operation selector. */
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#define M68K_FEXT_OPMODE(ext) ((ext) & 0x3f)
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/* Single/double precision flag (bit 6) -- 68040+ only. */
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#define M68K_FEXT_SD_FLAG(ext) (((ext) >> 6) & 1)
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/* FMOVECR signature: bits 15:10 == 0x17 (010111b). */
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#define M68K_FEXT_IS_FMOVECR(ext) (BITFIELD((ext), 15, 10) == 0x17)
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/* Register-select field for FMOVE to/from FPCR/FPSR/FPIAR (bits 12:10). */
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#define M68K_FEXT_REGSEL(ext) (((ext) >> 10) & 7)
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/* Direction bit for FMOVE FPCR (bit 13): 0 = ea->fpcr, 1 = fpcr->ea. */
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#define M68K_FEXT_DIR(ext) (((ext) >> 13) & 1)
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/* ── FPU condition-code mask ─────────────────────────────────────────
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* FBcc/FDBcc/FScc/FTRAPcc encode the FP condition in bits 5,3:0
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* of the extension word (or IR for FBcc). Bit 4 is always 0,
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* yielding the 0x2f mask. */
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#define M68K_FP_COND(x) ((x) & 0x2f)
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/* Maximum valid condition codes per coprocessor. */
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#define M68K_PMMU_MAX_COND 16
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#define M68K_FPU_MAX_COND 32
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/* ── FPU source-format constants (bits 12:10 of ext word) ───────────*/
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#define M68K_FPSRC_LONG 0x00 /* .l -- 32-bit integer */
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#define M68K_FPSRC_SINGLE 0x01 /* .s -- 32-bit IEEE single */
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#define M68K_FPSRC_EXTENDED 0x02 /* .x -- 96-bit extended real */
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#define M68K_FPSRC_PACKED 0x03 /* .p -- 96-bit packed decimal */
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#define M68K_FPSRC_WORD 0x04 /* .w -- 16-bit integer */
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#define M68K_FPSRC_DOUBLE 0x05 /* .d -- 64-bit IEEE double */
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#define M68K_FPSRC_BYTE 0x06 /* .b -- 8-bit integer */
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/* ── FPU special raw opmodes (before SD-flag masking) ───────────────
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* FSSQRT/FDSQRT have raw 7-bit opmodes 0x41/0x45. After the 6-bit
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* truncation (& 0x3f) they become 0x01/0x05 with the SD flag set. */
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#define M68K_FPOP_FSSQRT_RAW 0x01 /* 0x41 & 0x3f */
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#define M68K_FPOP_FDSQRT_RAW 0x05 /* 0x45 & 0x3f */
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/* ── CPU-type guard macros ───────────────────────────────────────────
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* These reference the `info` parameter available at each call site.
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* They early-return from the calling function on type mismatch. */
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#define LIMIT_CPU_TYPES(info, ALLOWED_CPU_TYPES) \
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do { \
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if (!(info->type & ALLOWED_CPU_TYPES)) { \
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d68000_invalid(info); \
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return; \
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} \
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} while (0)
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/* Like LIMIT_CPU_TYPES but also reverses the instruction word consumption,
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* so the invalid instruction produces size=0 (not decoded) instead of size=2.
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* Use for handlers that replace d68000_invalid in the dispatch table. */
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#define LIMIT_CPU_TYPES_UNDECODED(info, ALLOWED_CPU_TYPES) \
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do { \
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if (!(info->type & ALLOWED_CPU_TYPES)) { \
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info->pc -= 2; \
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d68000_invalid(info); \
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return; \
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} \
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} while (0)
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/* Like LIMIT_CPU_TYPES but also rejects CPU32. CPU32 shares TYPE_68020 but
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* lacks some 68020 instructions (CAS, CAS2, CHK.L, PACK, UNPK). */
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#define LIMIT_CPU_TYPES_NOT_CPU32(info, ALLOWED_CPU_TYPES) \
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do { \
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if (!(info->type & (ALLOWED_CPU_TYPES)) || \
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(info->type & TYPE_CPU32)) { \
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d68000_invalid(info); \
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return; \
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} \
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} while (0)
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/* Require CpID == FPU. Rejects all other coprocessor IDs.
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* Used by cpDBcc, cpScc, cpTRAPcc handlers. */
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#define REQUIRE_CPID_FPU(info) \
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do { \
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if (M68K_CPID(info) != M68K_CPID_FPU) { \
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d68000_invalid(info); \
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return; \
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} \
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} while (0)
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/* Require CpID == MMU or CpID == FPU.
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* CpID MMU is rejected on CPU32 (no PMMU). Used by cpSAVE/cpRESTORE. */
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#define REQUIRE_CPID_FPU_OR_PMMU(info) \
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do { \
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int _cpid = M68K_CPID(info); \
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if (_cpid == M68K_CPID_MMU && ((info)->type & TYPE_CPU32)) { \
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d68000_invalid(info); \
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return; \
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} \
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if (_cpid != M68K_CPID_MMU && _cpid != M68K_CPID_FPU) { \
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d68000_invalid(info); \
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return; \
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} \
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} while (0)
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/* ── EA / immediate convenience aliases ─────────────────────────────
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* Shorthand wrappers around the sized get_ea_mode_str / get_imm_str
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* functions. These expand at the call site where 'info' is in scope. */
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/* Fake a split interface */
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#define get_ea_mode_str_8(instruction) get_ea_mode_str(instruction, 0)
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#define get_ea_mode_str_16(instruction) get_ea_mode_str(instruction, 1)
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#define get_ea_mode_str_32(instruction) get_ea_mode_str(instruction, 2)
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#define get_imm_str_s8() get_imm_str_s(0)
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#define get_imm_str_s16() get_imm_str_s(1)
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#define get_imm_str_s32() get_imm_str_s(2)
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#define get_imm_str_u8() get_imm_str_u(0)
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#define get_imm_str_u16() get_imm_str_u(1)
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#define get_imm_str_u32() get_imm_str_u(2)
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/* ── Operand access shorthands ──────────────────────────────────────
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* Quick access to the operand array and instruction size via `info`. */
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#define IOPS(I) (&info->extension.operands[(I)])
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#define ISIZE (info->extension.op_size.cpu_size)
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/* ======================================================================== */
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/* ============================ INTERNAL TYPES ============================ */
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/* ======================================================================== */
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/* Private, For internal use only */
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typedef struct m68k_info {
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const uint8_t *code;
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size_t code_len;
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uint64_t baseAddress;
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MCInst *inst;
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unsigned int pc; /* program counter */
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unsigned int ir; /* instruction register */
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unsigned int type;
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unsigned int address_mask; /* Address mask to simulate address lines */
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cs_m68k extension;
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uint16_t regs_read
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[MAX_IMPL_R_REGS]; // list of implicit registers read by this insn
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uint8_t regs_read_count; // number of implicit registers read by this insn
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uint16_t regs_write
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[MAX_IMPL_W_REGS]; // list of implicit registers modified by this insn
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uint8_t regs_write_count; // number of implicit registers modified by this insn
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uint8_t groups[MAX_NUM_GROUPS];
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uint8_t groups_count;
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} m68k_info;
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bool M68K_getInstruction(csh ud, const uint8_t *code, size_t code_len,
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MCInst *instr, uint16_t *size, uint64_t address,
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void *info);
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#endif
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