27 lines
848 B
C
27 lines
848 B
C
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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RISCV_OP_GROUP_Operand = 0,
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RISCV_OP_GROUP_BranchOperand = 1,
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RISCV_OP_GROUP_VMaskReg = 2,
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RISCV_OP_GROUP_VTypeI = 3,
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RISCV_OP_GROUP_ZeroOffsetMemOp = 4,
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RISCV_OP_GROUP_Rlist = 5,
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RISCV_OP_GROUP_Spimm = 6,
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RISCV_OP_GROUP_CSRSystemRegister = 7,
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RISCV_OP_GROUP_RegReg = 8,
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RISCV_OP_GROUP_FRMArg = 9,
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RISCV_OP_GROUP_FRMArgLegacy = 10,
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RISCV_OP_GROUP_FenceArg = 11,
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RISCV_OP_GROUP_FPImmOperand = 12,
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