Merge commit '802798ce3c8baa4697120580f87bc1ee377306d3' as 'external/capstone'
This commit is contained in:
+143
@@ -0,0 +1,143 @@
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||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
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||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
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//
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||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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||||
//
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||||
//===----------------------------------------------------------------------===//
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//
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||||
// This file contains small standalone enum definitions for the RISC-V target
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// useful for the compiler back-end and the MC libraries.
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//
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||||
//===----------------------------------------------------------------------===//
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||||
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "RISCVBaseInfo.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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typedef struct {
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unsigned value;
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bool isFractional;
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} VLMULDecodeResult;
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VLMULDecodeResult decodeVLMUL(RISCVII_VLMUL VLMUL)
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{
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switch (VLMUL) {
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default:
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CS_ASSERT(0 && "Unexpected LMUL value!");
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break;
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case RISCVII_LMUL_1:
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case RISCVII_LMUL_2:
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case RISCVII_LMUL_4:
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case RISCVII_LMUL_8: {
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VLMULDecodeResult result = { .value = 1 << (unsigned)(VLMUL),
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.isFractional = false };
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return result;
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}
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case RISCVII_LMUL_F2:
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case RISCVII_LMUL_F4:
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case RISCVII_LMUL_F8: {
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VLMULDecodeResult result = { .value = 1 << (8 -
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(unsigned)(VLMUL)),
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.isFractional = true };
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return result;
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}
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}
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VLMULDecodeResult result = { .value = 0, .isFractional = false };
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return result;
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}
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void printVType(unsigned VType, SStream *OS)
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{
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unsigned Sew = RISCVVType_getSEW(VType);
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SStream_concat(OS, "%s", "e");
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printUInt64(OS, Sew);
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unsigned LMul;
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bool Fractional;
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VLMULDecodeResult result = decodeVLMUL(RISCVVType_getVLMUL(VType));
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LMul = result.value;
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Fractional = result.isFractional;
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if (Fractional)
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SStream_concat0(OS, ", mf");
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else
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SStream_concat0(OS, ", m");
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printUInt64(OS, LMul);
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if (RISCVVType_isTailAgnostic(VType))
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SStream_concat0(OS, ", ta");
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else
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SStream_concat0(OS, ", tu");
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if (RISCVVType_isMaskAgnostic(VType))
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SStream_concat0(OS, ", ma");
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else
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SStream_concat0(OS, ", mu");
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}
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typedef struct {
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uint8_t first;
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uint8_t second;
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} LoadFP32ImmArrElement;
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// Lookup table for fli.s for entries 2-31.
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static const LoadFP32ImmArrElement LoadFP32ImmArr[] = {
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{ 0x6f, 0x00 }, { 0x70, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 },
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{ 0x7b, 0x00 }, { 0x7c, 0x00 }, { 0x7d, 0x00 }, { 0x7d, 0x01 },
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{ 0x7d, 0x02 }, { 0x7d, 0x03 }, { 0x7e, 0x00 }, { 0x7e, 0x01 },
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{ 0x7e, 0x02 }, { 0x7e, 0x03 }, { 0x7f, 0x00 }, { 0x7f, 0x01 },
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{ 0x7f, 0x02 }, { 0x7f, 0x03 }, { 0x80, 0x00 }, { 0x80, 0x01 },
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{ 0x80, 0x02 }, { 0x81, 0x00 }, { 0x82, 0x00 }, { 0x83, 0x00 },
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{ 0x86, 0x00 }, { 0x87, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 },
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{ 0xff, 0x00 }, { 0xff, 0x02 },
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};
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||||
float getFPImm(unsigned Imm)
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||||
{
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CS_ASSERT(Imm != 1 && Imm != 30 && Imm != 31 &&
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||||
"Unsupported immediate");
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CS_ASSERT((Imm == 0 || (Imm >= 2 && Imm < 30)) &&
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||||
"Unsupported immediate");
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||||
// Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
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||||
uint32_t Sign = 0;
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if (Imm == 0) {
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Sign = 0x01;
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Imm = 16;
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}
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uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
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uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
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uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
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float result;
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memcpy(&result, &I, sizeof(float));
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return result;
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}
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void RISCVZC_printSpimm(int64_t Spimm, SStream *OS)
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{
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printInt32(OS, Spimm);
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}
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// namespace llvm
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+298
@@ -0,0 +1,298 @@
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||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
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||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains small standalone enum definitions for the RISC-V target
|
||||
// useful for the compiler back-end and the MC libraries.
|
||||
//
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||||
//===----------------------------------------------------------------------===//
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||||
#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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||||
#include <stdio.h>
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||||
#include <string.h>
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||||
#include <stdlib.h>
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||||
#include <capstone/platform.h>
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||||
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||||
#include "../../utils.h"
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||||
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||||
#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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||||
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||||
// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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// CS namespace begin: RISCVII
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// RISC-V Specific Machine Operand Flags
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enum {
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RISCVII_MO_None = 0,
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RISCVII_MO_CALL = 1,
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RISCVII_MO_LO = 3,
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RISCVII_MO_HI = 4,
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RISCVII_MO_PCREL_LO = 5,
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RISCVII_MO_PCREL_HI = 6,
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RISCVII_MO_GOT_HI = 7,
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RISCVII_MO_TPREL_LO = 8,
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RISCVII_MO_TPREL_HI = 9,
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RISCVII_MO_TPREL_ADD = 10,
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RISCVII_MO_TLS_GOT_HI = 11,
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RISCVII_MO_TLS_GD_HI = 12,
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RISCVII_MO_TLSDESC_HI = 13,
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RISCVII_MO_TLSDESC_LOAD_LO = 14,
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RISCVII_MO_TLSDESC_ADD_LO = 15,
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RISCVII_MO_TLSDESC_CALL = 16,
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||||
// Used to differentiate between target-specific "direct" flags and "bitmask"
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// flags. A machine operand can only have one "direct" flag, but can have
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// multiple "bitmask" flags.
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RISCVII_MO_DIRECT_FLAG_MASK = 31
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};
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typedef enum OperandType {
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RISCVOp_OPERAND_FIRST_RISCV_IMM = MCOI_OPERAND_FIRST_TARGET,
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RISCVOp_OPERAND_UIMM1 = RISCVOp_OPERAND_FIRST_RISCV_IMM,
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RISCVOp_OPERAND_UIMM2,
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RISCVOp_OPERAND_UIMM2_LSB0,
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RISCVOp_OPERAND_UIMM3,
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RISCVOp_OPERAND_UIMM4,
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RISCVOp_OPERAND_UIMM5,
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RISCVOp_OPERAND_UIMM6,
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RISCVOp_OPERAND_UIMM7,
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RISCVOp_OPERAND_UIMM7_LSB00,
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RISCVOp_OPERAND_UIMM8_LSB00,
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RISCVOp_OPERAND_UIMM8,
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RISCVOp_OPERAND_UIMM8_LSB000,
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RISCVOp_OPERAND_UIMM8_GE32,
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RISCVOp_OPERAND_UIMM9_LSB000,
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||||
RISCVOp_OPERAND_UIMM10_LSB00_NONZERO,
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RISCVOp_OPERAND_UIMM12,
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RISCVOp_OPERAND_ZERO,
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RISCVOp_OPERAND_SIMM5,
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RISCVOp_OPERAND_SIMM5_PLUS1,
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RISCVOp_OPERAND_SIMM6,
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RISCVOp_OPERAND_SIMM6_NONZERO,
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||||
RISCVOp_OPERAND_SIMM10_LSB0000_NONZERO,
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||||
RISCVOp_OPERAND_SIMM12,
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||||
RISCVOp_OPERAND_SIMM12_LSB00000,
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||||
RISCVOp_OPERAND_UIMM20,
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||||
RISCVOp_OPERAND_UIMMLOG2XLEN,
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RISCVOp_OPERAND_UIMMLOG2XLEN_NONZERO,
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||||
RISCVOp_OPERAND_CLUI_IMM,
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RISCVOp_OPERAND_VTYPEI10,
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RISCVOp_OPERAND_VTYPEI11,
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RISCVOp_OPERAND_RVKRNUM,
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RISCVOp_OPERAND_RVKRNUM_0_7,
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||||
RISCVOp_OPERAND_RVKRNUM_1_10,
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||||
RISCVOp_OPERAND_RVKRNUM_2_14,
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||||
OPERAND_LAST_RISCV_IMM = RISCVOp_OPERAND_RVKRNUM_2_14,
|
||||
// Operand is either a register or uimm5, this is used by V extension pseudo
|
||||
// instructions to represent a value that be passed as AVL to either vsetvli
|
||||
// or vsetivli.
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||||
RISCVOp_OPERAND_AVL,
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} RISCVOp_OperandType;
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||||
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||||
// Describes the predecessor/successor bits used in the FENCE instruction.
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||||
|
||||
typedef enum FenceField {
|
||||
RISCVFenceField_I = 8,
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RISCVFenceField_O = 4,
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RISCVFenceField_R = 2,
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||||
RISCVFenceField_W = 1
|
||||
} RISCVFenceField_FenceField;
|
||||
|
||||
// Describes the supported floating point rounding mode encodings.
|
||||
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typedef enum RoundingMode {
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RISCVFPRndMode_RNE = 0,
|
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RISCVFPRndMode_RTZ = 1,
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RISCVFPRndMode_RDN = 2,
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RISCVFPRndMode_RUP = 3,
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RISCVFPRndMode_RMM = 4,
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RISCVFPRndMode_DYN = 7,
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RISCVFPRndMode_Invalid
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} RISCVFPRndMode_RoundingMode;
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inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode)
|
||||
{
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||||
switch (Mode) {
|
||||
default:
|
||||
return false;
|
||||
case RISCVFPRndMode_RNE:
|
||||
case RISCVFPRndMode_RTZ:
|
||||
case RISCVFPRndMode_RDN:
|
||||
case RISCVFPRndMode_RUP:
|
||||
case RISCVFPRndMode_RMM:
|
||||
case RISCVFPRndMode_DYN:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
inline static const char *RISCVFPRndMode_roundingModeToString(unsigned RndMode)
|
||||
{
|
||||
switch (RndMode) {
|
||||
default:
|
||||
CS_ASSERT(0 && "Unknown floating point rounding mode");
|
||||
case RISCVFPRndMode_RNE:
|
||||
return "rne";
|
||||
case RISCVFPRndMode_RTZ:
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||||
return "rtz";
|
||||
case RISCVFPRndMode_RDN:
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||||
return "rdn";
|
||||
case RISCVFPRndMode_RUP:
|
||||
return "rup";
|
||||
case RISCVFPRndMode_RMM:
|
||||
return "rmm";
|
||||
case RISCVFPRndMode_DYN:
|
||||
return "dyn";
|
||||
}
|
||||
}
|
||||
|
||||
inline static bool RISCVVType_isTailAgnostic(unsigned VType)
|
||||
{
|
||||
return VType & 0x40;
|
||||
}
|
||||
|
||||
inline static bool RISCVVType_isMaskAgnostic(unsigned VType)
|
||||
{
|
||||
return VType & 0x80;
|
||||
}
|
||||
|
||||
typedef enum RLISTENCODE {
|
||||
RISCVZC_RLISTENCODE_RA = 4,
|
||||
RISCVZC_RLISTENCODE_RA_S0,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S1,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S2,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S3,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S4,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S5,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S6,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S7,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S8,
|
||||
RISCVZC_RLISTENCODE_RA_S0_S9,
|
||||
// note - to include s10, s11 must also be included
|
||||
RISCVZC_RLISTENCODE_RA_S0_S11,
|
||||
RISCVZC_RLISTENCODE_INVALID_RLIST,
|
||||
} RISCVZC_RLISTENCODE;
|
||||
|
||||
inline static unsigned RISCVZC_getStackAdjBase(unsigned RlistVal, bool IsRV64,
|
||||
bool IsEABI)
|
||||
{
|
||||
CS_ASSERT(RlistVal != RISCVZC_RLISTENCODE_INVALID_RLIST &&
|
||||
"{ra, s0-s10} is not supported, s11 must be included.");
|
||||
if (IsEABI)
|
||||
return 16;
|
||||
if (!IsRV64) {
|
||||
switch (RlistVal) {
|
||||
case RISCVZC_RLISTENCODE_RA:
|
||||
case RISCVZC_RLISTENCODE_RA_S0:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S1:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S2:
|
||||
return 16;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S3:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S4:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S5:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S6:
|
||||
return 32;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S7:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S8:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S9:
|
||||
return 48;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S11:
|
||||
return 64;
|
||||
}
|
||||
} else {
|
||||
switch (RlistVal) {
|
||||
case RISCVZC_RLISTENCODE_RA:
|
||||
case RISCVZC_RLISTENCODE_RA_S0:
|
||||
return 16;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S1:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S2:
|
||||
return 32;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S3:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S4:
|
||||
return 48;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S5:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S6:
|
||||
return 64;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S7:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S8:
|
||||
return 80;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S9:
|
||||
return 96;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S11:
|
||||
return 112;
|
||||
}
|
||||
}
|
||||
CS_ASSERT(0 && "Unexpected RlistVal");
|
||||
return 0; // unreachable
|
||||
}
|
||||
|
||||
typedef enum VLMUL {
|
||||
RISCVII_LMUL_1 = 0,
|
||||
RISCVII_LMUL_2,
|
||||
RISCVII_LMUL_4,
|
||||
RISCVII_LMUL_8,
|
||||
RISCVII_LMUL_RESERVED,
|
||||
RISCVII_LMUL_F8,
|
||||
RISCVII_LMUL_F4,
|
||||
RISCVII_LMUL_F2
|
||||
} RISCVII_VLMUL;
|
||||
|
||||
inline static RISCVII_VLMUL RISCVVType_getVLMUL(unsigned VType)
|
||||
{
|
||||
unsigned VLMUL = VType & 0x7;
|
||||
return (RISCVII_VLMUL)(VLMUL);
|
||||
}
|
||||
|
||||
inline static unsigned RISCVVType_decodeVSEW(unsigned VSEW)
|
||||
{
|
||||
CS_ASSERT(VSEW < 8 && "Unexpected VSEW value");
|
||||
return 1 << (VSEW + 3);
|
||||
}
|
||||
|
||||
inline static unsigned RISCVVType_getSEW(unsigned VType)
|
||||
{
|
||||
unsigned VSEW = (VType >> 3) & 0x7;
|
||||
return RISCVVType_decodeVSEW(VSEW);
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
unsigned raw_val;
|
||||
} RegVal;
|
||||
|
||||
typedef struct SysReg {
|
||||
const char *Name;
|
||||
RegVal val1;
|
||||
const char *AltName;
|
||||
RegVal val2;
|
||||
const char *DeprecatedName;
|
||||
unsigned Encoding;
|
||||
unsigned DummyFeatureArray[1];
|
||||
bool isRV32Only;
|
||||
} RISCV_SysReg;
|
||||
|
||||
void printVType(unsigned VType, SStream *OS);
|
||||
|
||||
float getFPImm(unsigned Imm);
|
||||
|
||||
void RISCVZC_printSpimm(int64_t Spimm, SStream *OS);
|
||||
|
||||
#endif
|
||||
+753
@@ -0,0 +1,753 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file implements the RISCVDisassembler class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <capstone/platform.h>
|
||||
|
||||
#include "../../MCInst.h"
|
||||
#include "../../MathExtras.h"
|
||||
#include "../../MCInstPrinter.h"
|
||||
#include "../../MCDisassembler.h"
|
||||
#include "../../MCFixedLenDisassembler.h"
|
||||
#include "../../cs_priv.h"
|
||||
#include "../../utils.h"
|
||||
#include "RISCVDisassemblerExtension.h"
|
||||
#include "RISCVBaseInfo.h"
|
||||
#include "RISCVMapping.h"
|
||||
|
||||
#define GET_SUBTARGETINFO_ENUM
|
||||
#include "RISCVGenSubtargetInfo.inc"
|
||||
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "RISCVGenRegisterInfo.inc"
|
||||
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "RISCVGenInstrInfo.inc"
|
||||
|
||||
#define CONCAT(a, b) CONCAT_(a, b)
|
||||
#define CONCAT_(a, b) a##_##b
|
||||
|
||||
#define DEBUG_TYPE "riscv-disassembler"
|
||||
|
||||
DecodeStatus RISCV_getInstruction(MCInst *Instr, uint16_t *Size,
|
||||
const uint8_t *Bytes, size_t BytesLen,
|
||||
uint64_t Address, SStream *CStream);
|
||||
void addSPOperands(MCInst *MI);
|
||||
;
|
||||
// end anonymous namespace
|
||||
|
||||
static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
bool IsRVE = RISCV_getFeatureBits(Inst->csh->mode, RISCV_FeatureRVE);
|
||||
|
||||
if (RegNo >= 32 || (IsRVE && RegNo >= 16))
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = RISCV_X0 + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
MCRegister Reg = RISCV_X0 + RegNo;
|
||||
if (Reg != RISCV_X1 && Reg != RISCV_X5)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = RISCV_F0_H + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = RISCV_F0_F + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 8) {
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
MCRegister Reg = RISCV_F8_F + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = RISCV_F0_D + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 8) {
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
MCRegister Reg = RISCV_F8_D + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo == 0) {
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
|
||||
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo,
|
||||
uint32_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo == 2) {
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
|
||||
return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 8)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = RISCV_X8 + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32 || RegNo & 1)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = RISCV_X0 + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSR07RegisterClass(MCInst *Inst, uint64_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 8)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV_X8) :
|
||||
(RegNo - 2 + RISCV_X18);
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVRRegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = RISCV_V0 + RegNo;
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVRM2RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32 || RegNo % 2)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = MCRegisterInfo_getMatchingSuperReg(
|
||||
Inst->MRI, RISCV_V0 + RegNo, RISCV_sub_vrm1_0,
|
||||
MCRegisterInfo_getRegClass(Inst->MRI, RISCV_VRM2RegClassID));
|
||||
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVRM4RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32 || RegNo % 4)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = MCRegisterInfo_getMatchingSuperReg(
|
||||
Inst->MRI, RISCV_V0 + RegNo, RISCV_sub_vrm1_0,
|
||||
MCRegisterInfo_getRegClass(Inst->MRI, RISCV_VRM4RegClassID));
|
||||
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVRM8RegisterClass(MCInst *Inst, uint32_t RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo >= 32 || RegNo % 8)
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCRegister Reg = MCRegisterInfo_getMatchingSuperReg(
|
||||
Inst->MRI, RISCV_V0 + RegNo, RISCV_sub_vrm1_0,
|
||||
MCRegisterInfo_getRegClass(Inst->MRI, RISCV_VRM8RegClassID));
|
||||
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeVMaskReg(MCInst *Inst, uint64_t RegNo,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
if (RegNo > 2) {
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
MCRegister Reg = (RegNo == 0) ? RISCV_V0 : RISCV_NoRegister;
|
||||
|
||||
MCOperand_CreateReg0(Inst, (Reg));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
#define DEFINE_decodeUImmOperand(N) \
|
||||
static DecodeStatus CONCAT(decodeUImmOperand, \
|
||||
N)(MCInst * Inst, uint32_t Imm, \
|
||||
int64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
CS_ASSERT(isUIntN(N, Imm) && "Invalid immediate"); \
|
||||
MCOperand_CreateImm0(Inst, (Imm)); \
|
||||
return MCDisassembler_Success; \
|
||||
}
|
||||
DEFINE_decodeUImmOperand(6);
|
||||
DEFINE_decodeUImmOperand(2);
|
||||
DEFINE_decodeUImmOperand(8);
|
||||
DEFINE_decodeUImmOperand(9);
|
||||
DEFINE_decodeUImmOperand(7);
|
||||
DEFINE_decodeUImmOperand(4);
|
||||
DEFINE_decodeUImmOperand(20);
|
||||
DEFINE_decodeUImmOperand(5);
|
||||
DEFINE_decodeUImmOperand(11);
|
||||
DEFINE_decodeUImmOperand(10);
|
||||
DEFINE_decodeUImmOperand(12);
|
||||
DEFINE_decodeUImmOperand(3);
|
||||
DEFINE_decodeUImmOperand(1);
|
||||
|
||||
#define DEFINE_decodeUImmNonZeroOperand(N) \
|
||||
static DecodeStatus CONCAT(decodeUImmNonZeroOperand, \
|
||||
N)(MCInst * Inst, uint32_t Imm, \
|
||||
int64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
if (Imm == 0) \
|
||||
return MCDisassembler_Fail; \
|
||||
return CONCAT(decodeUImmOperand, N)(Inst, Imm, Address, \
|
||||
Decoder); \
|
||||
}
|
||||
DEFINE_decodeUImmNonZeroOperand(10);
|
||||
|
||||
#define DEFINE_decodeSImmOperand(N) \
|
||||
static DecodeStatus CONCAT(decodeSImmOperand, \
|
||||
N)(MCInst * Inst, uint32_t Imm, \
|
||||
int64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
CS_ASSERT(isUIntN(N, Imm) && "Invalid immediate"); \
|
||||
\
|
||||
MCOperand_CreateImm0(Inst, (SignExtend64((Imm), N))); \
|
||||
return MCDisassembler_Success; \
|
||||
}
|
||||
DEFINE_decodeSImmOperand(6);
|
||||
DEFINE_decodeSImmOperand(12);
|
||||
DEFINE_decodeSImmOperand(5);
|
||||
DEFINE_decodeSImmOperand(10);
|
||||
|
||||
#define DEFINE_decodeSImmNonZeroOperand(N) \
|
||||
static DecodeStatus CONCAT(decodeSImmNonZeroOperand, \
|
||||
N)(MCInst * Inst, uint32_t Imm, \
|
||||
int64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
if (Imm == 0) \
|
||||
return MCDisassembler_Fail; \
|
||||
return CONCAT(decodeSImmOperand, N)(Inst, Imm, Address, \
|
||||
Decoder); \
|
||||
}
|
||||
DEFINE_decodeSImmNonZeroOperand(6);
|
||||
DEFINE_decodeSImmNonZeroOperand(10);
|
||||
|
||||
#define DEFINE_decodeSImmOperandAndLsl1(N) \
|
||||
static DecodeStatus CONCAT(decodeSImmOperandAndLsl1, \
|
||||
N)(MCInst * Inst, uint32_t Imm, \
|
||||
int64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
CS_ASSERT(isUIntN(N, Imm) && "Invalid immediate"); \
|
||||
\
|
||||
MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 1), N))); \
|
||||
return MCDisassembler_Success; \
|
||||
}
|
||||
DEFINE_decodeSImmOperandAndLsl1(12);
|
||||
DEFINE_decodeSImmOperandAndLsl1(9);
|
||||
DEFINE_decodeSImmOperandAndLsl1(13);
|
||||
DEFINE_decodeSImmOperandAndLsl1(21);
|
||||
|
||||
static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint32_t Imm,
|
||||
int64_t Address, const void *Decoder)
|
||||
{
|
||||
CS_ASSERT(isUIntN(6, Imm) && "Invalid immediate");
|
||||
if (Imm > 31) {
|
||||
Imm = (SignExtend64((Imm), 6) & 0xfffff);
|
||||
}
|
||||
MCOperand_CreateImm0(Inst, (Imm));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeFRMArg(MCInst *Inst, uint32_t Imm, int64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
CS_ASSERT(isUIntN(3, Imm) && "Invalid immediate");
|
||||
if (!RISCVFPRndMode_isValidRoundingMode(Imm))
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCOperand_CreateImm0(Inst, (Imm));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdSImm(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs2(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeXTHeadMemPair(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeZcmpRlist(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeRegReg(MCInst *Inst, uint32_t Insn, uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeZcmpSpimm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeCSSPushPopchk(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus decodeUImmLog2XLenOperand(MCInst *Inst, uint32_t Imm,
|
||||
int64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
CS_ASSERT(isUIntN(6, Imm) && "Invalid immediate");
|
||||
|
||||
if (!RISCV_getFeatureBits(Inst->csh->mode, RISCV_Feature64Bit) &&
|
||||
!isUIntN(5, Imm))
|
||||
return MCDisassembler_Fail;
|
||||
|
||||
MCOperand_CreateImm0(Inst, (Imm));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst *Inst, uint32_t Imm,
|
||||
int64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
if (Imm == 0)
|
||||
return MCDisassembler_Fail;
|
||||
return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
|
||||
}
|
||||
|
||||
#include "RISCVGenDisassemblerTables.inc"
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
uint32_t Rd = fieldFromInstruction_4(Insn, 7, 5);
|
||||
DecodeStatus Result =
|
||||
DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
|
||||
(void)Result;
|
||||
CS_ASSERT(Result == MCDisassembler_Success && "Invalid register");
|
||||
MCInst_addOperand2(Inst, (MCInst_getOperand(Inst, (0))));
|
||||
MCOperand_CreateImm0(Inst, (0));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeCSSPushPopchk(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
uint32_t Rs1 = fieldFromInstruction_4(Insn, 7, 5);
|
||||
DecodeStatus Result =
|
||||
DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
|
||||
(void)Result;
|
||||
CS_ASSERT(Result == MCDisassembler_Success && "Invalid register");
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdSImm(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
MCOperand_CreateReg0(Inst, (RISCV_X0));
|
||||
uint32_t SImm6 = fieldFromInstruction_4(Insn, 12, 1) << 5 |
|
||||
fieldFromInstruction_4(Insn, 2, 5);
|
||||
DecodeStatus Result =
|
||||
CONCAT(decodeSImmOperand, 6)(Inst, SImm6, Address, Decoder);
|
||||
(void)Result;
|
||||
CS_ASSERT(Result == MCDisassembler_Success && "Invalid immediate");
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
MCOperand_CreateReg0(Inst, (RISCV_X0));
|
||||
MCInst_addOperand2(Inst, (MCInst_getOperand(Inst, (0))));
|
||||
uint32_t UImm6 = fieldFromInstruction_4(Insn, 12, 1) << 5 |
|
||||
fieldFromInstruction_4(Insn, 2, 5);
|
||||
DecodeStatus Result =
|
||||
CONCAT(decodeUImmOperand, 6)(Inst, UImm6, Address, Decoder);
|
||||
(void)Result;
|
||||
CS_ASSERT(Result == MCDisassembler_Success && "Invalid immediate");
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs2(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
uint32_t Rd = fieldFromInstruction_4(Insn, 7, 5);
|
||||
uint32_t Rs2 = fieldFromInstruction_4(Insn, 2, 5);
|
||||
DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
|
||||
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
uint32_t Rd = fieldFromInstruction_4(Insn, 7, 5);
|
||||
uint32_t Rs2 = fieldFromInstruction_4(Insn, 2, 5);
|
||||
DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
|
||||
MCInst_addOperand2(Inst, (MCInst_getOperand(Inst, (0))));
|
||||
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeXTHeadMemPair(MCInst *Inst, uint32_t Insn,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
uint32_t Rd1 = fieldFromInstruction_4(Insn, 7, 5);
|
||||
uint32_t Rs1 = fieldFromInstruction_4(Insn, 15, 5);
|
||||
uint32_t Rd2 = fieldFromInstruction_4(Insn, 20, 5);
|
||||
uint32_t UImm2 = fieldFromInstruction_4(Insn, 25, 2);
|
||||
DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
|
||||
DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
|
||||
DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
|
||||
DecodeStatus Result =
|
||||
CONCAT(decodeUImmOperand, 2)(Inst, UImm2, Address, Decoder);
|
||||
(void)Result;
|
||||
CS_ASSERT(Result == MCDisassembler_Success && "Invalid immediate");
|
||||
|
||||
// Disassemble the final operand which is implicit.
|
||||
unsigned Opcode = MCInst_getOpcode(Inst);
|
||||
bool IsWordOp = (Opcode == RISCV_TH_LWD || Opcode == RISCV_TH_LWUD ||
|
||||
Opcode == RISCV_TH_SWD);
|
||||
if (IsWordOp)
|
||||
MCOperand_CreateImm0(Inst, (3));
|
||||
else
|
||||
MCOperand_CreateImm0(Inst, (4));
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeZcmpRlist(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
if (Imm <= 3)
|
||||
return MCDisassembler_Fail;
|
||||
MCOperand_CreateImm0(Inst, (Imm));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeRegReg(MCInst *Inst, uint32_t Insn, uint64_t Address,
|
||||
const void *Decoder)
|
||||
{
|
||||
uint32_t Rs1 = fieldFromInstruction_4(Insn, 0, 5);
|
||||
uint32_t Rs2 = fieldFromInstruction_4(Insn, 5, 5);
|
||||
DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
|
||||
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus decodeZcmpSpimm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, (Imm));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
// Add implied SP operand for C.*SP compressed instructions. The SP operand
|
||||
// isn't explicitly encoded in the instruction.
|
||||
void addSPOperands(MCInst *MI)
|
||||
{
|
||||
const MCInstrDesc *MCID = MCInstrDesc_get(MCInst_getOpcode(MI),
|
||||
RISCVDescs.Insts,
|
||||
ARR_SIZE(RISCVDescs.Insts));
|
||||
MCOperand SPReg;
|
||||
SPReg.MachineOperandType = kRegister;
|
||||
SPReg.Kind = kRegister;
|
||||
SPReg.RegVal = RISCV_X2;
|
||||
for (unsigned i = 0; i < MCID->NumOperands; i++)
|
||||
if (MCID->OpInfo[i].RegClass == RISCV_SPRegClassID)
|
||||
MCInst_insert0(MI, i, &SPReg);
|
||||
}
|
||||
|
||||
DecodeStatus RISCV_getInstruction(MCInst *MI, uint16_t *Size,
|
||||
const uint8_t *Bytes, size_t BytesLen,
|
||||
uint64_t Address, SStream *CS)
|
||||
{
|
||||
// TODO: This will need modification when supporting instruction set
|
||||
// extensions with instructions > 32-bits (up to 176 bits wide).
|
||||
uint32_t Insn;
|
||||
DecodeStatus Result;
|
||||
|
||||
#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION( \
|
||||
width, FEATURE_CHECKS, DECODER_TABLE, DESC, ADDITIONAL_OPERATION) \
|
||||
do { \
|
||||
if (FEATURE_CHECKS) { \
|
||||
Result = decodeInstruction_##width( \
|
||||
DECODER_TABLE, MI, Insn, Address, NULL); \
|
||||
if (Result != MCDisassembler_Fail) { \
|
||||
ADDITIONAL_OPERATION; \
|
||||
return Result; \
|
||||
} \
|
||||
} \
|
||||
} while (false)
|
||||
#define TRY_TO_DECODE_AND_ADD_SP(width, FEATURE_CHECKS, DECODER_TABLE, DESC) \
|
||||
TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION( \
|
||||
width, FEATURE_CHECKS, DECODER_TABLE, DESC, addSPOperands(MI))
|
||||
#define TRY_TO_DECODE(width, FEATURE_CHECKS, DECODER_TABLE, DESC) \
|
||||
TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION( \
|
||||
width, FEATURE_CHECKS, DECODER_TABLE, DESC, (void)NULL)
|
||||
#define TRY_TO_DECODE_FEATURE(width, FEATURE, DECODER_TABLE, DESC) \
|
||||
TRY_TO_DECODE(width, RISCV_getFeatureBits(MI->csh->mode, FEATURE), \
|
||||
DECODER_TABLE, DESC)
|
||||
|
||||
// It's a 32 bit instruction if bit 0 and 1 are 1.
|
||||
if ((Bytes[0] & 0x3) == 0x3) {
|
||||
if (BytesLen < 4) {
|
||||
*Size = 0;
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
*Size = 4;
|
||||
|
||||
Insn = readBytes32(MI, Bytes);
|
||||
|
||||
TRY_TO_DECODE(4,
|
||||
RISCV_getFeatureBits(MI->csh->mode,
|
||||
RISCV_FeatureStdExtZdinx) &&
|
||||
!RISCV_getFeatureBits(MI->csh->mode,
|
||||
RISCV_Feature64Bit),
|
||||
DecoderTableRV32Zdinx32,
|
||||
"RV32Zdinx table (Double in Integer and rv32)");
|
||||
TRY_TO_DECODE(4,
|
||||
RISCV_getFeatureBits(MI->csh->mode,
|
||||
RISCV_FeatureStdExtZacas) &&
|
||||
!RISCV_getFeatureBits(MI->csh->mode,
|
||||
RISCV_Feature64Bit),
|
||||
DecoderTableRV32Zacas32,
|
||||
"RV32Zacas table (Compare-And-Swap and rv32)");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureStdExtZfinx,
|
||||
DecoderTableRVZfinx32,
|
||||
"RVZfinx table (Float in Integer)");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXVentanaCondOps,
|
||||
DecoderTableXVentana32,
|
||||
"Ventana custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadBa,
|
||||
DecoderTableXTHeadBa32,
|
||||
"XTHeadBa custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadBb,
|
||||
DecoderTableXTHeadBb32,
|
||||
"XTHeadBb custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadBs,
|
||||
DecoderTableXTHeadBs32,
|
||||
"XTHeadBs custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadCondMov,
|
||||
DecoderTableXTHeadCondMov32,
|
||||
"XTHeadCondMov custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadCmo,
|
||||
DecoderTableXTHeadCmo32,
|
||||
"XTHeadCmo custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadFMemIdx,
|
||||
DecoderTableXTHeadFMemIdx32,
|
||||
"XTHeadFMemIdx custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadMac,
|
||||
DecoderTableXTHeadMac32,
|
||||
"XTHeadMac custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadMemIdx,
|
||||
DecoderTableXTHeadMemIdx32,
|
||||
"XTHeadMemIdx custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadMemPair,
|
||||
DecoderTableXTHeadMemPair32,
|
||||
"XTHeadMemPair custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadSync,
|
||||
DecoderTableXTHeadSync32,
|
||||
"XTHeadSync custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadVdot,
|
||||
DecoderTableXTHeadVdot32,
|
||||
"XTHeadVdot custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXSfvcp,
|
||||
DecoderTableXSfvcp32,
|
||||
"SiFive VCIX custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
4, RISCV_FeatureVendorXSfvqmaccdod,
|
||||
DecoderTableXSfvqmaccdod32,
|
||||
"SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
4, RISCV_FeatureVendorXSfvqmaccqoq,
|
||||
DecoderTableXSfvqmaccqoq32,
|
||||
"SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
4, RISCV_FeatureVendorXSfvfwmaccqqq,
|
||||
DecoderTableXSfvfwmaccqqq32,
|
||||
"SiFive Matrix Multiplication Instruction opcode table");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
4, RISCV_FeatureVendorXSfvfnrclipxfqf,
|
||||
DecoderTableXSfvfnrclipxfqf32,
|
||||
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
4, RISCV_FeatureVendorXCVbitmanip,
|
||||
DecoderTableXCVbitmanip32,
|
||||
"CORE-V Bit Manipulation custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCVelw,
|
||||
DecoderTableXCVelw32,
|
||||
"CORE-V Event load custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCVmac,
|
||||
DecoderTableXCVmac32,
|
||||
"CORE-V MAC custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCVmem,
|
||||
DecoderTableXCVmem32,
|
||||
"CORE-V MEM custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCValu,
|
||||
DecoderTableXCValu32,
|
||||
"CORE-V ALU custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
4, RISCV_FeatureVendorXCVsimd, DecoderTableXCVsimd32,
|
||||
"CORE-V SIMD extensions custom opcode table");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
4, RISCV_FeatureVendorXCVbi, DecoderTableXCVbi32,
|
||||
"CORE-V Immediate Branching custom opcode table");
|
||||
TRY_TO_DECODE(4, true, DecoderTable32, "RISCV32 table");
|
||||
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
|
||||
if (BytesLen < 2) {
|
||||
*Size = 0;
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
*Size = 2;
|
||||
|
||||
Insn = readBytes16(MI, Bytes);
|
||||
TRY_TO_DECODE_AND_ADD_SP(
|
||||
2, !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit),
|
||||
DecoderTableRISCV32Only_16,
|
||||
"RISCV32Only_16 table (16-bit Instruction)");
|
||||
TRY_TO_DECODE_FEATURE(2, RISCV_FeatureStdExtZicfiss,
|
||||
DecoderTableZicfiss16,
|
||||
"RVZicfiss table (Shadow Stack)");
|
||||
TRY_TO_DECODE_FEATURE(2, RISCV_FeatureStdExtZcmt, DecoderTableRVZcmt16,
|
||||
"Zcmt table (16-bit Table Jump Instructions)");
|
||||
TRY_TO_DECODE_FEATURE(
|
||||
2, RISCV_FeatureStdExtZcmp, DecoderTableRVZcmp16,
|
||||
"Zcmp table (16-bit Push/Pop & Double Move Instructions)");
|
||||
TRY_TO_DECODE_AND_ADD_SP(2, true, DecoderTable16,
|
||||
"RISCV_C table (16-bit Instruction)");
|
||||
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
|
||||
bool RISCV_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
|
||||
MCInst *MI, uint16_t *Size, uint64_t Address,
|
||||
void *Info)
|
||||
{
|
||||
RISCV_init_cs_detail(MI);
|
||||
MI->MRI = (MCRegisterInfo *)Info;
|
||||
return RISCV_getInstruction(MI, Size, Bytes, ByteLen, Address, NULL) !=
|
||||
MCDisassembler_Fail;
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
|
||||
Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
|
||||
|
||||
#ifndef CS_RISCVDISASSEMBLER_H
|
||||
#define CS_RISCVDISASSEMBLER_H
|
||||
|
||||
#include "../../include/capstone/capstone.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "../../MCInst.h"
|
||||
|
||||
void RISCV_init(MCRegisterInfo *MRI);
|
||||
|
||||
bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len,
|
||||
MCInst *instr, uint16_t *size, uint64_t address,
|
||||
void *info);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,90 @@
|
||||
#include "RISCVDisassemblerExtension.h"
|
||||
|
||||
#define GET_SUBTARGETINFO_ENUM
|
||||
#include "RISCVGenSubtargetInfo.inc"
|
||||
|
||||
bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature)
|
||||
{
|
||||
if (feature == RISCV_FeatureNoRVCHints) {
|
||||
return false;
|
||||
}
|
||||
|
||||
switch (feature) {
|
||||
case RISCV_Feature32Bit:
|
||||
return mode & CS_MODE_RISCV32;
|
||||
|
||||
case RISCV_Feature64Bit:
|
||||
return mode & CS_MODE_RISCV64;
|
||||
|
||||
case RISCV_FeatureStdExtF:
|
||||
case RISCV_FeatureStdExtD:
|
||||
return mode & CS_MODE_RISCV_FD;
|
||||
|
||||
case RISCV_FeatureStdExtV:
|
||||
return mode & CS_MODE_RISCV_V;
|
||||
|
||||
case RISCV_FeatureStdExtZfinx:
|
||||
case RISCV_FeatureStdExtZdinx:
|
||||
case RISCV_FeatureStdExtZhinx:
|
||||
case RISCV_FeatureStdExtZhinxmin:
|
||||
return mode & CS_MODE_RISCV_ZFINX;
|
||||
|
||||
case RISCV_FeatureStdExtC:
|
||||
return mode & CS_MODE_RISCV_C;
|
||||
|
||||
case RISCV_FeatureStdExtZcmp:
|
||||
case RISCV_FeatureStdExtZcmt:
|
||||
case RISCV_FeatureStdExtZce:
|
||||
return mode & CS_MODE_RISCV_ZCMP_ZCMT_ZCE;
|
||||
|
||||
case RISCV_FeatureStdExtZicfiss:
|
||||
return mode & CS_MODE_RISCV_ZICFISS;
|
||||
|
||||
case RISCV_FeatureRVE:
|
||||
return mode & CS_MODE_RISCV_E;
|
||||
|
||||
case RISCV_FeatureStdExtA:
|
||||
return mode & CS_MODE_RISCV_A;
|
||||
|
||||
case RISCV_FeatureVendorXCVelw:
|
||||
return mode & CS_MODE_RISCV_COREV;
|
||||
|
||||
case RISCV_FeatureVendorXSfvcp:
|
||||
case RISCV_FeatureVendorXSfvfnrclipxfqf:
|
||||
case RISCV_FeatureVendorXSfvfwmaccqqq:
|
||||
case RISCV_FeatureVendorXSfvqmaccdod:
|
||||
case RISCV_FeatureVendorXSfvqmaccqoq:
|
||||
return mode & CS_MODE_RISCV_SIFIVE;
|
||||
|
||||
case RISCV_FeatureVendorXTHeadBa:
|
||||
case RISCV_FeatureVendorXTHeadBb:
|
||||
case RISCV_FeatureVendorXTHeadBs:
|
||||
case RISCV_FeatureVendorXTHeadCmo:
|
||||
case RISCV_FeatureVendorXTHeadCondMov:
|
||||
case RISCV_FeatureVendorXTHeadFMemIdx:
|
||||
case RISCV_FeatureVendorXTHeadMac:
|
||||
case RISCV_FeatureVendorXTHeadMemIdx:
|
||||
case RISCV_FeatureVendorXTHeadMemPair:
|
||||
case RISCV_FeatureVendorXTHeadSync:
|
||||
case RISCV_FeatureVendorXTHeadVdot:
|
||||
return mode & CS_MODE_RISCV_THEAD;
|
||||
|
||||
case RISCV_FeatureStdExtZba:
|
||||
return mode & CS_MODE_RISCV_ZBA;
|
||||
case RISCV_FeatureStdExtZbb:
|
||||
return mode & CS_MODE_RISCV_ZBB;
|
||||
case RISCV_FeatureStdExtZbc:
|
||||
return mode & CS_MODE_RISCV_ZBC;
|
||||
case RISCV_FeatureStdExtZbkb:
|
||||
return mode & CS_MODE_RISCV_ZBKB;
|
||||
case RISCV_FeatureStdExtZbkc:
|
||||
return mode & CS_MODE_RISCV_ZBKC;
|
||||
case RISCV_FeatureStdExtZbkx:
|
||||
return mode & CS_MODE_RISCV_ZBKX;
|
||||
case RISCV_FeatureStdExtZbs:
|
||||
return mode & CS_MODE_RISCV_ZBS;
|
||||
default:
|
||||
// support everything by default
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,8 @@
|
||||
#ifndef CS_RISCV_DISASSEMBLER_EXTENSION_H
|
||||
#define CS_RISCV_DISASSEMBLER_EXTENSION_H
|
||||
|
||||
#include "../../cs_priv.h"
|
||||
|
||||
bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature);
|
||||
|
||||
#endif // CS_RISCV_DISASSEMBLER_EXTENSION_H
|
||||
+29572
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,99 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
RISCV_INS_ALIAS_NOP, // Real instr.: RISCV_ADDI
|
||||
RISCV_INS_ALIAS_LI, // Real instr.: RISCV_ADDI
|
||||
RISCV_INS_ALIAS_MV, // Real instr.: RISCV_ADDI
|
||||
RISCV_INS_ALIAS_NOT, // Real instr.: RISCV_XORI
|
||||
RISCV_INS_ALIAS_NEG, // Real instr.: RISCV_SUB
|
||||
RISCV_INS_ALIAS_NEGW, // Real instr.: RISCV_SUBW
|
||||
RISCV_INS_ALIAS_SEXT_W, // Real instr.: RISCV_ADDIW
|
||||
RISCV_INS_ALIAS_SEQZ, // Real instr.: RISCV_SLTIU
|
||||
RISCV_INS_ALIAS_SNEZ, // Real instr.: RISCV_SLTU
|
||||
RISCV_INS_ALIAS_SLTZ, // Real instr.: RISCV_SLT
|
||||
RISCV_INS_ALIAS_SGTZ, // Real instr.: RISCV_SLT
|
||||
RISCV_INS_ALIAS_BEQZ, // Real instr.: RISCV_BEQ
|
||||
RISCV_INS_ALIAS_BNEZ, // Real instr.: RISCV_BNE
|
||||
RISCV_INS_ALIAS_BLEZ, // Real instr.: RISCV_BGE
|
||||
RISCV_INS_ALIAS_BGEZ, // Real instr.: RISCV_BGE
|
||||
RISCV_INS_ALIAS_BLTZ, // Real instr.: RISCV_BLT
|
||||
RISCV_INS_ALIAS_BGTZ, // Real instr.: RISCV_BLT
|
||||
RISCV_INS_ALIAS_J, // Real instr.: RISCV_JAL
|
||||
RISCV_INS_ALIAS_JAL, // Real instr.: RISCV_JAL
|
||||
RISCV_INS_ALIAS_JR, // Real instr.: RISCV_JALR
|
||||
RISCV_INS_ALIAS_JALR, // Real instr.: RISCV_JALR
|
||||
RISCV_INS_ALIAS_RET, // Real instr.: RISCV_JALR
|
||||
RISCV_INS_ALIAS_FENCE, // Real instr.: RISCV_FENCE
|
||||
RISCV_INS_ALIAS_PAUSE, // Real instr.: RISCV_FENCE
|
||||
RISCV_INS_ALIAS_RDINSTRET, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_RDCYCLE, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_RDTIME, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_RDINSTRETH, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_RDCYCLEH, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_RDTIMEH, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_CSRR, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_CSRW, // Real instr.: RISCV_CSRRW
|
||||
RISCV_INS_ALIAS_CSRS, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_CSRC, // Real instr.: RISCV_CSRRC
|
||||
RISCV_INS_ALIAS_CSRWI, // Real instr.: RISCV_CSRRWI
|
||||
RISCV_INS_ALIAS_CSRSI, // Real instr.: RISCV_CSRRSI
|
||||
RISCV_INS_ALIAS_CSRCI, // Real instr.: RISCV_CSRRCI
|
||||
RISCV_INS_ALIAS_SFENCE_VMA, // Real instr.: RISCV_SFENCE_VMA
|
||||
RISCV_INS_ALIAS_HFENCE_GVMA, // Real instr.: RISCV_HFENCE_GVMA
|
||||
RISCV_INS_ALIAS_HFENCE_VVMA, // Real instr.: RISCV_HFENCE_VVMA
|
||||
RISCV_INS_ALIAS_NTL_P1, // Real instr.: RISCV_ADD
|
||||
RISCV_INS_ALIAS_NTL_PALL, // Real instr.: RISCV_ADD
|
||||
RISCV_INS_ALIAS_NTL_S1, // Real instr.: RISCV_ADD
|
||||
RISCV_INS_ALIAS_NTL_ALL, // Real instr.: RISCV_ADD
|
||||
RISCV_INS_ALIAS_LPAD, // Real instr.: RISCV_AUIPC
|
||||
RISCV_INS_ALIAS_FMV_S, // Real instr.: RISCV_FSGNJ_S
|
||||
RISCV_INS_ALIAS_FABS_S, // Real instr.: RISCV_FSGNJX_S
|
||||
RISCV_INS_ALIAS_FNEG_S, // Real instr.: RISCV_FSGNJN_S
|
||||
RISCV_INS_ALIAS_FRCSR, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_FSCSR, // Real instr.: RISCV_CSRRW
|
||||
RISCV_INS_ALIAS_FRRM, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_FSRM, // Real instr.: RISCV_CSRRW
|
||||
RISCV_INS_ALIAS_FSRMI, // Real instr.: RISCV_CSRRWI
|
||||
RISCV_INS_ALIAS_FRFLAGS, // Real instr.: RISCV_CSRRS
|
||||
RISCV_INS_ALIAS_FSFLAGS, // Real instr.: RISCV_CSRRW
|
||||
RISCV_INS_ALIAS_FSFLAGSI, // Real instr.: RISCV_CSRRWI
|
||||
RISCV_INS_ALIAS_FMV_D, // Real instr.: RISCV_FSGNJ_D
|
||||
RISCV_INS_ALIAS_FABS_D, // Real instr.: RISCV_FSGNJX_D
|
||||
RISCV_INS_ALIAS_FNEG_D, // Real instr.: RISCV_FSGNJN_D
|
||||
RISCV_INS_ALIAS_FMV_H, // Real instr.: RISCV_FSGNJ_H
|
||||
RISCV_INS_ALIAS_FABS_H, // Real instr.: RISCV_FSGNJX_H
|
||||
RISCV_INS_ALIAS_FNEG_H, // Real instr.: RISCV_FSGNJN_H
|
||||
RISCV_INS_ALIAS_ZEXT_W, // Real instr.: RISCV_ADD_UW
|
||||
RISCV_INS_ALIAS_VL1R_V, // Real instr.: RISCV_VL1RE8_V
|
||||
RISCV_INS_ALIAS_VL2R_V, // Real instr.: RISCV_VL2RE8_V
|
||||
RISCV_INS_ALIAS_VL4R_V, // Real instr.: RISCV_VL4RE8_V
|
||||
RISCV_INS_ALIAS_VL8R_V, // Real instr.: RISCV_VL8RE8_V
|
||||
RISCV_INS_ALIAS_VNEG_V, // Real instr.: RISCV_VRSUB_VX
|
||||
RISCV_INS_ALIAS_VWCVT_X_X_V, // Real instr.: RISCV_VWADD_VX
|
||||
RISCV_INS_ALIAS_VWCVTU_X_X_V, // Real instr.: RISCV_VWADDU_VX
|
||||
RISCV_INS_ALIAS_VNOT_V, // Real instr.: RISCV_VXOR_VI
|
||||
RISCV_INS_ALIAS_VNCVT_X_X_W, // Real instr.: RISCV_VNSRL_WX
|
||||
RISCV_INS_ALIAS_VFNEG_V, // Real instr.: RISCV_VFSGNJN_VV
|
||||
RISCV_INS_ALIAS_VFABS_V, // Real instr.: RISCV_VFSGNJX_VV
|
||||
RISCV_INS_ALIAS_VMMV_M, // Real instr.: RISCV_VMAND_MM
|
||||
RISCV_INS_ALIAS_VMCLR_M, // Real instr.: RISCV_VMXOR_MM
|
||||
RISCV_INS_ALIAS_VMSET_M, // Real instr.: RISCV_VMXNOR_MM
|
||||
RISCV_INS_ALIAS_VMNOT_M, // Real instr.: RISCV_VMNAND_MM
|
||||
RISCV_INS_ALIAS_C_NTL_P1, // Real instr.: RISCV_C_ADD_HINT
|
||||
RISCV_INS_ALIAS_C_NTL_PALL, // Real instr.: RISCV_C_ADD_HINT
|
||||
RISCV_INS_ALIAS_C_NTL_S1, // Real instr.: RISCV_C_ADD_HINT
|
||||
RISCV_INS_ALIAS_C_NTL_ALL, // Real instr.: RISCV_C_ADD_HINT
|
||||
RISCV_INS_ALIAS_CV_MULS, // Real instr.: RISCV_CV_MULSN
|
||||
RISCV_INS_ALIAS_CV_MULHHS, // Real instr.: RISCV_CV_MULHHSN
|
||||
RISCV_INS_ALIAS_CV_MULU, // Real instr.: RISCV_CV_MULUN
|
||||
RISCV_INS_ALIAS_CV_MULHHU, // Real instr.: RISCV_CV_MULHHUN
|
||||
@@ -0,0 +1,99 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
{ RISCV_INS_ALIAS_NOP, "nop" },
|
||||
{ RISCV_INS_ALIAS_LI, "li" },
|
||||
{ RISCV_INS_ALIAS_MV, "mv" },
|
||||
{ RISCV_INS_ALIAS_NOT, "not" },
|
||||
{ RISCV_INS_ALIAS_NEG, "neg" },
|
||||
{ RISCV_INS_ALIAS_NEGW, "negw" },
|
||||
{ RISCV_INS_ALIAS_SEXT_W, "sext.w" },
|
||||
{ RISCV_INS_ALIAS_SEQZ, "seqz" },
|
||||
{ RISCV_INS_ALIAS_SNEZ, "snez" },
|
||||
{ RISCV_INS_ALIAS_SLTZ, "sltz" },
|
||||
{ RISCV_INS_ALIAS_SGTZ, "sgtz" },
|
||||
{ RISCV_INS_ALIAS_BEQZ, "beqz" },
|
||||
{ RISCV_INS_ALIAS_BNEZ, "bnez" },
|
||||
{ RISCV_INS_ALIAS_BLEZ, "blez" },
|
||||
{ RISCV_INS_ALIAS_BGEZ, "bgez" },
|
||||
{ RISCV_INS_ALIAS_BLTZ, "bltz" },
|
||||
{ RISCV_INS_ALIAS_BGTZ, "bgtz" },
|
||||
{ RISCV_INS_ALIAS_J, "j" },
|
||||
{ RISCV_INS_ALIAS_JAL, "jal" },
|
||||
{ RISCV_INS_ALIAS_JR, "jr" },
|
||||
{ RISCV_INS_ALIAS_JALR, "jalr" },
|
||||
{ RISCV_INS_ALIAS_RET, "ret" },
|
||||
{ RISCV_INS_ALIAS_FENCE, "fence" },
|
||||
{ RISCV_INS_ALIAS_PAUSE, "pause" },
|
||||
{ RISCV_INS_ALIAS_RDINSTRET, "rdinstret" },
|
||||
{ RISCV_INS_ALIAS_RDCYCLE, "rdcycle" },
|
||||
{ RISCV_INS_ALIAS_RDTIME, "rdtime" },
|
||||
{ RISCV_INS_ALIAS_RDINSTRETH, "rdinstreth" },
|
||||
{ RISCV_INS_ALIAS_RDCYCLEH, "rdcycleh" },
|
||||
{ RISCV_INS_ALIAS_RDTIMEH, "rdtimeh" },
|
||||
{ RISCV_INS_ALIAS_CSRR, "csrr" },
|
||||
{ RISCV_INS_ALIAS_CSRW, "csrw" },
|
||||
{ RISCV_INS_ALIAS_CSRS, "csrs" },
|
||||
{ RISCV_INS_ALIAS_CSRC, "csrc" },
|
||||
{ RISCV_INS_ALIAS_CSRWI, "csrwi" },
|
||||
{ RISCV_INS_ALIAS_CSRSI, "csrsi" },
|
||||
{ RISCV_INS_ALIAS_CSRCI, "csrci" },
|
||||
{ RISCV_INS_ALIAS_SFENCE_VMA, "sfence.vma" },
|
||||
{ RISCV_INS_ALIAS_HFENCE_GVMA, "hfence.gvma" },
|
||||
{ RISCV_INS_ALIAS_HFENCE_VVMA, "hfence.vvma" },
|
||||
{ RISCV_INS_ALIAS_NTL_P1, "ntl.p1" },
|
||||
{ RISCV_INS_ALIAS_NTL_PALL, "ntl.pall" },
|
||||
{ RISCV_INS_ALIAS_NTL_S1, "ntl.s1" },
|
||||
{ RISCV_INS_ALIAS_NTL_ALL, "ntl.all" },
|
||||
{ RISCV_INS_ALIAS_LPAD, "lpad" },
|
||||
{ RISCV_INS_ALIAS_FMV_S, "fmv.s" },
|
||||
{ RISCV_INS_ALIAS_FABS_S, "fabs.s" },
|
||||
{ RISCV_INS_ALIAS_FNEG_S, "fneg.s" },
|
||||
{ RISCV_INS_ALIAS_FRCSR, "frcsr" },
|
||||
{ RISCV_INS_ALIAS_FSCSR, "fscsr" },
|
||||
{ RISCV_INS_ALIAS_FRRM, "frrm" },
|
||||
{ RISCV_INS_ALIAS_FSRM, "fsrm" },
|
||||
{ RISCV_INS_ALIAS_FSRMI, "fsrmi" },
|
||||
{ RISCV_INS_ALIAS_FRFLAGS, "frflags" },
|
||||
{ RISCV_INS_ALIAS_FSFLAGS, "fsflags" },
|
||||
{ RISCV_INS_ALIAS_FSFLAGSI, "fsflagsi" },
|
||||
{ RISCV_INS_ALIAS_FMV_D, "fmv.d" },
|
||||
{ RISCV_INS_ALIAS_FABS_D, "fabs.d" },
|
||||
{ RISCV_INS_ALIAS_FNEG_D, "fneg.d" },
|
||||
{ RISCV_INS_ALIAS_FMV_H, "fmv.h" },
|
||||
{ RISCV_INS_ALIAS_FABS_H, "fabs.h" },
|
||||
{ RISCV_INS_ALIAS_FNEG_H, "fneg.h" },
|
||||
{ RISCV_INS_ALIAS_ZEXT_W, "zext.w" },
|
||||
{ RISCV_INS_ALIAS_VL1R_V, "vl1r.v" },
|
||||
{ RISCV_INS_ALIAS_VL2R_V, "vl2r.v" },
|
||||
{ RISCV_INS_ALIAS_VL4R_V, "vl4r.v" },
|
||||
{ RISCV_INS_ALIAS_VL8R_V, "vl8r.v" },
|
||||
{ RISCV_INS_ALIAS_VNEG_V, "vneg.v" },
|
||||
{ RISCV_INS_ALIAS_VWCVT_X_X_V, "vwcvt.x.x.v" },
|
||||
{ RISCV_INS_ALIAS_VWCVTU_X_X_V, "vwcvtu.x.x.v" },
|
||||
{ RISCV_INS_ALIAS_VNOT_V, "vnot.v" },
|
||||
{ RISCV_INS_ALIAS_VNCVT_X_X_W, "vncvt.x.x.w" },
|
||||
{ RISCV_INS_ALIAS_VFNEG_V, "vfneg.v" },
|
||||
{ RISCV_INS_ALIAS_VFABS_V, "vfabs.v" },
|
||||
{ RISCV_INS_ALIAS_VMMV_M, "vmmv.m" },
|
||||
{ RISCV_INS_ALIAS_VMCLR_M, "vmclr.m" },
|
||||
{ RISCV_INS_ALIAS_VMSET_M, "vmset.m" },
|
||||
{ RISCV_INS_ALIAS_VMNOT_M, "vmnot.m" },
|
||||
{ RISCV_INS_ALIAS_C_NTL_P1, "c.ntl.p1" },
|
||||
{ RISCV_INS_ALIAS_C_NTL_PALL, "c.ntl.pall" },
|
||||
{ RISCV_INS_ALIAS_C_NTL_S1, "c.ntl.s1" },
|
||||
{ RISCV_INS_ALIAS_C_NTL_ALL, "c.ntl.all" },
|
||||
{ RISCV_INS_ALIAS_CV_MULS, "cv.muls" },
|
||||
{ RISCV_INS_ALIAS_CV_MULHHS, "cv.mulhhs" },
|
||||
{ RISCV_INS_ALIAS_CV_MULU, "cv.mulu" },
|
||||
{ RISCV_INS_ALIAS_CV_MULHHU, "cv.mulhhu" },
|
||||
@@ -0,0 +1,113 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
RISCV_FEATURE_HASSTDEXTI = 128,
|
||||
RISCV_FEATURE_HASSTDEXTZICBOM,
|
||||
RISCV_FEATURE_HASSTDEXTZICBOP,
|
||||
RISCV_FEATURE_HASSTDEXTZICBOZ,
|
||||
RISCV_FEATURE_HASSTDEXTZICSR,
|
||||
RISCV_FEATURE_HASSTDEXTZICOND,
|
||||
RISCV_FEATURE_HASSTDEXTZIFENCEI,
|
||||
RISCV_FEATURE_HASSTDEXTZIHINTPAUSE,
|
||||
RISCV_FEATURE_HASSTDEXTZIHINTNTL,
|
||||
RISCV_FEATURE_HASSTDEXTZIMOP,
|
||||
RISCV_FEATURE_HASSTDEXTZICFILP,
|
||||
RISCV_FEATURE_HASSTDEXTZICFISS,
|
||||
RISCV_FEATURE_HASSTDEXTM,
|
||||
RISCV_FEATURE_HASSTDEXTMORZMMUL,
|
||||
RISCV_FEATURE_HASSTDEXTA,
|
||||
RISCV_FEATURE_HASSTDEXTZTSO,
|
||||
RISCV_FEATURE_HASSTDEXTZACAS,
|
||||
RISCV_FEATURE_HASSTDEXTZAWRS,
|
||||
RISCV_FEATURE_HASSTDEXTF,
|
||||
RISCV_FEATURE_HASSTDEXTD,
|
||||
RISCV_FEATURE_HASSTDEXTZFHMIN,
|
||||
RISCV_FEATURE_HASSTDEXTZFH,
|
||||
RISCV_FEATURE_HASSTDEXTZFBFMIN,
|
||||
RISCV_FEATURE_HASHALFFPLOADSTOREMOVE,
|
||||
RISCV_FEATURE_HASSTDEXTZFA,
|
||||
RISCV_FEATURE_HASSTDEXTZFINX,
|
||||
RISCV_FEATURE_HASSTDEXTZDINX,
|
||||
RISCV_FEATURE_HASSTDEXTZHINXMIN,
|
||||
RISCV_FEATURE_HASSTDEXTZHINX,
|
||||
RISCV_FEATURE_HASSTDEXTC,
|
||||
RISCV_FEATURE_HASRVCHINTS,
|
||||
RISCV_FEATURE_HASSTDEXTCORZCA,
|
||||
RISCV_FEATURE_HASSTDEXTZCB,
|
||||
RISCV_FEATURE_HASSTDEXTCORZCD,
|
||||
RISCV_FEATURE_HASSTDEXTZCMP,
|
||||
RISCV_FEATURE_HASSTDEXTZCMT,
|
||||
RISCV_FEATURE_HASSTDEXTCORZCFORZCE,
|
||||
RISCV_FEATURE_HASSTDEXTZCMOP,
|
||||
RISCV_FEATURE_HASSTDEXTZBA,
|
||||
RISCV_FEATURE_HASSTDEXTZBB,
|
||||
RISCV_FEATURE_HASSTDEXTZBC,
|
||||
RISCV_FEATURE_HASSTDEXTZBS,
|
||||
RISCV_FEATURE_HASSTDEXTZBKB,
|
||||
RISCV_FEATURE_HASSTDEXTZBKX,
|
||||
RISCV_FEATURE_HASSTDEXTZBBORZBKB,
|
||||
RISCV_FEATURE_HASSTDEXTZBKC,
|
||||
RISCV_FEATURE_HASSTDEXTZBCORZBKC,
|
||||
RISCV_FEATURE_HASSTDEXTZKND,
|
||||
RISCV_FEATURE_HASSTDEXTZKNE,
|
||||
RISCV_FEATURE_HASSTDEXTZKNDORZKNE,
|
||||
RISCV_FEATURE_HASSTDEXTZKNH,
|
||||
RISCV_FEATURE_HASSTDEXTZKSED,
|
||||
RISCV_FEATURE_HASSTDEXTZKSH,
|
||||
RISCV_FEATURE_HASSTDEXTZKR,
|
||||
RISCV_FEATURE_HASSTDEXTZVFBFMIN,
|
||||
RISCV_FEATURE_HASSTDEXTZVFBFWMA,
|
||||
RISCV_FEATURE_HASSTDEXTZFHORZVFH,
|
||||
RISCV_FEATURE_HASSTDEXTZVKB,
|
||||
RISCV_FEATURE_HASSTDEXTZVBB,
|
||||
RISCV_FEATURE_HASSTDEXTZVBC,
|
||||
RISCV_FEATURE_HASSTDEXTZVKG,
|
||||
RISCV_FEATURE_HASSTDEXTZVKNED,
|
||||
RISCV_FEATURE_HASSTDEXTZVKNHA,
|
||||
RISCV_FEATURE_HASSTDEXTZVKNHB,
|
||||
RISCV_FEATURE_HASSTDEXTZVKNHAORZVKNHB,
|
||||
RISCV_FEATURE_HASSTDEXTZVKSED,
|
||||
RISCV_FEATURE_HASSTDEXTZVKSH,
|
||||
RISCV_FEATURE_HASVINSTRUCTIONS,
|
||||
RISCV_FEATURE_HASVINSTRUCTIONSI64,
|
||||
RISCV_FEATURE_HASVINSTRUCTIONSANYF,
|
||||
RISCV_FEATURE_HASVINSTRUCTIONSF16MINIMAL,
|
||||
RISCV_FEATURE_HASSTDEXTH,
|
||||
RISCV_FEATURE_HASSTDEXTSVINVAL,
|
||||
RISCV_FEATURE_HASVENDORXVENTANACONDOPS,
|
||||
RISCV_FEATURE_HASVENDORXTHEADBA,
|
||||
RISCV_FEATURE_HASVENDORXTHEADBB,
|
||||
RISCV_FEATURE_HASVENDORXTHEADBS,
|
||||
RISCV_FEATURE_HASVENDORXTHEADCONDMOV,
|
||||
RISCV_FEATURE_HASVENDORXTHEADCMO,
|
||||
RISCV_FEATURE_HASVENDORXTHEADFMEMIDX,
|
||||
RISCV_FEATURE_HASVENDORXTHEADMAC,
|
||||
RISCV_FEATURE_HASVENDORXTHEADMEMIDX,
|
||||
RISCV_FEATURE_HASVENDORXTHEADMEMPAIR,
|
||||
RISCV_FEATURE_HASVENDORXTHEADSYNC,
|
||||
RISCV_FEATURE_HASVENDORXTHEADVDOT,
|
||||
RISCV_FEATURE_HASVENDORXSFVCP,
|
||||
RISCV_FEATURE_HASVENDORXSFVQMACCDOD,
|
||||
RISCV_FEATURE_HASVENDORXSFVQMACCQOQ,
|
||||
RISCV_FEATURE_HASVENDORXSFVFWMACCQQQ,
|
||||
RISCV_FEATURE_HASVENDORXSFVFNRCLIPXFQF,
|
||||
RISCV_FEATURE_HASVENDORXCVELW,
|
||||
RISCV_FEATURE_HASVENDORXCVBITMANIP,
|
||||
RISCV_FEATURE_HASVENDORXCVMAC,
|
||||
RISCV_FEATURE_HASVENDORXCVMEM,
|
||||
RISCV_FEATURE_HASVENDORXCVALU,
|
||||
RISCV_FEATURE_HASVENDORXCVSIMD,
|
||||
RISCV_FEATURE_HASVENDORXCVBI,
|
||||
RISCV_FEATURE_ISRV64,
|
||||
RISCV_FEATURE_ISRV32,
|
||||
RISCV_FEATURE_ISRVE,
|
||||
@@ -0,0 +1,113 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
{ RISCV_FEATURE_HASSTDEXTI, "HasStdExtI" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZICBOM, "HasStdExtZicbom" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZICBOP, "HasStdExtZicbop" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZICBOZ, "HasStdExtZicboz" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZICSR, "HasStdExtZicsr" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZICOND, "HasStdExtZicond" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZIFENCEI, "HasStdExtZifencei" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZIHINTPAUSE, "HasStdExtZihintpause" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZIHINTNTL, "HasStdExtZihintntl" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZIMOP, "HasStdExtZimop" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZICFILP, "HasStdExtZicfilp" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZICFISS, "HasStdExtZicfiss" },
|
||||
{ RISCV_FEATURE_HASSTDEXTM, "HasStdExtM" },
|
||||
{ RISCV_FEATURE_HASSTDEXTMORZMMUL, "HasStdExtMOrZmmul" },
|
||||
{ RISCV_FEATURE_HASSTDEXTA, "HasStdExtA" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZTSO, "HasStdExtZtso" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZACAS, "HasStdExtZacas" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZAWRS, "HasStdExtZawrs" },
|
||||
{ RISCV_FEATURE_HASSTDEXTF, "HasStdExtF" },
|
||||
{ RISCV_FEATURE_HASSTDEXTD, "HasStdExtD" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZFHMIN, "HasStdExtZfhmin" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZFH, "HasStdExtZfh" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZFBFMIN, "HasStdExtZfbfmin" },
|
||||
{ RISCV_FEATURE_HASHALFFPLOADSTOREMOVE, "HasHalfFPLoadStoreMove" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZFA, "HasStdExtZfa" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZFINX, "HasStdExtZfinx" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZDINX, "HasStdExtZdinx" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZHINXMIN, "HasStdExtZhinxmin" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZHINX, "HasStdExtZhinx" },
|
||||
{ RISCV_FEATURE_HASSTDEXTC, "HasStdExtC" },
|
||||
{ RISCV_FEATURE_HASRVCHINTS, "HasRVCHints" },
|
||||
{ RISCV_FEATURE_HASSTDEXTCORZCA, "HasStdExtCOrZca" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZCB, "HasStdExtZcb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTCORZCD, "HasStdExtCOrZcd" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZCMP, "HasStdExtZcmp" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZCMT, "HasStdExtZcmt" },
|
||||
{ RISCV_FEATURE_HASSTDEXTCORZCFORZCE, "HasStdExtCOrZcfOrZce" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZCMOP, "HasStdExtZcmop" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBA, "HasStdExtZba" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBB, "HasStdExtZbb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBC, "HasStdExtZbc" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBS, "HasStdExtZbs" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBKB, "HasStdExtZbkb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBKX, "HasStdExtZbkx" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBBORZBKB, "HasStdExtZbbOrZbkb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBKC, "HasStdExtZbkc" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZBCORZBKC, "HasStdExtZbcOrZbkc" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZKND, "HasStdExtZknd" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZKNE, "HasStdExtZkne" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZKNDORZKNE, "HasStdExtZkndOrZkne" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZKNH, "HasStdExtZknh" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZKSED, "HasStdExtZksed" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZKSH, "HasStdExtZksh" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZKR, "HasStdExtZkr" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVFBFMIN, "HasStdExtZvfbfmin" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVFBFWMA, "HasStdExtZvfbfwma" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZFHORZVFH, "HasStdExtZfhOrZvfh" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKB, "HasStdExtZvkb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVBB, "HasStdExtZvbb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVBC, "HasStdExtZvbc" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKG, "HasStdExtZvkg" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKNED, "HasStdExtZvkned" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKNHA, "HasStdExtZvknha" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKNHB, "HasStdExtZvknhb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKNHAORZVKNHB, "HasStdExtZvknhaOrZvknhb" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKSED, "HasStdExtZvksed" },
|
||||
{ RISCV_FEATURE_HASSTDEXTZVKSH, "HasStdExtZvksh" },
|
||||
{ RISCV_FEATURE_HASVINSTRUCTIONS, "HasVInstructions" },
|
||||
{ RISCV_FEATURE_HASVINSTRUCTIONSI64, "HasVInstructionsI64" },
|
||||
{ RISCV_FEATURE_HASVINSTRUCTIONSANYF, "HasVInstructionsAnyF" },
|
||||
{ RISCV_FEATURE_HASVINSTRUCTIONSF16MINIMAL, "HasVInstructionsF16Minimal" },
|
||||
{ RISCV_FEATURE_HASSTDEXTH, "HasStdExtH" },
|
||||
{ RISCV_FEATURE_HASSTDEXTSVINVAL, "HasStdExtSvinval" },
|
||||
{ RISCV_FEATURE_HASVENDORXVENTANACONDOPS, "HasVendorXVentanaCondOps" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADBA, "HasVendorXTHeadBa" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADBB, "HasVendorXTHeadBb" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADBS, "HasVendorXTHeadBs" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADCONDMOV, "HasVendorXTHeadCondMov" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADCMO, "HasVendorXTHeadCmo" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADFMEMIDX, "HasVendorXTHeadFMemIdx" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADMAC, "HasVendorXTHeadMac" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADMEMIDX, "HasVendorXTHeadMemIdx" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADMEMPAIR, "HasVendorXTHeadMemPair" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADSYNC, "HasVendorXTHeadSync" },
|
||||
{ RISCV_FEATURE_HASVENDORXTHEADVDOT, "HasVendorXTHeadVdot" },
|
||||
{ RISCV_FEATURE_HASVENDORXSFVCP, "HasVendorXSfvcp" },
|
||||
{ RISCV_FEATURE_HASVENDORXSFVQMACCDOD, "HasVendorXSfvqmaccdod" },
|
||||
{ RISCV_FEATURE_HASVENDORXSFVQMACCQOQ, "HasVendorXSfvqmaccqoq" },
|
||||
{ RISCV_FEATURE_HASVENDORXSFVFWMACCQQQ, "HasVendorXSfvfwmaccqqq" },
|
||||
{ RISCV_FEATURE_HASVENDORXSFVFNRCLIPXFQF, "HasVendorXSfvfnrclipxfqf" },
|
||||
{ RISCV_FEATURE_HASVENDORXCVELW, "HasVendorXCVelw" },
|
||||
{ RISCV_FEATURE_HASVENDORXCVBITMANIP, "HasVendorXCVbitmanip" },
|
||||
{ RISCV_FEATURE_HASVENDORXCVMAC, "HasVendorXCVmac" },
|
||||
{ RISCV_FEATURE_HASVENDORXCVMEM, "HasVendorXCVmem" },
|
||||
{ RISCV_FEATURE_HASVENDORXCVALU, "HasVendorXCValu" },
|
||||
{ RISCV_FEATURE_HASVENDORXCVSIMD, "HasVendorXCVsimd" },
|
||||
{ RISCV_FEATURE_HASVENDORXCVBI, "HasVendorXCVbi" },
|
||||
{ RISCV_FEATURE_ISRV64, "IsRV64" },
|
||||
{ RISCV_FEATURE_ISRV32, "IsRV32" },
|
||||
{ RISCV_FEATURE_ISRVE, "IsRVE" },
|
||||
+1688
File diff suppressed because it is too large
Load Diff
+93486
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+47133
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,26 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
RISCV_OP_GROUP_Operand = 0,
|
||||
RISCV_OP_GROUP_BranchOperand = 1,
|
||||
RISCV_OP_GROUP_VMaskReg = 2,
|
||||
RISCV_OP_GROUP_VTypeI = 3,
|
||||
RISCV_OP_GROUP_ZeroOffsetMemOp = 4,
|
||||
RISCV_OP_GROUP_Rlist = 5,
|
||||
RISCV_OP_GROUP_Spimm = 6,
|
||||
RISCV_OP_GROUP_CSRSystemRegister = 7,
|
||||
RISCV_OP_GROUP_RegReg = 8,
|
||||
RISCV_OP_GROUP_FRMArg = 9,
|
||||
RISCV_OP_GROUP_FRMArgLegacy = 10,
|
||||
RISCV_OP_GROUP_FenceArg = 11,
|
||||
RISCV_OP_GROUP_FPImmOperand = 12,
|
||||
+473
@@ -0,0 +1,473 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
RISCV_REG_INVALID = 0,
|
||||
RISCV_REG_FFLAGS = 1,
|
||||
RISCV_REG_FRM = 2,
|
||||
RISCV_REG_SSP = 3,
|
||||
RISCV_REG_VL = 4,
|
||||
RISCV_REG_VLENB = 5,
|
||||
RISCV_REG_VTYPE = 6,
|
||||
RISCV_REG_VXRM = 7,
|
||||
RISCV_REG_VXSAT = 8,
|
||||
RISCV_REG_DUMMY_REG_PAIR_WITH_X0 = 9,
|
||||
RISCV_REG_V0 = 10,
|
||||
RISCV_REG_V1 = 11,
|
||||
RISCV_REG_V2 = 12,
|
||||
RISCV_REG_V3 = 13,
|
||||
RISCV_REG_V4 = 14,
|
||||
RISCV_REG_V5 = 15,
|
||||
RISCV_REG_V6 = 16,
|
||||
RISCV_REG_V7 = 17,
|
||||
RISCV_REG_V8 = 18,
|
||||
RISCV_REG_V9 = 19,
|
||||
RISCV_REG_V10 = 20,
|
||||
RISCV_REG_V11 = 21,
|
||||
RISCV_REG_V12 = 22,
|
||||
RISCV_REG_V13 = 23,
|
||||
RISCV_REG_V14 = 24,
|
||||
RISCV_REG_V15 = 25,
|
||||
RISCV_REG_V16 = 26,
|
||||
RISCV_REG_V17 = 27,
|
||||
RISCV_REG_V18 = 28,
|
||||
RISCV_REG_V19 = 29,
|
||||
RISCV_REG_V20 = 30,
|
||||
RISCV_REG_V21 = 31,
|
||||
RISCV_REG_V22 = 32,
|
||||
RISCV_REG_V23 = 33,
|
||||
RISCV_REG_V24 = 34,
|
||||
RISCV_REG_V25 = 35,
|
||||
RISCV_REG_V26 = 36,
|
||||
RISCV_REG_V27 = 37,
|
||||
RISCV_REG_V28 = 38,
|
||||
RISCV_REG_V29 = 39,
|
||||
RISCV_REG_V30 = 40,
|
||||
RISCV_REG_V31 = 41,
|
||||
RISCV_REG_X0 = 42,
|
||||
RISCV_REG_X1 = 43,
|
||||
RISCV_REG_X2 = 44,
|
||||
RISCV_REG_X3 = 45,
|
||||
RISCV_REG_X4 = 46,
|
||||
RISCV_REG_X5 = 47,
|
||||
RISCV_REG_X6 = 48,
|
||||
RISCV_REG_X7 = 49,
|
||||
RISCV_REG_X8 = 50,
|
||||
RISCV_REG_X9 = 51,
|
||||
RISCV_REG_X10 = 52,
|
||||
RISCV_REG_X11 = 53,
|
||||
RISCV_REG_X12 = 54,
|
||||
RISCV_REG_X13 = 55,
|
||||
RISCV_REG_X14 = 56,
|
||||
RISCV_REG_X15 = 57,
|
||||
RISCV_REG_X16 = 58,
|
||||
RISCV_REG_X17 = 59,
|
||||
RISCV_REG_X18 = 60,
|
||||
RISCV_REG_X19 = 61,
|
||||
RISCV_REG_X20 = 62,
|
||||
RISCV_REG_X21 = 63,
|
||||
RISCV_REG_X22 = 64,
|
||||
RISCV_REG_X23 = 65,
|
||||
RISCV_REG_X24 = 66,
|
||||
RISCV_REG_X25 = 67,
|
||||
RISCV_REG_X26 = 68,
|
||||
RISCV_REG_X27 = 69,
|
||||
RISCV_REG_X28 = 70,
|
||||
RISCV_REG_X29 = 71,
|
||||
RISCV_REG_X30 = 72,
|
||||
RISCV_REG_X31 = 73,
|
||||
RISCV_REG_F0_D = 74,
|
||||
RISCV_REG_F1_D = 75,
|
||||
RISCV_REG_F2_D = 76,
|
||||
RISCV_REG_F3_D = 77,
|
||||
RISCV_REG_F4_D = 78,
|
||||
RISCV_REG_F5_D = 79,
|
||||
RISCV_REG_F6_D = 80,
|
||||
RISCV_REG_F7_D = 81,
|
||||
RISCV_REG_F8_D = 82,
|
||||
RISCV_REG_F9_D = 83,
|
||||
RISCV_REG_F10_D = 84,
|
||||
RISCV_REG_F11_D = 85,
|
||||
RISCV_REG_F12_D = 86,
|
||||
RISCV_REG_F13_D = 87,
|
||||
RISCV_REG_F14_D = 88,
|
||||
RISCV_REG_F15_D = 89,
|
||||
RISCV_REG_F16_D = 90,
|
||||
RISCV_REG_F17_D = 91,
|
||||
RISCV_REG_F18_D = 92,
|
||||
RISCV_REG_F19_D = 93,
|
||||
RISCV_REG_F20_D = 94,
|
||||
RISCV_REG_F21_D = 95,
|
||||
RISCV_REG_F22_D = 96,
|
||||
RISCV_REG_F23_D = 97,
|
||||
RISCV_REG_F24_D = 98,
|
||||
RISCV_REG_F25_D = 99,
|
||||
RISCV_REG_F26_D = 100,
|
||||
RISCV_REG_F27_D = 101,
|
||||
RISCV_REG_F28_D = 102,
|
||||
RISCV_REG_F29_D = 103,
|
||||
RISCV_REG_F30_D = 104,
|
||||
RISCV_REG_F31_D = 105,
|
||||
RISCV_REG_F0_F = 106,
|
||||
RISCV_REG_F1_F = 107,
|
||||
RISCV_REG_F2_F = 108,
|
||||
RISCV_REG_F3_F = 109,
|
||||
RISCV_REG_F4_F = 110,
|
||||
RISCV_REG_F5_F = 111,
|
||||
RISCV_REG_F6_F = 112,
|
||||
RISCV_REG_F7_F = 113,
|
||||
RISCV_REG_F8_F = 114,
|
||||
RISCV_REG_F9_F = 115,
|
||||
RISCV_REG_F10_F = 116,
|
||||
RISCV_REG_F11_F = 117,
|
||||
RISCV_REG_F12_F = 118,
|
||||
RISCV_REG_F13_F = 119,
|
||||
RISCV_REG_F14_F = 120,
|
||||
RISCV_REG_F15_F = 121,
|
||||
RISCV_REG_F16_F = 122,
|
||||
RISCV_REG_F17_F = 123,
|
||||
RISCV_REG_F18_F = 124,
|
||||
RISCV_REG_F19_F = 125,
|
||||
RISCV_REG_F20_F = 126,
|
||||
RISCV_REG_F21_F = 127,
|
||||
RISCV_REG_F22_F = 128,
|
||||
RISCV_REG_F23_F = 129,
|
||||
RISCV_REG_F24_F = 130,
|
||||
RISCV_REG_F25_F = 131,
|
||||
RISCV_REG_F26_F = 132,
|
||||
RISCV_REG_F27_F = 133,
|
||||
RISCV_REG_F28_F = 134,
|
||||
RISCV_REG_F29_F = 135,
|
||||
RISCV_REG_F30_F = 136,
|
||||
RISCV_REG_F31_F = 137,
|
||||
RISCV_REG_F0_H = 138,
|
||||
RISCV_REG_F1_H = 139,
|
||||
RISCV_REG_F2_H = 140,
|
||||
RISCV_REG_F3_H = 141,
|
||||
RISCV_REG_F4_H = 142,
|
||||
RISCV_REG_F5_H = 143,
|
||||
RISCV_REG_F6_H = 144,
|
||||
RISCV_REG_F7_H = 145,
|
||||
RISCV_REG_F8_H = 146,
|
||||
RISCV_REG_F9_H = 147,
|
||||
RISCV_REG_F10_H = 148,
|
||||
RISCV_REG_F11_H = 149,
|
||||
RISCV_REG_F12_H = 150,
|
||||
RISCV_REG_F13_H = 151,
|
||||
RISCV_REG_F14_H = 152,
|
||||
RISCV_REG_F15_H = 153,
|
||||
RISCV_REG_F16_H = 154,
|
||||
RISCV_REG_F17_H = 155,
|
||||
RISCV_REG_F18_H = 156,
|
||||
RISCV_REG_F19_H = 157,
|
||||
RISCV_REG_F20_H = 158,
|
||||
RISCV_REG_F21_H = 159,
|
||||
RISCV_REG_F22_H = 160,
|
||||
RISCV_REG_F23_H = 161,
|
||||
RISCV_REG_F24_H = 162,
|
||||
RISCV_REG_F25_H = 163,
|
||||
RISCV_REG_F26_H = 164,
|
||||
RISCV_REG_F27_H = 165,
|
||||
RISCV_REG_F28_H = 166,
|
||||
RISCV_REG_F29_H = 167,
|
||||
RISCV_REG_F30_H = 168,
|
||||
RISCV_REG_F31_H = 169,
|
||||
RISCV_REG_X0_PAIR = 170,
|
||||
RISCV_REG_V0M2 = 171,
|
||||
RISCV_REG_V0M4 = 172,
|
||||
RISCV_REG_V0M8 = 173,
|
||||
RISCV_REG_V2M2 = 174,
|
||||
RISCV_REG_V4M2 = 175,
|
||||
RISCV_REG_V4M4 = 176,
|
||||
RISCV_REG_V6M2 = 177,
|
||||
RISCV_REG_V8M2 = 178,
|
||||
RISCV_REG_V8M4 = 179,
|
||||
RISCV_REG_V8M8 = 180,
|
||||
RISCV_REG_V10M2 = 181,
|
||||
RISCV_REG_V12M2 = 182,
|
||||
RISCV_REG_V12M4 = 183,
|
||||
RISCV_REG_V14M2 = 184,
|
||||
RISCV_REG_V16M2 = 185,
|
||||
RISCV_REG_V16M4 = 186,
|
||||
RISCV_REG_V16M8 = 187,
|
||||
RISCV_REG_V18M2 = 188,
|
||||
RISCV_REG_V20M2 = 189,
|
||||
RISCV_REG_V20M4 = 190,
|
||||
RISCV_REG_V22M2 = 191,
|
||||
RISCV_REG_V24M2 = 192,
|
||||
RISCV_REG_V24M4 = 193,
|
||||
RISCV_REG_V24M8 = 194,
|
||||
RISCV_REG_V26M2 = 195,
|
||||
RISCV_REG_V28M2 = 196,
|
||||
RISCV_REG_V28M4 = 197,
|
||||
RISCV_REG_V30M2 = 198,
|
||||
RISCV_REG_X2_X3 = 199,
|
||||
RISCV_REG_X4_X5 = 200,
|
||||
RISCV_REG_X6_X7 = 201,
|
||||
RISCV_REG_X8_X9 = 202,
|
||||
RISCV_REG_X10_X11 = 203,
|
||||
RISCV_REG_X12_X13 = 204,
|
||||
RISCV_REG_X14_X15 = 205,
|
||||
RISCV_REG_X16_X17 = 206,
|
||||
RISCV_REG_X18_X19 = 207,
|
||||
RISCV_REG_X20_X21 = 208,
|
||||
RISCV_REG_X22_X23 = 209,
|
||||
RISCV_REG_X24_X25 = 210,
|
||||
RISCV_REG_X26_X27 = 211,
|
||||
RISCV_REG_X28_X29 = 212,
|
||||
RISCV_REG_X30_X31 = 213,
|
||||
RISCV_REG_V1_V2 = 214,
|
||||
RISCV_REG_V2_V3 = 215,
|
||||
RISCV_REG_V3_V4 = 216,
|
||||
RISCV_REG_V4_V5 = 217,
|
||||
RISCV_REG_V5_V6 = 218,
|
||||
RISCV_REG_V6_V7 = 219,
|
||||
RISCV_REG_V7_V8 = 220,
|
||||
RISCV_REG_V8_V9 = 221,
|
||||
RISCV_REG_V9_V10 = 222,
|
||||
RISCV_REG_V10_V11 = 223,
|
||||
RISCV_REG_V11_V12 = 224,
|
||||
RISCV_REG_V12_V13 = 225,
|
||||
RISCV_REG_V13_V14 = 226,
|
||||
RISCV_REG_V14_V15 = 227,
|
||||
RISCV_REG_V15_V16 = 228,
|
||||
RISCV_REG_V16_V17 = 229,
|
||||
RISCV_REG_V17_V18 = 230,
|
||||
RISCV_REG_V18_V19 = 231,
|
||||
RISCV_REG_V19_V20 = 232,
|
||||
RISCV_REG_V20_V21 = 233,
|
||||
RISCV_REG_V21_V22 = 234,
|
||||
RISCV_REG_V22_V23 = 235,
|
||||
RISCV_REG_V23_V24 = 236,
|
||||
RISCV_REG_V24_V25 = 237,
|
||||
RISCV_REG_V25_V26 = 238,
|
||||
RISCV_REG_V26_V27 = 239,
|
||||
RISCV_REG_V27_V28 = 240,
|
||||
RISCV_REG_V28_V29 = 241,
|
||||
RISCV_REG_V29_V30 = 242,
|
||||
RISCV_REG_V30_V31 = 243,
|
||||
RISCV_REG_V0_V1 = 244,
|
||||
RISCV_REG_V2M2_V4M2 = 245,
|
||||
RISCV_REG_V4M2_V6M2 = 246,
|
||||
RISCV_REG_V6M2_V8M2 = 247,
|
||||
RISCV_REG_V8M2_V10M2 = 248,
|
||||
RISCV_REG_V10M2_V12M2 = 249,
|
||||
RISCV_REG_V12M2_V14M2 = 250,
|
||||
RISCV_REG_V14M2_V16M2 = 251,
|
||||
RISCV_REG_V16M2_V18M2 = 252,
|
||||
RISCV_REG_V18M2_V20M2 = 253,
|
||||
RISCV_REG_V20M2_V22M2 = 254,
|
||||
RISCV_REG_V22M2_V24M2 = 255,
|
||||
RISCV_REG_V24M2_V26M2 = 256,
|
||||
RISCV_REG_V26M2_V28M2 = 257,
|
||||
RISCV_REG_V28M2_V30M2 = 258,
|
||||
RISCV_REG_V0M2_V2M2 = 259,
|
||||
RISCV_REG_V4M4_V8M4 = 260,
|
||||
RISCV_REG_V8M4_V12M4 = 261,
|
||||
RISCV_REG_V12M4_V16M4 = 262,
|
||||
RISCV_REG_V16M4_V20M4 = 263,
|
||||
RISCV_REG_V20M4_V24M4 = 264,
|
||||
RISCV_REG_V24M4_V28M4 = 265,
|
||||
RISCV_REG_V0M4_V4M4 = 266,
|
||||
RISCV_REG_V1_V2_V3 = 267,
|
||||
RISCV_REG_V2_V3_V4 = 268,
|
||||
RISCV_REG_V3_V4_V5 = 269,
|
||||
RISCV_REG_V4_V5_V6 = 270,
|
||||
RISCV_REG_V5_V6_V7 = 271,
|
||||
RISCV_REG_V6_V7_V8 = 272,
|
||||
RISCV_REG_V7_V8_V9 = 273,
|
||||
RISCV_REG_V8_V9_V10 = 274,
|
||||
RISCV_REG_V9_V10_V11 = 275,
|
||||
RISCV_REG_V10_V11_V12 = 276,
|
||||
RISCV_REG_V11_V12_V13 = 277,
|
||||
RISCV_REG_V12_V13_V14 = 278,
|
||||
RISCV_REG_V13_V14_V15 = 279,
|
||||
RISCV_REG_V14_V15_V16 = 280,
|
||||
RISCV_REG_V15_V16_V17 = 281,
|
||||
RISCV_REG_V16_V17_V18 = 282,
|
||||
RISCV_REG_V17_V18_V19 = 283,
|
||||
RISCV_REG_V18_V19_V20 = 284,
|
||||
RISCV_REG_V19_V20_V21 = 285,
|
||||
RISCV_REG_V20_V21_V22 = 286,
|
||||
RISCV_REG_V21_V22_V23 = 287,
|
||||
RISCV_REG_V22_V23_V24 = 288,
|
||||
RISCV_REG_V23_V24_V25 = 289,
|
||||
RISCV_REG_V24_V25_V26 = 290,
|
||||
RISCV_REG_V25_V26_V27 = 291,
|
||||
RISCV_REG_V26_V27_V28 = 292,
|
||||
RISCV_REG_V27_V28_V29 = 293,
|
||||
RISCV_REG_V28_V29_V30 = 294,
|
||||
RISCV_REG_V29_V30_V31 = 295,
|
||||
RISCV_REG_V0_V1_V2 = 296,
|
||||
RISCV_REG_V2M2_V4M2_V6M2 = 297,
|
||||
RISCV_REG_V4M2_V6M2_V8M2 = 298,
|
||||
RISCV_REG_V6M2_V8M2_V10M2 = 299,
|
||||
RISCV_REG_V8M2_V10M2_V12M2 = 300,
|
||||
RISCV_REG_V10M2_V12M2_V14M2 = 301,
|
||||
RISCV_REG_V12M2_V14M2_V16M2 = 302,
|
||||
RISCV_REG_V14M2_V16M2_V18M2 = 303,
|
||||
RISCV_REG_V16M2_V18M2_V20M2 = 304,
|
||||
RISCV_REG_V18M2_V20M2_V22M2 = 305,
|
||||
RISCV_REG_V20M2_V22M2_V24M2 = 306,
|
||||
RISCV_REG_V22M2_V24M2_V26M2 = 307,
|
||||
RISCV_REG_V24M2_V26M2_V28M2 = 308,
|
||||
RISCV_REG_V26M2_V28M2_V30M2 = 309,
|
||||
RISCV_REG_V0M2_V2M2_V4M2 = 310,
|
||||
RISCV_REG_V1_V2_V3_V4 = 311,
|
||||
RISCV_REG_V2_V3_V4_V5 = 312,
|
||||
RISCV_REG_V3_V4_V5_V6 = 313,
|
||||
RISCV_REG_V4_V5_V6_V7 = 314,
|
||||
RISCV_REG_V5_V6_V7_V8 = 315,
|
||||
RISCV_REG_V6_V7_V8_V9 = 316,
|
||||
RISCV_REG_V7_V8_V9_V10 = 317,
|
||||
RISCV_REG_V8_V9_V10_V11 = 318,
|
||||
RISCV_REG_V9_V10_V11_V12 = 319,
|
||||
RISCV_REG_V10_V11_V12_V13 = 320,
|
||||
RISCV_REG_V11_V12_V13_V14 = 321,
|
||||
RISCV_REG_V12_V13_V14_V15 = 322,
|
||||
RISCV_REG_V13_V14_V15_V16 = 323,
|
||||
RISCV_REG_V14_V15_V16_V17 = 324,
|
||||
RISCV_REG_V15_V16_V17_V18 = 325,
|
||||
RISCV_REG_V16_V17_V18_V19 = 326,
|
||||
RISCV_REG_V17_V18_V19_V20 = 327,
|
||||
RISCV_REG_V18_V19_V20_V21 = 328,
|
||||
RISCV_REG_V19_V20_V21_V22 = 329,
|
||||
RISCV_REG_V20_V21_V22_V23 = 330,
|
||||
RISCV_REG_V21_V22_V23_V24 = 331,
|
||||
RISCV_REG_V22_V23_V24_V25 = 332,
|
||||
RISCV_REG_V23_V24_V25_V26 = 333,
|
||||
RISCV_REG_V24_V25_V26_V27 = 334,
|
||||
RISCV_REG_V25_V26_V27_V28 = 335,
|
||||
RISCV_REG_V26_V27_V28_V29 = 336,
|
||||
RISCV_REG_V27_V28_V29_V30 = 337,
|
||||
RISCV_REG_V28_V29_V30_V31 = 338,
|
||||
RISCV_REG_V0_V1_V2_V3 = 339,
|
||||
RISCV_REG_V2M2_V4M2_V6M2_V8M2 = 340,
|
||||
RISCV_REG_V4M2_V6M2_V8M2_V10M2 = 341,
|
||||
RISCV_REG_V6M2_V8M2_V10M2_V12M2 = 342,
|
||||
RISCV_REG_V8M2_V10M2_V12M2_V14M2 = 343,
|
||||
RISCV_REG_V10M2_V12M2_V14M2_V16M2 = 344,
|
||||
RISCV_REG_V12M2_V14M2_V16M2_V18M2 = 345,
|
||||
RISCV_REG_V14M2_V16M2_V18M2_V20M2 = 346,
|
||||
RISCV_REG_V16M2_V18M2_V20M2_V22M2 = 347,
|
||||
RISCV_REG_V18M2_V20M2_V22M2_V24M2 = 348,
|
||||
RISCV_REG_V20M2_V22M2_V24M2_V26M2 = 349,
|
||||
RISCV_REG_V22M2_V24M2_V26M2_V28M2 = 350,
|
||||
RISCV_REG_V24M2_V26M2_V28M2_V30M2 = 351,
|
||||
RISCV_REG_V0M2_V2M2_V4M2_V6M2 = 352,
|
||||
RISCV_REG_V1_V2_V3_V4_V5 = 353,
|
||||
RISCV_REG_V2_V3_V4_V5_V6 = 354,
|
||||
RISCV_REG_V3_V4_V5_V6_V7 = 355,
|
||||
RISCV_REG_V4_V5_V6_V7_V8 = 356,
|
||||
RISCV_REG_V5_V6_V7_V8_V9 = 357,
|
||||
RISCV_REG_V6_V7_V8_V9_V10 = 358,
|
||||
RISCV_REG_V7_V8_V9_V10_V11 = 359,
|
||||
RISCV_REG_V8_V9_V10_V11_V12 = 360,
|
||||
RISCV_REG_V9_V10_V11_V12_V13 = 361,
|
||||
RISCV_REG_V10_V11_V12_V13_V14 = 362,
|
||||
RISCV_REG_V11_V12_V13_V14_V15 = 363,
|
||||
RISCV_REG_V12_V13_V14_V15_V16 = 364,
|
||||
RISCV_REG_V13_V14_V15_V16_V17 = 365,
|
||||
RISCV_REG_V14_V15_V16_V17_V18 = 366,
|
||||
RISCV_REG_V15_V16_V17_V18_V19 = 367,
|
||||
RISCV_REG_V16_V17_V18_V19_V20 = 368,
|
||||
RISCV_REG_V17_V18_V19_V20_V21 = 369,
|
||||
RISCV_REG_V18_V19_V20_V21_V22 = 370,
|
||||
RISCV_REG_V19_V20_V21_V22_V23 = 371,
|
||||
RISCV_REG_V20_V21_V22_V23_V24 = 372,
|
||||
RISCV_REG_V21_V22_V23_V24_V25 = 373,
|
||||
RISCV_REG_V22_V23_V24_V25_V26 = 374,
|
||||
RISCV_REG_V23_V24_V25_V26_V27 = 375,
|
||||
RISCV_REG_V24_V25_V26_V27_V28 = 376,
|
||||
RISCV_REG_V25_V26_V27_V28_V29 = 377,
|
||||
RISCV_REG_V26_V27_V28_V29_V30 = 378,
|
||||
RISCV_REG_V27_V28_V29_V30_V31 = 379,
|
||||
RISCV_REG_V0_V1_V2_V3_V4 = 380,
|
||||
RISCV_REG_V1_V2_V3_V4_V5_V6 = 381,
|
||||
RISCV_REG_V2_V3_V4_V5_V6_V7 = 382,
|
||||
RISCV_REG_V3_V4_V5_V6_V7_V8 = 383,
|
||||
RISCV_REG_V4_V5_V6_V7_V8_V9 = 384,
|
||||
RISCV_REG_V5_V6_V7_V8_V9_V10 = 385,
|
||||
RISCV_REG_V6_V7_V8_V9_V10_V11 = 386,
|
||||
RISCV_REG_V7_V8_V9_V10_V11_V12 = 387,
|
||||
RISCV_REG_V8_V9_V10_V11_V12_V13 = 388,
|
||||
RISCV_REG_V9_V10_V11_V12_V13_V14 = 389,
|
||||
RISCV_REG_V10_V11_V12_V13_V14_V15 = 390,
|
||||
RISCV_REG_V11_V12_V13_V14_V15_V16 = 391,
|
||||
RISCV_REG_V12_V13_V14_V15_V16_V17 = 392,
|
||||
RISCV_REG_V13_V14_V15_V16_V17_V18 = 393,
|
||||
RISCV_REG_V14_V15_V16_V17_V18_V19 = 394,
|
||||
RISCV_REG_V15_V16_V17_V18_V19_V20 = 395,
|
||||
RISCV_REG_V16_V17_V18_V19_V20_V21 = 396,
|
||||
RISCV_REG_V17_V18_V19_V20_V21_V22 = 397,
|
||||
RISCV_REG_V18_V19_V20_V21_V22_V23 = 398,
|
||||
RISCV_REG_V19_V20_V21_V22_V23_V24 = 399,
|
||||
RISCV_REG_V20_V21_V22_V23_V24_V25 = 400,
|
||||
RISCV_REG_V21_V22_V23_V24_V25_V26 = 401,
|
||||
RISCV_REG_V22_V23_V24_V25_V26_V27 = 402,
|
||||
RISCV_REG_V23_V24_V25_V26_V27_V28 = 403,
|
||||
RISCV_REG_V24_V25_V26_V27_V28_V29 = 404,
|
||||
RISCV_REG_V25_V26_V27_V28_V29_V30 = 405,
|
||||
RISCV_REG_V26_V27_V28_V29_V30_V31 = 406,
|
||||
RISCV_REG_V0_V1_V2_V3_V4_V5 = 407,
|
||||
RISCV_REG_V1_V2_V3_V4_V5_V6_V7 = 408,
|
||||
RISCV_REG_V2_V3_V4_V5_V6_V7_V8 = 409,
|
||||
RISCV_REG_V3_V4_V5_V6_V7_V8_V9 = 410,
|
||||
RISCV_REG_V4_V5_V6_V7_V8_V9_V10 = 411,
|
||||
RISCV_REG_V5_V6_V7_V8_V9_V10_V11 = 412,
|
||||
RISCV_REG_V6_V7_V8_V9_V10_V11_V12 = 413,
|
||||
RISCV_REG_V7_V8_V9_V10_V11_V12_V13 = 414,
|
||||
RISCV_REG_V8_V9_V10_V11_V12_V13_V14 = 415,
|
||||
RISCV_REG_V9_V10_V11_V12_V13_V14_V15 = 416,
|
||||
RISCV_REG_V10_V11_V12_V13_V14_V15_V16 = 417,
|
||||
RISCV_REG_V11_V12_V13_V14_V15_V16_V17 = 418,
|
||||
RISCV_REG_V12_V13_V14_V15_V16_V17_V18 = 419,
|
||||
RISCV_REG_V13_V14_V15_V16_V17_V18_V19 = 420,
|
||||
RISCV_REG_V14_V15_V16_V17_V18_V19_V20 = 421,
|
||||
RISCV_REG_V15_V16_V17_V18_V19_V20_V21 = 422,
|
||||
RISCV_REG_V16_V17_V18_V19_V20_V21_V22 = 423,
|
||||
RISCV_REG_V17_V18_V19_V20_V21_V22_V23 = 424,
|
||||
RISCV_REG_V18_V19_V20_V21_V22_V23_V24 = 425,
|
||||
RISCV_REG_V19_V20_V21_V22_V23_V24_V25 = 426,
|
||||
RISCV_REG_V20_V21_V22_V23_V24_V25_V26 = 427,
|
||||
RISCV_REG_V21_V22_V23_V24_V25_V26_V27 = 428,
|
||||
RISCV_REG_V22_V23_V24_V25_V26_V27_V28 = 429,
|
||||
RISCV_REG_V23_V24_V25_V26_V27_V28_V29 = 430,
|
||||
RISCV_REG_V24_V25_V26_V27_V28_V29_V30 = 431,
|
||||
RISCV_REG_V25_V26_V27_V28_V29_V30_V31 = 432,
|
||||
RISCV_REG_V0_V1_V2_V3_V4_V5_V6 = 433,
|
||||
RISCV_REG_V1_V2_V3_V4_V5_V6_V7_V8 = 434,
|
||||
RISCV_REG_V2_V3_V4_V5_V6_V7_V8_V9 = 435,
|
||||
RISCV_REG_V3_V4_V5_V6_V7_V8_V9_V10 = 436,
|
||||
RISCV_REG_V4_V5_V6_V7_V8_V9_V10_V11 = 437,
|
||||
RISCV_REG_V5_V6_V7_V8_V9_V10_V11_V12 = 438,
|
||||
RISCV_REG_V6_V7_V8_V9_V10_V11_V12_V13 = 439,
|
||||
RISCV_REG_V7_V8_V9_V10_V11_V12_V13_V14 = 440,
|
||||
RISCV_REG_V8_V9_V10_V11_V12_V13_V14_V15 = 441,
|
||||
RISCV_REG_V9_V10_V11_V12_V13_V14_V15_V16 = 442,
|
||||
RISCV_REG_V10_V11_V12_V13_V14_V15_V16_V17 = 443,
|
||||
RISCV_REG_V11_V12_V13_V14_V15_V16_V17_V18 = 444,
|
||||
RISCV_REG_V12_V13_V14_V15_V16_V17_V18_V19 = 445,
|
||||
RISCV_REG_V13_V14_V15_V16_V17_V18_V19_V20 = 446,
|
||||
RISCV_REG_V14_V15_V16_V17_V18_V19_V20_V21 = 447,
|
||||
RISCV_REG_V15_V16_V17_V18_V19_V20_V21_V22 = 448,
|
||||
RISCV_REG_V16_V17_V18_V19_V20_V21_V22_V23 = 449,
|
||||
RISCV_REG_V17_V18_V19_V20_V21_V22_V23_V24 = 450,
|
||||
RISCV_REG_V18_V19_V20_V21_V22_V23_V24_V25 = 451,
|
||||
RISCV_REG_V19_V20_V21_V22_V23_V24_V25_V26 = 452,
|
||||
RISCV_REG_V20_V21_V22_V23_V24_V25_V26_V27 = 453,
|
||||
RISCV_REG_V21_V22_V23_V24_V25_V26_V27_V28 = 454,
|
||||
RISCV_REG_V22_V23_V24_V25_V26_V27_V28_V29 = 455,
|
||||
RISCV_REG_V23_V24_V25_V26_V27_V28_V29_V30 = 456,
|
||||
RISCV_REG_V24_V25_V26_V27_V28_V29_V30_V31 = 457,
|
||||
RISCV_REG_V0_V1_V2_V3_V4_V5_V6_V7 = 458,
|
||||
RISCV_REG_ENDING, // 459
|
||||
@@ -0,0 +1,510 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
#ifdef GET_ENUM_VALUES_RISCVMaskedPseudoInfo
|
||||
#undef GET_ENUM_VALUES_RISCVMaskedPseudoInfo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_RISCVOpcode
|
||||
#undef GET_ENUM_VALUES_RISCVOpcode
|
||||
RISCV_RISCVOPCODE_LOAD = 0x3,
|
||||
RISCV_RISCVOPCODE_LOAD_FP = 0x7,
|
||||
RISCV_RISCVOPCODE_CUSTOM_0 = 0xb,
|
||||
RISCV_RISCVOPCODE_MISC_MEM = 0xf,
|
||||
RISCV_RISCVOPCODE_OP_IMM = 0x13,
|
||||
RISCV_RISCVOPCODE_AUIPC = 0x17,
|
||||
RISCV_RISCVOPCODE_OP_IMM_32 = 0x1b,
|
||||
RISCV_RISCVOPCODE_STORE = 0x23,
|
||||
RISCV_RISCVOPCODE_STORE_FP = 0x27,
|
||||
RISCV_RISCVOPCODE_CUSTOM_1 = 0x2b,
|
||||
RISCV_RISCVOPCODE_AMO = 0x2f,
|
||||
RISCV_RISCVOPCODE_OP = 0x33,
|
||||
RISCV_RISCVOPCODE_LUI = 0x37,
|
||||
RISCV_RISCVOPCODE_OP_32 = 0x3b,
|
||||
RISCV_RISCVOPCODE_MADD = 0x43,
|
||||
RISCV_RISCVOPCODE_MSUB = 0x47,
|
||||
RISCV_RISCVOPCODE_NMSUB = 0x4b,
|
||||
RISCV_RISCVOPCODE_NMADD = 0x4f,
|
||||
RISCV_RISCVOPCODE_OP_FP = 0x53,
|
||||
RISCV_RISCVOPCODE_OP_V = 0x57,
|
||||
RISCV_RISCVOPCODE_CUSTOM_2 = 0x5b,
|
||||
RISCV_RISCVOPCODE_BRANCH = 0x63,
|
||||
RISCV_RISCVOPCODE_JALR = 0x67,
|
||||
RISCV_RISCVOPCODE_JAL = 0x6f,
|
||||
RISCV_RISCVOPCODE_SYSTEM = 0x73,
|
||||
RISCV_RISCVOPCODE_OP_P = 0x77,
|
||||
RISCV_RISCVOPCODE_CUSTOM_3 = 0x7b,
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_RISCVTuneInfo
|
||||
#undef GET_ENUM_VALUES_RISCVTuneInfo
|
||||
RISCV_RISCVTUNEINFO_GENERIC = 0x0,
|
||||
RISCV_RISCVTUNEINFO_GENERIC-RV32 = 0x0,
|
||||
RISCV_RISCVTUNEINFO_GENERIC-RV64 = 0x0,
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_RISCVVIntrinsicInfo
|
||||
#undef GET_ENUM_VALUES_RISCVVIntrinsicInfo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_PseudoInfo
|
||||
#undef GET_ENUM_VALUES_PseudoInfo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VLEPseudo
|
||||
#undef GET_ENUM_VALUES_VLEPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VLSEGPseudo
|
||||
#undef GET_ENUM_VALUES_VLSEGPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VLXSEGPseudo
|
||||
#undef GET_ENUM_VALUES_VLXSEGPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VLX_VSXPseudo
|
||||
#undef GET_ENUM_VALUES_VLX_VSXPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_PseudoInfo
|
||||
#undef GET_ENUM_VALUES_PseudoInfo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VSEPseudo
|
||||
#undef GET_ENUM_VALUES_VSEPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VSSEGPseudo
|
||||
#undef GET_ENUM_VALUES_VSSEGPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VSXSEGPseudo
|
||||
#undef GET_ENUM_VALUES_VSXSEGPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_VLX_VSXPseudo
|
||||
#undef GET_ENUM_VALUES_VLX_VSXPseudo
|
||||
#endif
|
||||
|
||||
#ifdef GET_ENUM_VALUES_SysReg
|
||||
#undef GET_ENUM_VALUES_SysReg
|
||||
RISCV_SYSREG_FFLAGS = 0x1,
|
||||
RISCV_SYSREG_FRM = 0x2,
|
||||
RISCV_SYSREG_FCSR = 0x3,
|
||||
RISCV_SYSREG_VSTART = 0x8,
|
||||
RISCV_SYSREG_VXSAT = 0x9,
|
||||
RISCV_SYSREG_VXRM = 0xa,
|
||||
RISCV_SYSREG_VCSR = 0xf,
|
||||
RISCV_SYSREG_SEED = 0x15,
|
||||
RISCV_SYSREG_JVT = 0x17,
|
||||
RISCV_SYSREG_SSTATUS = 0x100,
|
||||
RISCV_SYSREG_SIE = 0x104,
|
||||
RISCV_SYSREG_STVEC = 0x105,
|
||||
RISCV_SYSREG_SCOUNTEREN = 0x106,
|
||||
RISCV_SYSREG_SENVCFG = 0x10a,
|
||||
RISCV_SYSREG_SSTATEEN0 = 0x10c,
|
||||
RISCV_SYSREG_SSTATEEN1 = 0x10d,
|
||||
RISCV_SYSREG_SSTATEEN2 = 0x10e,
|
||||
RISCV_SYSREG_SSTATEEN3 = 0x10f,
|
||||
RISCV_SYSREG_SIEH = 0x114,
|
||||
RISCV_SYSREG_SSCRATCH = 0x140,
|
||||
RISCV_SYSREG_SEPC = 0x141,
|
||||
RISCV_SYSREG_SCAUSE = 0x142,
|
||||
RISCV_SYSREG_STVAL = 0x143,
|
||||
RISCV_SYSREG_SIP = 0x144,
|
||||
RISCV_SYSREG_STIMECMP = 0x14d,
|
||||
RISCV_SYSREG_SISELECT = 0x150,
|
||||
RISCV_SYSREG_SIREG = 0x151,
|
||||
RISCV_SYSREG_SIPH = 0x154,
|
||||
RISCV_SYSREG_STOPEI = 0x15c,
|
||||
RISCV_SYSREG_STIMECMPH = 0x15d,
|
||||
RISCV_SYSREG_SATP = 0x180,
|
||||
RISCV_SYSREG_VSSTATUS = 0x200,
|
||||
RISCV_SYSREG_VSIE = 0x204,
|
||||
RISCV_SYSREG_VSTVEC = 0x205,
|
||||
RISCV_SYSREG_VSIEH = 0x214,
|
||||
RISCV_SYSREG_VSSCRATCH = 0x240,
|
||||
RISCV_SYSREG_VSEPC = 0x241,
|
||||
RISCV_SYSREG_VSCAUSE = 0x242,
|
||||
RISCV_SYSREG_VSTVAL = 0x243,
|
||||
RISCV_SYSREG_VSIP = 0x244,
|
||||
RISCV_SYSREG_VSTIMECMP = 0x24d,
|
||||
RISCV_SYSREG_VSISELECT = 0x250,
|
||||
RISCV_SYSREG_VSIREG = 0x251,
|
||||
RISCV_SYSREG_VSIPH = 0x254,
|
||||
RISCV_SYSREG_VSTOPEI = 0x25c,
|
||||
RISCV_SYSREG_VSTIMECMPH = 0x25d,
|
||||
RISCV_SYSREG_VSATP = 0x280,
|
||||
RISCV_SYSREG_MSTATUS = 0x300,
|
||||
RISCV_SYSREG_MISA = 0x301,
|
||||
RISCV_SYSREG_MEDELEG = 0x302,
|
||||
RISCV_SYSREG_MIDELEG = 0x303,
|
||||
RISCV_SYSREG_MIE = 0x304,
|
||||
RISCV_SYSREG_MTVEC = 0x305,
|
||||
RISCV_SYSREG_MCOUNTEREN = 0x306,
|
||||
RISCV_SYSREG_MVIEN = 0x308,
|
||||
RISCV_SYSREG_MVIP = 0x309,
|
||||
RISCV_SYSREG_MENVCFG = 0x30a,
|
||||
RISCV_SYSREG_MSTATEEN0 = 0x30c,
|
||||
RISCV_SYSREG_MSTATEEN1 = 0x30d,
|
||||
RISCV_SYSREG_MSTATEEN2 = 0x30e,
|
||||
RISCV_SYSREG_MSTATEEN3 = 0x30f,
|
||||
RISCV_SYSREG_MSTATUSH = 0x310,
|
||||
RISCV_SYSREG_MIDELEGH = 0x313,
|
||||
RISCV_SYSREG_MIEH = 0x314,
|
||||
RISCV_SYSREG_MVIENH = 0x318,
|
||||
RISCV_SYSREG_MVIPH = 0x319,
|
||||
RISCV_SYSREG_MENVCFGH = 0x31a,
|
||||
RISCV_SYSREG_MSTATEEN0H = 0x31c,
|
||||
RISCV_SYSREG_MSTATEEN1H = 0x31d,
|
||||
RISCV_SYSREG_MSTATEEN2H = 0x31e,
|
||||
RISCV_SYSREG_MSTATEEN3H = 0x31f,
|
||||
RISCV_SYSREG_MCOUNTINHIBIT = 0x320,
|
||||
RISCV_SYSREG_MUCOUNTEREN = 0x320,
|
||||
RISCV_SYSREG_MHPMEVENT3 = 0x323,
|
||||
RISCV_SYSREG_MHPMEVENT4 = 0x324,
|
||||
RISCV_SYSREG_MHPMEVENT5 = 0x325,
|
||||
RISCV_SYSREG_MHPMEVENT6 = 0x326,
|
||||
RISCV_SYSREG_MHPMEVENT7 = 0x327,
|
||||
RISCV_SYSREG_MHPMEVENT8 = 0x328,
|
||||
RISCV_SYSREG_MHPMEVENT9 = 0x329,
|
||||
RISCV_SYSREG_MHPMEVENT10 = 0x32a,
|
||||
RISCV_SYSREG_MHPMEVENT11 = 0x32b,
|
||||
RISCV_SYSREG_MHPMEVENT12 = 0x32c,
|
||||
RISCV_SYSREG_MHPMEVENT13 = 0x32d,
|
||||
RISCV_SYSREG_MHPMEVENT14 = 0x32e,
|
||||
RISCV_SYSREG_MHPMEVENT15 = 0x32f,
|
||||
RISCV_SYSREG_MHPMEVENT16 = 0x330,
|
||||
RISCV_SYSREG_MHPMEVENT17 = 0x331,
|
||||
RISCV_SYSREG_MHPMEVENT18 = 0x332,
|
||||
RISCV_SYSREG_MHPMEVENT19 = 0x333,
|
||||
RISCV_SYSREG_MHPMEVENT20 = 0x334,
|
||||
RISCV_SYSREG_MHPMEVENT21 = 0x335,
|
||||
RISCV_SYSREG_MHPMEVENT22 = 0x336,
|
||||
RISCV_SYSREG_MHPMEVENT23 = 0x337,
|
||||
RISCV_SYSREG_MHPMEVENT24 = 0x338,
|
||||
RISCV_SYSREG_MHPMEVENT25 = 0x339,
|
||||
RISCV_SYSREG_MHPMEVENT26 = 0x33a,
|
||||
RISCV_SYSREG_MHPMEVENT27 = 0x33b,
|
||||
RISCV_SYSREG_MHPMEVENT28 = 0x33c,
|
||||
RISCV_SYSREG_MHPMEVENT29 = 0x33d,
|
||||
RISCV_SYSREG_MHPMEVENT30 = 0x33e,
|
||||
RISCV_SYSREG_MHPMEVENT31 = 0x33f,
|
||||
RISCV_SYSREG_MSCRATCH = 0x340,
|
||||
RISCV_SYSREG_MEPC = 0x341,
|
||||
RISCV_SYSREG_MCAUSE = 0x342,
|
||||
RISCV_SYSREG_MTVAL = 0x343,
|
||||
RISCV_SYSREG_MIP = 0x344,
|
||||
RISCV_SYSREG_MTINST = 0x34a,
|
||||
RISCV_SYSREG_MTVAL2 = 0x34b,
|
||||
RISCV_SYSREG_MISELECT = 0x350,
|
||||
RISCV_SYSREG_MIREG = 0x351,
|
||||
RISCV_SYSREG_MIPH = 0x354,
|
||||
RISCV_SYSREG_MTOPEI = 0x35c,
|
||||
RISCV_SYSREG_PMPCFG0 = 0x3a0,
|
||||
RISCV_SYSREG_PMPCFG1 = 0x3a1,
|
||||
RISCV_SYSREG_PMPCFG2 = 0x3a2,
|
||||
RISCV_SYSREG_PMPCFG3 = 0x3a3,
|
||||
RISCV_SYSREG_PMPCFG4 = 0x3a4,
|
||||
RISCV_SYSREG_PMPCFG5 = 0x3a5,
|
||||
RISCV_SYSREG_PMPCFG6 = 0x3a6,
|
||||
RISCV_SYSREG_PMPCFG7 = 0x3a7,
|
||||
RISCV_SYSREG_PMPCFG8 = 0x3a8,
|
||||
RISCV_SYSREG_PMPCFG9 = 0x3a9,
|
||||
RISCV_SYSREG_PMPCFG10 = 0x3aa,
|
||||
RISCV_SYSREG_PMPCFG11 = 0x3ab,
|
||||
RISCV_SYSREG_PMPCFG12 = 0x3ac,
|
||||
RISCV_SYSREG_PMPCFG13 = 0x3ad,
|
||||
RISCV_SYSREG_PMPCFG14 = 0x3ae,
|
||||
RISCV_SYSREG_PMPCFG15 = 0x3af,
|
||||
RISCV_SYSREG_PMPADDR0 = 0x3b0,
|
||||
RISCV_SYSREG_PMPADDR1 = 0x3b1,
|
||||
RISCV_SYSREG_PMPADDR2 = 0x3b2,
|
||||
RISCV_SYSREG_PMPADDR3 = 0x3b3,
|
||||
RISCV_SYSREG_PMPADDR4 = 0x3b4,
|
||||
RISCV_SYSREG_PMPADDR5 = 0x3b5,
|
||||
RISCV_SYSREG_PMPADDR6 = 0x3b6,
|
||||
RISCV_SYSREG_PMPADDR7 = 0x3b7,
|
||||
RISCV_SYSREG_PMPADDR8 = 0x3b8,
|
||||
RISCV_SYSREG_PMPADDR9 = 0x3b9,
|
||||
RISCV_SYSREG_PMPADDR10 = 0x3ba,
|
||||
RISCV_SYSREG_PMPADDR11 = 0x3bb,
|
||||
RISCV_SYSREG_PMPADDR12 = 0x3bc,
|
||||
RISCV_SYSREG_PMPADDR13 = 0x3bd,
|
||||
RISCV_SYSREG_PMPADDR14 = 0x3be,
|
||||
RISCV_SYSREG_PMPADDR15 = 0x3bf,
|
||||
RISCV_SYSREG_PMPADDR16 = 0x3c0,
|
||||
RISCV_SYSREG_PMPADDR17 = 0x3c1,
|
||||
RISCV_SYSREG_PMPADDR18 = 0x3c2,
|
||||
RISCV_SYSREG_PMPADDR19 = 0x3c3,
|
||||
RISCV_SYSREG_PMPADDR20 = 0x3c4,
|
||||
RISCV_SYSREG_PMPADDR21 = 0x3c5,
|
||||
RISCV_SYSREG_PMPADDR22 = 0x3c6,
|
||||
RISCV_SYSREG_PMPADDR23 = 0x3c7,
|
||||
RISCV_SYSREG_PMPADDR24 = 0x3c8,
|
||||
RISCV_SYSREG_PMPADDR25 = 0x3c9,
|
||||
RISCV_SYSREG_PMPADDR26 = 0x3ca,
|
||||
RISCV_SYSREG_PMPADDR27 = 0x3cb,
|
||||
RISCV_SYSREG_PMPADDR28 = 0x3cc,
|
||||
RISCV_SYSREG_PMPADDR29 = 0x3cd,
|
||||
RISCV_SYSREG_PMPADDR30 = 0x3ce,
|
||||
RISCV_SYSREG_PMPADDR31 = 0x3cf,
|
||||
RISCV_SYSREG_PMPADDR32 = 0x3d0,
|
||||
RISCV_SYSREG_PMPADDR33 = 0x3d1,
|
||||
RISCV_SYSREG_PMPADDR34 = 0x3d2,
|
||||
RISCV_SYSREG_PMPADDR35 = 0x3d3,
|
||||
RISCV_SYSREG_PMPADDR36 = 0x3d4,
|
||||
RISCV_SYSREG_PMPADDR37 = 0x3d5,
|
||||
RISCV_SYSREG_PMPADDR38 = 0x3d6,
|
||||
RISCV_SYSREG_PMPADDR39 = 0x3d7,
|
||||
RISCV_SYSREG_PMPADDR40 = 0x3d8,
|
||||
RISCV_SYSREG_PMPADDR41 = 0x3d9,
|
||||
RISCV_SYSREG_PMPADDR42 = 0x3da,
|
||||
RISCV_SYSREG_PMPADDR43 = 0x3db,
|
||||
RISCV_SYSREG_PMPADDR44 = 0x3dc,
|
||||
RISCV_SYSREG_PMPADDR45 = 0x3dd,
|
||||
RISCV_SYSREG_PMPADDR46 = 0x3de,
|
||||
RISCV_SYSREG_PMPADDR47 = 0x3df,
|
||||
RISCV_SYSREG_PMPADDR48 = 0x3e0,
|
||||
RISCV_SYSREG_PMPADDR49 = 0x3e1,
|
||||
RISCV_SYSREG_PMPADDR50 = 0x3e2,
|
||||
RISCV_SYSREG_PMPADDR51 = 0x3e3,
|
||||
RISCV_SYSREG_PMPADDR52 = 0x3e4,
|
||||
RISCV_SYSREG_PMPADDR53 = 0x3e5,
|
||||
RISCV_SYSREG_PMPADDR54 = 0x3e6,
|
||||
RISCV_SYSREG_PMPADDR55 = 0x3e7,
|
||||
RISCV_SYSREG_PMPADDR56 = 0x3e8,
|
||||
RISCV_SYSREG_PMPADDR57 = 0x3e9,
|
||||
RISCV_SYSREG_PMPADDR58 = 0x3ea,
|
||||
RISCV_SYSREG_PMPADDR59 = 0x3eb,
|
||||
RISCV_SYSREG_PMPADDR60 = 0x3ec,
|
||||
RISCV_SYSREG_PMPADDR61 = 0x3ed,
|
||||
RISCV_SYSREG_PMPADDR62 = 0x3ee,
|
||||
RISCV_SYSREG_PMPADDR63 = 0x3ef,
|
||||
RISCV_SYSREG_SCONTEXT = 0x5a8,
|
||||
RISCV_SYSREG_HSTATUS = 0x600,
|
||||
RISCV_SYSREG_HEDELEG = 0x602,
|
||||
RISCV_SYSREG_HIDELEG = 0x603,
|
||||
RISCV_SYSREG_HIE = 0x604,
|
||||
RISCV_SYSREG_HTIMEDELTA = 0x605,
|
||||
RISCV_SYSREG_HCOUNTEREN = 0x606,
|
||||
RISCV_SYSREG_HGEIE = 0x607,
|
||||
RISCV_SYSREG_HVIEN = 0x608,
|
||||
RISCV_SYSREG_HVICTL = 0x609,
|
||||
RISCV_SYSREG_HENVCFG = 0x60a,
|
||||
RISCV_SYSREG_HSTATEEN0 = 0x60c,
|
||||
RISCV_SYSREG_HSTATEEN1 = 0x60d,
|
||||
RISCV_SYSREG_HSTATEEN2 = 0x60e,
|
||||
RISCV_SYSREG_HSTATEEN3 = 0x60f,
|
||||
RISCV_SYSREG_HIDELEGH = 0x613,
|
||||
RISCV_SYSREG_HTIMEDELTAH = 0x615,
|
||||
RISCV_SYSREG_HVIENH = 0x618,
|
||||
RISCV_SYSREG_HENVCFGH = 0x61a,
|
||||
RISCV_SYSREG_HSTATEEN0H = 0x61c,
|
||||
RISCV_SYSREG_HSTATEEN1H = 0x61d,
|
||||
RISCV_SYSREG_HSTATEEN2H = 0x61e,
|
||||
RISCV_SYSREG_HSTATEEN3H = 0x61f,
|
||||
RISCV_SYSREG_HTVAL = 0x643,
|
||||
RISCV_SYSREG_HIP = 0x644,
|
||||
RISCV_SYSREG_HVIP = 0x645,
|
||||
RISCV_SYSREG_HVIPRIO1 = 0x646,
|
||||
RISCV_SYSREG_HVIPRIO2 = 0x647,
|
||||
RISCV_SYSREG_HTINST = 0x64a,
|
||||
RISCV_SYSREG_HVIPH = 0x655,
|
||||
RISCV_SYSREG_HVIPRIO1H = 0x656,
|
||||
RISCV_SYSREG_HVIPRIO2H = 0x657,
|
||||
RISCV_SYSREG_HGATP = 0x680,
|
||||
RISCV_SYSREG_HCONTEXT = 0x6a8,
|
||||
RISCV_SYSREG_MHPMEVENT3H = 0x723,
|
||||
RISCV_SYSREG_MHPMEVENT4H = 0x724,
|
||||
RISCV_SYSREG_MHPMEVENT5H = 0x725,
|
||||
RISCV_SYSREG_MHPMEVENT6H = 0x726,
|
||||
RISCV_SYSREG_MHPMEVENT7H = 0x727,
|
||||
RISCV_SYSREG_MHPMEVENT8H = 0x728,
|
||||
RISCV_SYSREG_MHPMEVENT9H = 0x729,
|
||||
RISCV_SYSREG_MHPMEVENT10H = 0x72a,
|
||||
RISCV_SYSREG_MHPMEVENT11H = 0x72b,
|
||||
RISCV_SYSREG_MHPMEVENT12H = 0x72c,
|
||||
RISCV_SYSREG_MHPMEVENT13H = 0x72d,
|
||||
RISCV_SYSREG_MHPMEVENT14H = 0x72e,
|
||||
RISCV_SYSREG_MHPMEVENT15H = 0x72f,
|
||||
RISCV_SYSREG_MHPMEVENT16H = 0x730,
|
||||
RISCV_SYSREG_MHPMEVENT17H = 0x731,
|
||||
RISCV_SYSREG_MHPMEVENT18H = 0x732,
|
||||
RISCV_SYSREG_MHPMEVENT19H = 0x733,
|
||||
RISCV_SYSREG_MHPMEVENT20H = 0x734,
|
||||
RISCV_SYSREG_MHPMEVENT21H = 0x735,
|
||||
RISCV_SYSREG_MHPMEVENT22H = 0x736,
|
||||
RISCV_SYSREG_MHPMEVENT23H = 0x737,
|
||||
RISCV_SYSREG_MHPMEVENT24H = 0x738,
|
||||
RISCV_SYSREG_MHPMEVENT25H = 0x739,
|
||||
RISCV_SYSREG_MHPMEVENT26H = 0x73a,
|
||||
RISCV_SYSREG_MHPMEVENT27H = 0x73b,
|
||||
RISCV_SYSREG_MHPMEVENT28H = 0x73c,
|
||||
RISCV_SYSREG_MHPMEVENT29H = 0x73d,
|
||||
RISCV_SYSREG_MHPMEVENT30H = 0x73e,
|
||||
RISCV_SYSREG_MHPMEVENT31H = 0x73f,
|
||||
RISCV_SYSREG_MSECCFG = 0x747,
|
||||
RISCV_SYSREG_MSECCFGH = 0x757,
|
||||
RISCV_SYSREG_TSELECT = 0x7a0,
|
||||
RISCV_SYSREG_TDATA1 = 0x7a1,
|
||||
RISCV_SYSREG_TDATA2 = 0x7a2,
|
||||
RISCV_SYSREG_TDATA3 = 0x7a3,
|
||||
RISCV_SYSREG_MCONTEXT = 0x7a8,
|
||||
RISCV_SYSREG_DCSR = 0x7b0,
|
||||
RISCV_SYSREG_DPC = 0x7b1,
|
||||
RISCV_SYSREG_DSCRATCH0 = 0x7b2,
|
||||
RISCV_SYSREG_DSCRATCH = 0x7b2,
|
||||
RISCV_SYSREG_DSCRATCH1 = 0x7b3,
|
||||
RISCV_SYSREG_MCYCLE = 0xb00,
|
||||
RISCV_SYSREG_MINSTRET = 0xb02,
|
||||
RISCV_SYSREG_MHPMCOUNTER3 = 0xb03,
|
||||
RISCV_SYSREG_MHPMCOUNTER4 = 0xb04,
|
||||
RISCV_SYSREG_MHPMCOUNTER5 = 0xb05,
|
||||
RISCV_SYSREG_MHPMCOUNTER6 = 0xb06,
|
||||
RISCV_SYSREG_MHPMCOUNTER7 = 0xb07,
|
||||
RISCV_SYSREG_MHPMCOUNTER8 = 0xb08,
|
||||
RISCV_SYSREG_MHPMCOUNTER9 = 0xb09,
|
||||
RISCV_SYSREG_MHPMCOUNTER10 = 0xb0a,
|
||||
RISCV_SYSREG_MHPMCOUNTER11 = 0xb0b,
|
||||
RISCV_SYSREG_MHPMCOUNTER12 = 0xb0c,
|
||||
RISCV_SYSREG_MHPMCOUNTER13 = 0xb0d,
|
||||
RISCV_SYSREG_MHPMCOUNTER14 = 0xb0e,
|
||||
RISCV_SYSREG_MHPMCOUNTER15 = 0xb0f,
|
||||
RISCV_SYSREG_MHPMCOUNTER16 = 0xb10,
|
||||
RISCV_SYSREG_MHPMCOUNTER17 = 0xb11,
|
||||
RISCV_SYSREG_MHPMCOUNTER18 = 0xb12,
|
||||
RISCV_SYSREG_MHPMCOUNTER19 = 0xb13,
|
||||
RISCV_SYSREG_MHPMCOUNTER20 = 0xb14,
|
||||
RISCV_SYSREG_MHPMCOUNTER21 = 0xb15,
|
||||
RISCV_SYSREG_MHPMCOUNTER22 = 0xb16,
|
||||
RISCV_SYSREG_MHPMCOUNTER23 = 0xb17,
|
||||
RISCV_SYSREG_MHPMCOUNTER24 = 0xb18,
|
||||
RISCV_SYSREG_MHPMCOUNTER25 = 0xb19,
|
||||
RISCV_SYSREG_MHPMCOUNTER26 = 0xb1a,
|
||||
RISCV_SYSREG_MHPMCOUNTER27 = 0xb1b,
|
||||
RISCV_SYSREG_MHPMCOUNTER28 = 0xb1c,
|
||||
RISCV_SYSREG_MHPMCOUNTER29 = 0xb1d,
|
||||
RISCV_SYSREG_MHPMCOUNTER30 = 0xb1e,
|
||||
RISCV_SYSREG_MHPMCOUNTER31 = 0xb1f,
|
||||
RISCV_SYSREG_MCYCLEH = 0xb80,
|
||||
RISCV_SYSREG_MINSTRETH = 0xb82,
|
||||
RISCV_SYSREG_MHPMCOUNTER3H = 0xb83,
|
||||
RISCV_SYSREG_MHPMCOUNTER4H = 0xb84,
|
||||
RISCV_SYSREG_MHPMCOUNTER5H = 0xb85,
|
||||
RISCV_SYSREG_MHPMCOUNTER6H = 0xb86,
|
||||
RISCV_SYSREG_MHPMCOUNTER7H = 0xb87,
|
||||
RISCV_SYSREG_MHPMCOUNTER8H = 0xb88,
|
||||
RISCV_SYSREG_MHPMCOUNTER9H = 0xb89,
|
||||
RISCV_SYSREG_MHPMCOUNTER10H = 0xb8a,
|
||||
RISCV_SYSREG_MHPMCOUNTER11H = 0xb8b,
|
||||
RISCV_SYSREG_MHPMCOUNTER12H = 0xb8c,
|
||||
RISCV_SYSREG_MHPMCOUNTER13H = 0xb8d,
|
||||
RISCV_SYSREG_MHPMCOUNTER14H = 0xb8e,
|
||||
RISCV_SYSREG_MHPMCOUNTER15H = 0xb8f,
|
||||
RISCV_SYSREG_MHPMCOUNTER16H = 0xb90,
|
||||
RISCV_SYSREG_MHPMCOUNTER17H = 0xb91,
|
||||
RISCV_SYSREG_MHPMCOUNTER18H = 0xb92,
|
||||
RISCV_SYSREG_MHPMCOUNTER19H = 0xb93,
|
||||
RISCV_SYSREG_MHPMCOUNTER20H = 0xb94,
|
||||
RISCV_SYSREG_MHPMCOUNTER21H = 0xb95,
|
||||
RISCV_SYSREG_MHPMCOUNTER22H = 0xb96,
|
||||
RISCV_SYSREG_MHPMCOUNTER23H = 0xb97,
|
||||
RISCV_SYSREG_MHPMCOUNTER24H = 0xb98,
|
||||
RISCV_SYSREG_MHPMCOUNTER25H = 0xb99,
|
||||
RISCV_SYSREG_MHPMCOUNTER26H = 0xb9a,
|
||||
RISCV_SYSREG_MHPMCOUNTER27H = 0xb9b,
|
||||
RISCV_SYSREG_MHPMCOUNTER28H = 0xb9c,
|
||||
RISCV_SYSREG_MHPMCOUNTER29H = 0xb9d,
|
||||
RISCV_SYSREG_MHPMCOUNTER30H = 0xb9e,
|
||||
RISCV_SYSREG_MHPMCOUNTER31H = 0xb9f,
|
||||
RISCV_SYSREG_CYCLE = 0xc00,
|
||||
RISCV_SYSREG_TIME = 0xc01,
|
||||
RISCV_SYSREG_INSTRET = 0xc02,
|
||||
RISCV_SYSREG_HPMCOUNTER3 = 0xc03,
|
||||
RISCV_SYSREG_HPMCOUNTER4 = 0xc04,
|
||||
RISCV_SYSREG_HPMCOUNTER5 = 0xc05,
|
||||
RISCV_SYSREG_HPMCOUNTER6 = 0xc06,
|
||||
RISCV_SYSREG_HPMCOUNTER7 = 0xc07,
|
||||
RISCV_SYSREG_HPMCOUNTER8 = 0xc08,
|
||||
RISCV_SYSREG_HPMCOUNTER9 = 0xc09,
|
||||
RISCV_SYSREG_HPMCOUNTER10 = 0xc0a,
|
||||
RISCV_SYSREG_HPMCOUNTER11 = 0xc0b,
|
||||
RISCV_SYSREG_HPMCOUNTER12 = 0xc0c,
|
||||
RISCV_SYSREG_HPMCOUNTER13 = 0xc0d,
|
||||
RISCV_SYSREG_HPMCOUNTER14 = 0xc0e,
|
||||
RISCV_SYSREG_HPMCOUNTER15 = 0xc0f,
|
||||
RISCV_SYSREG_HPMCOUNTER16 = 0xc10,
|
||||
RISCV_SYSREG_HPMCOUNTER17 = 0xc11,
|
||||
RISCV_SYSREG_HPMCOUNTER18 = 0xc12,
|
||||
RISCV_SYSREG_HPMCOUNTER19 = 0xc13,
|
||||
RISCV_SYSREG_HPMCOUNTER20 = 0xc14,
|
||||
RISCV_SYSREG_HPMCOUNTER21 = 0xc15,
|
||||
RISCV_SYSREG_HPMCOUNTER22 = 0xc16,
|
||||
RISCV_SYSREG_HPMCOUNTER23 = 0xc17,
|
||||
RISCV_SYSREG_HPMCOUNTER24 = 0xc18,
|
||||
RISCV_SYSREG_HPMCOUNTER25 = 0xc19,
|
||||
RISCV_SYSREG_HPMCOUNTER26 = 0xc1a,
|
||||
RISCV_SYSREG_HPMCOUNTER27 = 0xc1b,
|
||||
RISCV_SYSREG_HPMCOUNTER28 = 0xc1c,
|
||||
RISCV_SYSREG_HPMCOUNTER29 = 0xc1d,
|
||||
RISCV_SYSREG_HPMCOUNTER30 = 0xc1e,
|
||||
RISCV_SYSREG_HPMCOUNTER31 = 0xc1f,
|
||||
RISCV_SYSREG_VL = 0xc20,
|
||||
RISCV_SYSREG_VTYPE = 0xc21,
|
||||
RISCV_SYSREG_VLENB = 0xc22,
|
||||
RISCV_SYSREG_CYCLEH = 0xc80,
|
||||
RISCV_SYSREG_TIMEH = 0xc81,
|
||||
RISCV_SYSREG_INSTRETH = 0xc82,
|
||||
RISCV_SYSREG_HPMCOUNTER3H = 0xc83,
|
||||
RISCV_SYSREG_HPMCOUNTER4H = 0xc84,
|
||||
RISCV_SYSREG_HPMCOUNTER5H = 0xc85,
|
||||
RISCV_SYSREG_HPMCOUNTER6H = 0xc86,
|
||||
RISCV_SYSREG_HPMCOUNTER7H = 0xc87,
|
||||
RISCV_SYSREG_HPMCOUNTER8H = 0xc88,
|
||||
RISCV_SYSREG_HPMCOUNTER9H = 0xc89,
|
||||
RISCV_SYSREG_HPMCOUNTER10H = 0xc8a,
|
||||
RISCV_SYSREG_HPMCOUNTER11H = 0xc8b,
|
||||
RISCV_SYSREG_HPMCOUNTER12H = 0xc8c,
|
||||
RISCV_SYSREG_HPMCOUNTER13H = 0xc8d,
|
||||
RISCV_SYSREG_HPMCOUNTER14H = 0xc8e,
|
||||
RISCV_SYSREG_HPMCOUNTER15H = 0xc8f,
|
||||
RISCV_SYSREG_HPMCOUNTER16H = 0xc90,
|
||||
RISCV_SYSREG_HPMCOUNTER17H = 0xc91,
|
||||
RISCV_SYSREG_HPMCOUNTER18H = 0xc92,
|
||||
RISCV_SYSREG_HPMCOUNTER19H = 0xc93,
|
||||
RISCV_SYSREG_HPMCOUNTER20H = 0xc94,
|
||||
RISCV_SYSREG_HPMCOUNTER21H = 0xc95,
|
||||
RISCV_SYSREG_HPMCOUNTER22H = 0xc96,
|
||||
RISCV_SYSREG_HPMCOUNTER23H = 0xc97,
|
||||
RISCV_SYSREG_HPMCOUNTER24H = 0xc98,
|
||||
RISCV_SYSREG_HPMCOUNTER25H = 0xc99,
|
||||
RISCV_SYSREG_HPMCOUNTER26H = 0xc9a,
|
||||
RISCV_SYSREG_HPMCOUNTER27H = 0xc9b,
|
||||
RISCV_SYSREG_HPMCOUNTER28H = 0xc9c,
|
||||
RISCV_SYSREG_HPMCOUNTER29H = 0xc9d,
|
||||
RISCV_SYSREG_HPMCOUNTER30H = 0xc9e,
|
||||
RISCV_SYSREG_HPMCOUNTER31H = 0xc9f,
|
||||
RISCV_SYSREG_SCOUNTOVF = 0xda0,
|
||||
RISCV_SYSREG_STOPI = 0xdb0,
|
||||
RISCV_SYSREG_HGEIP = 0xe12,
|
||||
RISCV_SYSREG_VSTOPI = 0xeb0,
|
||||
RISCV_SYSREG_MVENDORID = 0xf11,
|
||||
RISCV_SYSREG_MARCHID = 0xf12,
|
||||
RISCV_SYSREG_MIMPID = 0xf13,
|
||||
RISCV_SYSREG_MHARTID = 0xf14,
|
||||
RISCV_SYSREG_MCONFIGPTR = 0xf15,
|
||||
RISCV_SYSREG_MTOPI = 0xfb0,
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+27679
File diff suppressed because it is too large
Load Diff
+2798
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,211 @@
|
||||
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
||||
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Do not edit. */
|
||||
|
||||
/* Capstone's LLVM TableGen Backends: */
|
||||
/* https://github.com/capstone-engine/llvm-capstone */
|
||||
|
||||
#ifdef GET_SUBTARGETINFO_ENUM
|
||||
#undef GET_SUBTARGETINFO_ENUM
|
||||
|
||||
enum {
|
||||
RISCV_Experimental = 0,
|
||||
RISCV_Feature32Bit = 1,
|
||||
RISCV_Feature64Bit = 2,
|
||||
RISCV_FeatureFastUnalignedAccess = 3,
|
||||
RISCV_FeatureForcedAtomics = 4,
|
||||
RISCV_FeatureNoRVCHints = 5,
|
||||
RISCV_FeaturePostRAScheduler = 6,
|
||||
RISCV_FeatureRVE = 7,
|
||||
RISCV_FeatureRelax = 8,
|
||||
RISCV_FeatureReserveX1 = 9,
|
||||
RISCV_FeatureReserveX2 = 10,
|
||||
RISCV_FeatureReserveX3 = 11,
|
||||
RISCV_FeatureReserveX4 = 12,
|
||||
RISCV_FeatureReserveX5 = 13,
|
||||
RISCV_FeatureReserveX6 = 14,
|
||||
RISCV_FeatureReserveX7 = 15,
|
||||
RISCV_FeatureReserveX8 = 16,
|
||||
RISCV_FeatureReserveX9 = 17,
|
||||
RISCV_FeatureReserveX10 = 18,
|
||||
RISCV_FeatureReserveX11 = 19,
|
||||
RISCV_FeatureReserveX12 = 20,
|
||||
RISCV_FeatureReserveX13 = 21,
|
||||
RISCV_FeatureReserveX14 = 22,
|
||||
RISCV_FeatureReserveX15 = 23,
|
||||
RISCV_FeatureReserveX16 = 24,
|
||||
RISCV_FeatureReserveX17 = 25,
|
||||
RISCV_FeatureReserveX18 = 26,
|
||||
RISCV_FeatureReserveX19 = 27,
|
||||
RISCV_FeatureReserveX20 = 28,
|
||||
RISCV_FeatureReserveX21 = 29,
|
||||
RISCV_FeatureReserveX22 = 30,
|
||||
RISCV_FeatureReserveX23 = 31,
|
||||
RISCV_FeatureReserveX24 = 32,
|
||||
RISCV_FeatureReserveX25 = 33,
|
||||
RISCV_FeatureReserveX26 = 34,
|
||||
RISCV_FeatureReserveX27 = 35,
|
||||
RISCV_FeatureReserveX28 = 36,
|
||||
RISCV_FeatureReserveX29 = 37,
|
||||
RISCV_FeatureReserveX30 = 38,
|
||||
RISCV_FeatureReserveX31 = 39,
|
||||
RISCV_FeatureSaveRestore = 40,
|
||||
RISCV_FeatureStdExtA = 41,
|
||||
RISCV_FeatureStdExtC = 42,
|
||||
RISCV_FeatureStdExtD = 43,
|
||||
RISCV_FeatureStdExtF = 44,
|
||||
RISCV_FeatureStdExtH = 45,
|
||||
RISCV_FeatureStdExtI = 46,
|
||||
RISCV_FeatureStdExtM = 47,
|
||||
RISCV_FeatureStdExtSmaia = 48,
|
||||
RISCV_FeatureStdExtSmepmp = 49,
|
||||
RISCV_FeatureStdExtSsaia = 50,
|
||||
RISCV_FeatureStdExtSvinval = 51,
|
||||
RISCV_FeatureStdExtSvnapot = 52,
|
||||
RISCV_FeatureStdExtSvpbmt = 53,
|
||||
RISCV_FeatureStdExtV = 54,
|
||||
RISCV_FeatureStdExtZa64rs = 55,
|
||||
RISCV_FeatureStdExtZa128rs = 56,
|
||||
RISCV_FeatureStdExtZacas = 57,
|
||||
RISCV_FeatureStdExtZawrs = 58,
|
||||
RISCV_FeatureStdExtZba = 59,
|
||||
RISCV_FeatureStdExtZbb = 60,
|
||||
RISCV_FeatureStdExtZbc = 61,
|
||||
RISCV_FeatureStdExtZbkb = 62,
|
||||
RISCV_FeatureStdExtZbkc = 63,
|
||||
RISCV_FeatureStdExtZbkx = 64,
|
||||
RISCV_FeatureStdExtZbs = 65,
|
||||
RISCV_FeatureStdExtZca = 66,
|
||||
RISCV_FeatureStdExtZcb = 67,
|
||||
RISCV_FeatureStdExtZcd = 68,
|
||||
RISCV_FeatureStdExtZce = 69,
|
||||
RISCV_FeatureStdExtZcf = 70,
|
||||
RISCV_FeatureStdExtZcmop = 71,
|
||||
RISCV_FeatureStdExtZcmp = 72,
|
||||
RISCV_FeatureStdExtZcmt = 73,
|
||||
RISCV_FeatureStdExtZdinx = 74,
|
||||
RISCV_FeatureStdExtZfa = 75,
|
||||
RISCV_FeatureStdExtZfbfmin = 76,
|
||||
RISCV_FeatureStdExtZfh = 77,
|
||||
RISCV_FeatureStdExtZfhmin = 78,
|
||||
RISCV_FeatureStdExtZfinx = 79,
|
||||
RISCV_FeatureStdExtZhinx = 80,
|
||||
RISCV_FeatureStdExtZhinxmin = 81,
|
||||
RISCV_FeatureStdExtZic64b = 82,
|
||||
RISCV_FeatureStdExtZicbom = 83,
|
||||
RISCV_FeatureStdExtZicbop = 84,
|
||||
RISCV_FeatureStdExtZicboz = 85,
|
||||
RISCV_FeatureStdExtZiccamoa = 86,
|
||||
RISCV_FeatureStdExtZiccif = 87,
|
||||
RISCV_FeatureStdExtZicclsm = 88,
|
||||
RISCV_FeatureStdExtZiccrse = 89,
|
||||
RISCV_FeatureStdExtZicfilp = 90,
|
||||
RISCV_FeatureStdExtZicfiss = 91,
|
||||
RISCV_FeatureStdExtZicntr = 92,
|
||||
RISCV_FeatureStdExtZicond = 93,
|
||||
RISCV_FeatureStdExtZicsr = 94,
|
||||
RISCV_FeatureStdExtZifencei = 95,
|
||||
RISCV_FeatureStdExtZihintntl = 96,
|
||||
RISCV_FeatureStdExtZihintpause = 97,
|
||||
RISCV_FeatureStdExtZihpm = 98,
|
||||
RISCV_FeatureStdExtZimop = 99,
|
||||
RISCV_FeatureStdExtZk = 100,
|
||||
RISCV_FeatureStdExtZkn = 101,
|
||||
RISCV_FeatureStdExtZknd = 102,
|
||||
RISCV_FeatureStdExtZkne = 103,
|
||||
RISCV_FeatureStdExtZknh = 104,
|
||||
RISCV_FeatureStdExtZkr = 105,
|
||||
RISCV_FeatureStdExtZks = 106,
|
||||
RISCV_FeatureStdExtZksed = 107,
|
||||
RISCV_FeatureStdExtZksh = 108,
|
||||
RISCV_FeatureStdExtZkt = 109,
|
||||
RISCV_FeatureStdExtZmmul = 110,
|
||||
RISCV_FeatureStdExtZtso = 111,
|
||||
RISCV_FeatureStdExtZvbb = 112,
|
||||
RISCV_FeatureStdExtZvbc = 113,
|
||||
RISCV_FeatureStdExtZve32f = 114,
|
||||
RISCV_FeatureStdExtZve32x = 115,
|
||||
RISCV_FeatureStdExtZve64d = 116,
|
||||
RISCV_FeatureStdExtZve64f = 117,
|
||||
RISCV_FeatureStdExtZve64x = 118,
|
||||
RISCV_FeatureStdExtZvfbfmin = 119,
|
||||
RISCV_FeatureStdExtZvfbfwma = 120,
|
||||
RISCV_FeatureStdExtZvfh = 121,
|
||||
RISCV_FeatureStdExtZvfhmin = 122,
|
||||
RISCV_FeatureStdExtZvkb = 123,
|
||||
RISCV_FeatureStdExtZvkg = 124,
|
||||
RISCV_FeatureStdExtZvkn = 125,
|
||||
RISCV_FeatureStdExtZvknc = 126,
|
||||
RISCV_FeatureStdExtZvkned = 127,
|
||||
RISCV_FeatureStdExtZvkng = 128,
|
||||
RISCV_FeatureStdExtZvknha = 129,
|
||||
RISCV_FeatureStdExtZvknhb = 130,
|
||||
RISCV_FeatureStdExtZvks = 131,
|
||||
RISCV_FeatureStdExtZvksc = 132,
|
||||
RISCV_FeatureStdExtZvksed = 133,
|
||||
RISCV_FeatureStdExtZvksg = 134,
|
||||
RISCV_FeatureStdExtZvksh = 135,
|
||||
RISCV_FeatureStdExtZvkt = 136,
|
||||
RISCV_FeatureStdExtZvl32b = 137,
|
||||
RISCV_FeatureStdExtZvl64b = 138,
|
||||
RISCV_FeatureStdExtZvl128b = 139,
|
||||
RISCV_FeatureStdExtZvl256b = 140,
|
||||
RISCV_FeatureStdExtZvl512b = 141,
|
||||
RISCV_FeatureStdExtZvl1024b = 142,
|
||||
RISCV_FeatureStdExtZvl2048b = 143,
|
||||
RISCV_FeatureStdExtZvl4096b = 144,
|
||||
RISCV_FeatureStdExtZvl8192b = 145,
|
||||
RISCV_FeatureStdExtZvl16384b = 146,
|
||||
RISCV_FeatureStdExtZvl32768b = 147,
|
||||
RISCV_FeatureStdExtZvl65536b = 148,
|
||||
RISCV_FeatureTaggedGlobals = 149,
|
||||
RISCV_FeatureTrailingSeqCstFence = 150,
|
||||
RISCV_FeatureVendorXCValu = 151,
|
||||
RISCV_FeatureVendorXCVbi = 152,
|
||||
RISCV_FeatureVendorXCVbitmanip = 153,
|
||||
RISCV_FeatureVendorXCVelw = 154,
|
||||
RISCV_FeatureVendorXCVmac = 155,
|
||||
RISCV_FeatureVendorXCVmem = 156,
|
||||
RISCV_FeatureVendorXCVsimd = 157,
|
||||
RISCV_FeatureVendorXSfvcp = 158,
|
||||
RISCV_FeatureVendorXSfvfnrclipxfqf = 159,
|
||||
RISCV_FeatureVendorXSfvfwmaccqqq = 160,
|
||||
RISCV_FeatureVendorXSfvqmaccdod = 161,
|
||||
RISCV_FeatureVendorXSfvqmaccqoq = 162,
|
||||
RISCV_FeatureVendorXTHeadBa = 163,
|
||||
RISCV_FeatureVendorXTHeadBb = 164,
|
||||
RISCV_FeatureVendorXTHeadBs = 165,
|
||||
RISCV_FeatureVendorXTHeadCmo = 166,
|
||||
RISCV_FeatureVendorXTHeadCondMov = 167,
|
||||
RISCV_FeatureVendorXTHeadFMemIdx = 168,
|
||||
RISCV_FeatureVendorXTHeadMac = 169,
|
||||
RISCV_FeatureVendorXTHeadMemIdx = 170,
|
||||
RISCV_FeatureVendorXTHeadMemPair = 171,
|
||||
RISCV_FeatureVendorXTHeadSync = 172,
|
||||
RISCV_FeatureVendorXTHeadVdot = 173,
|
||||
RISCV_FeatureVendorXVentanaCondOps = 174,
|
||||
RISCV_TuneAUIPCADDIFusion = 175,
|
||||
RISCV_TuneConditionalCompressedMoveFusion = 176,
|
||||
RISCV_TuneDLenFactor2 = 177,
|
||||
RISCV_TuneLDADDFusion = 178,
|
||||
RISCV_TuneLUIADDIFusion = 179,
|
||||
RISCV_TuneNoDefaultUnroll = 180,
|
||||
RISCV_TuneNoOptimizedZeroStrideLoad = 181,
|
||||
RISCV_TuneShiftedZExtWFusion = 182,
|
||||
RISCV_TuneShortForwardBranchOpt = 183,
|
||||
RISCV_TuneSiFive7 = 184,
|
||||
RISCV_TuneVentanaVeyron = 185,
|
||||
RISCV_TuneZExtHFusion = 186,
|
||||
RISCV_TuneZExtWFusion = 187,
|
||||
RISCV_NumSubtargetFeatures = 188
|
||||
};
|
||||
#endif // GET_SUBTARGETINFO_ENUM
|
||||
|
||||
|
||||
|
||||
+34192
File diff suppressed because it is too large
Load Diff
+448
@@ -0,0 +1,448 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This class prints an RISC-V MCInst to a .s file.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include <capstone/platform.h>
|
||||
#include "../../MathExtras.h"
|
||||
|
||||
#include "RISCVMapping.h"
|
||||
#include "RISCVInstPrinter.h"
|
||||
|
||||
#define GET_SUBTARGETINFO_ENUM
|
||||
#include "RISCVGenSubtargetInfo.inc"
|
||||
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "RISCVGenInstrInfo.inc"
|
||||
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "RISCVGenRegisterInfo.inc"
|
||||
|
||||
#define GET_SysRegsList_IMPL
|
||||
#include "RISCVGenSystemOperands.inc"
|
||||
|
||||
#define GEN_UNCOMPRESS_INSTR
|
||||
#include "RISCVGenCompressedInstructionsInfo.inc"
|
||||
|
||||
#include "RISCVMapping.h"
|
||||
#include "../../Mapping.h"
|
||||
|
||||
#define CONCAT(a, b) CONCAT_(a, b)
|
||||
#define CONCAT_(a, b) a##_##b
|
||||
|
||||
#define DEBUG_TYPE "asm-printer"
|
||||
|
||||
static void printCustomAliasOperand(MCInst *MI, uint64_t Address,
|
||||
unsigned OpIdx, unsigned PrintMethodIdx,
|
||||
SStream *OS);
|
||||
static inline void printRegName(SStream *O, MCRegister Reg);
|
||||
static inline void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
// Include the auto-generated portion of the assembly writer.
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "RISCVGenAsmWriter.inc"
|
||||
|
||||
// Print architectural register names rather than the ABI names (such as x2
|
||||
// instead of sp).
|
||||
// TODO: Make RISCVInstPrinter_doGetRegisterName non-static so that this can a
|
||||
// member.
|
||||
static bool ArchRegNames;
|
||||
|
||||
const char *doGetRegisterName(MCRegister Reg)
|
||||
{
|
||||
return getRegisterName(Reg, ArchRegNames ? RISCV_NoRegAltName :
|
||||
RISCV_ABIRegAltName);
|
||||
}
|
||||
|
||||
static inline void printRegName(SStream *O, MCRegister Reg)
|
||||
{
|
||||
SStream_concat0(markup_OS(O, Markup_Register), doGetRegisterName(Reg));
|
||||
}
|
||||
|
||||
bool haveRequiredFeatures(const RISCV_SysReg *Reg, MCInst *MI)
|
||||
{
|
||||
// Not in 32-bit mode.
|
||||
if (Reg->isRV32Only &&
|
||||
RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_Operand, OpNo);
|
||||
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNo));
|
||||
|
||||
if (MCOperand_isReg(MO)) {
|
||||
printRegName(O, MCOperand_getReg(MO));
|
||||
return;
|
||||
}
|
||||
|
||||
if (MCOperand_isImm(MO)) {
|
||||
printInt64(markup_OS(O, Markup_Immediate),
|
||||
MCOperand_getImm(MO));
|
||||
return;
|
||||
}
|
||||
|
||||
CS_ASSERT(MCOperand_isExpr(MO) &&
|
||||
"Unknown operand kind in printOperand");
|
||||
printExpr(O, MCOperand_getExpr(MO));
|
||||
}
|
||||
|
||||
void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_BranchOperand, OpNo);
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNo));
|
||||
if (!MCOperand_isImm(MO))
|
||||
return printOperand(MI, OpNo, O);
|
||||
|
||||
if (MI->csh->PrintBranchImmAsAddress) {
|
||||
uint64_t Target = Address + MCOperand_getImm(MO);
|
||||
if (!RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit))
|
||||
Target &= 0xffffffff;
|
||||
printUInt64(markup_OS(O, Markup_Target), Target);
|
||||
} else {
|
||||
printInt64(markup_OS(O, Markup_Target), MCOperand_getImm(MO));
|
||||
}
|
||||
}
|
||||
|
||||
void printCSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_CSRSystemRegister, OpNo);
|
||||
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
const RISCV_SysReg *SysReg = RISCV_lookupSysRegByEncoding(Imm);
|
||||
if (SysReg && haveRequiredFeatures(SysReg, MI))
|
||||
SStream_concat0(markup_OS(O, Markup_Register), SysReg->Name);
|
||||
else
|
||||
printUInt64(markup_OS(O, Markup_Register), Imm);
|
||||
}
|
||||
|
||||
void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_FenceArg, OpNo);
|
||||
unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
CS_ASSERT(((FenceArg >> 4) == 0) &&
|
||||
"Invalid immediate in printFenceArg");
|
||||
|
||||
if ((FenceArg & RISCVFenceField_I) != 0)
|
||||
SStream_concat0(O, "i");
|
||||
|
||||
if ((FenceArg & RISCVFenceField_O) != 0)
|
||||
SStream_concat0(O, "o");
|
||||
|
||||
if ((FenceArg & RISCVFenceField_R) != 0)
|
||||
SStream_concat0(O, "r");
|
||||
|
||||
if ((FenceArg & RISCVFenceField_W) != 0)
|
||||
SStream_concat0(O, "w");
|
||||
|
||||
if (FenceArg == 0)
|
||||
SStream_concat0(O, "0");
|
||||
}
|
||||
|
||||
void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_FRMArg, OpNo);
|
||||
unsigned FRMArg = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
if (!(MI->csh->syntax & CS_OPT_SYNTAX_NO_ALIAS_TEXT) &&
|
||||
FRMArg == RISCVFPRndMode_DYN)
|
||||
return;
|
||||
SStream_concat(O, "%s", ", ");
|
||||
SStream_concat0(O, RISCVFPRndMode_roundingModeToString(FRMArg));
|
||||
}
|
||||
|
||||
void printFRMArgLegacy(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_FRMArgLegacy, OpNo);
|
||||
unsigned FRMArg = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
// Never print rounding mode if it's the default 'rne'. This ensures the
|
||||
// output can still be parsed by older tools that erroneously failed to
|
||||
// accept a rounding mode.
|
||||
if (FRMArg == RISCVFPRndMode_RNE)
|
||||
return;
|
||||
SStream_concat(O, "%s", ", ");
|
||||
SStream_concat0(O, RISCVFPRndMode_roundingModeToString(FRMArg));
|
||||
}
|
||||
|
||||
void printFPImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_FPImmOperand, OpNo);
|
||||
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
if (Imm == 1) {
|
||||
SStream_concat0(markup_OS(O, Markup_Immediate), "min");
|
||||
} else if (Imm == 30) {
|
||||
SStream_concat0(markup_OS(O, Markup_Immediate), "inf");
|
||||
} else if (Imm == 31) {
|
||||
SStream_concat0(markup_OS(O, Markup_Immediate), "nan");
|
||||
} else {
|
||||
float FPVal = getFPImm(Imm);
|
||||
// If the value is an integer, print a .0 fraction. Otherwise, use %g to
|
||||
// which will not print trailing zeros and will use scientific notation
|
||||
// if it is shorter than printing as a decimal. The smallest value requires
|
||||
// 12 digits of precision including the decimal.
|
||||
if (FPVal == (int)(FPVal))
|
||||
printfFloat(markup_OS(O, Markup_Immediate), "%.1f",
|
||||
FPVal);
|
||||
else
|
||||
printfFloat(markup_OS(O, Markup_Immediate), "%.12g",
|
||||
FPVal);
|
||||
}
|
||||
}
|
||||
|
||||
void printZeroOffsetMemOp(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_ZeroOffsetMemOp, OpNo);
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNo));
|
||||
|
||||
CS_ASSERT(MCOperand_isReg(MO) &&
|
||||
"printZeroOffsetMemOp can only print register operands");
|
||||
SStream_concat0(O, "(");
|
||||
printRegName(O, MCOperand_getReg(MO));
|
||||
SStream_concat0(O, ")");
|
||||
}
|
||||
|
||||
void printVTypeI(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_VTypeI, OpNo);
|
||||
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
// Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
|
||||
// or non-zero in bits 8 and above.
|
||||
if (RISCVVType_getVLMUL(Imm) == RISCVII_LMUL_RESERVED ||
|
||||
RISCVVType_getSEW(Imm) > 64 || (Imm >> 8) != 0) {
|
||||
printUInt64(O, Imm);
|
||||
return;
|
||||
}
|
||||
// Print the text form.
|
||||
printVType(Imm, O);
|
||||
}
|
||||
|
||||
void printRlist(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_Rlist, OpNo);
|
||||
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
SStream_concat0(O, "{");
|
||||
switch (Imm) {
|
||||
case RISCVZC_RLISTENCODE_RA:
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x1" : "ra"));
|
||||
break;
|
||||
case RISCVZC_RLISTENCODE_RA_S0:
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x1" : "ra"));
|
||||
SStream_concat0(O, ", ");
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x8" : "s0"));
|
||||
break;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S1:
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x1" : "ra"));
|
||||
SStream_concat0(O, ", ");
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x8" : "s0"));
|
||||
SStream_concat0(O, "-");
|
||||
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x9" : "s1"));
|
||||
break;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S2:
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x1" : "ra"));
|
||||
SStream_concat0(O, ", ");
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x8" : "s0"));
|
||||
SStream_concat0(O, "-");
|
||||
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x9" : "s2"));
|
||||
if (ArchRegNames) {
|
||||
SStream_concat0(O, ", ");
|
||||
SStream_concat0(markup_OS(O, Markup_Register), "x18");
|
||||
}
|
||||
break;
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S3:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S4:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S5:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S6:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S7:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S8:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S9:
|
||||
case RISCVZC_RLISTENCODE_RA_S0_S11:
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x1" : "ra"));
|
||||
SStream_concat0(O, ", ");
|
||||
SStream_concat0(markup_OS(O, Markup_Register),
|
||||
(ArchRegNames ? "x8" : "s0"));
|
||||
SStream_concat0(O, "-");
|
||||
|
||||
if (ArchRegNames) {
|
||||
SStream_concat0(markup_OS(O, Markup_Register), "x9");
|
||||
SStream_concat0(O, ", ");
|
||||
SStream_concat0(markup_OS(O, Markup_Register), "x18");
|
||||
SStream_concat0(O, "-");
|
||||
}
|
||||
SStream_concat0(
|
||||
markup_OS(O, Markup_Register),
|
||||
doGetRegisterName(
|
||||
RISCV_X19 +
|
||||
(Imm == RISCVZC_RLISTENCODE_RA_S0_S11 ?
|
||||
8 :
|
||||
Imm - RISCVZC_RLISTENCODE_RA_S0_S3)));
|
||||
break;
|
||||
default:
|
||||
CS_ASSERT(0 && "invalid register list");
|
||||
}
|
||||
SStream_concat0(O, "}");
|
||||
}
|
||||
|
||||
void printRegReg(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_RegReg, OpNo);
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNo));
|
||||
|
||||
CS_ASSERT(MCOperand_isReg(MO) &&
|
||||
"printRegReg can only print register operands");
|
||||
if (MCOperand_getReg(MO) == RISCV_NoRegister)
|
||||
return;
|
||||
printRegName(O, MCOperand_getReg(MO));
|
||||
|
||||
SStream_concat0(O, "(");
|
||||
MCOperand *MO1 = MCInst_getOperand(MI, (OpNo + 1));
|
||||
CS_ASSERT(MCOperand_isReg(MO1) &&
|
||||
"printRegReg can only print register operands");
|
||||
printRegName(O, MCOperand_getReg(MO1));
|
||||
SStream_concat0(O, ")");
|
||||
}
|
||||
|
||||
void printSpimm(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_Spimm, OpNo);
|
||||
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
|
||||
unsigned Opcode = MCInst_getOpcode(MI);
|
||||
bool IsRV64 = RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit);
|
||||
bool IsEABI = RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureRVE);
|
||||
int64_t Spimm = 0;
|
||||
int64_t RlistVal = MCOperand_getImm(MCInst_getOperand(MI, (0)));
|
||||
CS_ASSERT(RlistVal != 16 && "Incorrect rlist.");
|
||||
unsigned Base = RISCVZC_getStackAdjBase(RlistVal, IsRV64, IsEABI);
|
||||
Spimm = Imm + Base;
|
||||
CS_ASSERT((Spimm >= Base && Spimm <= Base + 48) && "Incorrect spimm");
|
||||
if (Opcode == RISCV_CM_PUSH)
|
||||
Spimm = -Spimm;
|
||||
|
||||
RISCVZC_printSpimm(Spimm, markup_OS(O, Markup_Immediate));
|
||||
}
|
||||
|
||||
void printVMaskReg(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
RISCV_add_cs_detail_0(MI, RISCV_OP_GROUP_VMaskReg, OpNo);
|
||||
MCOperand *MO = MCInst_getOperand(MI, (OpNo));
|
||||
|
||||
CS_ASSERT(MCOperand_isReg(MO) &&
|
||||
"printVMaskReg can only print register operands");
|
||||
if (MCOperand_getReg(MO) == RISCV_NoRegister)
|
||||
return;
|
||||
SStream_concat0(O, ", ");
|
||||
printRegName(O, MCOperand_getReg(MO));
|
||||
SStream_concat0(O, ".t");
|
||||
}
|
||||
|
||||
void RISCV_LLVM_printInstruction(MCInst *MI, SStream *O,
|
||||
void * /* MCRegisterInfo* */ info)
|
||||
{
|
||||
MI->MRI = (MCRegisterInfo *)info;
|
||||
|
||||
MCInst_setIsAlias(MI, false);
|
||||
bool usesAliasDetails = map_use_alias_details(MI);
|
||||
MI->flat_insn->usesAliasDetails = usesAliasDetails;
|
||||
|
||||
/* check for a non-compressed instruction */
|
||||
MCInst Uncompressed;
|
||||
MCInst_Init(&Uncompressed, MI->csh->arch);
|
||||
|
||||
MCInst *McInstr = MI;
|
||||
bool is_uncompressed = false;
|
||||
// side-effectful check for compressed instructions that creates the equivalent uncompressed instruction in case of true
|
||||
// (LLVM doesn't generate an API for doing a pure check)
|
||||
if (uncompressInst(&Uncompressed, MI)) {
|
||||
McInstr = &Uncompressed;
|
||||
Uncompressed.address = MI->address;
|
||||
Uncompressed.MRI = MI->MRI;
|
||||
Uncompressed.csh = MI->csh;
|
||||
Uncompressed.flat_insn = MI->flat_insn;
|
||||
is_uncompressed = true;
|
||||
}
|
||||
|
||||
// print the exact instruction text and done
|
||||
bool print_exact_text =
|
||||
(MI->csh->syntax & CS_OPT_SYNTAX_NO_ALIAS_TEXT) ||
|
||||
(is_uncompressed &&
|
||||
MI->csh->syntax & CS_OPT_SYNTAX_NO_ALIAS_TEXT_COMPRESSED);
|
||||
if (print_exact_text) {
|
||||
printInstruction(MI, MI->address, O);
|
||||
} else {
|
||||
// side-effectful check for alias instructions that prints to the SStream if true
|
||||
if (printAliasInstr(McInstr, MI->address, O)) {
|
||||
MCInst_setIsAlias(MI, true);
|
||||
// do we still want the exact details even if the text is alias ?
|
||||
if (!usesAliasDetails && detail_is_set(MI)) {
|
||||
// disable actual printing
|
||||
SStream_Close(O);
|
||||
// discard the alias operands
|
||||
memset(MI->flat_insn->detail->riscv.operands, 0,
|
||||
sizeof(MI->flat_insn->detail->riscv
|
||||
.operands));
|
||||
MI->flat_insn->detail->riscv.op_count = 0;
|
||||
// re-disassemble again with no printing in order to obtain the full details
|
||||
// including the whole operands array
|
||||
printInstruction(MI, MI->address, O);
|
||||
// re-open the stream to restore the usual state
|
||||
SStream_Open(O);
|
||||
}
|
||||
} else // the instruction is not an alias
|
||||
printInstruction(McInstr, MI->address, O);
|
||||
}
|
||||
RISCV_add_groups(MI);
|
||||
RISCV_add_missing_write_access(MI);
|
||||
RISCV_compact_operands(MI);
|
||||
RISCV_set_alias_id(MI, O);
|
||||
}
|
||||
|
||||
const char *getSysRegName(unsigned reg)
|
||||
{
|
||||
const RISCV_SysReg *SysReg = RISCV_lookupSysRegByEncoding(reg);
|
||||
return SysReg->Name;
|
||||
}
|
||||
|
||||
const char *RISCV_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx)
|
||||
{
|
||||
return getRegisterName(RegNo, AltIdx);
|
||||
}
|
||||
|
||||
bool isCompressed(MCInst *MI)
|
||||
{
|
||||
MCInst unused;
|
||||
MCInst_Init(&unused, MI->csh->arch);
|
||||
return uncompressInst(&unused, MI);
|
||||
}
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
||||
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
||||
/* Automatically translated source file from LLVM. */
|
||||
|
||||
/* LLVM-commit: <commit> */
|
||||
/* LLVM-tag: <tag> */
|
||||
|
||||
/* Only small edits allowed. */
|
||||
/* For multiple similar edits, please create a Patch for the translator. */
|
||||
|
||||
/* Capstone's C++ file translator: */
|
||||
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
|
||||
|
||||
//===-- RISCVInstPrinter.h - Convert RISC-V MCInst to asm syntax --*- C++ -*--//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This class prints a RISC-V MCInst to a .s file.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVINSTPRINTER_H
|
||||
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVINSTPRINTER_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <capstone/platform.h>
|
||||
|
||||
#include "../../MCInstPrinter.h"
|
||||
#include "../../cs_priv.h"
|
||||
#include "../../SStream.h"
|
||||
#include "RISCVBaseInfo.h"
|
||||
#include "RISCVDisassemblerExtension.h"
|
||||
|
||||
#define CONCAT(a, b) CONCAT_(a, b)
|
||||
#define CONCAT_(a, b) a##_##b
|
||||
|
||||
void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
|
||||
SStream *O);
|
||||
void printCSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printFRMArgLegacy(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printFPImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printZeroOffsetMemOp(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printVTypeI(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printVMaskReg(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printRlist(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printSpimm(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
void printRegReg(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
|
||||
const char *RISCV_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
|
||||
|
||||
const char *getSysRegName(unsigned reg);
|
||||
|
||||
bool isCompressed(MCInst *MI);
|
||||
|
||||
#endif
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
#ifndef CS_MIPS_LINKAGE_H
|
||||
#define CS_MIPS_LINKAGE_H
|
||||
|
||||
#include "../../MCDisassembler.h"
|
||||
#include "../../MCInst.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "../../SStream.h"
|
||||
#include "capstone/capstone.h"
|
||||
|
||||
bool RISCV_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
|
||||
MCInst *MI, uint16_t *Size, uint64_t Address,
|
||||
void *Info);
|
||||
const char *RISCV_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
|
||||
void RISCV_LLVM_printInstruction(MCInst *MI, SStream *O,
|
||||
void * /* MCRegisterInfo* */ info);
|
||||
|
||||
#endif // CS_MIPS_LINKAGE_H
|
||||
+480
@@ -0,0 +1,480 @@
|
||||
#include "capstone/cs_operand.h"
|
||||
#include "capstone/riscv.h"
|
||||
#include <stdint.h>
|
||||
#include <float.h>
|
||||
#include <math.h>
|
||||
#ifdef CAPSTONE_HAS_RISCV
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "../../Mapping.h"
|
||||
#include "../../cs_simple_types.h"
|
||||
#include "../../utils.h"
|
||||
|
||||
#include "RISCVMapping.h"
|
||||
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "RISCVGenInstrInfo.inc"
|
||||
|
||||
#define GET_REGINFO_ENUM
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#include "RISCVGenRegisterInfo.inc"
|
||||
|
||||
#include "RISCVInstPrinter.h"
|
||||
|
||||
const char *RISCV_reg_name(csh handle, unsigned int reg)
|
||||
{
|
||||
int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
|
||||
|
||||
if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
|
||||
return RISCV_LLVM_getRegisterName(reg, RISCV_NoRegAltName);
|
||||
}
|
||||
return RISCV_LLVM_getRegisterName(reg, RISCV_ABIRegAltName);
|
||||
}
|
||||
|
||||
static const insn_map insns[] = {
|
||||
#include "RISCVGenCSMappingInsn.inc"
|
||||
};
|
||||
|
||||
const insn_map *RISCV_insns = insns;
|
||||
const unsigned int RISCV_insn_count = ARR_SIZE(insns);
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const map_insn_ops insn_operands[] = {
|
||||
#include "RISCVGenCSMappingInsnOp.inc"
|
||||
};
|
||||
|
||||
static const name_map insn_alias_mnem_map[] = {
|
||||
#include "RISCVGenCSAliasMnemMap.inc"
|
||||
};
|
||||
#endif
|
||||
|
||||
void RISCV_add_cs_detail_0(MCInst *MI, riscv_op_group opgroup, unsigned OpNum)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
return;
|
||||
// are not "true" arguments and has no Capstone equivalent
|
||||
if (opgroup == RISCV_OP_GROUP_FRMArg ||
|
||||
opgroup == RISCV_OP_GROUP_FRMArgLegacy)
|
||||
return;
|
||||
|
||||
if (opgroup == RISCV_OP_GROUP_FPImmOperand) {
|
||||
unsigned Imm = (unsigned)MCInst_getOperand(MI, OpNum)->ImmVal;
|
||||
cs_riscv_op *op = RISCV_get_detail_op_at(MI, OpNum);
|
||||
op->type = RISCV_OP_FP;
|
||||
op->access = (cs_ac_type)map_get_op_access(MI, OpNum);
|
||||
switch (Imm) {
|
||||
case 1: // min
|
||||
switch (MI->Opcode) {
|
||||
case RISCV_FLI_S:
|
||||
op->dimm = (double)FLT_MIN;
|
||||
break;
|
||||
case RISCV_FLI_D:
|
||||
op->dimm = (double)DBL_MIN;
|
||||
break;
|
||||
case RISCV_FLI_H:
|
||||
op->dimm = 6.103515625e-05;
|
||||
break;
|
||||
default:
|
||||
op->dimm = 0.0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 30: // inf
|
||||
op->dimm = INFINITY;
|
||||
break;
|
||||
case 31: // nan
|
||||
op->dimm = NAN;
|
||||
break;
|
||||
default:
|
||||
op->dimm = (double)getFPImm(Imm);
|
||||
break;
|
||||
}
|
||||
RISCV_inc_op_count(MI);
|
||||
return;
|
||||
}
|
||||
cs_riscv_op *op = RISCV_get_detail_op_at(MI, OpNum);
|
||||
op->type = (riscv_op_type)map_get_op_type(MI, OpNum);
|
||||
op->access = (cs_ac_type)map_get_op_access(MI, OpNum);
|
||||
switch (map_get_op_type(MI, OpNum)) {
|
||||
case CS_OP_REG:
|
||||
op->reg = MCInst_getOperand(MI, OpNum)->RegVal;
|
||||
break;
|
||||
case CS_OP_MEM:
|
||||
op->mem.base = 0;
|
||||
op->mem.disp = MCInst_getOperand(MI, OpNum)->ImmVal;
|
||||
break;
|
||||
case CS_OP_IMM: {
|
||||
uint64_t val = MCInst_getOperand(MI, OpNum)->ImmVal;
|
||||
if (opgroup != RISCV_OP_GROUP_CSRSystemRegister) {
|
||||
op->imm = val;
|
||||
if (opgroup == RISCV_OP_GROUP_BranchOperand) {
|
||||
op->imm += MI->address;
|
||||
}
|
||||
} else /* system register read-write */ {
|
||||
op->type = RISCV_OP_CSR;
|
||||
op->csr = val;
|
||||
// CSR instruction always read-writes the system operand
|
||||
op->access = CS_AC_READ_WRITE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case CS_OP_MEM_REG:
|
||||
op->type = (riscv_op_type)CS_OP_MEM;
|
||||
op->mem.base = MCInst_getOperand(MI, OpNum)->RegVal;
|
||||
break;
|
||||
case CS_OP_MEM_IMM:
|
||||
// fill in the disp in the last operand
|
||||
op = RISCV_get_detail_op_at(MI, OpNum - 1);
|
||||
op->type = (riscv_op_type)CS_OP_MEM;
|
||||
op->mem.disp = MCInst_getOperand(MI, OpNum)->ImmVal;
|
||||
RISCV_dec_op_count(
|
||||
MI); // don't increase the count, cancel the coming increment
|
||||
break;
|
||||
case CS_OP_INVALID:
|
||||
break;
|
||||
default: {
|
||||
CS_ASSERT(0 && "unhandled operand type");
|
||||
}
|
||||
}
|
||||
RISCV_inc_op_count(MI);
|
||||
}
|
||||
|
||||
static inline void RISCV_add_adhoc_groups(MCInst *MI);
|
||||
|
||||
void RISCV_add_groups(MCInst *MI)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
return;
|
||||
|
||||
get_detail(MI)->groups_count = 0;
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
int i = 0;
|
||||
while (insns[MI->Opcode].groups[i] != 0) {
|
||||
add_group(MI, insns[MI->Opcode].groups[i]);
|
||||
i++;
|
||||
}
|
||||
#endif
|
||||
|
||||
RISCV_add_adhoc_groups(MI);
|
||||
}
|
||||
|
||||
enum {
|
||||
#define GET_ENUM_VALUES_RISCVOpcode
|
||||
#include "RISCVGenCSSystemOperandsEnum.inc"
|
||||
};
|
||||
|
||||
static inline void RISCV_add_privileged_group(MCInst *MI)
|
||||
{
|
||||
const uint8_t *bytes = MI->flat_insn->bytes;
|
||||
uint8_t opcode = bytes[0] & 0x80;
|
||||
// no privileged instruction has a major opcode other than SYSTEM
|
||||
if (opcode != RISCV_RISCVOPCODE_SYSTEM) {
|
||||
return;
|
||||
}
|
||||
uint8_t func3 = (bytes[1] >> 4) & 0x7;
|
||||
// no privileged instruction has a minor opcode other than PRIV or PRIVM
|
||||
if (func3 != 0 && func3 != 0x4) {
|
||||
return;
|
||||
}
|
||||
uint16_t func12 = readBytes16(MI, &(bytes[2])) >> 4;
|
||||
// ecall and ebreak has SYSTEM and PRIV but aren't privileged
|
||||
if (func12 == 0 || func12 == 1) {
|
||||
return;
|
||||
}
|
||||
uint8_t func6 = func12 >> 6;
|
||||
// a subspace under extension-defined custom SYSTEM instructions that is not privileged
|
||||
if (func6 == 0x23 || func6 == 0x33) {
|
||||
return;
|
||||
}
|
||||
add_group(MI, RISCV_GRP_PRIVILEGE);
|
||||
}
|
||||
|
||||
static inline void RISCV_add_interrupt_group(MCInst *MI)
|
||||
{
|
||||
if (MI->Opcode == RISCV_ECALL || MI->Opcode == RISCV_EBREAK) {
|
||||
add_group(MI, RISCV_GRP_INT);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void RISCV_add_interrupt_ret_group(MCInst *MI)
|
||||
{
|
||||
if (MI->Opcode == RISCV_MRET || MI->Opcode == RISCV_SRET) {
|
||||
add_group(MI, RISCV_GRP_IRET);
|
||||
}
|
||||
}
|
||||
|
||||
// calls are implemented in RISCV as plain jumps that happen to set a link register containing the return address
|
||||
// but this link register could be given as the null register x0, discarding the return address and making them jumps
|
||||
static inline void RISCV_add_call_group(MCInst *MI)
|
||||
{
|
||||
if (MI->Opcode == RISCV_JAL || MI->Opcode == RISCV_JALR) {
|
||||
cs_riscv_op *op = RISCV_get_detail_op_at(MI, 0);
|
||||
if ((op->type == (riscv_op_type)CS_OP_REG) &&
|
||||
op->reg != RISCV_REG_X0 && (op->access & CS_AC_WRITE)) {
|
||||
add_group(MI, RISCV_GRP_CALL);
|
||||
}
|
||||
if (MI->Opcode == RISCV_JAL) {
|
||||
add_group(MI, RISCV_GRP_BRANCH_RELATIVE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// returns are implemented in RISCV as a plain indirect jump that happen to reference the return address register ra == x1
|
||||
static inline void RISCV_add_ret_group(MCInst *MI)
|
||||
{
|
||||
if (MI->Opcode == RISCV_C_JR) {
|
||||
// indirect jumps whose source is ra
|
||||
cs_riscv_op *op = RISCV_get_detail_op_at(MI, 0);
|
||||
if ((op->type == (riscv_op_type)CS_OP_REG) &&
|
||||
op->reg == RISCV_REG_X1) {
|
||||
add_group(MI, RISCV_GRP_RET);
|
||||
} else {
|
||||
add_group(MI, RISCV_GRP_JUMP);
|
||||
}
|
||||
}
|
||||
if (MI->Opcode == RISCV_JALR) {
|
||||
// indirect jumps whose source is ra
|
||||
cs_riscv_op *dstreg = RISCV_get_detail_op_at(MI, 0);
|
||||
cs_riscv_op *op = RISCV_get_detail_op_at(MI, 1);
|
||||
cs_riscv_op *op2 = RISCV_get_detail_op_at(MI, 2);
|
||||
if ((op->type == (riscv_op_type)CS_OP_REG) &&
|
||||
op->reg == RISCV_REG_X1 &&
|
||||
op2->type == (riscv_op_type)CS_OP_IMM && op2->imm == 0 &&
|
||||
dstreg->type == (riscv_op_type)CS_OP_REG &&
|
||||
dstreg->reg == RISCV_REG_X0) {
|
||||
add_group(MI, RISCV_GRP_RET);
|
||||
} else {
|
||||
if (!((dstreg->type == (riscv_op_type)CS_OP_REG) &&
|
||||
dstreg->reg != RISCV_REG_X0 &&
|
||||
(dstreg->access & CS_AC_WRITE))) {
|
||||
add_group(MI, RISCV_GRP_JUMP);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void RISCV_add_adhoc_groups(MCInst *MI)
|
||||
{
|
||||
RISCV_add_privileged_group(MI);
|
||||
RISCV_add_interrupt_group(MI);
|
||||
RISCV_add_interrupt_ret_group(MI);
|
||||
RISCV_add_call_group(MI);
|
||||
RISCV_add_ret_group(MI);
|
||||
}
|
||||
|
||||
// memset all stalled values in the detail struct to 0 before disassembling any next instruction
|
||||
void RISCV_init_cs_detail(MCInst *MI)
|
||||
{
|
||||
if (detail_is_set(MI))
|
||||
memset(get_detail(MI), 0,
|
||||
offsetof(cs_detail, riscv) + sizeof(cs_riscv));
|
||||
}
|
||||
|
||||
// for weird reasons some instructions end up with valid operands that are
|
||||
// interspersed with invalid operands, i.e. the operands array is an "island"
|
||||
// of valid operands with invalid gaps between them, this function will compactify
|
||||
// all the valid operands and pad the rest of the array to invalid
|
||||
void RISCV_compact_operands(MCInst *MI)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
return;
|
||||
cs_riscv_op *ops = RISCV_get_detail(MI)->operands;
|
||||
unsigned int write_pos = 0;
|
||||
|
||||
// Move valid elements to front
|
||||
for (unsigned int read_pos = 0; read_pos < NUM_RISCV_OPS; read_pos++) {
|
||||
if (ops[read_pos].type != (riscv_op_type)CS_OP_INVALID) {
|
||||
if (write_pos != read_pos) {
|
||||
ops[write_pos] = ops[read_pos];
|
||||
}
|
||||
write_pos++;
|
||||
}
|
||||
}
|
||||
// fill the rest, if any, with invalid
|
||||
memset((void *)(&ops[write_pos]), CS_OP_INVALID,
|
||||
(NUM_RISCV_OPS - write_pos) * sizeof(cs_riscv_op));
|
||||
}
|
||||
|
||||
// some RISC-V instructions have only 2 apparent operands, one of them is read-write
|
||||
// the actual operand information for those instruction should have 3 operands, the first and second are the same operand,
|
||||
// but once with read and once write access
|
||||
// when those instructions are disassembled only the operand entry with the read access is used,
|
||||
// and therefore the read-write operand is wrongly classified as only-read
|
||||
// this logic tries to correct that
|
||||
void RISCV_add_missing_write_access(MCInst *MI)
|
||||
{
|
||||
if (!detail_is_set(MI))
|
||||
return;
|
||||
if (!isCompressed(MI))
|
||||
return;
|
||||
|
||||
cs_riscv *riscv_details = RISCV_get_detail(MI);
|
||||
cs_riscv_op *ops = riscv_details->operands;
|
||||
// make the detection condition as specific as possible
|
||||
// so it doesn't accidentally trigger for other cases
|
||||
if (riscv_details->op_count == 2 && ops[0].type == RISCV_OP_INVALID &&
|
||||
ops[1].type == RISCV_OP_REG && ops[1].access == CS_AC_READ) {
|
||||
ops[1].access |= CS_AC_WRITE;
|
||||
}
|
||||
}
|
||||
|
||||
// given internal insn id, return public instruction info
|
||||
void RISCV_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
||||
{
|
||||
insn_map const *insn_map = NULL;
|
||||
|
||||
if ((insn_map = lookup_insn_map(h, id))) {
|
||||
insn->id = insn_map->mapid;
|
||||
|
||||
if (h->detail_opt) {
|
||||
#ifndef CAPSTONE_DIET
|
||||
memcpy(insn->detail->regs_read, insn_map->regs_use,
|
||||
sizeof(insn_map->regs_use));
|
||||
insn->detail->regs_read_count =
|
||||
(uint8_t)count_positive(insn_map->regs_use);
|
||||
|
||||
memcpy(insn->detail->regs_write, insn_map->regs_mod,
|
||||
sizeof(insn_map->regs_mod));
|
||||
insn->detail->regs_write_count =
|
||||
(uint8_t)count_positive(insn_map->regs_mod);
|
||||
|
||||
memcpy(insn->detail->groups, insn_map->groups,
|
||||
sizeof(insn_map->groups));
|
||||
insn->detail->groups_count =
|
||||
(uint8_t)count_positive8(insn_map->groups);
|
||||
|
||||
if (insn_map->branch || insn_map->indirect_branch) {
|
||||
// this insn also belongs to JUMP group. add JUMP group
|
||||
insn->detail
|
||||
->groups[insn->detail->groups_count] =
|
||||
RISCV_GRP_JUMP;
|
||||
insn->detail->groups_count++;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const char *const insn_name_maps[] = {
|
||||
#include "RISCVGenCSMappingInsnName.inc"
|
||||
};
|
||||
|
||||
// called from RISCV_LLVM_printInstruction() to avoid exporting
|
||||
// insn_alias_mnem_map and its size via extern declarations
|
||||
void RISCV_set_alias_id(MCInst *MI, SStream *O)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
map_set_alias_id(MI, O, insn_alias_mnem_map,
|
||||
ARR_SIZE(insn_alias_mnem_map));
|
||||
#endif
|
||||
}
|
||||
|
||||
const char *RISCV_insn_name(csh handle, unsigned int id)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
if (id < RISCV_INS_ENDING)
|
||||
return insn_name_maps[id];
|
||||
|
||||
if (id < RISCV_INS_ALIAS_END)
|
||||
return insn_alias_mnem_map[id - RISCV_INS_ALIAS_BEGIN - 1].name;
|
||||
#endif
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ RISCV_GRP_INVALID, NULL },
|
||||
{ RISCV_GRP_JUMP, "jump" },
|
||||
{ RISCV_GRP_CALL, "call" },
|
||||
{ RISCV_GRP_RET, "ret" },
|
||||
{ RISCV_GRP_INT, "int" },
|
||||
{ RISCV_GRP_IRET, "iret" },
|
||||
{ RISCV_GRP_PRIVILEGE, "privileged" },
|
||||
{ RISCV_GRP_BRANCH_RELATIVE, "branch_relative" },
|
||||
|
||||
// architecture specific
|
||||
#include "RISCVGenCSFeatureName.inc"
|
||||
|
||||
{ RISCV_GRP_ENDING, NULL }
|
||||
};
|
||||
#endif
|
||||
|
||||
const char *RISCV_group_name(csh handle, unsigned int id)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
// verify group id
|
||||
// if past the end
|
||||
if (id >= RISCV_GRP_ENDING ||
|
||||
// or in the encoding gap between generic groups and arch-specific groups
|
||||
(id > RISCV_GRP_BRANCH_RELATIVE && id < RISCV_FEATURE_HASSTDEXTI))
|
||||
return NULL;
|
||||
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
// map instruction name to public instruction ID
|
||||
riscv_insn RISCV_map_insn(const char *name)
|
||||
{
|
||||
unsigned int i;
|
||||
for (i = 1; i < ARR_SIZE(insn_name_maps); i++) {
|
||||
if (!strcmp(name, insn_name_maps[i]))
|
||||
return i;
|
||||
}
|
||||
#ifndef CAPSTONE_DIET
|
||||
for (i = 0; i < ARR_SIZE(insn_alias_mnem_map); i++) {
|
||||
if (!strcmp(name, insn_alias_mnem_map[i].name))
|
||||
return insn_alias_mnem_map[i].id;
|
||||
}
|
||||
#endif
|
||||
return RISCV_INS_INVALID;
|
||||
}
|
||||
|
||||
void RISCV_reg_access(const cs_insn *insn, cs_regs regs_read,
|
||||
uint8_t *regs_read_count, cs_regs regs_write,
|
||||
uint8_t *regs_write_count)
|
||||
{
|
||||
const cs_riscv *riscv = &(insn->detail->riscv);
|
||||
uint8_t read_count = 0;
|
||||
uint8_t write_count = 0;
|
||||
|
||||
for (int j = 0; j < riscv->op_count; j++) {
|
||||
const cs_riscv_op *op = &riscv->operands[j];
|
||||
|
||||
if (op->type == RISCV_OP_REG) {
|
||||
if ((op->access & CS_AC_WRITE) &&
|
||||
!arr_exist(regs_write, write_count, op->reg)) {
|
||||
regs_write[write_count++] = (uint16_t)op->reg;
|
||||
}
|
||||
if ((op->access & CS_AC_READ) &&
|
||||
!arr_exist(regs_read, read_count, op->reg)) {
|
||||
regs_read[read_count++] = (uint16_t)op->reg;
|
||||
}
|
||||
} else if (op->type == RISCV_OP_MEM) {
|
||||
if (op->mem.base != RISCV_REG_INVALID &&
|
||||
!arr_exist(regs_read, read_count, op->mem.base)) {
|
||||
regs_read[read_count++] =
|
||||
(uint16_t)op->mem.base;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*regs_read_count = read_count;
|
||||
*regs_write_count = write_count;
|
||||
}
|
||||
|
||||
void RISCV_init(MCRegisterInfo *MRI)
|
||||
{
|
||||
MCRegisterInfo_InitMCRegisterInfo(MRI, RISCVRegDesc, RISCV_REG_ENDING,
|
||||
0, 0, RISCVMCRegisterClasses,
|
||||
ARR_SIZE(RISCVMCRegisterClasses), 0,
|
||||
0, RISCVRegDiffLists, 0,
|
||||
RISCVSubRegIdxLists,
|
||||
ARR_SIZE(RISCVSubRegIdxLists), 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
+45
@@ -0,0 +1,45 @@
|
||||
|
||||
#ifndef CS_RISCV_MAP_H
|
||||
#define CS_RISCV_MAP_H
|
||||
|
||||
#include "../../include/capstone/capstone.h"
|
||||
#include "../../cs_priv.h"
|
||||
|
||||
typedef enum {
|
||||
#include "RISCVGenCSOpGroup.inc"
|
||||
} riscv_op_group;
|
||||
|
||||
extern const insn_map *RISCV_insns;
|
||||
extern const unsigned int RISCV_insn_count;
|
||||
|
||||
// given internal insn id, return public instruction info
|
||||
void RISCV_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
|
||||
|
||||
void RISCV_set_alias_id(MCInst *MI, SStream *O);
|
||||
|
||||
const char *RISCV_insn_name(csh handle, unsigned int id);
|
||||
|
||||
const char *RISCV_group_name(csh handle, unsigned int id);
|
||||
|
||||
const char *RISCV_reg_name(csh handle, unsigned int reg);
|
||||
|
||||
void RISCV_add_cs_detail_0(MCInst *MI, riscv_op_group opgroup, unsigned OpNum);
|
||||
|
||||
void RISCV_add_groups(MCInst *MI);
|
||||
|
||||
void RISCV_init_cs_detail(MCInst *MI);
|
||||
|
||||
void RISCV_compact_operands(MCInst *MI);
|
||||
|
||||
void RISCV_add_missing_write_access(MCInst *MI);
|
||||
|
||||
// map instruction name to instruction ID
|
||||
riscv_insn RISCV_map_insn(const char *name);
|
||||
|
||||
void RISCV_init(MCRegisterInfo *MRI);
|
||||
|
||||
void RISCV_reg_access(const cs_insn *insn, cs_regs regs_read,
|
||||
uint8_t *regs_read_count, cs_regs regs_write,
|
||||
uint8_t *regs_write_count);
|
||||
|
||||
#endif
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
|
||||
Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_RISCV
|
||||
|
||||
#include "../../utils.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "RISCVInstPrinter.h"
|
||||
#include "RISCVMapping.h"
|
||||
#include "RISCVModule.h"
|
||||
#include "RISCVLinkage.h"
|
||||
|
||||
cs_err RISCV_global_init(cs_struct *ud)
|
||||
{
|
||||
MCRegisterInfo *mri;
|
||||
mri = cs_mem_malloc(sizeof(*mri));
|
||||
if (!mri)
|
||||
return CS_ERR_MEM;
|
||||
|
||||
RISCV_init(mri);
|
||||
ud->printer = RISCV_LLVM_printInstruction;
|
||||
ud->printer_info = mri;
|
||||
ud->getinsn_info = mri;
|
||||
ud->disasm = RISCV_LLVM_getInstruction;
|
||||
ud->post_printer = NULL;
|
||||
|
||||
ud->reg_name = RISCV_reg_name;
|
||||
ud->insn_id = RISCV_get_insn_id;
|
||||
ud->insn_name = RISCV_insn_name;
|
||||
ud->group_name = RISCV_group_name;
|
||||
ud->insn_map = RISCV_insns;
|
||||
ud->insn_map_size = RISCV_insn_count;
|
||||
ud->reg_access = RISCV_reg_access;
|
||||
|
||||
return CS_ERR_OK;
|
||||
}
|
||||
|
||||
cs_err RISCV_option(cs_struct *handle, cs_opt_type type, size_t value)
|
||||
{
|
||||
if (type == CS_OPT_SYNTAX) {
|
||||
handle->syntax |= (int)value;
|
||||
} else if (type == CS_OPT_MODE) {
|
||||
handle->mode = (cs_mode)value;
|
||||
}
|
||||
|
||||
return CS_ERR_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
|
||||
|
||||
#ifndef CS_RISCV_MODULE_H
|
||||
#define CS_RISCV_MODULE_H
|
||||
|
||||
#include "../../utils.h"
|
||||
|
||||
cs_err RISCV_global_init(cs_struct *ud);
|
||||
cs_err RISCV_option(cs_struct *handle, cs_opt_type type, size_t value);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user