Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
This commit is contained in:
@@ -0,0 +1,362 @@
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# CS_ARCH_AARCH64, 0, None
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0x1f,0x20,0x03,0xd5 = nop
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0x9f,0x20,0x03,0xd5 = sev
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0xbf,0x20,0x03,0xd5 = sevl
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0x5f,0x20,0x03,0xd5 = wfe
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0x7f,0x20,0x03,0xd5 = wfi
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0x3f,0x20,0x03,0xd5 = yield
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0x5f,0x3a,0x03,0xd5 = clrex #10
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0xdf,0x3f,0x03,0xd5 = isb
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0xdf,0x3f,0x03,0xd5 = isb
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0xbf,0x33,0x03,0xd5 = dmb osh
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0xbf,0x33,0x03,0xd5 = dmb osh
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0x9f,0x37,0x03,0xd5 = dsb nsh
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0x9f,0x37,0x03,0xd5 = dsb nsh
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0xff,0x05,0x0a,0xd5 = sys #2, c0, c5, #7
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0xe7,0x6a,0x0f,0xd5 = sys #7, c6, c10, #7, x7
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0xf4,0x3f,0x2e,0xd5 = sysl x20, #6, c3, c15, #7
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0x23,0x10,0x18,0xd5 = msr ACTLR_EL1, x3
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0x23,0x10,0x1c,0xd5 = msr ACTLR_EL2, x3
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0x23,0x10,0x1e,0xd5 = msr ACTLR_EL3, x3
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0x03,0x51,0x18,0xd5 = msr AFSR0_EL1, x3
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0x03,0x51,0x1c,0xd5 = msr AFSR0_EL2, x3
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0x03,0x51,0x1e,0xd5 = msr AFSR0_EL3, x3
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0x23,0x51,0x18,0xd5 = msr AFSR1_EL1, x3
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0x23,0x51,0x1c,0xd5 = msr AFSR1_EL2, x3
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0x23,0x51,0x1e,0xd5 = msr AFSR1_EL3, x3
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0x03,0xa3,0x18,0xd5 = msr AMAIR_EL1, x3
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0x03,0xa3,0x1c,0xd5 = msr AMAIR_EL2, x3
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0x03,0xa3,0x1e,0xd5 = msr AMAIR_EL3, x3
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0x03,0xe0,0x1b,0xd5 = msr CNTFRQ_EL0, x3
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0x03,0xe1,0x1c,0xd5 = msr CNTHCTL_EL2, x3
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0x23,0xe2,0x1c,0xd5 = msr CNTHP_CTL_EL2, x3
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0x43,0xe2,0x1c,0xd5 = msr CNTHP_CVAL_EL2, x3
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0x03,0xe2,0x1c,0xd5 = msr CNTHP_TVAL_EL2, x3
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0x03,0xe1,0x18,0xd5 = msr CNTKCTL_EL1, x3
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0x23,0xe2,0x1b,0xd5 = msr CNTP_CTL_EL0, x3
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0x43,0xe2,0x1b,0xd5 = msr CNTP_CVAL_EL0, x3
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0x03,0xe2,0x1b,0xd5 = msr CNTP_TVAL_EL0, x3
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0x63,0xe0,0x1c,0xd5 = msr CNTVOFF_EL2, x3
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0x23,0xe3,0x1b,0xd5 = msr CNTV_CTL_EL0, x3
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0x43,0xe3,0x1b,0xd5 = msr CNTV_CVAL_EL0, x3
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0x03,0xe3,0x1b,0xd5 = msr CNTV_TVAL_EL0, x3
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0x23,0xd0,0x18,0xd5 = msr CONTEXTIDR_EL1, x3
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0x43,0x10,0x18,0xd5 = msr CPACR_EL1, x3
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0x43,0x11,0x1c,0xd5 = msr CPTR_EL2, x3
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0x43,0x11,0x1e,0xd5 = msr CPTR_EL3, x3
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0x03,0x00,0x1a,0xd5 = msr CSSELR_EL1, x3
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0x03,0x30,0x1c,0xd5 = msr DACR32_EL2, x3
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0x03,0x52,0x18,0xd5 = msr ESR_EL1, x3
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0x03,0x52,0x1c,0xd5 = msr ESR_EL2, x3
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0x03,0x52,0x1e,0xd5 = msr ESR_EL3, x3
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0x03,0x60,0x18,0xd5 = msr FAR_EL1, x3
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0x03,0x60,0x1c,0xd5 = msr FAR_EL2, x3
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0x03,0x60,0x1e,0xd5 = msr FAR_EL3, x3
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0x03,0x53,0x1c,0xd5 = msr FPEXC32_EL2, x3
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0xe3,0x11,0x1c,0xd5 = msr HACR_EL2, x3
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0x03,0x11,0x1c,0xd5 = msr HCR_EL2, x3
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0x83,0x60,0x1c,0xd5 = msr HPFAR_EL2, x3
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0x63,0x11,0x1c,0xd5 = msr HSTR_EL2, x3
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0x23,0x50,0x1c,0xd5 = msr IFSR32_EL2, x3
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0x03,0xa2,0x18,0xd5 = msr MAIR_EL1, x3
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0x03,0xa2,0x1c,0xd5 = msr MAIR_EL2, x3
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0x03,0xa2,0x1e,0xd5 = msr MAIR_EL3, x3
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0x23,0x11,0x1c,0xd5 = msr MDCR_EL2, x3
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0x23,0x13,0x1e,0xd5 = msr MDCR_EL3, x3
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0x03,0x74,0x18,0xd5 = msr PAR_EL1, x3
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0x03,0x11,0x1e,0xd5 = msr SCR_EL3, x3
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0x03,0x10,0x18,0xd5 = msr SCTLR_EL1, x3
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0x03,0x10,0x1c,0xd5 = msr SCTLR_EL2, x3
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0x03,0x10,0x1e,0xd5 = msr SCTLR_EL3, x3
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0x23,0x11,0x1e,0xd5 = msr SDER32_EL3, x3
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0x43,0x20,0x18,0xd5 = msr TCR_EL1, x3
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0x43,0x20,0x1c,0xd5 = msr TCR_EL2, x3
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0x43,0x20,0x1e,0xd5 = msr TCR_EL3, x3
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0x03,0x00,0x12,0xd5 = msr TEECR32_EL1, x3
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0x03,0x10,0x12,0xd5 = msr TEEHBR32_EL1, x3
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0x63,0xd0,0x1b,0xd5 = msr TPIDRRO_EL0, x3
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0x43,0xd0,0x1b,0xd5 = msr TPIDR_EL0, x3
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0x83,0xd0,0x18,0xd5 = msr TPIDR_EL1, x3
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0x43,0xd0,0x1c,0xd5 = msr TPIDR_EL2, x3
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0x43,0xd0,0x1e,0xd5 = msr TPIDR_EL3, x3
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0x03,0x20,0x18,0xd5 = msr TTBR0_EL1, x3
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0x03,0x20,0x1c,0xd5 = msr TTBR0_EL2, x3
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0x03,0x20,0x1e,0xd5 = msr TTBR0_EL3, x3
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0x23,0x20,0x18,0xd5 = msr TTBR1_EL1, x3
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0x03,0xc0,0x18,0xd5 = msr VBAR_EL1, x3
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0x03,0xc0,0x1c,0xd5 = msr VBAR_EL2, x3
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0x03,0xc0,0x1e,0xd5 = msr VBAR_EL3, x3
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0xa3,0x00,0x1c,0xd5 = msr VMPIDR_EL2, x3
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0x03,0x00,0x1c,0xd5 = msr VPIDR_EL2, x3
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0x43,0x21,0x1c,0xd5 = msr VTCR_EL2, x3
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0x03,0x21,0x1c,0xd5 = msr VTTBR_EL2, x3
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0x03,0x42,0x18,0xd5 = msr SPSel, x3
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0x23,0xa3,0x18,0xd5 = msr AMAIR2_EL1, x3
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0x23,0xa3,0x1d,0xd5 = msr AMAIR2_EL12, x3
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0x23,0xa3,0x1c,0xd5 = msr AMAIR2_EL2, x3
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0x23,0xa3,0x1e,0xd5 = msr AMAIR2_EL3, x3
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0x23,0xa2,0x18,0xd5 = msr MAIR2_EL1, x3
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0x23,0xa2,0x1d,0xd5 = msr MAIR2_EL12, x3
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0x23,0xa1,0x1c,0xd5 = msr MAIR2_EL2, x3
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0x23,0xa1,0x1e,0xd5 = msr MAIR2_EL3, x3
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0x43,0xa2,0x18,0xd5 = msr PIRE0_EL1, x3
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0x43,0xa2,0x1d,0xd5 = msr PIRE0_EL12, x3
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0x43,0xa2,0x1c,0xd5 = msr PIRE0_EL2, x3
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0x63,0xa2,0x18,0xd5 = msr PIR_EL1, x3
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0x63,0xa2,0x1d,0xd5 = msr PIR_EL12, x3
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0x63,0xa2,0x1c,0xd5 = msr PIR_EL2, x3
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0x63,0xa2,0x1e,0xd5 = msr PIR_EL3, x3
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0xa3,0xa2,0x1c,0xd5 = msr S2PIR_EL2, x3
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0x83,0xa2,0x1b,0xd5 = msr POR_EL0, x3
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0x83,0xa2,0x18,0xd5 = msr POR_EL1, x3
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0x83,0xa2,0x1d,0xd5 = msr POR_EL12, x3
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0x83,0xa2,0x1c,0xd5 = msr POR_EL2, x3
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0x83,0xa2,0x1e,0xd5 = msr POR_EL3, x3
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0xa3,0xa2,0x18,0xd5 = msr S2POR_EL1, x3
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0x63,0x10,0x18,0xd5 = msr SCTLR2_EL1, x3
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0x63,0x10,0x1d,0xd5 = msr SCTLR2_EL12, x3
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0x63,0x10,0x1c,0xd5 = msr SCTLR2_EL2, x3
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0x63,0x10,0x1e,0xd5 = msr SCTLR2_EL3, x3
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0x63,0x20,0x18,0xd5 = msr TCR2_EL1, x3
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0x63,0x20,0x1d,0xd5 = msr TCR2_EL12, x3
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0x63,0x20,0x1c,0xd5 = msr TCR2_EL2, x3
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0x81,0xb6,0x1a,0xd5 = msr S3_2_C11_C6_4, x1
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0x00,0x00,0x00,0xd5 = msr S0_0_C0_C0_0, x0
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0xa2,0x34,0x0a,0xd5 = sys #2, c3, c4, #5, x2
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0x23,0x10,0x38,0xd5 = mrs x3, ACTLR_EL1
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0x23,0x10,0x3c,0xd5 = mrs x3, ACTLR_EL2
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0x23,0x10,0x3e,0xd5 = mrs x3, ACTLR_EL3
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0x03,0x51,0x38,0xd5 = mrs x3, AFSR0_EL1
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0x03,0x51,0x3c,0xd5 = mrs x3, AFSR0_EL2
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0x03,0x51,0x3e,0xd5 = mrs x3, AFSR0_EL3
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0xe3,0x00,0x39,0xd5 = mrs x3, AIDR_EL1
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0x23,0x51,0x38,0xd5 = mrs x3, AFSR1_EL1
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0x23,0x51,0x3c,0xd5 = mrs x3, AFSR1_EL2
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0x23,0x51,0x3e,0xd5 = mrs x3, AFSR1_EL3
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0x03,0xa3,0x38,0xd5 = mrs x3, AMAIR_EL1
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0x03,0xa3,0x3c,0xd5 = mrs x3, AMAIR_EL2
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0x03,0xa3,0x3e,0xd5 = mrs x3, AMAIR_EL3
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0x03,0x00,0x39,0xd5 = mrs x3, CCSIDR_EL1
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0x23,0x00,0x39,0xd5 = mrs x3, CLIDR_EL1
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0x43,0x00,0x39,0xd5 = mrs x3, CCSIDR2_EL1
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0x03,0xe0,0x3b,0xd5 = mrs x3, CNTFRQ_EL0
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0x03,0xe1,0x3c,0xd5 = mrs x3, CNTHCTL_EL2
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0x23,0xe2,0x3c,0xd5 = mrs x3, CNTHP_CTL_EL2
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0x43,0xe2,0x3c,0xd5 = mrs x3, CNTHP_CVAL_EL2
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0x03,0xe2,0x3c,0xd5 = mrs x3, CNTHP_TVAL_EL2
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0x03,0xe1,0x38,0xd5 = mrs x3, CNTKCTL_EL1
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0x23,0xe0,0x3b,0xd5 = mrs x3, CNTPCT_EL0
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0x23,0xe2,0x3b,0xd5 = mrs x3, CNTP_CTL_EL0
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0x43,0xe2,0x3b,0xd5 = mrs x3, CNTP_CVAL_EL0
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0x03,0xe2,0x3b,0xd5 = mrs x3, CNTP_TVAL_EL0
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0x43,0xe0,0x3b,0xd5 = mrs x3, CNTVCT_EL0
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0x63,0xe0,0x3c,0xd5 = mrs x3, CNTVOFF_EL2
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0x23,0xe3,0x3b,0xd5 = mrs x3, CNTV_CTL_EL0
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0x43,0xe3,0x3b,0xd5 = mrs x3, CNTV_CVAL_EL0
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0x03,0xe3,0x3b,0xd5 = mrs x3, CNTV_TVAL_EL0
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0x23,0xd0,0x38,0xd5 = mrs x3, CONTEXTIDR_EL1
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0x43,0x10,0x38,0xd5 = mrs x3, CPACR_EL1
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0x43,0x11,0x3c,0xd5 = mrs x3, CPTR_EL2
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0x43,0x11,0x3e,0xd5 = mrs x3, CPTR_EL3
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0x03,0x00,0x3a,0xd5 = mrs x3, CSSELR_EL1
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0x23,0x00,0x3b,0xd5 = mrs x3, CTR_EL0
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0x43,0x42,0x38,0xd5 = mrs x3, CurrentEL
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0x03,0x30,0x3c,0xd5 = mrs x3, DACR32_EL2
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0xe3,0x00,0x3b,0xd5 = mrs x3, DCZID_EL0
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0xc3,0x00,0x38,0xd5 = mrs x3, REVIDR_EL1
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0x03,0x52,0x38,0xd5 = mrs x3, ESR_EL1
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0x03,0x52,0x3c,0xd5 = mrs x3, ESR_EL2
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0x03,0x52,0x3e,0xd5 = mrs x3, ESR_EL3
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0x03,0x60,0x38,0xd5 = mrs x3, FAR_EL1
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0x03,0x60,0x3c,0xd5 = mrs x3, FAR_EL2
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0x03,0x60,0x3e,0xd5 = mrs x3, FAR_EL3
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0x03,0x53,0x3c,0xd5 = mrs x3, FPEXC32_EL2
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0xe3,0x11,0x3c,0xd5 = mrs x3, HACR_EL2
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0x03,0x11,0x3c,0xd5 = mrs x3, HCR_EL2
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0x83,0x60,0x3c,0xd5 = mrs x3, HPFAR_EL2
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0x63,0x11,0x3c,0xd5 = mrs x3, HSTR_EL2
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0x03,0x05,0x38,0xd5 = mrs x3, ID_AA64DFR0_EL1
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0x23,0x05,0x38,0xd5 = mrs x3, ID_AA64DFR1_EL1
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0x03,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR0_EL1
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0x23,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR1_EL1
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0x43,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR2_EL1
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0x03,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR0_EL1
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0x23,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR1_EL1
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0x43,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR2_EL1
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0x63,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR3_EL1
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0x83,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR4_EL1
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0x03,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR0_EL1
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0x23,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR1_EL1
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0x43,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR2_EL1
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0x23,0x50,0x3c,0xd5 = mrs x3, IFSR32_EL2
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0x03,0xc1,0x38,0xd5 = mrs x3, ISR_EL1
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0x03,0xa2,0x38,0xd5 = mrs x3, MAIR_EL1
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0x03,0xa2,0x3c,0xd5 = mrs x3, MAIR_EL2
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0x03,0xa2,0x3e,0xd5 = mrs x3, MAIR_EL3
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0x23,0x11,0x3c,0xd5 = mrs x3, MDCR_EL2
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0x23,0x13,0x3e,0xd5 = mrs x3, MDCR_EL3
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0x03,0x00,0x38,0xd5 = mrs x3, MIDR_EL1
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0xa3,0x00,0x38,0xd5 = mrs x3, MPIDR_EL1
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0x03,0x03,0x38,0xd5 = mrs x3, MVFR0_EL1
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0x23,0x03,0x38,0xd5 = mrs x3, MVFR1_EL1
|
||||
0x03,0x74,0x38,0xd5 = mrs x3, PAR_EL1
|
||||
0x23,0xc0,0x38,0xd5 = mrs x3, RVBAR_EL1
|
||||
0x23,0xc0,0x3c,0xd5 = mrs x3, RVBAR_EL2
|
||||
0x23,0xc0,0x3e,0xd5 = mrs x3, RVBAR_EL3
|
||||
0x03,0x11,0x3e,0xd5 = mrs x3, SCR_EL3
|
||||
0x03,0x10,0x38,0xd5 = mrs x3, SCTLR_EL1
|
||||
0x03,0x10,0x3c,0xd5 = mrs x3, SCTLR_EL2
|
||||
0x03,0x10,0x3e,0xd5 = mrs x3, SCTLR_EL3
|
||||
0x23,0x11,0x3e,0xd5 = mrs x3, SDER32_EL3
|
||||
0x43,0x20,0x38,0xd5 = mrs x3, TCR_EL1
|
||||
0x43,0x20,0x3c,0xd5 = mrs x3, TCR_EL2
|
||||
0x43,0x20,0x3e,0xd5 = mrs x3, TCR_EL3
|
||||
0x03,0x00,0x32,0xd5 = mrs x3, TEECR32_EL1
|
||||
0x03,0x10,0x32,0xd5 = mrs x3, TEEHBR32_EL1
|
||||
0x63,0xd0,0x3b,0xd5 = mrs x3, TPIDRRO_EL0
|
||||
0x43,0xd0,0x3b,0xd5 = mrs x3, TPIDR_EL0
|
||||
0x83,0xd0,0x38,0xd5 = mrs x3, TPIDR_EL1
|
||||
0x43,0xd0,0x3c,0xd5 = mrs x3, TPIDR_EL2
|
||||
0x43,0xd0,0x3e,0xd5 = mrs x3, TPIDR_EL3
|
||||
0x03,0x20,0x38,0xd5 = mrs x3, TTBR0_EL1
|
||||
0x03,0x20,0x3c,0xd5 = mrs x3, TTBR0_EL2
|
||||
0x03,0x20,0x3e,0xd5 = mrs x3, TTBR0_EL3
|
||||
0x23,0x20,0x38,0xd5 = mrs x3, TTBR1_EL1
|
||||
0x03,0xc0,0x38,0xd5 = mrs x3, VBAR_EL1
|
||||
0x03,0xc0,0x3c,0xd5 = mrs x3, VBAR_EL2
|
||||
0x03,0xc0,0x3e,0xd5 = mrs x3, VBAR_EL3
|
||||
0xa3,0x00,0x3c,0xd5 = mrs x3, VMPIDR_EL2
|
||||
0x03,0x00,0x3c,0xd5 = mrs x3, VPIDR_EL2
|
||||
0x43,0x21,0x3c,0xd5 = mrs x3, VTCR_EL2
|
||||
0x03,0x21,0x3c,0xd5 = mrs x3, VTTBR_EL2
|
||||
0x03,0x01,0x33,0xd5 = mrs x3, MDCCSR_EL0
|
||||
0x03,0x02,0x30,0xd5 = mrs x3, MDCCINT_EL1
|
||||
0x03,0x04,0x33,0xd5 = mrs x3, DBGDTR_EL0
|
||||
0x03,0x05,0x33,0xd5 = mrs x3, DBGDTRRX_EL0
|
||||
0x03,0x07,0x34,0xd5 = mrs x3, DBGVCR32_EL2
|
||||
0x43,0x00,0x30,0xd5 = mrs x3, OSDTRRX_EL1
|
||||
0x43,0x02,0x30,0xd5 = mrs x3, MDSCR_EL1
|
||||
0x43,0x03,0x30,0xd5 = mrs x3, OSDTRTX_EL1
|
||||
0x43,0x06,0x30,0xd5 = mrs x3, OSECCR_EL1
|
||||
0x83,0x00,0x30,0xd5 = mrs x3, DBGBVR0_EL1
|
||||
0x83,0x01,0x30,0xd5 = mrs x3, DBGBVR1_EL1
|
||||
0x83,0x02,0x30,0xd5 = mrs x3, DBGBVR2_EL1
|
||||
0x83,0x03,0x30,0xd5 = mrs x3, DBGBVR3_EL1
|
||||
0x83,0x04,0x30,0xd5 = mrs x3, DBGBVR4_EL1
|
||||
0x83,0x05,0x30,0xd5 = mrs x3, DBGBVR5_EL1
|
||||
0x83,0x06,0x30,0xd5 = mrs x3, DBGBVR6_EL1
|
||||
0x83,0x07,0x30,0xd5 = mrs x3, DBGBVR7_EL1
|
||||
0x83,0x08,0x30,0xd5 = mrs x3, DBGBVR8_EL1
|
||||
0x83,0x09,0x30,0xd5 = mrs x3, DBGBVR9_EL1
|
||||
0x83,0x0a,0x30,0xd5 = mrs x3, DBGBVR10_EL1
|
||||
0x83,0x0b,0x30,0xd5 = mrs x3, DBGBVR11_EL1
|
||||
0x83,0x0c,0x30,0xd5 = mrs x3, DBGBVR12_EL1
|
||||
0x83,0x0d,0x30,0xd5 = mrs x3, DBGBVR13_EL1
|
||||
0x83,0x0e,0x30,0xd5 = mrs x3, DBGBVR14_EL1
|
||||
0x83,0x0f,0x30,0xd5 = mrs x3, DBGBVR15_EL1
|
||||
0xa3,0x00,0x30,0xd5 = mrs x3, DBGBCR0_EL1
|
||||
0xa3,0x01,0x30,0xd5 = mrs x3, DBGBCR1_EL1
|
||||
0xa3,0x02,0x30,0xd5 = mrs x3, DBGBCR2_EL1
|
||||
0xa3,0x03,0x30,0xd5 = mrs x3, DBGBCR3_EL1
|
||||
0xa3,0x04,0x30,0xd5 = mrs x3, DBGBCR4_EL1
|
||||
0xa3,0x05,0x30,0xd5 = mrs x3, DBGBCR5_EL1
|
||||
0xa3,0x06,0x30,0xd5 = mrs x3, DBGBCR6_EL1
|
||||
0xa3,0x07,0x30,0xd5 = mrs x3, DBGBCR7_EL1
|
||||
0xa3,0x08,0x30,0xd5 = mrs x3, DBGBCR8_EL1
|
||||
0xa3,0x09,0x30,0xd5 = mrs x3, DBGBCR9_EL1
|
||||
0xa3,0x0a,0x30,0xd5 = mrs x3, DBGBCR10_EL1
|
||||
0xa3,0x0b,0x30,0xd5 = mrs x3, DBGBCR11_EL1
|
||||
0xa3,0x0c,0x30,0xd5 = mrs x3, DBGBCR12_EL1
|
||||
0xa3,0x0d,0x30,0xd5 = mrs x3, DBGBCR13_EL1
|
||||
0xa3,0x0e,0x30,0xd5 = mrs x3, DBGBCR14_EL1
|
||||
0xa3,0x0f,0x30,0xd5 = mrs x3, DBGBCR15_EL1
|
||||
0xc3,0x00,0x30,0xd5 = mrs x3, DBGWVR0_EL1
|
||||
0xc3,0x01,0x30,0xd5 = mrs x3, DBGWVR1_EL1
|
||||
0xc3,0x02,0x30,0xd5 = mrs x3, DBGWVR2_EL1
|
||||
0xc3,0x03,0x30,0xd5 = mrs x3, DBGWVR3_EL1
|
||||
0xc3,0x04,0x30,0xd5 = mrs x3, DBGWVR4_EL1
|
||||
0xc3,0x05,0x30,0xd5 = mrs x3, DBGWVR5_EL1
|
||||
0xc3,0x06,0x30,0xd5 = mrs x3, DBGWVR6_EL1
|
||||
0xc3,0x07,0x30,0xd5 = mrs x3, DBGWVR7_EL1
|
||||
0xc3,0x08,0x30,0xd5 = mrs x3, DBGWVR8_EL1
|
||||
0xc3,0x09,0x30,0xd5 = mrs x3, DBGWVR9_EL1
|
||||
0xc3,0x0a,0x30,0xd5 = mrs x3, DBGWVR10_EL1
|
||||
0xc3,0x0b,0x30,0xd5 = mrs x3, DBGWVR11_EL1
|
||||
0xc3,0x0c,0x30,0xd5 = mrs x3, DBGWVR12_EL1
|
||||
0xc3,0x0d,0x30,0xd5 = mrs x3, DBGWVR13_EL1
|
||||
0xc3,0x0e,0x30,0xd5 = mrs x3, DBGWVR14_EL1
|
||||
0xc3,0x0f,0x30,0xd5 = mrs x3, DBGWVR15_EL1
|
||||
0xe3,0x00,0x30,0xd5 = mrs x3, DBGWCR0_EL1
|
||||
0xe3,0x01,0x30,0xd5 = mrs x3, DBGWCR1_EL1
|
||||
0xe3,0x02,0x30,0xd5 = mrs x3, DBGWCR2_EL1
|
||||
0xe3,0x03,0x30,0xd5 = mrs x3, DBGWCR3_EL1
|
||||
0xe3,0x04,0x30,0xd5 = mrs x3, DBGWCR4_EL1
|
||||
0xe3,0x05,0x30,0xd5 = mrs x3, DBGWCR5_EL1
|
||||
0xe3,0x06,0x30,0xd5 = mrs x3, DBGWCR6_EL1
|
||||
0xe3,0x07,0x30,0xd5 = mrs x3, DBGWCR7_EL1
|
||||
0xe3,0x08,0x30,0xd5 = mrs x3, DBGWCR8_EL1
|
||||
0xe3,0x09,0x30,0xd5 = mrs x3, DBGWCR9_EL1
|
||||
0xe3,0x0a,0x30,0xd5 = mrs x3, DBGWCR10_EL1
|
||||
0xe3,0x0b,0x30,0xd5 = mrs x3, DBGWCR11_EL1
|
||||
0xe3,0x0c,0x30,0xd5 = mrs x3, DBGWCR12_EL1
|
||||
0xe3,0x0d,0x30,0xd5 = mrs x3, DBGWCR13_EL1
|
||||
0xe3,0x0e,0x30,0xd5 = mrs x3, DBGWCR14_EL1
|
||||
0xe3,0x0f,0x30,0xd5 = mrs x3, DBGWCR15_EL1
|
||||
0x03,0x10,0x30,0xd5 = mrs x3, MDRAR_EL1
|
||||
0x83,0x11,0x30,0xd5 = mrs x3, OSLSR_EL1
|
||||
0x83,0x13,0x30,0xd5 = mrs x3, OSDLR_EL1
|
||||
0x83,0x14,0x30,0xd5 = mrs x3, DBGPRCR_EL1
|
||||
0xc3,0x78,0x30,0xd5 = mrs x3, DBGCLAIMSET_EL1
|
||||
0xc3,0x79,0x30,0xd5 = mrs x3, DBGCLAIMCLR_EL1
|
||||
0xc3,0x7e,0x30,0xd5 = mrs x3, DBGAUTHSTATUS_EL1
|
||||
0x23,0xa3,0x38,0xd5 = mrs x3, AMAIR2_EL1
|
||||
0x23,0xa3,0x3d,0xd5 = mrs x3, AMAIR2_EL12
|
||||
0x23,0xa3,0x3c,0xd5 = mrs x3, AMAIR2_EL2
|
||||
0x23,0xa3,0x3e,0xd5 = mrs x3, AMAIR2_EL3
|
||||
0x23,0xa2,0x38,0xd5 = mrs x3, MAIR2_EL1
|
||||
0x23,0xa2,0x3d,0xd5 = mrs x3, MAIR2_EL12
|
||||
0x23,0xa1,0x3c,0xd5 = mrs x3, MAIR2_EL2
|
||||
0x23,0xa1,0x3e,0xd5 = mrs x3, MAIR2_EL3
|
||||
0x43,0xa2,0x38,0xd5 = mrs x3, PIRE0_EL1
|
||||
0x43,0xa2,0x3d,0xd5 = mrs x3, PIRE0_EL12
|
||||
0x43,0xa2,0x3c,0xd5 = mrs x3, PIRE0_EL2
|
||||
0x63,0xa2,0x38,0xd5 = mrs x3, PIR_EL1
|
||||
0x63,0xa2,0x3d,0xd5 = mrs x3, PIR_EL12
|
||||
0x63,0xa2,0x3c,0xd5 = mrs x3, PIR_EL2
|
||||
0x63,0xa2,0x3e,0xd5 = mrs x3, PIR_EL3
|
||||
0xa3,0xa2,0x3c,0xd5 = mrs x3, S2PIR_EL2
|
||||
0x83,0xa2,0x3b,0xd5 = mrs x3, POR_EL0
|
||||
0x83,0xa2,0x38,0xd5 = mrs x3, POR_EL1
|
||||
0x83,0xa2,0x3d,0xd5 = mrs x3, POR_EL12
|
||||
0x83,0xa2,0x3c,0xd5 = mrs x3, POR_EL2
|
||||
0x83,0xa2,0x3e,0xd5 = mrs x3, POR_EL3
|
||||
0xa3,0xa2,0x38,0xd5 = mrs x3, S2POR_EL1
|
||||
0x63,0x10,0x38,0xd5 = mrs x3, SCTLR2_EL1
|
||||
0x63,0x10,0x3d,0xd5 = mrs x3, SCTLR2_EL12
|
||||
0x63,0x10,0x3c,0xd5 = mrs x3, SCTLR2_EL2
|
||||
0x63,0x10,0x3e,0xd5 = mrs x3, SCTLR2_EL3
|
||||
0x63,0x20,0x38,0xd5 = mrs x3, TCR2_EL1
|
||||
0x63,0x20,0x3d,0xd5 = mrs x3, TCR2_EL12
|
||||
0x63,0x20,0x3c,0xd5 = mrs x3, TCR2_EL2
|
||||
0x81,0xf6,0x3a,0xd5 = mrs x1, S3_2_C15_C6_4
|
||||
0x83,0xb1,0x3b,0xd5 = mrs x3, S3_3_C11_C1_4
|
||||
0x83,0xb1,0x3b,0xd5 = mrs x3, S3_3_C11_C1_4
|
||||
0x40,0xc0,0x1e,0xd5 = msr RMR_EL3, x0
|
||||
0x40,0xc0,0x1c,0xd5 = msr RMR_EL2, x0
|
||||
0x40,0xc0,0x18,0xd5 = msr RMR_EL1, x0
|
||||
0x83,0x10,0x10,0xd5 = msr OSLAR_EL1, x3
|
||||
0x03,0x05,0x13,0xd5 = msr DBGDTRTX_EL0, x3
|
||||
0x00,0x01,0x38,0xd5 = mrs x0, ID_PFR0_EL1
|
||||
0x20,0x01,0x38,0xd5 = mrs x0, ID_PFR1_EL1
|
||||
0x40,0x01,0x38,0xd5 = mrs x0, ID_DFR0_EL1
|
||||
0xa0,0x03,0x38,0xd5 = mrs x0, ID_DFR1_EL1
|
||||
0x60,0x01,0x38,0xd5 = mrs x0, ID_AFR0_EL1
|
||||
0x00,0x02,0x38,0xd5 = mrs x0, ID_ISAR0_EL1
|
||||
0x20,0x02,0x38,0xd5 = mrs x0, ID_ISAR1_EL1
|
||||
0x40,0x02,0x38,0xd5 = mrs x0, ID_ISAR2_EL1
|
||||
0x60,0x02,0x38,0xd5 = mrs x0, ID_ISAR3_EL1
|
||||
0x80,0x02,0x38,0xd5 = mrs x0, ID_ISAR4_EL1
|
||||
0xa0,0x02,0x38,0xd5 = mrs x0, ID_ISAR5_EL1
|
||||
0x20,0x51,0x38,0xd5 = mrs x0, AFSR1_EL1
|
||||
0x00,0x51,0x38,0xd5 = mrs x0, AFSR0_EL1
|
||||
0xc0,0x00,0x38,0xd5 = mrs x0, REVIDR_EL1
|
||||
Reference in New Issue
Block a user