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Mem and Regs not part of cpu anymore.

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SimoZ64
2025-08-01 21:05:11 +02:00
parent 812b905bdf
commit 010bb5e0bb
35 changed files with 246 additions and 250 deletions
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166
src/backend/core/interpreter/cop1instructions.cpp
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@@ -132,7 +132,7 @@ bool Cop1::isqnan<double>(const double f) {
template <>
bool Cop1::CheckCVTArg<s32>(const float f) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
switch (std::fpclassify(f)) {
case FP_SUBNORMAL:
case FP_INFINITE:
@@ -153,7 +153,7 @@ bool Cop1::CheckCVTArg<s32>(const float f) {
template <>
bool Cop1::CheckCVTArg<s32>(const double f) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
switch (std::fpclassify(f)) {
case FP_SUBNORMAL:
case FP_INFINITE:
@@ -174,7 +174,7 @@ bool Cop1::CheckCVTArg<s32>(const double f) {
template <>
bool Cop1::CheckCVTArg<s64>(const float f) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
switch (std::fpclassify(f)) {
case FP_SUBNORMAL:
case FP_INFINITE:
@@ -195,7 +195,7 @@ bool Cop1::CheckCVTArg<s64>(const float f) {
template <>
bool Cop1::CheckCVTArg<s64>(const double f) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
switch (std::fpclassify(f)) {
case FP_SUBNORMAL:
case FP_INFINITE:
@@ -216,7 +216,7 @@ bool Cop1::CheckCVTArg<s64>(const double f) {
template <typename T>
bool Cop1::CheckArg(const T f) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
switch (std::fpclassify(f)) {
case FP_SUBNORMAL:
SetCauseUnimplemented();
@@ -234,7 +234,7 @@ bool Cop1::CheckArg(const T f) {
template <typename T>
bool Cop1::CheckArgs(const T f1, const T f2) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
auto class1 = std::fpclassify(f1), class2 = std::fpclassify(f2);
if ((class1 == FP_NAN && !isqnan(f1)) || (class2 == FP_NAN && !isqnan(f2))) {
SetCauseUnimplemented();
@@ -260,7 +260,7 @@ bool Cop1::CheckArgs(const T f1, const T f2) {
template <bool preserveCause>
bool Cop1::CheckFPUUsable() {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if constexpr (preserveCause) {
if (!regs.cop0.status.cu1) {
regs.cop0.FireException(ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
@@ -295,7 +295,7 @@ FORCE_INLINE T FlushResult(T f, const u32 round) {
template <>
bool Cop1::CheckResult<float>(float &f) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
switch (std::fpclassify(f)) {
case FP_SUBNORMAL:
if (!fcr31.fs || fcr31.enable.underflow || fcr31.enable.inexact_operation) {
@@ -318,7 +318,7 @@ bool Cop1::CheckResult<float>(float &f) {
template <>
bool Cop1::CheckResult<double>(double &f) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
switch (std::fpclassify(f)) {
case FP_SUBNORMAL:
if (!fcr31.fs || fcr31.enable.underflow || fcr31.enable.inexact_operation) {
@@ -341,7 +341,7 @@ bool Cop1::CheckResult<double>(double &f) {
template <bool cvt>
bool Cop1::TestExceptions() {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
const u32 exc = std::fetestexcept(FE_ALL_EXCEPT);
if (!exc)
@@ -445,7 +445,7 @@ bool Cop1::SetCauseInvalid() {
#define CHECK_FPE_CONV_CONST(type, res, operation) CHECK_FPE_IMPL_CONST(type, res, operation, true)
void Cop1::absd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -458,7 +458,7 @@ void Cop1::absd(const u32 instr) {
}
void Cop1::abss(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -471,7 +471,7 @@ void Cop1::abss(const u32 instr) {
}
void Cop1::adds(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -485,7 +485,7 @@ void Cop1::adds(const u32 instr) {
}
void Cop1::addd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -499,7 +499,7 @@ void Cop1::addd(const u32 instr) {
}
void Cop1::ceills(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -510,7 +510,7 @@ void Cop1::ceills(const u32 instr) {
}
void Cop1::ceilld(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -521,7 +521,7 @@ void Cop1::ceilld(const u32 instr) {
}
void Cop1::ceilws(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -532,7 +532,7 @@ void Cop1::ceilws(const u32 instr) {
}
void Cop1::ceilwd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -543,7 +543,7 @@ void Cop1::ceilwd(const u32 instr) {
}
void Cop1::cfc1(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable<true>())
return;
const u8 fd = RD(instr);
@@ -562,7 +562,7 @@ void Cop1::cfc1(const u32 instr) {
}
void Cop1::ctc1(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable<true>())
return;
const u8 fs = RD(instr);
@@ -610,7 +610,7 @@ void Cop1::ctc1(const u32 instr) {
}
void Cop1::cvtds(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -623,7 +623,7 @@ void Cop1::cvtds(const u32 instr) {
}
void Cop1::cvtsd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -636,7 +636,7 @@ void Cop1::cvtsd(const u32 instr) {
}
void Cop1::cvtsw(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<s32>(regs.cop0.status, FS(instr));
@@ -647,7 +647,7 @@ void Cop1::cvtsw(const u32 instr) {
}
void Cop1::cvtsl(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<s64>(regs.cop0.status, FS(instr));
@@ -663,7 +663,7 @@ void Cop1::cvtsl(const u32 instr) {
}
void Cop1::cvtwd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -674,7 +674,7 @@ void Cop1::cvtwd(const u32 instr) {
}
void Cop1::cvtws(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -685,7 +685,7 @@ void Cop1::cvtws(const u32 instr) {
}
void Cop1::cvtls(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -696,7 +696,7 @@ void Cop1::cvtls(const u32 instr) {
}
void Cop1::cvtdw(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<s32>(regs.cop0.status, FS(instr));
@@ -707,7 +707,7 @@ void Cop1::cvtdw(const u32 instr) {
}
void Cop1::cvtdl(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
@@ -725,7 +725,7 @@ void Cop1::cvtdl(const u32 instr) {
}
void Cop1::cvtld(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -737,7 +737,7 @@ void Cop1::cvtld(const u32 instr) {
template <typename T, bool quiet, bool cf>
bool Cop1::XORDERED(const T fs, const T ft) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (std::isnan(fs) || std::isnan(ft)) {
if (std::isnan(fs) && (!quiet || isqnan(fs)) && SetCauseInvalid()) {
regs.cop0.FireException(ExceptionCode::FloatingPointError, 0, regs.oldPC);
@@ -759,7 +759,7 @@ bool Cop1::XORDERED(const T fs, const T ft) {
template <typename T>
void Cop1::cf(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
@@ -771,7 +771,7 @@ void Cop1::cf(const u32 instr) {
template <typename T>
void Cop1::cun(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -782,7 +782,7 @@ void Cop1::cun(const u32 instr) {
template <typename T>
void Cop1::ceq(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -794,7 +794,7 @@ void Cop1::ceq(const u32 instr) {
template <typename T>
void Cop1::cueq(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -806,7 +806,7 @@ void Cop1::cueq(const u32 instr) {
template <typename T>
void Cop1::colt(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -818,7 +818,7 @@ void Cop1::colt(const u32 instr) {
template <typename T>
void Cop1::cult(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -830,7 +830,7 @@ void Cop1::cult(const u32 instr) {
template <typename T>
void Cop1::cole(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -842,7 +842,7 @@ void Cop1::cole(const u32 instr) {
template <typename T>
void Cop1::cule(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -854,7 +854,7 @@ void Cop1::cule(const u32 instr) {
template <typename T>
void Cop1::csf(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -865,7 +865,7 @@ void Cop1::csf(const u32 instr) {
template <typename T>
void Cop1::cngle(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -876,7 +876,7 @@ void Cop1::cngle(const u32 instr) {
template <typename T>
void Cop1::cseq(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -888,7 +888,7 @@ void Cop1::cseq(const u32 instr) {
template <typename T>
void Cop1::cngl(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -900,7 +900,7 @@ void Cop1::cngl(const u32 instr) {
template <typename T>
void Cop1::clt(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -912,7 +912,7 @@ void Cop1::clt(const u32 instr) {
template <typename T>
void Cop1::cnge(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -924,7 +924,7 @@ void Cop1::cnge(const u32 instr) {
template <typename T>
void Cop1::cle(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -936,7 +936,7 @@ void Cop1::cle(const u32 instr) {
template <typename T>
void Cop1::cngt(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const T fs = FGR_S<T>(regs.cop0.status, FS(instr));
@@ -980,7 +980,7 @@ template void Cop1::cle<double>(u32 instr);
template void Cop1::cngt<double>(u32 instr);
void Cop1::divs(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -994,7 +994,7 @@ void Cop1::divs(const u32 instr) {
}
void Cop1::divd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1008,7 +1008,7 @@ void Cop1::divd(const u32 instr) {
}
void Cop1::muls(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1022,7 +1022,7 @@ void Cop1::muls(const u32 instr) {
}
void Cop1::muld(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1036,7 +1036,7 @@ void Cop1::muld(const u32 instr) {
}
void Cop1::subs(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1050,7 +1050,7 @@ void Cop1::subs(const u32 instr) {
}
void Cop1::subd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1066,14 +1066,14 @@ void Cop1::subd(const u32 instr) {
void Cop1::movs(const u32 instr) { movd(instr); }
void Cop1::movd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable<true>())
return;
FGR_D<double>(regs.cop0.status, FD(instr)) = FGR_S<double>(regs.cop0.status, FS(instr));
}
void Cop1::negs(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1086,7 +1086,7 @@ void Cop1::negs(const u32 instr) {
}
void Cop1::negd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1099,7 +1099,7 @@ void Cop1::negd(const u32 instr) {
}
void Cop1::sqrts(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1112,7 +1112,7 @@ void Cop1::sqrts(const u32 instr) {
}
void Cop1::sqrtd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1125,7 +1125,7 @@ void Cop1::sqrtd(const u32 instr) {
}
void Cop1::roundls(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1140,7 +1140,7 @@ void Cop1::roundls(const u32 instr) {
}
void Cop1::roundld(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1155,7 +1155,7 @@ void Cop1::roundld(const u32 instr) {
}
void Cop1::roundws(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1170,7 +1170,7 @@ void Cop1::roundws(const u32 instr) {
}
void Cop1::roundwd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1185,7 +1185,7 @@ void Cop1::roundwd(const u32 instr) {
}
void Cop1::floorls(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1196,7 +1196,7 @@ void Cop1::floorls(const u32 instr) {
}
void Cop1::floorld(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1207,7 +1207,7 @@ void Cop1::floorld(const u32 instr) {
}
void Cop1::floorws(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1218,7 +1218,7 @@ void Cop1::floorws(const u32 instr) {
}
void Cop1::floorwd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1229,7 +1229,7 @@ void Cop1::floorwd(const u32 instr) {
}
void Cop1::truncws(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1244,7 +1244,7 @@ void Cop1::truncws(const u32 instr) {
}
void Cop1::truncwd(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1259,7 +1259,7 @@ void Cop1::truncwd(const u32 instr) {
}
void Cop1::truncls(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<float>(regs.cop0.status, FS(instr));
@@ -1274,7 +1274,7 @@ void Cop1::truncls(const u32 instr) {
}
void Cop1::truncld(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
const auto fs = FGR_S<double>(regs.cop0.status, FS(instr));
@@ -1289,8 +1289,8 @@ void Cop1::truncld(const u32 instr) {
}
void Cop1::lwc1(u32 instr) {
Mem& mem = Core::GetInstance().cpu->GetMem();
Registers& regs = Core::GetInstance().cpu->GetRegs();
Mem& mem = Core::GetMem();
Registers& regs = Core::GetRegs();
const u64 addr = static_cast<s64>(static_cast<s16>(instr)) + regs.Read<s64>(BASE(instr));
if (u32 physical; !regs.cop0.MapVAddr(Cop0::LOAD, addr, physical)) {
@@ -1303,8 +1303,8 @@ void Cop1::lwc1(u32 instr) {
}
void Cop1::swc1(u32 instr) {
Mem& mem = Core::GetInstance().cpu->GetMem();
Registers& regs = Core::GetInstance().cpu->GetRegs();
Mem& mem = Core::GetMem();
Registers& regs = Core::GetRegs();
const u64 addr = static_cast<s64>(static_cast<s16>(instr)) + regs.Read<s64>(BASE(instr));
if (u32 physical; !regs.cop0.MapVAddr(Cop0::STORE, addr, physical)) {
@@ -1316,8 +1316,8 @@ void Cop1::swc1(u32 instr) {
}
void Cop1::ldc1(u32 instr) {
Mem& mem = Core::GetInstance().cpu->GetMem();
Registers& regs = Core::GetInstance().cpu->GetRegs();
Mem& mem = Core::GetMem();
Registers& regs = Core::GetRegs();
const u64 addr = static_cast<s64>(static_cast<s16>(instr)) + regs.Read<s64>(BASE(instr));
if (u32 physical; !regs.cop0.MapVAddr(Cop0::LOAD, addr, physical)) {
@@ -1330,8 +1330,8 @@ void Cop1::ldc1(u32 instr) {
}
void Cop1::sdc1(u32 instr) {
Mem& mem = Core::GetInstance().cpu->GetMem();
Registers& regs = Core::GetInstance().cpu->GetRegs();
Mem& mem = Core::GetMem();
Registers& regs = Core::GetRegs();
const u64 addr = static_cast<s64>(static_cast<s16>(instr)) + regs.Read<s64>(BASE(instr));
if (u32 physical; !regs.cop0.MapVAddr(Cop0::STORE, addr, physical)) {
@@ -1343,7 +1343,7 @@ void Cop1::sdc1(u32 instr) {
}
void Cop1::unimplemented() {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable())
return;
SetCauseUnimplemented();
@@ -1351,28 +1351,28 @@ void Cop1::unimplemented() {
}
void Cop1::mfc1(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable<true>())
return;
regs.Write(RT(instr), FGR_T<s32>(regs.cop0.status, FS(instr)));
}
void Cop1::dmfc1(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable<true>())
return;
regs.Write(RT(instr), FGR_S<s64>(regs.cop0.status, FS(instr)));
}
void Cop1::mtc1(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable<true>())
return;
FGR_T<s32>(regs.cop0.status, FS(instr)) = regs.Read<s64>(RT(instr));
}
void Cop1::dmtc1(const u32 instr) {
Registers& regs = Core::GetInstance().cpu->GetRegs();
Registers& regs = Core::GetRegs();
if (!CheckFPUUsable<true>())
return;
FGR_S<u64>(regs.cop0.status, FS(instr)) = regs.Read<s64>(RT(instr));