Rename dynarec to JIT everywhere

2023-02-21 02:20:35 +01:00
parent 1c42170810
commit 030f04df03
25 changed files with 437 additions and 429 deletions
--- a/src/backend/Core.hpp
+++ b/src/backend/Core.hpp
@@ -3,7 +3,7 @@
 #include <backend/core/Interpreter.hpp>
 #include <backend/core/Mem.hpp>
 #include <string>
-#include <backend/core/Dynarec.hpp>
+#include <backend/core/JIT.hpp>
 #include <backend/core/registers/Registers.hpp>
 #include <Debugger.hpp>
 #include <SDL2/SDL_timer.h>
@@ -12,7 +12,7 @@ struct Window;

 namespace n64 {
 enum class CpuType {
-  Dynarec, Interpreter, NONE
+  Interpreter, JIT, COUNT
 };

 struct Core {
@@ -31,7 +31,7 @@ struct Core {
  bool romLoaded = false;
  bool done = false;
  std::string rom;
-  CpuType cpuType = CpuType::NONE;
+  CpuType cpuType = CpuType::COUNT;
  std::unique_ptr<BaseCPU> cpu;
  Debugger debugger{*this};
 };
--- a/src/backend/core/Dynarec.cpp
+++ b/src/backend/core/Dynarec.cpp
@@ -1,18 +1,17 @@
-#include <Core.hpp>
 #include <Registers.hpp>
 #include <filesystem>
-#include "Dynarec.hpp"
+#include <JIT.hpp>


 namespace n64 {
 namespace fs = std::filesystem;

-Dynarec::~Dynarec() {
+JIT::~JIT() {
  Util::aligned_free(codeCache);
  dump.close();
 }

-Dynarec::Dynarec() : code(CODECACHE_SIZE, codeCache) {
+JIT::JIT() : code(CODECACHE_SIZE, codeCache) {
  codeCache = (u8*)Util::aligned_alloc(4096, CODECACHE_SIZE);
  CodeArray::protect(
    codeCache,
@@ -47,7 +46,7 @@ inline void CheckCompareInterrupt(MI& mi, Registers& regs) {
  }
 }

-void Dynarec::Recompile(Mem& mem, u32 pc) {
+void JIT::Recompile(Mem& mem, u32 pc) {
  bool branch = false, prevBranch = false;
  u32 startPC = pc;
  u32 loopPC = pc;
@@ -95,11 +94,11 @@ void Dynarec::Recompile(Mem& mem, u32 pc) {
  blockCache[startPC >> 20][startPC & 0xFFF]();
 }

-void Dynarec::AllocateOuter(u32 pc) {
+void JIT::AllocateOuter(u32 pc) {
  blockCache[pc >> 20] = (Fn*)bumpAlloc(0x1000 * sizeof(Fn));
 }

-int Dynarec::Run() {
+int JIT::Run() {
  /*instrInBlock = 0;
  regs.gpr[0] = 0;
  regs.prevDelaySlot = regs.delaySlot;
@@ -134,7 +133,7 @@ int Dynarec::Run() {
  Util::panic("JIT RECOMPILER NOT YET IMPLEMENTED!\n");
 }

-void Dynarec::Reset() {
+void JIT::Reset() {
  code.reset();
  regs.Reset();
  InvalidateCache();
--- a/src/backend/core/Dynarec.hpp
+++ b/src/backend/core/Dynarec.hpp
@@ -14,9 +14,9 @@ using Fn = void (*)();
 #define CODECACHE_SIZE (2 << 25)
 #define CODECACHE_OVERHEAD (CODECACHE_SIZE - 1_kb)

-struct Dynarec : BaseCPU {
-  Dynarec();
-  ~Dynarec() override;
+struct JIT : BaseCPU {
+  JIT();
+  ~JIT() override;
  int Run() override;
  void Reset() override;
  u64 cop2Latch{};
--- a/src/backend/core/Mem.cpp
+++ b/src/backend/core/Mem.cpp
@@ -3,7 +3,7 @@
 #include <core/registers/Registers.hpp>
 #include <core/registers/Cop0.hpp>
 #include <core/Interpreter.hpp>
-#include <core/Dynarec.hpp>
+#include <core/JIT.hpp>
 #include <File.hpp>

 namespace n64 {
@@ -217,22 +217,22 @@ u64 Mem::Read64(n64::Registers &regs, u32 paddr) {
  }
 }

-void Mem::Write8(Registers& regs, n64::Dynarec& dyn, u32 paddr, u32 val) {
+void Mem::Write8(Registers& regs, JIT& dyn, u32 paddr, u32 val) {
  dyn.InvalidatePage(BYTE_ADDRESS(paddr));
  return Write8(regs, paddr, val);
 }

-void Mem::Write16(Registers& regs, n64::Dynarec& dyn, u32 paddr, u32 val) {
+void Mem::Write16(Registers& regs, JIT& dyn, u32 paddr, u32 val) {
  dyn.InvalidatePage(HALF_ADDRESS(paddr));
  return Write16(regs, paddr, val);
 }

-void Mem::Write32(Registers& regs, n64::Dynarec& dyn, u32 paddr, u32 val) {
+void Mem::Write32(Registers& regs, JIT& dyn, u32 paddr, u32 val) {
  dyn.InvalidatePage(paddr);
  return Write32(regs, paddr, val);
 }

-void Mem::Write64(Registers& regs, n64::Dynarec& dyn, u32 paddr, u64 val) {
+void Mem::Write64(Registers& regs, JIT& dyn, u32 paddr, u64 val) {
  dyn.InvalidatePage(paddr);
  return Write64(regs, paddr, val);
 }
--- a/src/backend/core/Mem.hpp
+++ b/src/backend/core/Mem.hpp
@@ -15,7 +15,7 @@ struct CartInfo {
  u32 crc;
 };

-struct Dynarec;
+struct JIT;

 struct Mem {
  ~Mem() {
@@ -32,10 +32,10 @@ struct Mem {
  u16 Read16(Registers&, u32);
  u32 Read32(Registers&, u32);
  u64 Read64(Registers&, u32);
-  void Write8(Registers&, Dynarec&, u32, u32);
-  void Write16(Registers&, Dynarec&, u32, u32);
-  void Write32(Registers&, Dynarec&, u32, u32);
-  void Write64(Registers&, Dynarec&, u32, u64);
+  void Write8(Registers&, JIT&, u32, u32);
+  void Write16(Registers&, JIT&, u32, u32);
+  void Write32(Registers&, JIT&, u32, u32);
+  void Write64(Registers&, JIT&, u32, u64);
  void Write8(Registers&, u32, u32);
  void Write16(Registers&, u32, u32);
  void Write32(Registers&, u32, u32);
--- a/src/backend/core/dynarec/cop/cop0decode.hpp
+++ b/src/backend/core/dynarec/cop/cop0decode.hpp
@@ -1,7 +0,0 @@
-#pragma once
-#include <Dynarec.hpp>
-
-namespace n64 {
-struct Registers;
-void cop0Decode(Registers&, Dynarec& cpu, u32 instr);
-}
--- a/src/backend/core/dynarec/cop/cop0instructions.hpp
+++ b/src/backend/core/dynarec/cop/cop0instructions.hpp
@@ -1,13 +0,0 @@
-#pragma once
-#include <Dynarec.hpp>
-
-namespace n64 {
-void mtc0(Dynarec&, u32);
-void dmtc0(Dynarec&, u32);
-void mfc0(Dynarec&, u32);
-void dmfc0(Dynarec&, u32);
-void eret(Dynarec&);
-void tlbr(Dynarec&);
-void tlbw(Dynarec&, int);
-void tlbp(Dynarec&);
-}
--- a/src/backend/core/dynarec/cop/cop1decode.hpp
+++ b/src/backend/core/dynarec/cop/cop1decode.hpp
@@ -1,6 +0,0 @@
-#pragma once
-#include <dynarec/cop/cop1instructions.hpp>
-
-namespace n64 {
-bool cop1Decode(Registers&, Dynarec& cpu, u32 instr);
-}
--- a/src/backend/core/dynarec/cop/cop1instructions.hpp
+++ b/src/backend/core/dynarec/cop/cop1instructions.hpp
@@ -1,68 +0,0 @@
-#pragma once
-#include <Dynarec.hpp>
-#include <Cop1.hpp>
-
-namespace n64 {
-void absd(Dynarec&, u32 instr);
-void abss(Dynarec&, u32 instr);
-void absw(Dynarec&, u32 instr);
-void absl(Dynarec&, u32 instr);
-void adds(Dynarec&, u32 instr);
-void addd(Dynarec&, u32 instr);
-void subs(Dynarec&, u32 instr);
-void subd(Dynarec&, u32 instr);
-void subw(Dynarec&, u32 instr);
-void subl(Dynarec&, u32 instr);
-void ceills(Dynarec&, u32 instr);
-void ceilws(Dynarec&, u32 instr);
-void ceilld(Dynarec&, u32 instr);
-void ceilwd(Dynarec&, u32 instr);
-void cfc1(Dynarec&, u32 instr);
-void ctc1(Dynarec&, u32 instr);
-void roundls(Dynarec&, u32 instr);
-void roundld(Dynarec&, u32 instr);
-void roundws(Dynarec&, u32 instr);
-void roundwd(Dynarec&, u32 instr);
-void floorls(Dynarec&, u32 instr);
-void floorld(Dynarec&, u32 instr);
-void floorws(Dynarec&, u32 instr);
-void floorwd(Dynarec&, u32 instr);
-void cvtls(Dynarec&, u32 instr);
-void cvtws(Dynarec&, u32 instr);
-void cvtds(Dynarec&, u32 instr);
-void cvtsw(Dynarec&, u32 instr);
-void cvtdw(Dynarec&, u32 instr);
-void cvtsd(Dynarec&, u32 instr);
-void cvtwd(Dynarec&, u32 instr);
-void cvtld(Dynarec&, u32 instr);
-void cvtdl(Dynarec&, u32 instr);
-void cvtsl(Dynarec&, u32 instr);
-template <typename T>
-void ccond(Dynarec&, u32 instr, CompConds);
-void divs(Dynarec&, u32 instr);
-void divd(Dynarec&, u32 instr);
-void muls(Dynarec&, u32 instr);
-void muld(Dynarec&, u32 instr);
-void mulw(Dynarec&, u32 instr);
-void mull(Dynarec&, u32 instr);
-void movs(Dynarec&, u32 instr);
-void movd(Dynarec&, u32 instr);
-void movw(Dynarec&, u32 instr);
-void movl(Dynarec&, u32 instr);
-void negs(Dynarec&, u32 instr);
-void negd(Dynarec&, u32 instr);
-void sqrts(Dynarec&, u32 instr);
-void sqrtd(Dynarec&, u32 instr);
-void lwc1(Dynarec&, u32 instr);
-void swc1(Dynarec&, u32 instr);
-void ldc1(Dynarec&, u32 instr);
-void mfc1(Dynarec&, u32 instr);
-void dmfc1(Dynarec&, u32 instr);
-void mtc1(Dynarec&, u32 instr);
-void dmtc1(Dynarec&, u32 instr);
-void sdc1(Dynarec&, u32 instr);
-void truncws(Dynarec&, u32 instr);
-void truncwd(Dynarec&, u32 instr);
-void truncls(Dynarec&, u32 instr);
-void truncld(Dynarec&, u32 instr);
-}
--- a/src/backend/core/dynarec/instructions.hpp
+++ b/src/backend/core/dynarec/instructions.hpp
@@ -1,94 +0,0 @@
-#pragma once
-#include <Dynarec.hpp>
-
-namespace n64 {
-void add(Dynarec&, u32);
-void addu(Dynarec&, u32);
-void addi(Dynarec&, u32);
-void addiu(Dynarec&, u32);
-void andi(Dynarec&, u32);
-void and_(Dynarec&, u32);
-void branch(Dynarec&, bool, s64);
-void branch_likely(Dynarec&, bool, s64);
-void b(Dynarec&, u32, bool);
-void blink(Dynarec&, u32, bool);
-void bl(Dynarec&, u32, bool);
-void bllink(Dynarec&, u32, bool);
-void dadd(Dynarec&, u32);
-void daddu(Dynarec&, u32);
-void daddi(Dynarec&, u32);
-void daddiu(Dynarec&, u32);
-void ddiv(Dynarec&, u32);
-void ddivu(Dynarec&, u32);
-void div(Dynarec&, u32);
-void divu(Dynarec&, u32);
-void dmult(Dynarec&, u32);
-void dmultu(Dynarec&, u32);
-void dsll(Dynarec&, u32);
-void dsllv(Dynarec&, u32);
-void dsll32(Dynarec&, u32);
-void dsra(Dynarec&, u32);
-void dsrav(Dynarec&, u32);
-void dsra32(Dynarec&, u32);
-void dsrl(Dynarec&, u32);
-void dsrlv(Dynarec&, u32);
-void dsrl32(Dynarec&, u32);
-void dsub(Dynarec&, u32);
-void dsubu(Dynarec&, u32);
-void j(Dynarec&, u32);
-void jr(Dynarec&, u32);
-void jal(Dynarec&, u32);
-void jalr(Dynarec&, u32);
-void lui(Dynarec&, u32);
-void lbu(Dynarec&, u32);
-void lb(Dynarec&, u32);
-void ld(Dynarec&, u32);
-void ldl(Dynarec&, u32);
-void ldr(Dynarec&, u32);
-void lh(Dynarec&, u32);
-void lhu(Dynarec&, u32);
-void ll(Dynarec&, u32);
-void lld(Dynarec&, u32);
-void lw(Dynarec&, u32);
-void lwl(Dynarec&, u32);
-void lwu(Dynarec&, u32);
-void lwr(Dynarec&, u32);
-void mfhi(Dynarec&, u32);
-void mflo(Dynarec&, u32);
-void mult(Dynarec&, u32);
-void multu(Dynarec&, u32);
-void mthi(Dynarec&, u32);
-void mtlo(Dynarec&, u32);
-void nor(Dynarec&, u32);
-void sb(Dynarec&, u32);
-void sc(Dynarec&, u32);
-void scd(Dynarec&, u32);
-void sd(Dynarec&, u32);
-void sdl(Dynarec&, u32);
-void sdr(Dynarec&, u32);
-void sh(Dynarec&, u32);
-void sw(Dynarec&, u32);
-void swl(Dynarec&, u32);
-void swr(Dynarec&, u32);
-void slti(Dynarec&, u32);
-void sltiu(Dynarec&, u32);
-void slt(Dynarec&, u32);
-void sltu(Dynarec&, u32);
-void sll(Dynarec&, u32);
-void sllv(Dynarec&, u32);
-void sub(Dynarec&, u32);
-void subu(Dynarec&, u32);
-void sra(Dynarec&, u32);
-void srav(Dynarec&, u32);
-void srl(Dynarec&, u32);
-void srlv(Dynarec&, u32);
-void trap(Dynarec&, bool);
-void or_(Dynarec&, u32);
-void ori(Dynarec&, u32);
-void xor_(Dynarec&, u32);
-void xori(Dynarec&, u32);
-void mtc2(Dynarec&, u32);
-void mfc2(Dynarec&, u32);
-void dmtc2(Dynarec&, u32);
-void dmfc2(Dynarec&, u32);
-}
--- a/src/backend/core/dynarec/CMakeLists.txt
+++ b/src/backend/core/dynarec/CMakeLists.txt
@@ -1,4 +1,4 @@
 file(GLOB_RECURSE SOURCES *.cpp)
 file(GLOB_RECURSE HEADERS *.hpp)

-add_library(dynarec ${SOURCES} ${HEADERS})
+add_library(jit ${SOURCES} ${HEADERS})
--- a/src/backend/core/dynarec/MemoryManagement.cpp
+++ b/src/backend/core/dynarec/MemoryManagement.cpp
@@ -1,18 +1,18 @@
-#include <core/Dynarec.hpp>
+#include <core/JIT.hpp>

 namespace n64 {
-void Dynarec::InvalidatePage(u32 paddr) {
+void JIT::InvalidatePage(u32 paddr) {
  blockCache[paddr >> 20] = nullptr;
 }

-void Dynarec::InvalidateCache() {
+void JIT::InvalidateCache() {
  sizeUsed = 0;
  for(int i = 0; i < 0x80000; i++) {
    blockCache[i] = nullptr;
  }
 }

-void* Dynarec::bumpAlloc(u64 size, u8 val) {
+void* JIT::bumpAlloc(u64 size, u8 val) {
  if(sizeUsed + size >= CODECACHE_SIZE) {
    InvalidateCache();
  }
--- a/src/backend/core/dynarec/cop/cop0decode.cpp
+++ b/src/backend/core/dynarec/cop/cop0decode.cpp
@@ -1,9 +1,9 @@
-#include <dynarec/cop/cop0decode.hpp>
+#include <jit/cop/cop0decode.hpp>
+#include <jit/cop/cop0instructions.hpp>
 #include <Registers.hpp>
-#include <dynarec/cop/cop0instructions.hpp>

 namespace n64 {
-void cop0Decode(Registers& regs, Dynarec& cpu, u32 instr) {
+void cop0Decode(Registers& regs, JIT& cpu, u32 instr) {
  u8 mask_cop = (instr >> 21) & 0x1F;
  u8 mask_cop2 = instr & 0x3F;
  Xbyak::CodeGenerator& code = cpu.code;
--- a/src/backend/core/jit/cop/cop0decode.hpp
+++ b/src/backend/core/jit/cop/cop0decode.hpp
@@ -0,0 +1,7 @@
+#pragma once
+#include <JIT.hpp>
+
+namespace n64 {
+struct Registers;
+void cop0Decode(Registers&, JIT& cpu, u32 instr);
+}
--- a/src/backend/core/dynarec/cop/cop0instructions.cpp
+++ b/src/backend/core/dynarec/cop/cop0instructions.cpp
@@ -1,29 +1,29 @@
-#include <dynarec/cop/cop0instructions.hpp>
+#include <jit/cop/cop0instructions.hpp>
 #include <log.hpp>
 #include <Registers.hpp>

 namespace n64 {
-void mtc0(Dynarec& cpu, u32 instr) {
+void mtc0(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop0.SetReg32(RD(instr), regs.gpr[RT(instr)]);
 }

-void dmtc0(Dynarec& cpu, u32 instr) {
+void dmtc0(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop0.SetReg64(RD(instr), regs.gpr[RT(instr)]);
 }

-void mfc0(Dynarec& cpu, u32 instr) {
+void mfc0(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.gpr[RT(instr)] = s32(regs.cop0.GetReg32(RD(instr)));
 }

-void dmfc0(Dynarec& cpu, u32 instr) {
+void dmfc0(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.gpr[RT(instr)] = s64(regs.cop0.GetReg64(RD(instr)));
 }

-void eret(Dynarec& cpu) {
+void eret(JIT& cpu) {
  Registers& regs = cpu.regs;
  if(regs.cop0.status.erl) {
    regs.SetPC64(regs.cop0.ErrorEPC);
@@ -36,7 +36,7 @@ void eret(Dynarec& cpu) {
 }


-void tlbr(Dynarec& cpu) {
+void tlbr(JIT& cpu) {
  Registers& regs = cpu.regs;
  u8 Index = regs.cop0.index & 0b111111;
  if (Index >= 32) {
@@ -54,7 +54,7 @@ void tlbr(Dynarec& cpu) {
  regs.cop0.pageMask.raw = entry.pageMask.raw;
 }

-void tlbw(Dynarec& cpu, int index_) {
+void tlbw(JIT& cpu, int index_) {
  Registers& regs = cpu.regs;
  PageMask page_mask = regs.cop0.pageMask;
  u32 top = page_mask.mask & 0xAAA;
@@ -75,7 +75,7 @@ void tlbw(Dynarec& cpu, int index_) {
  regs.cop0.tlb[index_].initialized = true;
 }

-void tlbp(Dynarec& cpu) {
+void tlbp(JIT& cpu) {
  Registers& regs = cpu.regs;
  int match = -1;
  TLBEntry* entry = TLBTryMatch(regs, regs.cop0.entryHi.raw, &match);
--- a/src/backend/core/jit/cop/cop0instructions.hpp
+++ b/src/backend/core/jit/cop/cop0instructions.hpp
@@ -0,0 +1,13 @@
+#pragma once
+#include <JIT.hpp>
+
+namespace n64 {
+void mtc0(JIT&, u32);
+void dmtc0(JIT&, u32);
+void mfc0(JIT&, u32);
+void dmfc0(JIT&, u32);
+void eret(JIT&);
+void tlbr(JIT&);
+void tlbw(JIT&, int);
+void tlbp(JIT&);
+}
--- a/src/backend/core/dynarec/cop/cop1decode.cpp
+++ b/src/backend/core/dynarec/cop/cop1decode.cpp
@@ -1,9 +1,9 @@
-#include <dynarec/cop/cop1decode.hpp>
-#include <dynarec/instructions.hpp>
+#include <jit/cop/cop1decode.hpp>
+#include <jit/instructions.hpp>
 #include <Registers.hpp>

 namespace n64 {
-bool cop1Decode(Registers& regs, Dynarec& cpu, u32 instr) {
+bool cop1Decode(Registers& regs, JIT& cpu, u32 instr) {
  Xbyak::CodeGenerator& code = cpu.code;

  u8 mask_sub = (instr >> 21) & 0x1F;
--- a/src/backend/core/jit/cop/cop1decode.hpp
+++ b/src/backend/core/jit/cop/cop1decode.hpp
@@ -0,0 +1,6 @@
+#pragma once
+#include <jit/cop/cop1instructions.hpp>
+
+namespace n64 {
+bool cop1Decode(Registers&, JIT& cpu, u32 instr);
+}
--- a/src/backend/core/dynarec/cop/cop1instructions.cpp
+++ b/src/backend/core/dynarec/cop/cop1instructions.cpp
@@ -1,4 +1,4 @@
-#include <dynarec/cop/cop1instructions.hpp>
+#include <jit/cop/cop1instructions.hpp>
 #include <cfenv>
 #include <cmath>
 #include <Cop1.hpp>
@@ -29,31 +29,31 @@ inline int PushRoundingMode(const FCR31& fcr31) {
  }                               \
 } while(0)

-void absd(Dynarec& cpu, u32 instr) {
+void absd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  regs.cop1.SetCop1Reg<double>(regs.cop0, FD(instr), std::abs(fs));
 }

-void abss(Dynarec& cpu, u32 instr) {
+void abss(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  regs.cop1.SetCop1Reg<float>(regs.cop0, FD(instr), std::abs(fs));
 }

-void absw(Dynarec& cpu, u32 instr) {
+void absw(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  s32 fs = regs.cop1.GetReg<s32>(regs.cop0, FS(instr));
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), std::abs(fs));
 }

-void absl(Dynarec& cpu, u32 instr) {
+void absl(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  s64 fs = regs.cop1.GetReg<s64>(regs.cop0, FS(instr));
  regs.cop1.SetReg(regs.cop0, FD(instr), std::abs(fs));
 }

-void adds(Dynarec& cpu, u32 instr) {
+void adds(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  auto ft = regs.cop1.GetCop1Reg<float>(regs.cop0, FT(instr));
@@ -62,7 +62,7 @@ void adds(Dynarec& cpu, u32 instr) {
  regs.cop1.SetCop1Reg<float>(regs.cop0, FD(instr), result);
 }

-void addd(Dynarec& cpu, u32 instr) {
+void addd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  auto ft = regs.cop1.GetCop1Reg<double>(regs.cop0, FT(instr));
@@ -71,35 +71,35 @@ void addd(Dynarec& cpu, u32 instr) {
  regs.cop1.SetCop1Reg<double>(regs.cop0, FD(instr), result);
 }

-void ceills(Dynarec& cpu, u32 instr) {
+void ceills(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  s64 result = std::ceil(fs);
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), result);
 }

-void ceilws(Dynarec& cpu, u32 instr) {
+void ceilws(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  s32 result = std::ceil(fs);
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), result);
 }

-void ceilld(Dynarec& cpu, u32 instr) {
+void ceilld(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  s64 result = std::ceil(fs);
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), result);
 }

-void ceilwd(Dynarec& cpu, u32 instr) {
+void ceilwd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  auto fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  s32 result = std::ceil(fs);
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), result);
 }

-void cfc1(Dynarec& cpu, u32 instr) {
+void cfc1(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  u8 fd = RD(instr);
  s32 val = 0;
@@ -111,7 +111,7 @@ void cfc1(Dynarec& cpu, u32 instr) {
  regs.gpr[RT(instr)] = val;
 }

-void ctc1(Dynarec& cpu, u32 instr) {
+void ctc1(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  u8 fs = FS(instr);
  u32 val = regs.gpr[RT(instr)];
@@ -125,7 +125,7 @@ void ctc1(Dynarec& cpu, u32 instr) {
  }
 }

-void cvtds(Dynarec& cpu, u32 instr) {
+void cvtds(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<double>(
    regs.cop0,
@@ -137,7 +137,7 @@ void cvtds(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtsd(Dynarec& cpu, u32 instr) {
+void cvtsd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<float>(
    regs.cop0,
@@ -149,7 +149,7 @@ void cvtsd(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtwd(Dynarec& cpu, u32 instr) {
+void cvtwd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u32>(
    regs.cop0,
@@ -161,7 +161,7 @@ void cvtwd(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtws(Dynarec& cpu, u32 instr) {
+void cvtws(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u32>(
    regs.cop0,
@@ -173,7 +173,7 @@ void cvtws(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtls(Dynarec& cpu, u32 instr) {
+void cvtls(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u64>(
    regs.cop0,
@@ -185,7 +185,7 @@ void cvtls(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtsl(Dynarec& cpu, u32 instr) {
+void cvtsl(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<float>(
    regs.cop0,
@@ -197,7 +197,7 @@ void cvtsl(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtdw(Dynarec& cpu, u32 instr) {
+void cvtdw(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<double>(
    regs.cop0,
@@ -209,7 +209,7 @@ void cvtdw(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtsw(Dynarec& cpu, u32 instr) {
+void cvtsw(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<float>(
    regs.cop0,
@@ -221,7 +221,7 @@ void cvtsw(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtdl(Dynarec& cpu, u32 instr) {
+void cvtdl(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<double>(
    regs.cop0,
@@ -233,7 +233,7 @@ void cvtdl(Dynarec& cpu, u32 instr) {
  );
 }

-void cvtld(Dynarec& cpu, u32 instr) {
+void cvtld(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u64>(
    regs.cop0,
@@ -246,7 +246,7 @@ void cvtld(Dynarec& cpu, u32 instr) {
 }

 template <typename T>
-inline bool CalculateCondition(Dynarec& cpu, T fs, T ft, CompConds cond) {
+inline bool CalculateCondition(JIT& cpu, T fs, T ft, CompConds cond) {
  Registers& regs = cpu.regs;
  switch(cond) {
    case F: return false;
@@ -270,7 +270,7 @@ inline bool CalculateCondition(Dynarec& cpu, T fs, T ft, CompConds cond) {
 }

 template <typename T>
-void ccond(Dynarec& cpu, u32 instr, CompConds cond) {
+void ccond(JIT& cpu, u32 instr, CompConds cond) {
  Registers& regs = cpu.regs;
  T fs = regs.cop1.GetCop1Reg<T>(regs.cop0, FS(instr));
  T ft = regs.cop1.GetCop1Reg<T>(regs.cop0, FT(instr));
@@ -278,80 +278,80 @@ void ccond(Dynarec& cpu, u32 instr, CompConds cond) {
  regs.cop1.fcr31.compare = CalculateCondition(cpu, fs, ft, cond);
 }

-template void ccond<float>(Dynarec& cpu, u32 instr, CompConds cond);
-template void ccond<double>(Dynarec& cpu, u32 instr, CompConds cond);
+template void ccond<float>(JIT& cpu, u32 instr, CompConds cond);
+template void ccond<double>(JIT& cpu, u32 instr, CompConds cond);

-void divs(Dynarec& cpu, u32 instr) {
+void divs(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  float ft = regs.cop1.GetCop1Reg<float>(regs.cop0, FT(instr));
  regs.cop1.SetCop1Reg<float>(regs.cop0, FD(instr), fs / ft);
 }

-void divd(Dynarec& cpu, u32 instr) {
+void divd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  double ft = regs.cop1.GetCop1Reg<double>(regs.cop0, FT(instr));
  regs.cop1.SetCop1Reg<double>(regs.cop0, FD(instr), fs / ft);
 }

-void muls(Dynarec& cpu, u32 instr) {
+void muls(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  float ft = regs.cop1.GetCop1Reg<float>(regs.cop0, FT(instr));
  regs.cop1.SetCop1Reg<float>(regs.cop0, FD(instr), fs * ft);
 }

-void muld(Dynarec& cpu, u32 instr) {
+void muld(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  double ft = regs.cop1.GetCop1Reg<double>(regs.cop0, FT(instr));
  regs.cop1.SetCop1Reg<double>(regs.cop0, FD(instr), fs * ft);
 }

-void mulw(Dynarec& cpu, u32 instr) {
+void mulw(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  u32 fs = regs.cop1.GetReg<u32>(regs.cop0, FS(instr));
  u32 ft = regs.cop1.GetReg<u32>(regs.cop0, FT(instr));
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), fs * ft);
 }

-void mull(Dynarec& cpu, u32 instr) {
+void mull(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  u64 fs = regs.cop1.GetReg<u64>(regs.cop0, FS(instr));
  u64 ft = regs.cop1.GetReg<u64>(regs.cop0, FT(instr));
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), fs * ft);
 }

-void subs(Dynarec& cpu, u32 instr) {
+void subs(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  float ft = regs.cop1.GetCop1Reg<float>(regs.cop0, FT(instr));
  regs.cop1.SetCop1Reg<float>(regs.cop0, FD(instr), fs - ft);
 }

-void subd(Dynarec& cpu, u32 instr) {
+void subd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  double ft = regs.cop1.GetCop1Reg<double>(regs.cop0, FT(instr));
  regs.cop1.SetCop1Reg<double>(regs.cop0, FD(instr), fs - ft);
 }

-void subw(Dynarec& cpu, u32 instr) {
+void subw(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  u32 fs = regs.cop1.GetReg<u32>(regs.cop0, FS(instr));
  u32 ft = regs.cop1.GetReg<u32>(regs.cop0, FT(instr));
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), fs - ft);
 }

-void subl(Dynarec& cpu, u32 instr) {
+void subl(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  u64 fs = regs.cop1.GetReg<u64>(regs.cop0, FS(instr));
  u64 ft = regs.cop1.GetReg<u64>(regs.cop0, FT(instr));
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), fs - ft);
 }

-void movs(Dynarec& cpu, u32 instr) {
+void movs(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<float>(
    regs.cop0,
@@ -363,7 +363,7 @@ void movs(Dynarec& cpu, u32 instr) {
  );
 }

-void movd(Dynarec& cpu, u32 instr) {
+void movd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<double>(
    regs.cop0,
@@ -375,7 +375,7 @@ void movd(Dynarec& cpu, u32 instr) {
  );
 }

-void movw(Dynarec& cpu, u32 instr) {
+void movw(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u32>(
    regs.cop0,
@@ -387,7 +387,7 @@ void movw(Dynarec& cpu, u32 instr) {
  );
 }

-void movl(Dynarec& cpu, u32 instr) {
+void movl(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u64>(
    regs.cop0,
@@ -399,7 +399,7 @@ void movl(Dynarec& cpu, u32 instr) {
  );
 }

-void negs(Dynarec& cpu, u32 instr) {
+void negs(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<float>(
    regs.cop0,
@@ -411,7 +411,7 @@ void negs(Dynarec& cpu, u32 instr) {
  );
 }

-void negd(Dynarec& cpu, u32 instr) {
+void negd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetCop1Reg<double>(
    regs.cop0,
@@ -423,19 +423,19 @@ void negd(Dynarec& cpu, u32 instr) {
  );
 }

-void sqrts(Dynarec& cpu, u32 instr) {
+void sqrts(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  regs.cop1.SetCop1Reg<float>(regs.cop0, FD(instr), std::sqrt(fs));
 }

-void sqrtd(Dynarec& cpu, u32 instr) {
+void sqrtd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  regs.cop1.SetCop1Reg<double>(regs.cop0, FD(instr), std::sqrt(fs));
 }

-void roundls(Dynarec& cpu, u32 instr) {
+void roundls(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  PUSHROUNDINGMODE;
@@ -443,7 +443,7 @@ void roundls(Dynarec& cpu, u32 instr) {
  POPROUNDINGMODE;
 }

-void roundld(Dynarec& cpu, u32 instr) {
+void roundld(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  PUSHROUNDINGMODE;
@@ -451,7 +451,7 @@ void roundld(Dynarec& cpu, u32 instr) {
  POPROUNDINGMODE;
 }

-void roundws(Dynarec& cpu, u32 instr) {
+void roundws(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  PUSHROUNDINGMODE;
@@ -459,7 +459,7 @@ void roundws(Dynarec& cpu, u32 instr) {
  POPROUNDINGMODE;
 }

-void roundwd(Dynarec& cpu, u32 instr) {
+void roundwd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  PUSHROUNDINGMODE;
@@ -467,31 +467,31 @@ void roundwd(Dynarec& cpu, u32 instr) {
  POPROUNDINGMODE;
 }

-void floorls(Dynarec& cpu, u32 instr) {
+void floorls(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), (s64)std::floor(fs));
 }

-void floorld(Dynarec& cpu, u32 instr) {
+void floorld(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), (s64)std::floor(fs));
 }

-void floorws(Dynarec& cpu, u32 instr) {
+void floorws(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), (s64)std::floor(fs));
 }

-void floorwd(Dynarec& cpu, u32 instr) {
+void floorwd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), (s64)std::floor(fs));
 }

-void lwc1(Dynarec& cpu, u32 instr) {
+void lwc1(JIT& cpu, u32 instr) {
  Mem& mem = cpu.mem;
  Registers& regs = cpu.regs;
  if(!regs.cop0.status.cu1) {
@@ -511,7 +511,7 @@ void lwc1(Dynarec& cpu, u32 instr) {
  }
 }

-void swc1(Dynarec& cpu, u32 instr) {
+void swc1(JIT& cpu, u32 instr) {
  Mem& mem = cpu.mem;
  Registers& regs = cpu.regs;
  if(!regs.cop0.status.cu1) {
@@ -530,7 +530,7 @@ void swc1(Dynarec& cpu, u32 instr) {
  }
 }

-void ldc1(Dynarec& cpu, u32 instr) {
+void ldc1(JIT& cpu, u32 instr) {
  Mem& mem = cpu.mem;
  Registers& regs = cpu.regs;
  if(!regs.cop0.status.cu1) {
@@ -550,7 +550,7 @@ void ldc1(Dynarec& cpu, u32 instr) {
  }
 }

-void sdc1(Dynarec& cpu, u32 instr) {
+void sdc1(JIT& cpu, u32 instr) {
  Mem& mem = cpu.mem;
  Registers& regs = cpu.regs;
  if(!regs.cop0.status.cu1) {
@@ -569,50 +569,50 @@ void sdc1(Dynarec& cpu, u32 instr) {
  }
 }

-void truncws(Dynarec& cpu, u32 instr) {
+void truncws(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  s32 result = (s32)std::trunc(fs);
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), result);
 }

-void truncwd(Dynarec& cpu, u32 instr) {
+void truncwd(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  s32 result = (s32)std::trunc(fs);
  regs.cop1.SetReg<u32>(regs.cop0, FD(instr), result);
 }

-void truncls(Dynarec& cpu, u32 instr) {
+void truncls(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  float fs = regs.cop1.GetCop1Reg<float>(regs.cop0, FS(instr));
  s64 result = (s64)std::trunc(fs);
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), result);
 }

-void truncld(Dynarec& cpu, u32 instr) {
+void truncld(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  double fs = regs.cop1.GetCop1Reg<double>(regs.cop0, FS(instr));
  s64 result = (s64)std::trunc(fs);
  regs.cop1.SetReg<u64>(regs.cop0, FD(instr), result);
 }

-void mfc1(Dynarec& cpu, u32 instr) {
+void mfc1(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.gpr[RT(instr)] = (s32)regs.cop1.GetReg<u32>(regs.cop0, FS(instr));
 }

-void dmfc1(Dynarec& cpu, u32 instr) {
+void dmfc1(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.gpr[RT(instr)] = (s64)regs.cop1.GetReg<u64>(regs.cop0, FS(instr));
 }

-void mtc1(Dynarec& cpu, u32 instr) {
+void mtc1(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u32>(regs.cop0, FS(instr), regs.gpr[RT(instr)]);
 }

-void dmtc1(Dynarec& cpu, u32 instr) {
+void dmtc1(JIT& cpu, u32 instr) {
  Registers& regs = cpu.regs;
  regs.cop1.SetReg<u64>(regs.cop0, FS(instr), regs.gpr[RT(instr)]);
 }
--- a/src/backend/core/jit/cop/cop1instructions.hpp
+++ b/src/backend/core/jit/cop/cop1instructions.hpp
@@ -0,0 +1,68 @@
+#pragma once
+#include <JIT.hpp>
+#include <Cop1.hpp>
+
+namespace n64 {
+void absd(JIT&, u32 instr);
+void abss(JIT&, u32 instr);
+void absw(JIT&, u32 instr);
+void absl(JIT&, u32 instr);
+void adds(JIT&, u32 instr);
+void addd(JIT&, u32 instr);
+void subs(JIT&, u32 instr);
+void subd(JIT&, u32 instr);
+void subw(JIT&, u32 instr);
+void subl(JIT&, u32 instr);
+void ceills(JIT&, u32 instr);
+void ceilws(JIT&, u32 instr);
+void ceilld(JIT&, u32 instr);
+void ceilwd(JIT&, u32 instr);
+void cfc1(JIT&, u32 instr);
+void ctc1(JIT&, u32 instr);
+void roundls(JIT&, u32 instr);
+void roundld(JIT&, u32 instr);
+void roundws(JIT&, u32 instr);
+void roundwd(JIT&, u32 instr);
+void floorls(JIT&, u32 instr);
+void floorld(JIT&, u32 instr);
+void floorws(JIT&, u32 instr);
+void floorwd(JIT&, u32 instr);
+void cvtls(JIT&, u32 instr);
+void cvtws(JIT&, u32 instr);
+void cvtds(JIT&, u32 instr);
+void cvtsw(JIT&, u32 instr);
+void cvtdw(JIT&, u32 instr);
+void cvtsd(JIT&, u32 instr);
+void cvtwd(JIT&, u32 instr);
+void cvtld(JIT&, u32 instr);
+void cvtdl(JIT&, u32 instr);
+void cvtsl(JIT&, u32 instr);
+template <typename T>
+void ccond(JIT&, u32 instr, CompConds);
+void divs(JIT&, u32 instr);
+void divd(JIT&, u32 instr);
+void muls(JIT&, u32 instr);
+void muld(JIT&, u32 instr);
+void mulw(JIT&, u32 instr);
+void mull(JIT&, u32 instr);
+void movs(JIT&, u32 instr);
+void movd(JIT&, u32 instr);
+void movw(JIT&, u32 instr);
+void movl(JIT&, u32 instr);
+void negs(JIT&, u32 instr);
+void negd(JIT&, u32 instr);
+void sqrts(JIT&, u32 instr);
+void sqrtd(JIT&, u32 instr);
+void lwc1(JIT&, u32 instr);
+void swc1(JIT&, u32 instr);
+void ldc1(JIT&, u32 instr);
+void mfc1(JIT&, u32 instr);
+void dmfc1(JIT&, u32 instr);
+void mtc1(JIT&, u32 instr);
+void dmtc1(JIT&, u32 instr);
+void sdc1(JIT&, u32 instr);
+void truncws(JIT&, u32 instr);
+void truncwd(JIT&, u32 instr);
+void truncls(JIT&, u32 instr);
+void truncld(JIT&, u32 instr);
+}
--- a/src/backend/core/dynarec/decode.cpp
+++ b/src/backend/core/dynarec/decode.cpp
@@ -1,10 +1,10 @@
-#include <dynarec/instructions.hpp>
-#include <dynarec/cop/cop1decode.hpp>
-#include <dynarec/cop/cop0decode.hpp>
+#include <jit/instructions.hpp>
+#include <jit/cop/cop1decode.hpp>
+#include <jit/cop/cop0decode.hpp>
 #include <Registers.hpp>

 namespace n64 {
-void Dynarec::cop2Decode(u32 instr) {
+void JIT::cop2Decode(u32 instr) {
  code.mov(rdi, (u64)this);
  code.mov(rsi, (u64)&regs);
  code.mov(rdx, instr);
@@ -32,7 +32,7 @@ void Dynarec::cop2Decode(u32 instr) {
  }
 }

-bool Dynarec::special(u32 instr) {
+bool JIT::special(u32 instr) {
  u8 mask = (instr & 0x3F);
  bool res = false;

@@ -327,7 +327,7 @@ bool Dynarec::special(u32 instr) {
  return res;
 }

-bool Dynarec::regimm(u32 instr) {
+bool JIT::regimm(u32 instr) {
  u8 mask = ((instr >> 16) & 0x1F);
  // 000r_rccc
  switch (mask) { // TODO: named constants for clearer code
@@ -458,7 +458,7 @@ bool Dynarec::regimm(u32 instr) {
  return true;
 }

-bool Dynarec::Exec(Mem& mem, u32 instr) {
+bool JIT::Exec(Mem& mem, u32 instr) {
  u8 mask = (instr >> 26) & 0x3f;
  bool res = false;

--- a/src/backend/core/dynarec/instructions.cpp
+++ b/src/backend/core/dynarec/instructions.cpp
@@ -1,4 +1,4 @@
-#include <core/Dynarec.hpp>
+#include <core/JIT.hpp>

 #define se_imm(x) ((s16)((x) & 0xFFFF))
 #define check_address_error(mask, addr) (((!regs.cop0.is_64bit_addressing) && (s32)(addr) != (addr)) || (((addr) & (mask)) != 0))
@@ -6,7 +6,7 @@
 #define check_signed_underflow(op1, op2, res) (((((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)

 namespace n64 {
-void add(Dynarec& dyn, u32 instr) {
+void add(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u32 rs = (s32)regs.gpr[RS(instr)];
  u32 rt = (s32)regs.gpr[RT(instr)];
@@ -20,7 +20,7 @@ void add(Dynarec& dyn, u32 instr) {
  }
 }

-void addu(Dynarec& dyn, u32 instr) {
+void addu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s32 rs = (s32)regs.gpr[RS(instr)];
@@ -30,7 +30,7 @@ void addu(Dynarec& dyn, u32 instr) {
  }
 }

-void addi(Dynarec& dyn, u32 instr) {
+void addi(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u32 rs = regs.gpr[RS(instr)];
  u32 imm = s32(s16(instr));
@@ -42,7 +42,7 @@ void addi(Dynarec& dyn, u32 instr) {
  }
 }

-void addiu(Dynarec& dyn, u32 instr) {
+void addiu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s32 rs = (s32)regs.gpr[RS(instr)];
  s16 imm = (s16)(instr);
@@ -50,7 +50,7 @@ void addiu(Dynarec& dyn, u32 instr) {
  regs.gpr[RT(instr)] = result;
 }

-void dadd(Dynarec& dyn, u32 instr) {
+void dadd(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u64 rs = regs.gpr[RS(instr)];
  u64 rt = regs.gpr[RT(instr)];
@@ -64,7 +64,7 @@ void dadd(Dynarec& dyn, u32 instr) {
  }
 }

-void daddu(Dynarec& dyn, u32 instr) {
+void daddu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s64 rs = regs.gpr[RS(instr)];
@@ -73,7 +73,7 @@ void daddu(Dynarec& dyn, u32 instr) {
  }
 }

-void daddi(Dynarec& dyn, u32 instr) {
+void daddi(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u64 imm = s64(s16(instr));
  u64 rs = regs.gpr[RS(instr)];
@@ -85,14 +85,14 @@ void daddi(Dynarec& dyn, u32 instr) {
  }
 }

-void daddiu(Dynarec& dyn, u32 instr) {
+void daddiu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s16 imm = (s16)(instr);
  s64 rs = regs.gpr[RS(instr)];
  regs.gpr[RT(instr)] = rs + imm;
 }

-void div(Dynarec& dyn, u32 instr) {
+void div(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 dividend = (s32)regs.gpr[RS(instr)];
  s64 divisor = (s32)regs.gpr[RT(instr)];
@@ -112,7 +112,7 @@ void div(Dynarec& dyn, u32 instr) {
  }
 }

-void divu(Dynarec& dyn, u32 instr) {
+void divu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u32 dividend = regs.gpr[RS(instr)];
  u32 divisor = regs.gpr[RT(instr)];
@@ -127,7 +127,7 @@ void divu(Dynarec& dyn, u32 instr) {
  }
 }

-void ddiv(Dynarec& dyn, u32 instr) {
+void ddiv(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 dividend = regs.gpr[RS(instr)];
  s64 divisor = regs.gpr[RT(instr)];
@@ -149,7 +149,7 @@ void ddiv(Dynarec& dyn, u32 instr) {
  }
 }

-void ddivu(Dynarec& dyn, u32 instr) {
+void ddivu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u64 dividend = regs.gpr[RS(instr)];
  u64 divisor = regs.gpr[RT(instr)];
@@ -164,7 +164,7 @@ void ddivu(Dynarec& dyn, u32 instr) {
  }
 }

-void branch(Dynarec& dyn, bool cond, s64 address) {
+void branch(JIT& dyn, bool cond, s64 address) {
  Registers& regs = dyn.regs;
  regs.delaySlot = true;
  if (cond) {
@@ -172,7 +172,7 @@ void branch(Dynarec& dyn, bool cond, s64 address) {
  }
 }

-void branch_likely(Dynarec& dyn, bool cond, s64 address) {
+void branch_likely(JIT& dyn, bool cond, s64 address) {
  Registers& regs = dyn.regs;
  regs.delaySlot = true;
  if (cond) {
@@ -182,14 +182,14 @@ void branch_likely(Dynarec& dyn, bool cond, s64 address) {
  }
 }

-void b(Dynarec& dyn, u32 instr, bool cond) {
+void b(JIT& dyn, u32 instr, bool cond) {
  Registers& regs = dyn.regs;
  s64 offset = (s64)se_imm(instr) << 2;
  s64 address = regs.pc + offset;
  branch(dyn, cond, address);
 }

-void blink(Dynarec& dyn, u32 instr, bool cond) {
+void blink(JIT& dyn, u32 instr, bool cond) {
  Registers& regs = dyn.regs;
  regs.gpr[31] = regs.nextPC;
  s64 offset = (s64)se_imm(instr) << 2;
@@ -197,14 +197,14 @@ void blink(Dynarec& dyn, u32 instr, bool cond) {
  branch(dyn, cond, address);
 }

-void bl(Dynarec& dyn, u32 instr, bool cond) {
+void bl(JIT& dyn, u32 instr, bool cond) {
  Registers& regs = dyn.regs;
  s64 offset = (s64)se_imm(instr) << 2;
  s64 address = regs.pc + offset;
  branch_likely(dyn, cond, address);
 }

-void bllink(Dynarec& dyn, u32 instr, bool cond) {
+void bllink(JIT& dyn, u32 instr, bool cond) {
  Registers& regs = dyn.regs;
  regs.gpr[31] = regs.nextPC;
  s64 offset = (s64)se_imm(instr) << 2;
@@ -212,14 +212,14 @@ void bllink(Dynarec& dyn, u32 instr, bool cond) {
  branch_likely(dyn, cond, address);
 }

-void lui(Dynarec& dyn, u32 instr) {
+void lui(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 val = (s16)instr;
  val <<= 16;
  regs.gpr[RT(instr)] = val;
 }

-void lb(Dynarec& dyn, u32 instr) {
+void lb(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -232,7 +232,7 @@ void lb(Dynarec& dyn, u32 instr) {
  }
 }

-void lh(Dynarec& dyn, u32 instr) {
+void lh(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -251,7 +251,7 @@ void lh(Dynarec& dyn, u32 instr) {
  }
 }

-void lw(Dynarec& dyn, u32 instr) {
+void lw(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s16 offset = instr;
@@ -271,7 +271,7 @@ void lw(Dynarec& dyn, u32 instr) {
  }
 }

-void ll(Dynarec& dyn, u32 instr) {
+void ll(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -292,7 +292,7 @@ void ll(Dynarec& dyn, u32 instr) {
  regs.cop0.LLAddr = physical >> 4;
 }

-void lwl(Dynarec& dyn, u32 instr) {
+void lwl(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -309,7 +309,7 @@ void lwl(Dynarec& dyn, u32 instr) {
  }
 }

-void lwr(Dynarec& dyn, u32 instr) {
+void lwr(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -326,7 +326,7 @@ void lwr(Dynarec& dyn, u32 instr) {
  }
 }

-void ld(Dynarec& dyn, u32 instr) {
+void ld(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -340,7 +340,7 @@ void ld(Dynarec& dyn, u32 instr) {
  regs.gpr[RT(instr)] = value;
 }

-void lld(Dynarec& dyn, u32 instr) {
+void lld(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) {
@@ -364,7 +364,7 @@ void lld(Dynarec& dyn, u32 instr) {
  }
 }

-void ldl(Dynarec& dyn, u32 instr) {
+void ldl(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -381,7 +381,7 @@ void ldl(Dynarec& dyn, u32 instr) {
  }
 }

-void ldr(Dynarec& dyn, u32 instr) {
+void ldr(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -398,7 +398,7 @@ void ldr(Dynarec& dyn, u32 instr) {
  }
 }

-void lbu(Dynarec& dyn, u32 instr) {
+void lbu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -406,7 +406,7 @@ void lbu(Dynarec& dyn, u32 instr) {
  regs.gpr[RT(instr)] = value;
 }

-void lhu(Dynarec& dyn, u32 instr) {
+void lhu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -420,7 +420,7 @@ void lhu(Dynarec& dyn, u32 instr) {
  regs.gpr[RT(instr)] = value;
 }

-void lwu(Dynarec& dyn, u32 instr) {
+void lwu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -434,14 +434,14 @@ void lwu(Dynarec& dyn, u32 instr) {
  regs.gpr[RT(instr)] = value;
 }

-void sb(Dynarec& dyn, u32 instr) {
+void sb(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u32 address = regs.gpr[RS(instr)] + (s16)instr;
  mem.Write8(regs, dyn, address, regs.gpr[RT(instr)]);
 }

-void sc(Dynarec& dyn, u32 instr) {
+void sc(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -466,7 +466,7 @@ void sc(Dynarec& dyn, u32 instr) {
  }
 }

-void scd(Dynarec& dyn, u32 instr) {
+void scd(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -484,7 +484,7 @@ void scd(Dynarec& dyn, u32 instr) {
  regs.cop0.llbit = false;
 }

-void sh(Dynarec& dyn, u32 instr) {
+void sh(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -503,7 +503,7 @@ void sh(Dynarec& dyn, u32 instr) {
  }
 }

-void sw(Dynarec& dyn, u32 instr) {
+void sw(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s16 offset = instr;
@@ -523,7 +523,7 @@ void sw(Dynarec& dyn, u32 instr) {
  }
 }

-void sd(Dynarec& dyn, u32 instr) {
+void sd(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  s64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -543,7 +543,7 @@ void sd(Dynarec& dyn, u32 instr) {

 }

-void sdl(Dynarec& dyn, u32 instr) {
+void sdl(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -560,7 +560,7 @@ void sdl(Dynarec& dyn, u32 instr) {
  }
 }

-void sdr(Dynarec& dyn, u32 instr) {
+void sdr(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -577,7 +577,7 @@ void sdr(Dynarec& dyn, u32 instr) {
  }
 }

-void swl(Dynarec& dyn, u32 instr) {
+void swl(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -594,7 +594,7 @@ void swl(Dynarec& dyn, u32 instr) {
  }
 }

-void swr(Dynarec& dyn, u32 instr) {
+void swr(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  Mem& mem = dyn.mem;
  u64 address = regs.gpr[RS(instr)] + (s16)instr;
@@ -611,28 +611,28 @@ void swr(Dynarec& dyn, u32 instr) {
  }
 }

-void ori(Dynarec& dyn, u32 instr) {
+void ori(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 imm = (u16)instr;
  s64 result = imm | regs.gpr[RS(instr)];
  regs.gpr[RT(instr)] = result;
 }

-void or_(Dynarec& dyn, u32 instr) {
+void or_(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = regs.gpr[RS(instr)] | regs.gpr[RT(instr)];
  }
 }

-void nor(Dynarec& dyn, u32 instr) {
+void nor(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = ~(regs.gpr[RS(instr)] | regs.gpr[RT(instr)]);
  }
 }

-void j(Dynarec& dyn, u32 instr) {
+void j(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u64 target = (instr & 0x3ffffff) << 2;
  u64 address = ((regs.pc - 4) & ~0xfffffff) | target;
@@ -640,13 +640,13 @@ void j(Dynarec& dyn, u32 instr) {
  branch(dyn, true, address);
 }

-void jal(Dynarec& dyn, u32 instr) {
+void jal(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  regs.gpr[31] = regs.nextPC;
  j(dyn, instr);
 }

-void jalr(Dynarec& dyn, u32 instr) {
+void jalr(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  branch(dyn, true, regs.gpr[RS(instr)]);
  if(likely(RD(instr) != 0)) {
@@ -654,57 +654,57 @@ void jalr(Dynarec& dyn, u32 instr) {
  }
 }

-void slti(Dynarec& dyn, u32 instr) {
+void slti(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  regs.gpr[RT(instr)] = regs.gpr[RS(instr)] < se_imm(instr);
 }

-void sltiu(Dynarec& dyn, u32 instr) {
+void sltiu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  regs.gpr[RT(instr)] = (u64)regs.gpr[RS(instr)] < se_imm(instr);
 }

-void slt(Dynarec& dyn, u32 instr) {
+void slt(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = regs.gpr[RS(instr)] < regs.gpr[RT(instr)];
  }
 }

-void sltu(Dynarec& dyn, u32 instr) {
+void sltu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = (u64) regs.gpr[RS(instr)] < (u64) regs.gpr[RT(instr)];
  }
 }

-void xori(Dynarec& dyn, u32 instr) {
+void xori(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 imm = (u16)instr;
  regs.gpr[RT(instr)] = regs.gpr[RS(instr)] ^ imm;
 }

-void xor_(Dynarec& dyn, u32 instr) {
+void xor_(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = regs.gpr[RT(instr)] ^ regs.gpr[RS(instr)];
  }
 }

-void andi(Dynarec& dyn, u32 instr) {
+void andi(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 imm = (u16)instr;
  regs.gpr[RT(instr)] = regs.gpr[RS(instr)] & imm;
 }

-void and_(Dynarec& dyn, u32 instr) {
+void and_(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = regs.gpr[RS(instr)] & regs.gpr[RT(instr)];
  }
 }

-void sll(Dynarec& dyn, u32 instr) {
+void sll(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u8 sa = ((instr >> 6) & 0x1f);
@@ -713,7 +713,7 @@ void sll(Dynarec& dyn, u32 instr) {
  }
 }

-void sllv(Dynarec& dyn, u32 instr) {
+void sllv(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u8 sa = (regs.gpr[RS(instr)]) & 0x1F;
@@ -723,7 +723,7 @@ void sllv(Dynarec& dyn, u32 instr) {
  }
 }

-void dsll32(Dynarec& dyn, u32 instr) {
+void dsll32(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u8 sa = ((instr >> 6) & 0x1f);
@@ -732,7 +732,7 @@ void dsll32(Dynarec& dyn, u32 instr) {
  }
 }

-void dsll(Dynarec& dyn, u32 instr) {
+void dsll(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u8 sa = ((instr >> 6) & 0x1f);
@@ -741,7 +741,7 @@ void dsll(Dynarec& dyn, u32 instr) {
  }
 }

-void dsllv(Dynarec& dyn, u32 instr) {
+void dsllv(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s64 sa = regs.gpr[RS(instr)] & 63;
@@ -750,7 +750,7 @@ void dsllv(Dynarec& dyn, u32 instr) {
  }
 }

-void srl(Dynarec& dyn, u32 instr) {
+void srl(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u32 rt = regs.gpr[RT(instr)];
@@ -760,7 +760,7 @@ void srl(Dynarec& dyn, u32 instr) {
  }
 }

-void srlv(Dynarec& dyn, u32 instr) {
+void srlv(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u8 sa = (regs.gpr[RS(instr)] & 0x1F);
@@ -770,7 +770,7 @@ void srlv(Dynarec& dyn, u32 instr) {
  }
 }

-void dsrl(Dynarec& dyn, u32 instr) {
+void dsrl(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u64 rt = regs.gpr[RT(instr)];
@@ -780,7 +780,7 @@ void dsrl(Dynarec& dyn, u32 instr) {
  }
 }

-void dsrlv(Dynarec& dyn, u32 instr) {
+void dsrlv(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u8 amount = (regs.gpr[RS(instr)] & 63);
@@ -790,7 +790,7 @@ void dsrlv(Dynarec& dyn, u32 instr) {
  }
 }

-void dsrl32(Dynarec& dyn, u32 instr) {
+void dsrl32(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u64 rt = regs.gpr[RT(instr)];
@@ -800,7 +800,7 @@ void dsrl32(Dynarec& dyn, u32 instr) {
  }
 }

-void sra(Dynarec& dyn, u32 instr) {
+void sra(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s64 rt = regs.gpr[RT(instr)];
@@ -810,7 +810,7 @@ void sra(Dynarec& dyn, u32 instr) {
  }
 }

-void srav(Dynarec& dyn, u32 instr) {
+void srav(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s64 rt = regs.gpr[RT(instr)];
@@ -821,7 +821,7 @@ void srav(Dynarec& dyn, u32 instr) {
  }
 }

-void dsra(Dynarec& dyn, u32 instr) {
+void dsra(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s64 rt = regs.gpr[RT(instr)];
@@ -831,7 +831,7 @@ void dsra(Dynarec& dyn, u32 instr) {
  }
 }

-void dsrav(Dynarec& dyn, u32 instr) {
+void dsrav(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s64 rt = regs.gpr[RT(instr)];
@@ -842,7 +842,7 @@ void dsrav(Dynarec& dyn, u32 instr) {
  }
 }

-void dsra32(Dynarec& dyn, u32 instr) {
+void dsra32(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    s64 rt = regs.gpr[RT(instr)];
@@ -852,7 +852,7 @@ void dsra32(Dynarec& dyn, u32 instr) {
  }
 }

-void jr(Dynarec& dyn, u32 instr) {
+void jr(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 address = regs.gpr[RS(instr)];
  if (check_address_error(address, 0b11)) {
@@ -863,7 +863,7 @@ void jr(Dynarec& dyn, u32 instr) {
  branch(dyn, true, address);
 }

-void dsub(Dynarec& dyn, u32 instr) {
+void dsub(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 rt = regs.gpr[RT(instr)];
  s64 rs = regs.gpr[RS(instr)];
@@ -877,7 +877,7 @@ void dsub(Dynarec& dyn, u32 instr) {
  }
 }

-void dsubu(Dynarec& dyn, u32 instr) {
+void dsubu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u64 rt = regs.gpr[RT(instr)];
@@ -887,7 +887,7 @@ void dsubu(Dynarec& dyn, u32 instr) {
  }
 }

-void sub(Dynarec& dyn, u32 instr) {
+void sub(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s32 rt = regs.gpr[RT(instr)];
  s32 rs = regs.gpr[RS(instr)];
@@ -901,7 +901,7 @@ void sub(Dynarec& dyn, u32 instr) {
  }
 }

-void subu(Dynarec& dyn, u32 instr) {
+void subu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    u32 rt = regs.gpr[RT(instr)];
@@ -911,7 +911,7 @@ void subu(Dynarec& dyn, u32 instr) {
  }
 }

-void dmultu(Dynarec& dyn, u32 instr) {
+void dmultu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u64 rt = regs.gpr[RT(instr)];
  u64 rs = regs.gpr[RS(instr)];
@@ -920,7 +920,7 @@ void dmultu(Dynarec& dyn, u32 instr) {
  regs.hi = (s64)(result >> 64);
 }

-void dmult(Dynarec& dyn, u32 instr) {
+void dmult(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s64 rt = regs.gpr[RT(instr)];
  s64 rs = regs.gpr[RS(instr)];
@@ -929,7 +929,7 @@ void dmult(Dynarec& dyn, u32 instr) {
  regs.hi = result >> 64;
 }

-void multu(Dynarec& dyn, u32 instr) {
+void multu(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  u32 rt = regs.gpr[RT(instr)];
  u32 rs = regs.gpr[RS(instr)];
@@ -938,7 +938,7 @@ void multu(Dynarec& dyn, u32 instr) {
  regs.hi = (s64)((s32)(result >> 32));
 }

-void mult(Dynarec& dyn, u32 instr) {
+void mult(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s32 rt = regs.gpr[RT(instr)];
  s32 rs = regs.gpr[RS(instr)];
@@ -947,54 +947,54 @@ void mult(Dynarec& dyn, u32 instr) {
  regs.hi = (s64)((s32)(result >> 32));
 }

-void mflo(Dynarec& dyn, u32 instr) {
+void mflo(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = regs.lo;
  }
 }

-void mfhi(Dynarec& dyn, u32 instr) {
+void mfhi(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  if(likely(RD(instr) != 0)) {
    regs.gpr[RD(instr)] = regs.hi;
  }
 }

-void mtlo(Dynarec& dyn, u32 instr) {
+void mtlo(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  regs.lo = regs.gpr[RS(instr)];
 }

-void mthi(Dynarec& dyn, u32 instr) {
+void mthi(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  regs.hi = regs.gpr[RS(instr)];
 }

-void trap(Dynarec& dyn, bool cond) {
+void trap(JIT& dyn, bool cond) {
  Registers& regs = dyn.regs;
  if(cond) {
    FireException(regs, ExceptionCode::Trap, 0, true);
  }
 }

-void mtc2(Dynarec& dyn, u32 instr) {
+void mtc2(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  dyn.cop2Latch = regs.gpr[RT(instr)];
 }

-void mfc2(Dynarec& dyn, u32 instr) {
+void mfc2(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  s32 value = dyn.cop2Latch;
  regs.gpr[RT(instr)] = value;
 }

-void dmtc2(Dynarec& dyn, u32 instr) {
+void dmtc2(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  dyn.cop2Latch = regs.gpr[RT(instr)];
 }

-void dmfc2(Dynarec& dyn, u32 instr) {
+void dmfc2(JIT& dyn, u32 instr) {
  Registers& regs = dyn.regs;
  regs.gpr[RT(instr)] = dyn.cop2Latch;
 }
--- a/src/backend/core/jit/instructions.hpp
+++ b/src/backend/core/jit/instructions.hpp
@@ -0,0 +1,94 @@
+#pragma once
+#include <JIT.hpp>
+
+namespace n64 {
+void add(JIT&, u32);
+void addu(JIT&, u32);
+void addi(JIT&, u32);
+void addiu(JIT&, u32);
+void andi(JIT&, u32);
+void and_(JIT&, u32);
+void branch(JIT&, bool, s64);
+void branch_likely(JIT&, bool, s64);
+void b(JIT&, u32, bool);
+void blink(JIT&, u32, bool);
+void bl(JIT&, u32, bool);
+void bllink(JIT&, u32, bool);
+void dadd(JIT&, u32);
+void daddu(JIT&, u32);
+void daddi(JIT&, u32);
+void daddiu(JIT&, u32);
+void ddiv(JIT&, u32);
+void ddivu(JIT&, u32);
+void div(JIT&, u32);
+void divu(JIT&, u32);
+void dmult(JIT&, u32);
+void dmultu(JIT&, u32);
+void dsll(JIT&, u32);
+void dsllv(JIT&, u32);
+void dsll32(JIT&, u32);
+void dsra(JIT&, u32);
+void dsrav(JIT&, u32);
+void dsra32(JIT&, u32);
+void dsrl(JIT&, u32);
+void dsrlv(JIT&, u32);
+void dsrl32(JIT&, u32);
+void dsub(JIT&, u32);
+void dsubu(JIT&, u32);
+void j(JIT&, u32);
+void jr(JIT&, u32);
+void jal(JIT&, u32);
+void jalr(JIT&, u32);
+void lui(JIT&, u32);
+void lbu(JIT&, u32);
+void lb(JIT&, u32);
+void ld(JIT&, u32);
+void ldl(JIT&, u32);
+void ldr(JIT&, u32);
+void lh(JIT&, u32);
+void lhu(JIT&, u32);
+void ll(JIT&, u32);
+void lld(JIT&, u32);
+void lw(JIT&, u32);
+void lwl(JIT&, u32);
+void lwu(JIT&, u32);
+void lwr(JIT&, u32);
+void mfhi(JIT&, u32);
+void mflo(JIT&, u32);
+void mult(JIT&, u32);
+void multu(JIT&, u32);
+void mthi(JIT&, u32);
+void mtlo(JIT&, u32);
+void nor(JIT&, u32);
+void sb(JIT&, u32);
+void sc(JIT&, u32);
+void scd(JIT&, u32);
+void sd(JIT&, u32);
+void sdl(JIT&, u32);
+void sdr(JIT&, u32);
+void sh(JIT&, u32);
+void sw(JIT&, u32);
+void swl(JIT&, u32);
+void swr(JIT&, u32);
+void slti(JIT&, u32);
+void sltiu(JIT&, u32);
+void slt(JIT&, u32);
+void sltu(JIT&, u32);
+void sll(JIT&, u32);
+void sllv(JIT&, u32);
+void sub(JIT&, u32);
+void subu(JIT&, u32);
+void sra(JIT&, u32);
+void srav(JIT&, u32);
+void srl(JIT&, u32);
+void srlv(JIT&, u32);
+void trap(JIT&, bool);
+void or_(JIT&, u32);
+void ori(JIT&, u32);
+void xor_(JIT&, u32);
+void xori(JIT&, u32);
+void mtc2(JIT&, u32);
+void mfc2(JIT&, u32);
+void dmtc2(JIT&, u32);
+void dmfc2(JIT&, u32);
+}