These should be throwing
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@@ -145,12 +145,14 @@ FORCE_INLINE void SetCauseByArgWCVT(Registers& regs, T f) {
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case FP_INFINITE:
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case FP_SUBNORMAL:
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regs.cop1.SetCauseUnimplemented(regs);
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CheckFPUException();
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break;
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case FP_NORMAL:
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// Check overflow
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if (f >= 2147483648.0f || f < -2147483648.0f) {
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regs.cop1.SetCauseUnimplemented(regs);
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CheckFPUException();
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}
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break;
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@@ -166,12 +168,14 @@ FORCE_INLINE void SetCauseByArgLCVT(Registers& regs, T f) {
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case FP_INFINITE:
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case FP_SUBNORMAL:
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regs.cop1.SetCauseUnimplemented(regs);
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CheckFPUException();
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break;
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case FP_NORMAL:
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// Check overflow
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if (f >= 9007199254740992.000000 || f <= -9007199254740992.000000) {
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regs.cop1.SetCauseUnimplemented(regs);
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CheckFPUException();
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}
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break;
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@@ -248,12 +252,15 @@ FORCE_INLINE void SetCauseByArg(Registers& regs, T f) {
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case FP_NAN:
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if(isqnan(f)) {
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regs.cop1.SetCauseInvalid(regs);
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CheckFPUException();
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} else {
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regs.cop1.SetCauseUnimplemented(regs);
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CheckFPUException();
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}
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break;
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case FP_SUBNORMAL:
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regs.cop1.SetCauseUnimplemented(regs);
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CheckFPUException();
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break;
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case FP_INFINITE:
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case FP_ZERO:
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@@ -287,6 +294,7 @@ FORCE_INLINE void SetCauseOnResult(Registers& regs, T& d) {
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case FP_SUBNORMAL:
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if (!cop1.fcr31.fs || cop1.fcr31.enable_underflow || cop1.fcr31.enable_inexact_operation) {
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regs.cop1.SetCauseUnimplemented(regs);
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CheckFPUException();
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} else {
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// Since the if statement checks for the corresponding enable bits, it's safe to turn these cause bits on here.
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regs.cop1.SetCauseUnderflow(regs);
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