Share registers between both cores

This commit is contained in:
CocoSimone
2022-12-25 00:01:31 +01:00
parent 20115595be
commit 138c3f6a98
10 changed files with 335 additions and 352 deletions

View File

@@ -5,7 +5,7 @@ void Dynarec::Reset() {
}
void Dynarec::Step(Mem &mem) {
void Dynarec::Step(Mem &mem, Registers& regs) {
}
}