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update prdp

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This commit is contained in:
CocoSimone
2022-09-17 17:44:35 +02:00
parent d8e415d2cf
commit 13c32cd8d9
8 changed files with 24 additions and 18 deletions
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4
src/n64/core/Mem.cpp
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@@ -122,7 +122,7 @@ T Mem::Read(Registers& regs, u32 vaddr, s64 pc) {
case 0x04200000 ... 0x042FFFFF:
case 0x04900000 ... 0x07FFFFFF: case 0x08000000 ... 0x0FFFFFFF:
case 0x80000000 ... 0xFFFFFFFF: case 0x1FC00800 ... 0x7FFFFFFF: return 0;
default: util::panic("Unimplemented {}-bit read at address {:08X} (PC = {:016X})\n", sizeof(T) * 8, paddr, regs.pc);
default: util::panic("Unimplemented {}-bit read at address {:08X} (PC = {:016X})\n", sizeof(T) * 8, paddr, (u64)regs.pc);
}
return 0;
}
@@ -208,7 +208,7 @@ void Mem::Write(Registers& regs, u32 vaddr, T val, s64 pc) {
case 0x04200000 ... 0x042FFFFF: case 0x04900000 ... 0x07FFFFFF:
case 0x08000000 ... 0x0FFFFFFF:
case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
default: util::panic("Unimplemented {}-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", sizeof(T) * 8, paddr, val, regs.pc);
default: util::panic("Unimplemented {}-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", sizeof(T) * 8, paddr, val, (u64)regs.pc);
}
}

10
src/n64/core/RSP.cpp
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@@ -9,7 +9,7 @@ RSP::RSP() {
}
void RSP::Reset() {
spStatus.raw = 0;
spStatus.raw = 0x1;
spStatus.halt = true;
oldPC = 0;
pc = 0;
@@ -102,9 +102,11 @@ void RSP::Write(Mem& mem, Registers& regs, u32 addr, u32 value) {
case 0x04040010: {
auto write = SPStatusWrite{.raw = value};
CLEAR_SET(spStatus.halt, write.clearHalt, write.setHalt);
CLEAR_SET(spStatus.broke, write.clearBroke, false);
if(write.clearIntr) InterruptLower(mi, regs, Interrupt::SP);
if(write.setIntr) InterruptRaise(mi, regs, Interrupt::SP);
if(write.clearBroke) spStatus.broke = false;
if(write.clearIntr && !write.setIntr)
InterruptLower(mi, regs, Interrupt::SP);
if(write.setIntr && !write.clearIntr)
InterruptRaise(mi, regs, Interrupt::SP);
CLEAR_SET(spStatus.singleStep, write.clearSstep, write.setSstep);
CLEAR_SET(spStatus.interruptOnBreak, write.clearIntrOnBreak, write.setIntrOnBreak);
CLEAR_SET(spStatus.signal0Set, write.clearSignal0, write.setSignal0);

4
src/n64/core/RSP.hpp
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@@ -102,8 +102,8 @@ struct Registers;
#define DE(x) (((x) >> 11) & 0x1F)
#define CLEAR_SET(val, clear, set) do { \
if(clear) (val) = 0; \
if(set) (val) = 1; \
if(clear && !set) (val) = 0; \
if(set && !clear) (val) = 1; \
} while(0)
struct RSP {

2
src/n64/core/cpu/instructions.cpp
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@@ -321,7 +321,7 @@ void Cpu::sc(Mem& mem, u32 instr) {
mem.Write<u32>(regs, address, regs.gpr[RT(instr)], regs.oldPC);
}
regs.gpr[RT(instr)] = (s64)((u64)regs.cop0.llbit);
regs.gpr[RT(instr)] = (u64)regs.cop0.llbit;
regs.cop0.llbit = false;
}

4
src/n64/core/cpu/registers/Cop0.cpp
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@@ -136,10 +136,10 @@ void Cop0::SetReg64(u8 addr, u64 value) {
case COP0_REG_ENTRYLO0: entryLo0.raw = value & ENTRY_LO_MASK; break;
case COP0_REG_ENTRYLO1: entryLo1.raw = value & ENTRY_LO_MASK; break;
case COP0_REG_CONTEXT:
context.raw = (((s64)(s32)value) & 0xFFFFFFFFFF800000) | (context.raw & 0x7FFFFF);
context.raw = (value & 0xFFFFFFFFFF800000) | (context.raw & 0x7FFFFF);
break;
case COP0_REG_XCONTEXT:
context.raw = (((s64)(s32)value) & 0xFFFFFFFE00000000) | (xcontext.raw & 0x1FFFFFFFF);
xcontext.raw = (value & 0xFFFFFFFE00000000) | (xcontext.raw & 0x1FFFFFFFF);
break;
case COP0_REG_ENTRYHI: entryHi.raw = value & ENTRY_HI_MASK; break;
case COP0_REG_STATUS: status.raw = value; break;

4
src/n64/core/rsp/instructions.cpp
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@@ -18,6 +18,10 @@ inline void ReleaseSemaphore(RSP& rsp) {
inline auto GetCop0Reg(RSP& rsp, RDP& rdp, u8 index) -> u32{
switch(index) {
case 0: return rsp.spDMASPAddr.raw;
case 1: return rsp.spDMADRAMAddr.raw;
case 2: return rsp.spDMARDLen.raw;
case 3: return rsp.spDMAWRLen.raw;
case 4: return rsp.spStatus.raw;
case 5: return rsp.spStatus.dmaFull;
case 6: return 0;