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Squashed 'external/capstone/' changes from b102f1b8..5af28808

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5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705)
99f018ac Python binding: (#2742)
a07baf83 Auto-Sync update Sparc LLVM-18 (#2704)
81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733)
a25d4980 Add warning about naive search and replace to patch reg names. (#2728)
7ac87d17 Print immediate only memory operands for AArch64. (#2732)
c34034c8 Add x30 implicit read to the RET alias. (#2739)
95a4ca3e Update source list before installing valgrind. (#2730)
6909724e Make assertion hit warnings optional in release builds. (#2729)
fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723)
21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721)
df26583f clang-format: change license to BSD-3-Clause (#2724)
280b749e Remove unused files. (#2709)
87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707)
efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720)
2ae64133 Fix missing sp register read in ret instruction (#2719)
8df252a6 Fix arm pop reg access (#2718)
14612272 ARM: fix typo, cspr -> cpsr (#2716)
f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701)
829be2bf LoongArch: Compute absolute address for address operand (#2699)
42fbce6c Add jump group for generic jirl (#2698)
fc525c73 Apple AArch64 proprietary (#2692)
895f2f2e Build PDB for debugging on Windows (#2685)
5c3aef03 Version: Update to v6.0.0-alpha4 (#2682)
106f7d3b Update read/written registers for x87 comparison instructions (#2680)
ebe3ef2a Add workflow for building on Windows (#2675)
72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678)
5b5c5ed8 Fix nanomips decoding of jalrc (#2672)
ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673)
21178aea Add a script to compare the inc file content with the latest generated ones. (#2667)
81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665)
98a393e3 Stringify BH fields when printing ppc details (#2663)
2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661)
5058c634 Decode BH field in print_insn_detail_ppc (#2662)
6461ed08 Add Call group to svc, smc and hvc. (#2651)
e2f1dc8d Tms32c64x Little Endian (#2648)
5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645)
bb2f6579 Enhance shift value and types of shift instructions. (#2638)
cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633)
dc0c0909 cmake: Fix building capstone as sub-project (#2629)
cd8dd20c - Added missing files for sdist archive (#2624)
9affd99b Give the user some guidance where to add missing enumeration values. (#2639)
1bea3fab Add checks for MIPS details on cstest_py (#2640)
ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635)
1abe1868 Build Tarball before DEB/RPM package. (#2627)
0a012190 Switch to ubuntu-24.04-arm runner image (#2625)
4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620)
8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616)
d7ef910b Rebased #2570 (#2614)
c831cd5e Fix SystemZ macro in Makefile (#2603)
30601176 Apply new EVM opcode updates (#2602)
3c4d7fc8 Add tricore tc1.8 instructions (#2595)
5f290cad Create debian and rpm package on releases (#2590)
0f09210a delete travis (#2600)
5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598)

git-subtree-dir: external/capstone
git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
This commit is contained in:
irisz64
2025-06-26 22:15:44 +02:00
parent 3621a6c080
commit 16a2cf3873
876 changed files with 168071 additions and 411897 deletions
Download Patch File Download Diff File Expand all files Collapse all files

65
bindings/python/capstone/__init__.py
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@@ -42,6 +42,7 @@ __all__ = [
'CS_ARCH_HPPA',
'CS_ARCH_LOONGARCH',
'CS_ARCH_XTENSA',
'CS_ARCH_ARC',
'CS_ARCH_ALL',
'CS_MODE_LITTLE_ENDIAN',
@@ -53,6 +54,7 @@ __all__ = [
'CS_MODE_THUMB',
'CS_MODE_MCLASS',
'CS_MODE_V8',
'CS_MODE_APPLE_PROPRIETARY',
'CS_MODE_V9',
'CS_MODE_QPX',
'CS_MODE_SPE',
@@ -126,6 +128,7 @@ __all__ = [
'CS_MODE_TRICORE_160',
'CS_MODE_TRICORE_161',
'CS_MODE_TRICORE_162',
"CS_MODE_TRICORE_180",
'CS_MODE_HPPA_11',
'CS_MODE_HPPA_20',
'CS_MODE_HPPA_20W',
@@ -269,9 +272,13 @@ CS_ARCH_ALPHA = 18
CS_ARCH_HPPA = 19
CS_ARCH_LOONGARCH = 20
CS_ARCH_XTENSA = 21
CS_ARCH_MAX = 21
CS_ARCH_ARC = 22
CS_ARCH_MAX = 22
CS_ARCH_ALL = 0xFFFF
CS_MODE_AARCH64_ISA_BITS = 0x00fffff8
CS_MODE_VENDOR_AARCH64_BIT0 = 30
# disasm mode
CS_MODE_LITTLE_ENDIAN = 0 # little-endian mode (default mode)
CS_MODE_ARM = 0 # ARM mode
@@ -281,6 +288,7 @@ CS_MODE_64 = (1 << 3) # 64-bit mode (for X86, PPC)
CS_MODE_THUMB = (1 << 4) # ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = (1 << 5) # ARM's Cortex-M series
CS_MODE_V8 = (1 << 6) # ARMv8 A32 encodings for ARM
CS_MODE_APPLE_PROPRIETARY = (1 << CS_MODE_VENDOR_AARCH64_BIT0) # Apple proprietary AArch64 instructions like AMX, MUL53, and others.
CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
CS_MODE_MIPS3 = (1 << 5) # Mips III ISA
CS_MODE_MIPS32R6 = (1 << 6) # Mips32r6 ISA
@@ -367,6 +375,7 @@ CS_MODE_TRICORE_131 = 1 << 4 # Tricore 1.3.1
CS_MODE_TRICORE_160 = 1 << 5 # Tricore 1.6
CS_MODE_TRICORE_161 = 1 << 6 # Tricore 1.6.1
CS_MODE_TRICORE_162 = 1 << 7 # Tricore 1.6.2
CS_MODE_TRICORE_180 = 1 << 8 # Tricore 1.8.0
CS_MODE_HPPA_11 = 1 << 1 # HPPA 1.1
CS_MODE_HPPA_20 = 1 << 2 # HPPA 2.0
CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide
@@ -561,7 +570,7 @@ def copy_ctypes_list(src):
# Weird import placement because these modules are needed by the below code but need the above functions
from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, \
riscv, sh, tricore, alpha, hppa, loongarch, xtensa
riscv, sh, tricore, alpha, hppa, loongarch, arc, xtensa
class _cs_arch(ctypes.Union):
@@ -588,6 +597,7 @@ class _cs_arch(ctypes.Union):
('hppa', hppa.CsHPPA),
('loongarch', loongarch.CsLoongArch),
('xtensa', xtensa.CsXtensa),
('arc', arc.CsARC),
)
@@ -615,6 +625,7 @@ class _cs_insn(ctypes.Structure):
('op_str', ctypes.c_char * 160),
('is_alias', ctypes.c_bool),
('usesAliasDetails', ctypes.c_bool),
('illegal', ctypes.c_bool),
('detail', ctypes.POINTER(_cs_detail)),
)
@@ -786,7 +797,7 @@ class CsInsn(object):
def __init__(self, cs, all_info):
self._raw = copy_ctypes(all_info)
self._cs = cs
if self._cs._detail and self._raw.id != 0:
if self._cs._detail and not self.is_invalid_insn():
# save detail
self._raw.detail = ctypes.pointer(all_info.detail._type_())
ctypes.memmove(ctypes.byref(self._raw.detail[0]), ctypes.byref(all_info.detail[0]),
@@ -795,6 +806,14 @@ class CsInsn(object):
def __repr__(self):
return '<CsInsn 0x%x [%s]: %s %s>' % (self.address, self.bytes.hex(), self.mnemonic, self.op_str)
# return if the instruction is invalid
def is_invalid_insn(self):
arch = self._cs.arch
if arch == CS_ARCH_EVM:
return self.id == evm.EVM_INS_INVALID
else:
return self.id == 0
# return instruction's ID.
@property
def id(self):
@@ -815,6 +834,13 @@ class CsInsn(object):
def is_alias(self):
return self._raw.is_alias
# return instruction's illegal flag
# Set if instruction can be decoded but is invalid
# due to context or illegal operands.
@property
def illegal(self):
return self._raw.illegal
# return instruction's alias_id
@property
def alias_id(self):
@@ -851,7 +877,7 @@ class CsInsn(object):
# return list of all implicit registers being read.
@property
def regs_read(self):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
if self._cs._diet:
@@ -866,7 +892,7 @@ class CsInsn(object):
# return list of all implicit registers being modified
@property
def regs_write(self):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
if self._cs._diet:
@@ -881,7 +907,7 @@ class CsInsn(object):
# return list of semantic groups this instruction belongs to.
@property
def groups(self):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
if self._cs._diet:
@@ -896,7 +922,7 @@ class CsInsn(object):
# return whether instruction has writeback operands.
@property
def writeback(self):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
if self._cs._diet:
@@ -909,7 +935,7 @@ class CsInsn(object):
raise CsError(CS_ERR_DETAIL)
def __gen_detail(self):
if self._raw.id == 0:
if self.is_invalid_insn():
# do nothing in skipdata mode
return
@@ -935,7 +961,7 @@ class CsInsn(object):
(self.bc, self.update_cr0, self.format, self.operands) = \
ppc.get_arch_info(self._raw.detail.contents.arch.ppc)
elif arch == CS_ARCH_SPARC:
(self.cc, self.hint, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc)
(self.cc, self.cc_field, self.hint, self.format, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc)
elif arch == CS_ARCH_SYSTEMZ:
(self.cc, self.format, self.operands) = systemz.get_arch_info(self._raw.detail.contents.arch.systemz)
elif arch == CS_ARCH_XCORE:
@@ -964,6 +990,8 @@ class CsInsn(object):
(self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa)
elif arch == CS_ARCH_LOONGARCH:
(self.format, self.operands) = loongarch.get_arch_info(self._raw.detail.contents.arch.loongarch)
elif arch == CS_ARCH_ARC:
(self.operands) = arc.get_arch_info(self._raw.detail.contents.arch.arc)
elif arch == CS_ARCH_XTENSA:
(self.operands) = xtensa.get_arch_info(self._raw.detail.contents.arch.xtensa)
@@ -978,7 +1006,7 @@ class CsInsn(object):
if 'operands' not in _dict:
self.__gen_detail()
if name not in _dict:
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
raise AttributeError(f"'CsInsn' has no attribute '{name}'")
return _dict[name]
@@ -1001,7 +1029,7 @@ class CsInsn(object):
# Diet engine cannot provide instruction name
raise CsError(CS_ERR_DIET)
if self._raw.id == 0:
if self.is_invalid_insn():
return default
return _ascii_name_or_default(_cs.cs_insn_name(self._cs.csh, self.id), default)
@@ -1016,7 +1044,7 @@ class CsInsn(object):
# verify if this insn belong to group with id as @group_id
def group(self, group_id):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
if self._cs._diet:
@@ -1027,7 +1055,7 @@ class CsInsn(object):
# verify if this instruction implicitly read register @reg_id
def reg_read(self, reg_id):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
if self._cs._diet:
@@ -1038,7 +1066,7 @@ class CsInsn(object):
# verify if this instruction implicitly modified register @reg_id
def reg_write(self, reg_id):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
if self._cs._diet:
@@ -1049,7 +1077,7 @@ class CsInsn(object):
# return number of operands having same operand type @op_type
def op_count(self, op_type):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
c = 0
@@ -1060,7 +1088,7 @@ class CsInsn(object):
# get the operand at position @position of all operands having the same type @op_type
def op_find(self, op_type, position):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
c = 0
@@ -1073,7 +1101,7 @@ class CsInsn(object):
# Return (list-of-registers-read, list-of-registers-modified) by this instructions.
# This includes all the implicit & explicit registers.
def regs_access(self):
if self._raw.id == 0:
if self.is_invalid_insn():
raise CsError(CS_ERR_SKIPDATA)
regs_read = (ctypes.c_uint16 * 64)()
@@ -1440,7 +1468,8 @@ def debug():
"m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA,
'arc': CS_ARCH_ARC
}
all_archs = ""