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Start implementing some instructions

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This commit is contained in:
SimoneN64
2023-08-13 09:42:00 +02:00
parent f708f0452d
commit 180f07c23f
3 changed files with 70 additions and 83 deletions
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32
src/backend/core/JIT.cpp
View File

@@ -35,14 +35,16 @@ Fn JIT::Recompile() {
cycles = 0; cycles = 0;
prologue(); prologue();
while(stable) { while(stable) {
mov(rdi, u64(this) + offsetof(JIT, regs));
cycles++;
CheckCompareInterrupt(); CheckCompareInterrupt();
regs.prevDelaySlot = regs.delaySlot; mov(rax, byte[rdi + offsetof(Registers, delaySlot)]);
regs.delaySlot = false; mov(byte[rdi + offsetof(Registers, prevDelaySlot)], rax);
\ mov(byte[rdi + offsetof(Registers, delaySlot)], 0);
u32 paddr = 0; u32 paddr = 0;
if (!MapVAddr(regs, LOAD, regs.pc, paddr)) { if (!MapVAddr(regs, LOAD, regs.pc, paddr)) {
mov(rdi, u64(this) + offsetof(JIT, regs));
mov(rsi, regs.pc); mov(rsi, regs.pc);
push(rax); push(rax);
call(HandleTLBException); call(HandleTLBException);
@@ -51,28 +53,33 @@ Fn JIT::Recompile() {
CodeGenerator::xor_(rcx, rcx); CodeGenerator::xor_(rcx, rcx);
push(rax); push(rax);
call(FireException); call(FireException);
return getCode<Fn>(); goto _epilogue;
} }
u32 instr = mem.Read32(regs, paddr); u32 instr = mem.Read32(regs, paddr);
stable = isStable(instr); stable = isStable(instr);
Emit(instr);
if (ShouldServiceInterrupt()) { if (ShouldServiceInterrupt()) {
mov(rdi, u64(this) + offsetof(JIT, regs));
mov(rsi, u64(ExceptionCode::Interrupt)); mov(rsi, u64(ExceptionCode::Interrupt));
CodeGenerator::xor_(rdx, rdx); CodeGenerator::xor_(rdx, rdx);
CodeGenerator::xor_(rcx, rcx); CodeGenerator::xor_(rcx, rcx);
push(rax); push(rax);
call(FireException); call(FireException);
return getCode<Fn>(); goto _epilogue;
} }
regs.oldPC = regs.pc; mov(rax, qword[rdi + offsetof(Registers, pc)]);
regs.pc = regs.nextPC; mov(qword[rdi + offsetof(Registers, oldPC)], rax);
regs.nextPC += 4; mov(rax, qword[rdi + offsetof(Registers, nextPC)]);
mov(qword[rdi + offsetof(Registers, pc)], rax);
CodeGenerator::add(qword[rdi + offsetof(Registers, nextPC)], 4);
} }
_epilogue:
epilogue(); epilogue();
mov(rax, cycles);
ready();
return getCode<Fn>();
} }
int JIT::Step() { int JIT::Step() {
@@ -85,7 +92,6 @@ int JIT::Step() {
blocks[regs.pc >> 20][regs.pc & 0xfff] = Recompile(); blocks[regs.pc >> 20][regs.pc & 0xfff] = Recompile();
} }
blocks[regs.pc >> 20][regs.pc & 0xfff](); return blocks[regs.pc >> 20][regs.pc & 0xfff]();
return cycles;
} }
} }

26
src/backend/core/JIT.hpp
View File

@@ -3,9 +3,10 @@
#include <vector> #include <vector>
#include <BaseCPU.hpp> #include <BaseCPU.hpp>
#include <xbyak.h> #include <xbyak.h>
#include "CpuDefinitions.hpp"
namespace n64 { namespace n64 {
using Fn = void(*)(); using Fn = int(*)();
struct JIT : BaseCPU, Xbyak::CodeGenerator { struct JIT : BaseCPU, Xbyak::CodeGenerator {
JIT(); JIT();
@@ -21,8 +22,27 @@ private:
Fn Recompile(); Fn Recompile();
bool isStable(u32 instr) { bool isStable(u32 instr) {
switch(instr) { u8 mask = (instr >> 26) & 0x3f;
default: return false; switch(mask) {
case SPECIAL:
mask = instr & 0x3f;
switch(mask) {
case JR ... JALR:
case SYSCALL: case BREAK:
case TGE ... TNE:
return false;
default: return true;
}
case REGIMM:
case J ... BGTZ:
case BEQL ... BGTZL:
return false;
case COP1:
mask = (instr >> 16) & 0x1f;
if(mask >= 0 && mask <= 3) {
return false;
}
default: return true;
} }
} }

95
src/backend/core/JIT/instructions.cpp
View File

@@ -6,105 +6,66 @@
namespace n64 { namespace n64 {
void JIT::add(u32 instr) { void JIT::add(u32 instr) {
u32 rs = (s32)regs.gpr[RS(instr)]; if(likely(RD(instr) != 0)) {
u32 rt = (s32)regs.gpr[RT(instr)]; movsx(eax, dword[rdi + offsetof(Registers, gpr[RS(instr)])]); // rs
u32 result = rs + rt; movsx(ecx, dword[rdi + offsetof(Registers, gpr[RT(instr)])]); // rt
if(check_signed_overflow(rs, rt, result)) { CodeGenerator::add(eax, ecx);
FireException(regs, ExceptionCode::Overflow, 0, true); mov(dword[rdi + offsetof(Registers, gpr[RD(instr)])], eax); // rd
} else {
if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = s32(result);
}
} }
} }
void JIT::addu(u32 instr) { void JIT::addu(u32 instr) {
if(likely(RD(instr) != 0)) { add(instr);
s32 rs = (s32)regs.gpr[RS(instr)];
s32 rt = (s32)regs.gpr[RT(instr)];
s32 result = rs + rt;
regs.gpr[RD(instr)] = result;
}
} }
void JIT::addi(u32 instr) { void JIT::addi(u32 instr) {
u32 rs = regs.gpr[RS(instr)]; if(likely(RT(instr) != 0)) {
u32 imm = s32(s16(instr)); movsx(eax, dword[rdi + offsetof(Registers, gpr[RS(instr)])]);
u32 result = rs + imm; mov(ecx, s32(s16(instr)));
if(check_signed_overflow(rs, imm, result)) { CodeGenerator::add(eax, ecx);
FireException(regs, ExceptionCode::Overflow, 0, true); mov(dword[rdi + offsetof(Registers, gpr[RT(instr)])], eax);
} else {
regs.gpr[RT(instr)] = s32(result);
} }
} }
void JIT::addiu(u32 instr) { void JIT::addiu(u32 instr) {
s32 rs = (s32)regs.gpr[RS(instr)]; addi(instr);
s16 imm = (s16)(instr);
s32 result = rs + imm;
regs.gpr[RT(instr)] = result;
} }
void JIT::dadd(u32 instr) { void JIT::dadd(u32 instr) {
u64 rs = regs.gpr[RS(instr)]; if(likely(RD(instr) != 0)) {
u64 rt = regs.gpr[RT(instr)]; mov(rax, qword[rdi + offsetof(Registers, gpr[RS(instr)])]); // rs
u64 result = rt + rs; mov(rcx, qword[rdi + offsetof(Registers, gpr[RT(instr)])]); // rt
if(check_signed_overflow(rs, rt, result)) { CodeGenerator::add(rax, rcx);
FireException(regs, ExceptionCode::Overflow, 0, true); mov(qword[rdi + offsetof(Registers, gpr[RD(instr)])], rax); // rd
} else {
if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = result;
}
} }
} }
void JIT::daddu(u32 instr) { void JIT::daddu(u32 instr) {
if(likely(RD(instr) != 0)) { dadd(instr);
s64 rs = regs.gpr[RS(instr)];
s64 rt = regs.gpr[RT(instr)];
regs.gpr[RD(instr)] = rs + rt;
}
} }
void JIT::daddi(u32 instr) { void JIT::daddi(u32 instr) {
u64 imm = s64(s16(instr)); if(likely(RT(instr) != 0)) {
u64 rs = regs.gpr[RS(instr)]; mov(rax, qword[rdi + offsetof(Registers, gpr[RS(instr)])]);
u64 result = imm + rs; mov(rcx, s64(s16(instr)));
if(check_signed_overflow(rs, imm, result)) { CodeGenerator::add(rax, rcx);
FireException(regs, ExceptionCode::Overflow, 0, true); mov(qword[rdi + offsetof(Registers, gpr[RT(instr)])], rax);
} else {
regs.gpr[RT(instr)] = result;
} }
} }
void JIT::daddiu(u32 instr) { void JIT::daddiu(u32 instr) {
s16 imm = (s16)(instr); daddi(instr);
s64 rs = regs.gpr[RS(instr)];
regs.gpr[RT(instr)] = rs + imm;
} }
void JIT::div(u32 instr) { void JIT::div(u32 instr) {
s64 dividend = (s32)regs.gpr[RS(instr)];
s64 divisor = (s32)regs.gpr[RT(instr)];
if(divisor == 0) {
regs.hi = dividend;
if(dividend >= 0) {
regs.lo = s64(-1);
} else {
regs.lo = s64(1);
}
} else {
s32 quotient = dividend / divisor;
s32 remainder = dividend % divisor;
regs.lo = quotient;
regs.hi = remainder;
}
} }
void JIT::divu(u32 instr) { void JIT::divu(u32 instr) {
u32 dividend = regs.gpr[RS(instr)]; mov(rax, dword[rdi + offsetof(Registers, gpr[RS(instr)])]);
u32 divisor = regs.gpr[RT(instr)]; mov(rcx, dword[rdi + offsetof(Registers, gpr[RS(instr)])]);
cmp(rcx, 0);
je("");
if(divisor == 0) { if(divisor == 0) {
regs.lo = -1; regs.lo = -1;
regs.hi = (s32)dividend; regs.hi = (s32)dividend;