Implement overflow and STORE and LOAD exceptions (add, addi, dadd, daddi, sub, dsub, lwl, ldl, lwr, ldr, swl, swr, sdl, sdr)
This commit is contained in:
CocoSimone
@@ -3,14 +3,20 @@
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#define se_imm(x) ((s16)((x) & 0xFFFF))
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#define check_address_error(mask, addr) (((!regs.cop0.is_64bit_addressing) && (s32)(addr) != (addr)) || (((addr) & (mask)) != 0))
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#define check_signed_overflow(op1, op2, res) (((~((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
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#define check_signed_underflow(op1, op2, res) (((((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
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namespace n64 {
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void Cpu::add(u32 instr) {
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s32 rs = (s32)regs.gpr[RS(instr)];
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s32 rt = (s32)regs.gpr[RT(instr)];
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s32 result = rs + rt;
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regs.gpr[RD(instr)] = result;
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u32 rs = (s32)regs.gpr[RS(instr)];
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u32 rt = (s32)regs.gpr[RT(instr)];
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u32 result = rs + rt;
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if(check_signed_overflow(rs, rt, result)) {
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FireException(regs, Overflow, 0, regs.oldPC);
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} else {
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regs.gpr[RD(instr)] = s32(result);
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}
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}
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void Cpu::addu(u32 instr) {
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@@ -21,10 +27,14 @@ void Cpu::addu(u32 instr) {
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}
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void Cpu::addi(u32 instr) {
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s32 rs = (s32)regs.gpr[RS(instr)];
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s16 imm = (s16)(instr);
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s32 result = rs + imm;
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regs.gpr[RT(instr)] = result;
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u32 rs = (s32)regs.gpr[RS(instr)];
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u32 imm = s32(s16(instr));
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u32 result = rs + imm;
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if(check_signed_overflow(rs, imm, result)) {
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FireException(regs, Overflow, 0, regs.oldPC);
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} else {
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regs.gpr[RD(instr)] = s32(result);
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}
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}
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void Cpu::addiu(u32 instr) {
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@@ -35,9 +45,14 @@ void Cpu::addiu(u32 instr) {
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}
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void Cpu::dadd(u32 instr) {
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s64 rs = regs.gpr[RS(instr)];
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s64 rt = regs.gpr[RT(instr)];
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regs.gpr[RD(instr)] = rs + rt;
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u64 rs = regs.gpr[RS(instr)];
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u64 rt = regs.gpr[RT(instr)];
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u64 result = rt + rs;
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if(check_signed_overflow(rs, rt, result)) {
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FireException(regs, Overflow, 0, regs.oldPC);
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} else {
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regs.gpr[RD(instr)] = result;
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}
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}
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void Cpu::daddu(u32 instr) {
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@@ -47,9 +62,14 @@ void Cpu::daddu(u32 instr) {
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}
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void Cpu::daddi(u32 instr) {
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s16 imm = (s16)(instr);
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s64 rs = regs.gpr[RS(instr)];
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regs.gpr[RT(instr)] = rs + imm;
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u64 imm = s64(s16(instr));
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u64 rs = regs.gpr[RS(instr)];
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u64 result = imm + rs;
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if(check_signed_overflow(rs, imm, result)) {
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FireException(regs, Overflow, 0, regs.oldPC);
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} else {
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regs.gpr[RD(instr)] = result;
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}
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}
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void Cpu::daddiu(u32 instr) {
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@@ -214,23 +234,33 @@ void Cpu::ll(Mem& mem, u32 instr) {
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}
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void Cpu::lwl(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr = 0;
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if(!MapVAddr(regs, LOAD, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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} else {
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u32 shift = 8 * ((address ^ 0) & 3);
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u32 mask = 0xFFFFFFFF << shift;
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u32 data = mem.Read32(regs, address & ~3, regs.oldPC);
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s64 rt = regs.gpr[RT(instr)];
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s32 result = (s32)((rt & ~mask) | (data << shift));
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u32 data = mem.Read32<false>(regs, paddr & ~3, regs.oldPC);
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s32 result = (s32) ((regs.gpr[RT(instr)] & ~mask) | (data << shift));
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regs.gpr[RT(instr)] = result;
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}
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}
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void Cpu::lwr(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr = 0;
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if(!MapVAddr(regs, LOAD, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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} else {
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u32 shift = 8 * ((address ^ 3) & 3);
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u32 mask = 0xFFFFFFFF >> shift;
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u32 data = mem.Read32(regs, address & ~3, regs.oldPC);
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s64 rt = regs.gpr[RT(instr)];
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s32 result = (s32)((rt & ~mask) | (data >> shift));
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u32 data = mem.Read32<false>(regs, paddr & ~3, regs.oldPC);
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s32 result = (s32) ((regs.gpr[RT(instr)] & ~mask) | (data >> shift));
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regs.gpr[RT(instr)] = result;
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}
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}
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void Cpu::ld(Mem& mem, u32 instr) {
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@@ -246,36 +276,46 @@ void Cpu::ld(Mem& mem, u32 instr) {
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void Cpu::lld(Mem& mem, u32 instr) {
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s64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 physical;
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if (!MapVAddr(regs, LOAD, address, physical)) {
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u32 paddr;
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if (!MapVAddr(regs, LOAD, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
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} else {
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regs.gpr[RT(instr)] = mem.Read64<false>(regs, physical, regs.oldPC);
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regs.gpr[RT(instr)] = mem.Read64<false>(regs, paddr, regs.oldPC);
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}
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regs.cop0.llbit = true;
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regs.cop0.LLAddr = physical >> 4;
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regs.cop0.LLAddr = paddr >> 4;
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}
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void Cpu::ldl(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr = 0;
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if (!MapVAddr(regs, LOAD, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
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} else {
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s32 shift = 8 * ((address ^ 0) & 7);
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u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
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u64 data = mem.Read64(regs, address & ~7, regs.oldPC);
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s64 rt = regs.gpr[RT(instr)];
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s64 result = (s64)((rt & ~mask) | (data << shift));
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u64 data = mem.Read64<false>(regs, paddr & ~7, regs.oldPC);
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s64 result = (s64) ((regs.gpr[RT(instr)] & ~mask) | (data << shift));
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regs.gpr[RT(instr)] = result;
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}
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}
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void Cpu::ldr(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr;
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if (!MapVAddr(regs, LOAD, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
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} else {
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s32 shift = 8 * ((address ^ 7) & 7);
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u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
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u64 data = mem.Read64(regs, address & ~7, regs.oldPC);
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s64 rt = regs.gpr[RT(instr)];
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s64 result = (s64)((rt & ~mask) | (data >> shift));
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u64 data = mem.Read64<false>(regs, paddr & ~7, regs.oldPC);
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s64 result = (s64) ((regs.gpr[RT(instr)] & ~mask) | (data >> shift));
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regs.gpr[RT(instr)] = result;
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}
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}
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void Cpu::lbu(Mem& mem, u32 instr) {
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@@ -372,39 +412,63 @@ void Cpu::sd(Mem& mem, u32 instr) {
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}
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void Cpu::sdl(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr;
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if (!MapVAddr(regs, STORE, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
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} else {
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s32 shift = 8 * ((address ^ 0) & 7);
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u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
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u64 data = mem.Read64(regs, address & ~7, regs.oldPC);
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u64 data = mem.Read64<false>(regs, paddr & ~7, regs.oldPC);
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s64 rt = regs.gpr[RT(instr)];
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mem.Write64(regs, address & ~7, (data & ~mask) | (rt >> shift), regs.oldPC);
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mem.Write64<false>(regs, paddr & ~7, (data & ~mask) | (rt >> shift), regs.oldPC);
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}
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}
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void Cpu::sdr(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr;
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if (!MapVAddr(regs, STORE, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
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} else {
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s32 shift = 8 * ((address ^ 7) & 7);
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u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
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u64 data = mem.Read64(regs, address & ~7, regs.oldPC);
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u64 data = mem.Read64<false>(regs, paddr & ~7, regs.oldPC);
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s64 rt = regs.gpr[RT(instr)];
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mem.Write64(regs, address & ~7, (data & ~mask) | (rt << shift), regs.oldPC);
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mem.Write64<false>(regs, paddr & ~7, (data & ~mask) | (rt << shift), regs.oldPC);
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}
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}
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void Cpu::swl(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr;
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if (!MapVAddr(regs, STORE, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
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} else {
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u32 shift = 8 * ((address ^ 0) & 3);
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u32 mask = 0xFFFFFFFF >> shift;
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u32 data = mem.Read32(regs, address & ~3, regs.oldPC);
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u32 data = mem.Read32<false>(regs, paddr & ~3, regs.oldPC);
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u32 rt = regs.gpr[RT(instr)];
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mem.Write32(regs, address & ~3, (data & ~mask) | (rt >> shift), regs.oldPC);
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mem.Write32<false>(regs, paddr & ~3, (data & ~mask) | (rt >> shift), regs.oldPC);
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}
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}
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void Cpu::swr(Mem& mem, u32 instr) {
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u32 address = regs.gpr[RS(instr)] + (s16)instr;
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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u32 paddr;
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if (!MapVAddr(regs, STORE, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
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} else {
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u32 shift = 8 * ((address ^ 3) & 3);
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u32 mask = 0xFFFFFFFF << shift;
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u32 data = mem.Read32(regs, address & ~3, regs.oldPC);
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u32 data = mem.Read32<false>(regs, paddr & ~3, regs.oldPC);
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u32 rt = regs.gpr[RT(instr)];
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mem.Write32(regs, address & ~3, (data & ~mask) | (rt << shift), regs.oldPC);
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mem.Write32<false>(regs, paddr & ~3, (data & ~mask) | (rt << shift), regs.oldPC);
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}
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}
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void Cpu::ori(u32 instr) {
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@@ -593,7 +657,11 @@ void Cpu::dsub(u32 instr) {
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s64 rt = regs.gpr[RT(instr)];
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s64 rs = regs.gpr[RS(instr)];
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s64 result = rs - rt;
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if(check_signed_underflow(rs, rt, result)) {
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FireException(regs, Overflow, 0, regs.oldPC);
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} else {
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regs.gpr[RD(instr)] = result;
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}
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}
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void Cpu::dsubu(u32 instr) {
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@@ -607,7 +675,11 @@ void Cpu::sub(u32 instr) {
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s32 rt = regs.gpr[RT(instr)];
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s32 rs = regs.gpr[RS(instr)];
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s32 result = rs - rt;
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regs.gpr[RD(instr)] = (s64)result;
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if(check_signed_underflow(rs, rt, result)) {
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FireException(regs, Overflow, 0, regs.oldPC);
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} else {
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regs.gpr[RD(instr)] = result;
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}
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}
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void Cpu::subu(u32 instr) {
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