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Merge commit '3621a6c08002c6b3e5b6f91bb0e20d8372613160' into dev

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This commit is contained in:
Simone
2025-01-07 15:08:55 +00:00
parent 07758051c6 3621a6c080
commit 20b08aeefb
1521 changed files with 323443 additions and 365407 deletions
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26
external/capstone/arch/Alpha/AlphaGenAsmWriter.inc vendored
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@@ -12,7 +12,7 @@
/* https://github.com/capstone-engine/llvm-capstone */
#include <capstone/platform.h>
#include <assert.h>
#include "../../cs_priv.h"
/// getMnemonic - This method is automatically generated by tablegen
/// from the instruction set description.
@@ -1218,11 +1218,11 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
SStream_concat0(O, MnemonicInfo.first);
uint32_t Bits = MnemonicInfo.second;
assert(Bits != 0 && "Cannot print this instruction.");
CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
// Fragment 0 encoded into 3 bits for 5 unique commands.
switch ((uint32_t)((Bits >> 11) & 7)) {
default: assert(0 && "Invalid command number.");
switch ((Bits >> 11) & 7) {
default: CS_ASSERT_RET(0 && "Invalid command number.");
case 0:
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
return;
@@ -1252,8 +1252,8 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
// Fragment 1 encoded into 4 bits for 13 unique commands.
switch ((uint32_t)((Bits >> 14) & 15)) {
default: assert(0 && "Invalid command number.");
switch ((Bits >> 14) & 15) {
default: CS_ASSERT_RET(0 && "Invalid command number.");
case 0:
// ADJUSTSTACKDOWN, ADJUSTSTACKUP, BR, RC, RPCC, RS
return;
@@ -1343,8 +1343,8 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
// Fragment 2 encoded into 2 bits for 4 unique commands.
switch ((uint32_t)((Bits >> 18) & 3)) {
default: assert(0 && "Invalid command number.");
switch ((Bits >> 18) & 3) {
default: CS_ASSERT_RET(0 && "Invalid command number.");
case 0:
// ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BICi, BICr, BISi, ...
printOperand(MI, 2, O);
@@ -1369,8 +1369,8 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
// Fragment 3 encoded into 3 bits for 6 unique commands.
switch ((uint32_t)((Bits >> 20) & 7)) {
default: assert(0 && "Invalid command number.");
switch ((Bits >> 20) & 7) {
default: CS_ASSERT_RET(0 && "Invalid command number.");
case 0:
// ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BICi, BICr, BISi, ...
SStream_concat1(O, ',');
@@ -1414,7 +1414,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
/// for the specified register.
static const char *getRegisterName(unsigned RegNo) {
#ifndef CAPSTONE_DIET
assert(RegNo && RegNo < 65 && "Invalid register number!");
CS_ASSERT_RET_VAL(RegNo && RegNo < 65 && "Invalid register number!", NULL);
static const char AsmStrs[] = {
/* 0 */ "$0\0"
@@ -1490,8 +1490,8 @@ static const char *getRegisterName(unsigned RegNo) {
130, 155, 180, 205, 230, 255, 21, 55,
};
assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
"Invalid alt name index for register!");
CS_ASSERT_RET_VAL(*(AsmStrs+RegAsmOffset[RegNo-1]) &&
"Invalid alt name index for register!", NULL);
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;

1
external/capstone/arch/Alpha/AlphaGenDisassemblerTables.inc vendored
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@@ -12,6 +12,7 @@
/* https://github.com/capstone-engine/llvm-capstone */
#include "../../MCInst.h"
#include "../../cs_priv.h"
#include "../../LEB128.h"
// Helper function for extracting fields from encoded instructions.

12
external/capstone/arch/Alpha/AlphaMapping.c vendored
View File

@@ -47,7 +47,7 @@ void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum)
else if (op_type == CS_OP_REG)
Alpha_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
else
assert(0 && "Op type not handled.");
CS_ASSERT_RET(0 && "Op type not handled.");
}
void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
@@ -55,9 +55,9 @@ void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
{
if (!detail_is_set(MI))
return;
assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
assert(map_get_op_type(MI, OpNum) == CS_OP_IMM);
assert(ImmType == ALPHA_OP_IMM);
CS_ASSERT_RET(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
CS_ASSERT_RET(map_get_op_type(MI, OpNum) == CS_OP_IMM);
CS_ASSERT_RET(ImmType == ALPHA_OP_IMM);
Alpha_get_detail_op(MI, 0)->type = ImmType;
Alpha_get_detail_op(MI, 0)->imm = Imm;
@@ -69,8 +69,8 @@ void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg)
{
if (!detail_is_set(MI))
return;
assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
assert(map_get_op_type(MI, OpNum) == CS_OP_REG);
CS_ASSERT_RET(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
CS_ASSERT_RET(map_get_op_type(MI, OpNum) == CS_OP_REG);
Alpha_get_detail_op(MI, 0)->type = ALPHA_OP_REG;
Alpha_get_detail_op(MI, 0)->reg = Reg;