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Merge commit '3621a6c08002c6b3e5b6f91bb0e20d8372613160' into dev

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Simone
2025-01-07 15:08:55 +00:00
parent 07758051c6 3621a6c080
commit 20b08aeefb
1521 changed files with 323443 additions and 365407 deletions
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74
external/capstone/cstool/cstool.c vendored
View File

@@ -41,12 +41,32 @@ static struct {
{ "+percentage", "Adds % in front of the registers", {
CS_ARCH_PPC, CS_ARCH_MAX }, CS_OPT_SYNTAX_PERCENT, 0 },
{ "+nodollar", "Removes $ in front of the registers", {
CS_ARCH_MIPS, CS_ARCH_MAX }, CS_OPT_SYNTAX_NO_DOLLAR, 0 },
CS_ARCH_LOONGARCH, CS_ARCH_MIPS, CS_ARCH_MAX }, CS_OPT_SYNTAX_NO_DOLLAR, 0 },
// cs_mode only
{ "+nofloat", "Disables floating point support", {
CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_NOFLOAT },
{ "+ptr64", "Enables 64-bit pointers support", {
CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_PTR64 },
{ "+thumb", "Enables Thumb mode for ARM.", {
CS_ARCH_ARM, CS_ARCH_MAX }, 0, CS_MODE_THUMB },
{ "+m", "Enables the M extension for ARM.", {
CS_ARCH_ARM, CS_ARCH_MAX }, 0, CS_MODE_MCLASS },
{ "+v8", "Sets the ARM version to v8+", {
CS_ARCH_ARM, CS_ARCH_MAX }, 0, CS_MODE_V8 },
{ "+aix", "Enables AIX OS assembly", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_AIX_OS },
{ "+booke", "Enables BOOKE extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_BOOKE },
{ "+maix", "Enables Modern AIX assembly", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_MODERN_AIX_AS },
{ "+msync", "Has only the msync instruction instead of sync. Implies BookE.", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_MSYNC },
{ "+qpx", "Enables QPX extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_QPX },
{ "+ps", "Enables PS extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_PS },
{ "+spe", "Enables SPE extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_SPE },
{ NULL }
};
@@ -59,15 +79,6 @@ static struct {
{ "arm", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM },
{ "armle", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
{ "armbe", "ARM, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
{ "armv8", "ARM v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 },
{ "armv8be", "ARM v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
{ "cortexm", "ARM Cortex-M Thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS },
{ "cortexmv8", "ARM Cortex-M Thumb, v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 },
{ "thumb", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
{ "thumble", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
{ "thumbbe", "ARM Thumb mode, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
{ "thumbv8", "ARM Thumb v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 },
{ "thumbv8be", "ARM Thumb v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
{ "aarch64", "AArch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN },
{ "aarch64be", "AArch64, big endian", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN },
@@ -134,26 +145,30 @@ static struct {
{ "ppc32", "PowerPC 32-bit, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN },
{ "ppc32be", "PowerPC 32-bit, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN },
{ "ppc32qpx", "PowerPC 32-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beqpx", "PowerPC 32-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "ppc32ps", "PowerPC 32-bit, ps, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beps", "PowerPC 32-bit, ps, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN },
{ "ppc64", "PowerPC 64-bit, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64be", "PowerPC 64-bit, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN },
{ "ppc64qpx", "PowerPC 64-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc64beqpx", "PowerPC 64-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr7", "PowerPC 64-bit, Power7 (ISA v2.06), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR7 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr7", "PowerPC 64-bit, Power7 (ISA v2.06), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR7 | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr8", "PowerPC 64-bit, Power8 (ISA v2.07), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR8 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr8", "PowerPC 64-bit, Power8 (ISA v2.07), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR8 | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr9", "PowerPC 64-bit, Power9 (ISA v3.0), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR9 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr9", "PowerPC 64-bit, Power9 (ISA v3.0), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR9 | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr10", "PowerPC 64-bit, Power10 (ISA v3.1), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR10 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr10", "PowerPC 64-bit, Power10 (ISA v3.1), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR10 | CS_MODE_BIG_ENDIAN },
{ "ppc64FutureISA", "PowerPC 64-bit, Future ISA, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PPC_ISA_FUTURE | CS_MODE_LITTLE_ENDIAN },
{ "ppc64beFutureISA", "PowerPC 64-bit, Future ISA, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PPC_ISA_FUTURE | CS_MODE_BIG_ENDIAN },
{ "sparc", "Sparc, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN },
{ "sparcv9", "Sparc v9, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 },
{ "systemz", "systemz (s390x) - all features", CS_ARCH_SYSTEMZ, CS_MODE_BIG_ENDIAN },
{ "systemz_arch8", "(arch8/z10/generic)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH8 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch9", "(arch9/z196)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH9 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch10", "(arch10/zec12)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH10 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch11", "(arch11/z13)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH11 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch12", "(arch12/z14)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH12 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch13", "(arch13/z15)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH13 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch14", "(arch14/z16)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH14 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch8", "(arch8/z10/generic)", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH8 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch9", "(arch9/z196)", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH9 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch10", "(arch10/zec12)", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH10 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch11", "(arch11/z13)", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH11 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch12", "(arch12/z14)", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH12 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch13", "(arch13/z15)", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH13 | CS_MODE_BIG_ENDIAN },
{ "systemz_arch14", "(arch14/z16)", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH14 | CS_MODE_BIG_ENDIAN },
{ "s390x", "SystemZ s390x, big endian", CS_ARCH_SYSTEMZ, CS_MODE_BIG_ENDIAN },
@@ -221,6 +236,9 @@ static struct {
{ "loongarch32", "LoongArch 32-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 },
{ "loongarch64", "LoongArch 64-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 },
{ "esp32", "Xtensa ESP32", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32 },
{ "esp32s2", "Xtensa ESP32S2", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S2 },
{ "esp8266", "Xtensa ESP8266", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP8266 },
{ NULL }
};
@@ -422,6 +440,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
case CS_ARCH_LOONGARCH:
print_insn_detail_loongarch(handle, ins);
break;
case CS_ARCH_XTENSA:
print_insn_detail_xtensa(handle, ins);
break;
default: break;
}
@@ -608,6 +629,10 @@ int main(int argc, char **argv)
printf("loongarch=1 ");
}
if (cs_support(CS_ARCH_XTENSA)) {
printf("xtensa=1 ");
}
printf("\n");
return 0;
case 'h':
@@ -637,6 +662,7 @@ int main(int argc, char **argv)
address = strtoull(src, &temp, 16);
if (temp == src || *temp != '\0' || errno == ERANGE) {
fprintf(stderr, "ERROR: invalid address argument, quit!\n");
free(assembly);
return -2;
}
}
@@ -670,6 +696,7 @@ int main(int argc, char **argv)
if (arch == CS_ARCH_ALL) {
fprintf(stderr, "ERROR: Invalid <arch+mode>: \"%s\", quit!\n", choosen_arch);
usage(argv[0]);
free(assembly);
return -1;
}
@@ -677,6 +704,7 @@ int main(int argc, char **argv)
const char *error = cs_strerror(err);
fprintf(stderr, "ERROR: Failed on cs_open(): %s\n", error);
usage(argv[0]);
free(assembly);
return -1;
}

1
external/capstone/cstool/cstool.h vendored
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@@ -22,5 +22,6 @@ void print_insn_detail_tricore(csh handle, cs_insn *ins);
void print_insn_detail_alpha(csh handle, cs_insn *ins);
void print_insn_detail_hppa(csh handle, cs_insn *ins);
void print_insn_detail_loongarch(csh handle, cs_insn *ins);
void print_insn_detail_xtensa(csh handle, cs_insn *ins);
#endif //CAPSTONE_CSTOOL_CSTOOL_H_

1
external/capstone/cstool/cstool_aarch64.c vendored
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@@ -175,6 +175,7 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
break;
case AARCH64_OP_EXACTFPIMM:
printf("\t\toperands[%u].subtype EXACTFPIMM = %d\n", i, op->sysop.imm.exactfpimm);
printf("\t\toperands[%u].fp = %.1f\n", i, op->fp);
break;
case AARCH64_OP_DBNXS:
printf("\t\toperands[%u].subtype DBNXS = %d\n", i, op->sysop.imm.dbnxs);

92
external/capstone/cstool/cstool_xtensa.c vendored Normal file
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@@ -0,0 +1,92 @@
/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#include <stdio.h>
#include <capstone/capstone.h>
#include <capstone/xtensa.h>
static const char *xtensa_insn_form_strs[] = {
[XTENSA_INSN_FORM_INVALID] = "XTENSA_INSN_FORM_INVALID",
[XTENSA_INSN_FORM_RRR] = "XTENSA_INSN_FORM_RRR",
[XTENSA_INSN_FORM_RRI8] = "XTENSA_INSN_FORM_RRI8",
[XTENSA_INSN_FORM_RRRN] = "XTENSA_INSN_FORM_RRRN",
[XTENSA_INSN_FORM_AEINST24] = "XTENSA_INSN_FORM_AEINST24",
[XTENSA_INSN_FORM_BRI12] = "XTENSA_INSN_FORM_BRI12",
[XTENSA_INSN_FORM_CALL] = "XTENSA_INSN_FORM_CALL",
[XTENSA_INSN_FORM_CALLX] = "XTENSA_INSN_FORM_CALLX",
[XTENSA_INSN_FORM_EE_INST24] = "XTENSA_INSN_FORM_EE_INST24",
[XTENSA_INSN_FORM_RRI4] = "XTENSA_INSN_FORM_RRI4",
[XTENSA_INSN_FORM_RI16] = "XTENSA_INSN_FORM_RI16",
[XTENSA_INSN_FORM_RI7] = "XTENSA_INSN_FORM_RI7",
[XTENSA_INSN_FORM_RSR] = "XTENSA_INSN_FORM_RSR",
};
void print_insn_detail_xtensa(csh handle, cs_insn *ins)
{
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
cs_xtensa *detail = &(ins->detail->xtensa);
if (detail->format && detail->format < XTENSA_INSN_FORM_MAX) {
printf("\tformat: %s\n", xtensa_insn_form_strs[detail->format]);
}
if (detail->op_count)
printf("\top_count: %u\n", detail->op_count);
for (i = 0; i < detail->op_count; i++) {
cs_xtensa_op *op = &(detail->operands[i]);
if (op->type == CS_OP_REG)
printf("\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
else if (op->type == CS_OP_IMM)
printf("\t\toperands[%u].type: IMM = 0x%" PRIx32 "\n",
i, op->imm);
else if (op->type == CS_OP_MEM)
printf("\t\toperands[%u].type: MEM\n"
"\t\t\t.mem.base: REG = %s\n"
"\t\t\t.mem.disp: 0x%" PRIx32 "\n",
i, cs_reg_name(handle, op->mem.base),
op->mem.disp);
else if (op->type == XTENSA_OP_L32R) {
printf("\t\toperands[%u].type: L32R\n"
"\t\t\t.l32r = %" PRIx32 "\n",
i, op->imm);
}
if (op->access & CS_AC_READ)
printf("\t\t\t.access: READ\n");
else if (op->access & CS_AC_WRITE)
printf("\t\t\t.access: WRITE\n");
else if (op->access & (CS_AC_READ | CS_AC_WRITE))
printf("\t\t\t.access: READ | WRITE\n");
}
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
printf(" %s",
cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
printf(" %s",
cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}
}