Merge commit '3621a6c08002c6b3e5b6f91bb0e20d8372613160' into dev

external/capstone/include/capstone/aarch64.h

@@ -1972,13 +1972,13 @@ typedef union {
 	aarch64_sysreg sysreg;
 	aarch64_tlbi tlbi;
 	aarch64_ic ic;
-	uint64_t raw_val;
+	int raw_val;
 } aarch64_sysop_reg;
 
 typedef union {
 	aarch64_dbnxs dbnxs;
 	aarch64_exactfpimm exactfpimm;
-	uint64_t raw_val;
+	int raw_val;
 } aarch64_sysop_imm;
 
 typedef union {
@@ -1997,7 +1997,7 @@ typedef union {
 	aarch64_bti bti;
 	aarch64_svepredpat svepredpat;
 	aarch64_sveveclenspecifier sveveclenspecifier;
-	uint64_t raw_val;
+	int raw_val;
 } aarch64_sysop_alias;
 
 /// Operand type for instruction's operands
@@ -2772,16 +2772,6 @@ typedef struct aarch64_op_mem {
   int32_t disp;	   ///< displacement/offset value
 } aarch64_op_mem;
 
-/// Components of an SME matrix.
-/// Used when an sme operand is set to signal which part should be set.
-typedef enum {
-	AARCH64_SME_MATRIX_TILE,
-	AARCH64_SME_MATRIX_TILE_LIST,
-	AARCH64_SME_MATRIX_SLICE_REG,
-	AARCH64_SME_MATRIX_SLICE_OFF,
-	AARCH64_SME_MATRIX_SLICE_OFF_RANGE,
-} aarch64_sme_op_part;
-
 typedef enum {
 	AARCH64_SME_OP_INVALID,
 	AARCH64_SME_OP_TILE, ///< SME operand is a single tile.
@@ -2836,10 +2826,10 @@ typedef struct cs_aarch64_op {
 		aarch64_imm_range imm_range; ///< An immediate range
     double fp;		 ///< floating point value for FP operand
     aarch64_op_mem mem;	 ///< base/index/scale/disp value for MEM operand
-		aarch64_sysop sysop; ///< System operand
     aarch64_op_sme sme; ///< SME matrix operand
     aarch64_op_pred pred; ///< Predicate register
   };
+  aarch64_sysop sysop; ///< System operand
 
   /// How is this operand accessed? (READ, WRITE or READ|WRITE)
   /// This field is combined of cs_ac_type.

external/capstone/include/capstone/arm.h

@@ -40,6 +40,7 @@ typedef enum CondCodes {
   ARMCC_LE, // Less than or equal         <, ==, or unordered
   ARMCC_AL, // Always (unconditional)     Always (unconditional)
   ARMCC_UNDEF = 15, // Undefined
+  ARMCC_Invalid = 16, // Invalid
 } ARMCC_CondCodes;
 
 inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
@@ -414,6 +415,7 @@ typedef enum {
 typedef union {
   arm_sysreg mclasssysreg;
   arm_bankedreg bankedreg;
+  int raw_val; ///< Raw value for assignment in generated files.
 } arm_sysop_reg;
 
 /// Operand type for instruction's operands
@@ -893,6 +895,10 @@ typedef struct cs_arm_op {
 	int8_t neon_lane;
 } cs_arm_op;
 
+typedef struct {
+	cs_ac_type mem_acc; ///< CGI memory access according to mayLoad and mayStore
+} arm_suppl_info;
+
 #define NUM_ARM_OPS 36
 
 /// Instruction structure
@@ -950,6 +956,8 @@ typedef enum arm_insn {
 	ARM_INS_LDRSH,
 	ARM_INS_MOVS,
 	ARM_INS_MOV,
+	ARM_INS_STRB,
+	ARM_INS_STRH,
 	ARM_INS_STR,
 	ARM_INS_ADC,
 	ARM_INS_ADD,
@@ -1362,13 +1370,11 @@ typedef enum arm_insn {
 	ARM_INS_STMDB,
 	ARM_INS_STM,
 	ARM_INS_STMIB,
-	ARM_INS_STRB,
 	ARM_INS_STRD,
 	ARM_INS_STREX,
 	ARM_INS_STREXB,
 	ARM_INS_STREXD,
 	ARM_INS_STREXH,
-	ARM_INS_STRH,
 	ARM_INS_STRHT,
 	ARM_INS_SUB,
 	ARM_INS_SVC,
@@ -1642,63 +1648,73 @@ typedef enum arm_insn_group {
 	// generated content <ARMGenCSFeatureEnum.inc> begin
 	// clang-format off
 
-	ARM_FEATURE_IsARM = 128,
-	ARM_FEATURE_HasV5T,
-	ARM_FEATURE_HasV4T,
-	ARM_FEATURE_HasVFP2,
-	ARM_FEATURE_HasV5TE,
-	ARM_FEATURE_HasV6T2,
-	ARM_FEATURE_HasMVEInt,
-	ARM_FEATURE_HasNEON,
-	ARM_FEATURE_HasFPRegs64,
-	ARM_FEATURE_HasFPRegs,
-	ARM_FEATURE_IsThumb2,
-	ARM_FEATURE_HasV8_1MMainline,
-	ARM_FEATURE_HasLOB,
-	ARM_FEATURE_IsThumb,
-	ARM_FEATURE_HasV8MBaseline,
-	ARM_FEATURE_Has8MSecExt,
-	ARM_FEATURE_HasV8,
-	ARM_FEATURE_HasAES,
-	ARM_FEATURE_HasBF16,
-	ARM_FEATURE_HasCDE,
-	ARM_FEATURE_PreV8,
-	ARM_FEATURE_HasV6K,
-	ARM_FEATURE_HasCRC,
-	ARM_FEATURE_HasV7,
-	ARM_FEATURE_HasDB,
-	ARM_FEATURE_HasVirtualization,
-	ARM_FEATURE_HasVFP3,
-	ARM_FEATURE_HasDPVFP,
-	ARM_FEATURE_HasFullFP16,
-	ARM_FEATURE_HasV6,
-	ARM_FEATURE_HasAcquireRelease,
-	ARM_FEATURE_HasV7Clrex,
-	ARM_FEATURE_HasMVEFloat,
-	ARM_FEATURE_HasFPRegsV8_1M,
-	ARM_FEATURE_HasMP,
-	ARM_FEATURE_HasSB,
-	ARM_FEATURE_HasDivideInARM,
-	ARM_FEATURE_HasV8_1a,
-	ARM_FEATURE_HasSHA2,
-	ARM_FEATURE_HasTrustZone,
-	ARM_FEATURE_UseNaClTrap,
-	ARM_FEATURE_HasV8_4a,
-	ARM_FEATURE_HasV8_3a,
-	ARM_FEATURE_HasFPARMv8,
-	ARM_FEATURE_HasFP16,
-	ARM_FEATURE_HasVFP4,
-	ARM_FEATURE_HasFP16FML,
-	ARM_FEATURE_HasFPRegs16,
-	ARM_FEATURE_HasV8MMainline,
-	ARM_FEATURE_HasDotProd,
-	ARM_FEATURE_HasMatMulInt8,
-	ARM_FEATURE_IsMClass,
-	ARM_FEATURE_HasPACBTI,
-	ARM_FEATURE_IsNotMClass,
-	ARM_FEATURE_HasDSP,
-	ARM_FEATURE_HasDivideInThumb,
-	ARM_FEATURE_HasV6M,
+	ARM_FEATURE_HASV4T = 128,
+	ARM_FEATURE_HASV5T,
+	ARM_FEATURE_HASV5TE,
+	ARM_FEATURE_HASV6,
+	ARM_FEATURE_HASV6M,
+	ARM_FEATURE_HASV8MBASELINE,
+	ARM_FEATURE_HASV8MMAINLINE,
+	ARM_FEATURE_HASV8_1MMAINLINE,
+	ARM_FEATURE_HASMVEINT,
+	ARM_FEATURE_HASMVEFLOAT,
+	ARM_FEATURE_HASCDE,
+	ARM_FEATURE_HASFPREGS,
+	ARM_FEATURE_HASFPREGS16,
+	ARM_FEATURE_HASNOFPREGS16,
+	ARM_FEATURE_HASFPREGS64,
+	ARM_FEATURE_HASFPREGSV8_1M,
+	ARM_FEATURE_HASV6T2,
+	ARM_FEATURE_HASV6K,
+	ARM_FEATURE_HASV7,
+	ARM_FEATURE_HASV8,
+	ARM_FEATURE_PREV8,
+	ARM_FEATURE_HASV8_1A,
+	ARM_FEATURE_HASV8_2A,
+	ARM_FEATURE_HASV8_3A,
+	ARM_FEATURE_HASV8_4A,
+	ARM_FEATURE_HASV8_5A,
+	ARM_FEATURE_HASV8_6A,
+	ARM_FEATURE_HASV8_7A,
+	ARM_FEATURE_HASVFP2,
+	ARM_FEATURE_HASVFP3,
+	ARM_FEATURE_HASVFP4,
+	ARM_FEATURE_HASDPVFP,
+	ARM_FEATURE_HASFPARMV8,
+	ARM_FEATURE_HASNEON,
+	ARM_FEATURE_HASSHA2,
+	ARM_FEATURE_HASAES,
+	ARM_FEATURE_HASCRYPTO,
+	ARM_FEATURE_HASDOTPROD,
+	ARM_FEATURE_HASCRC,
+	ARM_FEATURE_HASRAS,
+	ARM_FEATURE_HASLOB,
+	ARM_FEATURE_HASPACBTI,
+	ARM_FEATURE_HASFP16,
+	ARM_FEATURE_HASFULLFP16,
+	ARM_FEATURE_HASFP16FML,
+	ARM_FEATURE_HASBF16,
+	ARM_FEATURE_HASMATMULINT8,
+	ARM_FEATURE_HASDIVIDEINTHUMB,
+	ARM_FEATURE_HASDIVIDEINARM,
+	ARM_FEATURE_HASDSP,
+	ARM_FEATURE_HASDB,
+	ARM_FEATURE_HASDFB,
+	ARM_FEATURE_HASV7CLREX,
+	ARM_FEATURE_HASACQUIRERELEASE,
+	ARM_FEATURE_HASMP,
+	ARM_FEATURE_HASVIRTUALIZATION,
+	ARM_FEATURE_HASTRUSTZONE,
+	ARM_FEATURE_HAS8MSECEXT,
+	ARM_FEATURE_ISTHUMB,
+	ARM_FEATURE_ISTHUMB2,
+	ARM_FEATURE_ISMCLASS,
+	ARM_FEATURE_ISNOTMCLASS,
+	ARM_FEATURE_ISARM,
+	ARM_FEATURE_USENACLTRAP,
+	ARM_FEATURE_USENEGATIVEIMMEDIATES,
+	ARM_FEATURE_HASSB,
+	ARM_FEATURE_HASCLRBHB,
 
 	// clang-format on
 	// generated content <ARMGenCSFeatureEnum.inc> end
@@ -1706,6 +1722,26 @@ typedef enum arm_insn_group {
 	ARM_GRP_ENDING,
 } arm_insn_group;
 
+#ifdef CAPSTONE_ARM_COMPAT_HEADER
+#define arm_cc ARMCC_CondCodes
+#define ARM_CC_EQ ARMCC_EQ
+#define ARM_CC_NE ARMCC_NE
+#define ARM_CC_HS ARMCC_HS
+#define ARM_CC_LO ARMCC_LO
+#define ARM_CC_MI ARMCC_MI
+#define ARM_CC_PL ARMCC_PL
+#define ARM_CC_VS ARMCC_VS
+#define ARM_CC_VC ARMCC_VC
+#define ARM_CC_HI ARMCC_HI
+#define ARM_CC_LS ARMCC_LS
+#define ARM_CC_GE ARMCC_GE
+#define ARM_CC_LT ARMCC_LT
+#define ARM_CC_GT ARMCC_GT
+#define ARM_CC_LE ARMCC_LE
+#define ARM_CC_AL ARMCC_AL
+#define ARM_CC_INVALID ARMCC_Invalid
+#endif
+
 #ifdef __cplusplus
 }
 #endif

external/capstone/include/capstone/arm64.h

@@ -8,7 +8,7 @@
 extern "C" {
 #endif
 
-#include <capstone/aarch64.h>
+#include "aarch64.h"
 #include "cs_operand.h"
 #include "platform.h"
 
@@ -2626,20 +2626,15 @@ typedef enum {
 
 typedef aarch64_op_mem arm64_op_mem;
 
-typedef enum {
-	ARM64_SME_MATRIX_TILE = AARCH64_SME_MATRIX_TILE,
-	ARM64_SME_MATRIX_TILE_LIST = AARCH64_SME_MATRIX_TILE_LIST,
-	ARM64_SME_MATRIX_SLICE_REG = AARCH64_SME_MATRIX_SLICE_REG,
-	ARM64_SME_MATRIX_SLICE_OFF = AARCH64_SME_MATRIX_SLICE_OFF,
-	ARM64_SME_MATRIX_SLICE_OFF_RANGE = AARCH64_SME_MATRIX_SLICE_OFF_RANGE,
-} arm64_sme_op_part;
-
 typedef enum {
 	ARM64_SME_OP_INVALID = AARCH64_SME_OP_INVALID,
 	ARM64_SME_OP_TILE = AARCH64_SME_OP_TILE,
 	ARM64_SME_OP_TILE_VEC = AARCH64_SME_OP_TILE_VEC,
 } arm64_sme_op_type;
 
+#define ARM64_SLICE_IMM_INVALID UINT16_MAX
+#define ARM64_SLICE_IMM_RANGE_INVALID UINT8_MAX
+
 typedef aarch64_imm_range arm64_imm_range;
 
 typedef aarch64_op_sme arm64_op_sme;
@@ -2650,7 +2645,7 @@ typedef cs_aarch64_op cs_arm64_op;
 
 typedef aarch64_suppl_info arm64_suppl_info;
 
-#define MAX_ARM64_OPS 8
+#define NUM_ARM64_OPS 16
 
 typedef cs_aarch64 cs_arm64;
 
@@ -4581,3 +4576,38 @@ typedef enum {
 #endif
 
 #endif
+
+#define arm64_cc AArch64CC_CondCode
+#define ARM64_CC_EQ AArch64CC_EQ
+#define ARM64_CC_NE AArch64CC_NE
+#define ARM64_CC_HS AArch64CC_HS
+#define ARM64_CC_LO AArch64CC_LO
+#define ARM64_CC_MI AArch64CC_MI
+#define ARM64_CC_PL AArch64CC_PL
+#define ARM64_CC_VS AArch64CC_VS
+#define ARM64_CC_VC AArch64CC_VC
+#define ARM64_CC_HI AArch64CC_HI
+#define ARM64_CC_LS AArch64CC_LS
+#define ARM64_CC_GE AArch64CC_GE
+#define ARM64_CC_LT AArch64CC_LT
+#define ARM64_CC_GT AArch64CC_GT
+#define ARM64_CC_LE AArch64CC_LE
+#define ARM64_CC_AL AArch64CC_AL
+#define ARM64_CC_NV AArch64CC_NV
+#define ARM64_CC_INVALID AArch64CC_Invalid
+#define ARM64_VAS_INVALID AARCH64LAYOUT_INVALID
+#define ARM64_VAS_16B AARCH64LAYOUT_VL_16B
+#define ARM64_VAS_8B AARCH64LAYOUT_VL_8B
+#define ARM64_VAS_4B AARCH64LAYOUT_VL_4B
+#define ARM64_VAS_1B AARCH64LAYOUT_VL_1B
+#define ARM64_VAS_8H AARCH64LAYOUT_VL_8H
+#define ARM64_VAS_4H AARCH64LAYOUT_VL_4H
+#define ARM64_VAS_2H AARCH64LAYOUT_VL_2H
+#define ARM64_VAS_1H AARCH64LAYOUT_VL_1H
+#define ARM64_VAS_4S AARCH64LAYOUT_VL_4S
+#define ARM64_VAS_2S AARCH64LAYOUT_VL_2S
+#define ARM64_VAS_1S AARCH64LAYOUT_VL_1S
+#define ARM64_VAS_2D AARCH64LAYOUT_VL_2D
+#define ARM64_VAS_1D AARCH64LAYOUT_VL_1D
+#define ARM64_VAS_1Q AARCH64LAYOUT_VL_1Q
+#define arm64_vas AArch64Layout_VectorLayout

external/capstone/include/capstone/bpf.h

@@ -1,5 +1,7 @@
 /* Capstone Disassembly Engine */
 /* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
+/* SPDX-License-Identifier: BSD-3 */
 
 #ifndef CAPSTONE_BPF_H
 #define CAPSTONE_BPF_H
@@ -11,9 +13,10 @@ extern "C" {
 #include "platform.h"
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+#define NUM_BPF_OPS 3
 /// Operand type for instruction's operands
 typedef enum bpf_op_type {
 	BPF_OP_INVALID = 0,
@@ -22,9 +25,9 @@ typedef enum bpf_op_type {
 	BPF_OP_IMM,
 	BPF_OP_OFF,
 	BPF_OP_MEM,
-	BPF_OP_MMEM,	///< M[k] in cBPF
-	BPF_OP_MSH,	///< corresponds to cBPF's BPF_MSH mode
-	BPF_OP_EXT,	///< cBPF's extension (not eBPF)
+	BPF_OP_MMEM, ///< M[k] in cBPF
+	BPF_OP_MSH,  ///< corresponds to cBPF's BPF_MSH mode
+	BPF_OP_EXT,  ///< cBPF's extension (not eBPF)
 } bpf_op_type;
 
 /// BPF registers
@@ -54,8 +57,8 @@ typedef enum bpf_reg {
 /// Instruction's operand referring to memory
 /// This is associated with BPF_OP_MEM operand type above
 typedef struct bpf_op_mem {
-	bpf_reg base;	///< base register
-	uint32_t disp;	///< offset value
+	bpf_reg base;  ///< base register
+	uint32_t disp; ///< offset value
 } bpf_op_mem;
 
 typedef enum bpf_ext_type {
@@ -71,13 +74,15 @@ typedef struct cs_bpf_op {
 		uint8_t reg;	///< register value for REG operand
 		uint64_t imm;	///< immediate value IMM operand
 		uint32_t off;	///< offset value, used in jump & call
-		bpf_op_mem mem;	///< base/disp value for MEM operand
+		bpf_op_mem mem; ///< base/disp value for MEM operand
 		/* cBPF only */
-		uint32_t mmem;	///< M[k] in cBPF
-		uint32_t msh;	///< corresponds to cBPF's BPF_MSH mode
-		uint32_t ext;	///< cBPF's extension (not eBPF)
+		uint32_t mmem; ///< M[k] in cBPF
+		uint32_t msh;  ///< corresponds to cBPF's BPF_MSH mode
+		uint32_t ext;  ///< cBPF's extension (not eBPF)
 	};
 
+	bool is_signed; ///< is this operand signed? It is set for memory, immediate and offset operands.
+	bool is_pkt; ///< is this operand referring to packet data? It is set for memory operands.
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
 	/// This field is combined of cs_ac_type.
 	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
@@ -99,29 +104,38 @@ typedef enum bpf_insn {
 	BPF_INS_SUB,
 	BPF_INS_MUL,
 	BPF_INS_DIV,
+	BPF_INS_SDIV,
 	BPF_INS_OR,
 	BPF_INS_AND,
 	BPF_INS_LSH,
 	BPF_INS_RSH,
 	BPF_INS_NEG,
 	BPF_INS_MOD,
+	BPF_INS_SMOD,
 	BPF_INS_XOR,
-	BPF_INS_MOV,	///< eBPF only
-	BPF_INS_ARSH,	///< eBPF only
+	BPF_INS_MOV,   ///< eBPF only
+	BPF_INS_MOVSB, ///< eBPF only
+	BPF_INS_MOVSH, ///< eBPF only
+	BPF_INS_ARSH,  ///< eBPF only
 
 	///< ALU64, eBPF only
 	BPF_INS_ADD64,
 	BPF_INS_SUB64,
 	BPF_INS_MUL64,
 	BPF_INS_DIV64,
+	BPF_INS_SDIV64,
 	BPF_INS_OR64,
 	BPF_INS_AND64,
 	BPF_INS_LSH64,
 	BPF_INS_RSH64,
 	BPF_INS_NEG64,
 	BPF_INS_MOD64,
+	BPF_INS_SMOD64,
 	BPF_INS_XOR64,
 	BPF_INS_MOV64,
+	BPF_INS_MOVSB64,
+	BPF_INS_MOVSH64,
+	BPF_INS_MOVSW64,
 	BPF_INS_ARSH64,
 
 	///< Byteswap, eBPF only
@@ -136,14 +150,21 @@ typedef enum bpf_insn {
 	BPF_INS_BSWAP64,
 
 	///< Load
-	BPF_INS_LDW,	///< eBPF only
+	BPF_INS_LDW,   ///< eBPF only
 	BPF_INS_LDH,
 	BPF_INS_LDB,
-	BPF_INS_LDDW,	///< eBPF only: load 64-bit imm
-	BPF_INS_LDXW,	///< eBPF only
-	BPF_INS_LDXH,	///< eBPF only
-	BPF_INS_LDXB,	///< eBPF only
-	BPF_INS_LDXDW,	///< eBPF only
+	BPF_INS_LDDW,  ///< eBPF only: load 64-bit imm
+	BPF_INS_LDXW,  ///< eBPF only
+	BPF_INS_LDXH,  ///< eBPF only
+	BPF_INS_LDXB,  ///< eBPF only
+	BPF_INS_LDXDW, ///< eBPF only
+	///< Packet data access
+	BPF_INS_LDABSW, ///< eBPF only
+	BPF_INS_LDABSH, ///< eBPF only
+	BPF_INS_LDABSB, ///< eBPF only
+	BPF_INS_LDINDW, ///< eBPF only
+	BPF_INS_LDINDH, ///< eBPF only
+	BPF_INS_LDINDB, ///< eBPF only
 
 	///< Store
 	BPF_INS_STW,	///< eBPF only
@@ -155,28 +176,64 @@ typedef enum bpf_insn {
 	BPF_INS_STXB,	///< eBPF only
 	BPF_INS_STXDW,	///< eBPF only
 	BPF_INS_XADDW,	///< eBPF only
-	BPF_INS_XADDDW,	///< eBPF only
+	BPF_INS_XADDDW, ///< eBPF only
 
 	///< Jump
-	BPF_INS_JMP,
+	BPF_INS_JA,
 	BPF_INS_JEQ,
 	BPF_INS_JGT,
 	BPF_INS_JGE,
 	BPF_INS_JSET,
-	BPF_INS_JNE,	///< eBPF only
-	BPF_INS_JSGT,	///< eBPF only
-	BPF_INS_JSGE,	///< eBPF only
-	BPF_INS_CALL,	///< eBPF only
-	BPF_INS_CALLX,	///< eBPF only
-	BPF_INS_EXIT,	///< eBPF only
-	BPF_INS_JLT,	///< eBPF only
-	BPF_INS_JLE,	///< eBPF only
-	BPF_INS_JSLT,	///< eBPF only
-	BPF_INS_JSLE,	///< eBPF only
+	BPF_INS_JNE,   ///< eBPF only
+	BPF_INS_JSGT,  ///< eBPF only
+	BPF_INS_JSGE,  ///< eBPF only
+	BPF_INS_CALL,  ///< eBPF only
+	BPF_INS_CALLX, ///< eBPF only
+	BPF_INS_EXIT,  ///< eBPF only
+	BPF_INS_JLT,   ///< eBPF only
+	BPF_INS_JLE,   ///< eBPF only
+	BPF_INS_JSLT,  ///< eBPF only
+	BPF_INS_JSLE,  ///< eBPF only
+
+	///< Jump32, eBPF only
+	BPF_INS_JAL,
+	BPF_INS_JEQ32,
+	BPF_INS_JGT32,
+	BPF_INS_JGE32,
+	BPF_INS_JSET32,
+	BPF_INS_JNE32,
+	BPF_INS_JSGT32,
+	BPF_INS_JSGE32,
+	BPF_INS_JLT32,
+	BPF_INS_JLE32,
+	BPF_INS_JSLT32,
+	BPF_INS_JSLE32,
 
 	///< Return, cBPF only
 	BPF_INS_RET,
 
+	///< Atomic, eBPF only
+	BPF_INS_AADD,
+	BPF_INS_AOR,
+	BPF_INS_AAND,
+	BPF_INS_AXOR,
+	BPF_INS_AFADD,
+	BPF_INS_AFOR,
+	BPF_INS_AFAND,
+	BPF_INS_AFXOR,
+
+	///< Atomic 64-bit, eBPF only
+	BPF_INS_AXCHG64,
+	BPF_INS_ACMPXCHG64,
+	BPF_INS_AADD64,
+	BPF_INS_AOR64,
+	BPF_INS_AAND64,
+	BPF_INS_AXOR64,
+	BPF_INS_AFADD64,
+	BPF_INS_AFOR64,
+	BPF_INS_AFAND64,
+	BPF_INS_AFXOR64,
+
 	///< Misc, cBPF only
 	BPF_INS_TAX,
 	BPF_INS_TXA,
@@ -184,10 +241,10 @@ typedef enum bpf_insn {
 	BPF_INS_ENDING,
 
 	// alias instructions
-	BPF_INS_LD = BPF_INS_LDW,	///< cBPF only
-	BPF_INS_LDX = BPF_INS_LDXW,	///< cBPF only
-	BPF_INS_ST = BPF_INS_STW,	///< cBPF only
-	BPF_INS_STX = BPF_INS_STXW,	///< cBPF only
+	BPF_INS_LD = BPF_INS_LDW,   ///< cBPF only
+	BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only
+	BPF_INS_ST = BPF_INS_STW,   ///< cBPF only
+	BPF_INS_STX = BPF_INS_STXW, ///< cBPF only
 } bpf_insn;
 
 /// Group of BPF instructions

external/capstone/include/capstone/capstone.h

@@ -48,13 +48,13 @@ extern "C" {
 #endif
 
 // Capstone API version
-#define CS_API_MAJOR 5
+#define CS_API_MAJOR 6
 #define CS_API_MINOR 0
 
 // Version for bleeding edge code of the Github's "next" branch.
 // Use this if you want the absolutely latest development code.
 // This version number will be bumped up whenever we have a new major change.
-#define CS_NEXT_VERSION 6
+#define CS_NEXT_VERSION 7
 
 // Capstone package version
 #define CS_VERSION_MAJOR CS_API_MAJOR
@@ -102,6 +102,7 @@ typedef enum cs_arch {
 	CS_ARCH_ALPHA, 		///< Alpha architecture
 	CS_ARCH_HPPA, 		///< HPPA architecture
 	CS_ARCH_LOONGARCH, 	///< LoongArch architecture
+	CS_ARCH_XTENSA, 	///< Xtensa architecture
 	CS_ARCH_MAX,
 	CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
 } cs_arch;
@@ -131,6 +132,14 @@ typedef enum cs_mode {
 	CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
 	CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
 	CS_MODE_PS = 1 << 7, ///< Paired-singles mode (PPC)
+	CS_MODE_AIX_OS = 1 << 8, ///< PowerPC AIX-OS
+	CS_MODE_PWR7 = 1 << 9, ///< Power 7
+	CS_MODE_PWR8 = 1 << 10, ///< Power 8
+	CS_MODE_PWR9 = 1 << 11, ///< Power 9
+	CS_MODE_PWR10 = 1 << 12, ///< Power 10
+	CS_MODE_PPC_ISA_FUTURE = 1 << 13, ///< Power ISA Future
+	CS_MODE_MODERN_AIX_AS = 1 << 14, ///< PowerPC AIX-OS with modern assembly
+	CS_MODE_MSYNC = 1 << 15, ///< PowerPC Has only the msync instruction instead of sync. Implies BOOKE
 	CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
 	CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
 	CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode
@@ -221,6 +230,9 @@ typedef enum cs_mode {
 	CS_MODE_SYSTEMZ_Z15 = 1 << 13, ///< Enables features of the Z15 processor
 	CS_MODE_SYSTEMZ_Z16 = 1 << 14, ///< Enables features of the Z16 processor
 	CS_MODE_SYSTEMZ_GENERIC = 1 << 15, ///< Enables features of the generic processor
+	CS_MODE_XTENSA_ESP32 = 1 << 1,	 ///< Xtensa ESP32
+	CS_MODE_XTENSA_ESP32S2 = 1 << 2, ///< Xtensa ESP32S2
+	CS_MODE_XTENSA_ESP8266 = 1 << 3, ///< Xtensa ESP328266
 } cs_mode;
 
 typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
@@ -262,7 +274,8 @@ typedef enum cs_opt_type {
 	CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option
 	CS_OPT_MNEMONIC,       ///< Customize instruction mnemonic
 	CS_OPT_UNSIGNED,       ///< print immediate operands in unsigned form
-	CS_OPT_NO_BRANCH_OFFSET, ///< ARM, PPC, AArch64, prints branch immediates without offset.
+	CS_OPT_ONLY_OFFSET_BRANCH, ///< ARM, PPC, AArch64: Don't add the branch immediate value to the PC.
+	CS_OPT_LITBASE, ///< Xtensa, set the LITBASE value. LITBASE is set to 0 by default.
 } cs_opt_type;
 
 /// Runtime option value (associated with option type above)
@@ -277,7 +290,7 @@ typedef enum cs_opt_value {
 	CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix
 	CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
 	CS_OPT_SYNTAX_PERCENT = 1 << 8, ///< Prints the % in front of PPC registers.
-	CS_OPT_SYNTAX_NO_DOLLAR = 1 << 9, ///< Does not print the $ in front of Mips registers.
+	CS_OPT_SYNTAX_NO_DOLLAR = 1 << 9, ///< Does not print the $ in front of Mips, LoongArch registers.
 	CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias.
 } cs_opt_value;
 
@@ -377,6 +390,7 @@ typedef struct cs_opt_skipdata {
 #include "alpha.h"
 #include "hppa.h"
 #include "loongarch.h"
+#include "xtensa.h"
 
 #define MAX_IMPL_W_REGS 47
 #define MAX_IMPL_R_REGS 20
@@ -433,6 +447,7 @@ typedef struct cs_detail {
 		cs_alpha alpha; ///< Alpha architecture
 		cs_hppa hppa; ///< HPPA architecture
 		cs_loongarch loongarch; ///< LoongArch architecture
+		cs_xtensa xtensa; ///< Xtensa architecture
 	};
 } cs_detail;
 

external/capstone/include/capstone/loongarch.h

@@ -2473,6 +2473,23 @@ typedef enum loongarch_insn {
 	// generated content <LoongArchGenCSInsnEnum.inc> end
 
 	LOONGARCH_INS_ENDING,
+
+	LOONGARCH_INS_ALIAS_BEGIN,
+	// generated content <LoongArchGenCSAliasEnum.inc> begin
+	// clang-format off
+
+	LOONGARCH_INS_ALIAS_LA, // Real instr.: LOONGARCH_PseudoLA_GOT
+	LOONGARCH_INS_ALIAS_LA_GLOBAL, // Real instr.: LOONGARCH_PseudoLA_GOT
+	LOONGARCH_INS_ALIAS_LA_LOCAL, // Real instr.: LOONGARCH_PseudoLA_PCREL
+	LOONGARCH_INS_ALIAS_NOP, // Real instr.: LOONGARCH_ANDI
+	LOONGARCH_INS_ALIAS_MOVE, // Real instr.: LOONGARCH_OR
+	LOONGARCH_INS_ALIAS_RET, // Real instr.: LOONGARCH_JIRL
+	LOONGARCH_INS_ALIAS_JR, // Real instr.: LOONGARCH_JIRL
+
+	// clang-format on
+	// generated content <LoongArchGenCSInsnEnum.inc> end
+	LOONGARCH_INS_ALIAS_END,
+
 } loongarch_insn;
 
 //> Group of LOONGARCH instructions

external/capstone/include/capstone/systemz.h

@@ -374,7 +374,7 @@ typedef struct cs_systemz_op {
 	uint8_t imm_width; ///< Bit width of the immediate. 0 if not specified.
 } cs_systemz_op;
 
-#define MAX_SYSTEMZ_OPS 6
+#define NUM_SYSTEMZ_OPS 6
 
 // Instruction structure
 typedef struct cs_systemz {
@@ -383,7 +383,7 @@ typedef struct cs_systemz {
 	/// Number of operands of this instruction,
 	/// or 0 when instruction has no operand.
 	uint8_t op_count;
-	cs_systemz_op operands[MAX_SYSTEMZ_OPS]; ///< operands for this instruction.
+	cs_systemz_op operands[NUM_SYSTEMZ_OPS]; ///< operands for this instruction.
 } cs_systemz;
 
 /// SystemZ instruction

external/capstone/include/capstone/systemz_compatibility.h

@@ -9,7 +9,7 @@
 extern "C" {
 #endif
 
-#include <capstone/systemz.h>
+#include "systemz.h"
 #include "platform.h"
 #include "cs_operand.h"
 
@@ -340,7 +340,7 @@ typedef systemz_op_mem sysz_op_mem;
 
 typedef cs_systemz_op cs_sysz_op;
 
-#define MAX_SYSZ_OPS 6
+#define NUM_SYSZ_OPS 6
 
 typedef cs_systemz cs_sysz;
 

external/capstone/include/capstone/tricore.h

@@ -60,7 +60,7 @@ typedef struct cs_tricore {
 
 /// TriCore registers
 typedef enum tricore_reg {
-	// generate content <TriCoreGenCSRegEnum.inc> begin
+	// generated content <TriCoreGenCSRegEnum.inc> begin
 	// clang-format off
 
 	TRICORE_REG_INVALID = 0,
@@ -127,16 +127,15 @@ typedef enum tricore_reg {
 	TRICORE_REG_ENDING, // 61
 
 	// clang-format on
-	// generate content <TriCoreGenCSRegEnum.inc> end
+	// generated content <TriCoreGenCSRegEnum.inc> end
 } tricore_reg;
 
 /// TriCore instruction
 typedef enum tricore_insn {
-	TRICORE_INS_INVALID = 0,
-	// generate content <TriCoreGenCSInsnEnum.inc> begin
+	// generated content <TriCoreGenCSInsnEnum.inc> begin
 	// clang-format off
 
-	TRICORE_INS_XOR_T,
+	TRICORE_INS_INVALID,
 	TRICORE_INS_ABSDIFS_B,
 	TRICORE_INS_ABSDIFS_H,
 	TRICORE_INS_ABSDIFS,
@@ -525,10 +524,11 @@ typedef enum tricore_insn {
 	TRICORE_INS_XOR_LT_U,
 	TRICORE_INS_XOR_LT,
 	TRICORE_INS_XOR_NE,
+	TRICORE_INS_XOR_T,
 	TRICORE_INS_XOR,
 
 	// clang-format on
-	// generate content <TriCoreGenCSInsnEnum.inc> end
+	// generated content <TriCoreGenCSInsnEnum.inc> end
 	TRICORE_INS_ENDING, // <-- mark the end of the list of instructions
 } tricore_insn;
 
@@ -543,21 +543,31 @@ typedef enum tricore_insn_group {
 
 typedef enum tricore_feature_t {
 	TRICORE_FEATURE_INVALID = 0,
-	// generate content <TriCoreGenCSFeatureEnum.inc> begin
+	// generated content <TriCoreGenCSFeatureEnum.inc> begin
 	// clang-format off
 
-	TRICORE_FEATURE_HasV110 = 128,
-	TRICORE_FEATURE_HasV120_UP,
-	TRICORE_FEATURE_HasV130_UP,
-	TRICORE_FEATURE_HasV161,
-	TRICORE_FEATURE_HasV160_UP,
-	TRICORE_FEATURE_HasV131_UP,
-	TRICORE_FEATURE_HasV161_UP,
-	TRICORE_FEATURE_HasV162,
-	TRICORE_FEATURE_HasV162_UP,
+	TRICORE_FEATURE_HASV110 = 128,
+	TRICORE_FEATURE_HASV120,
+	TRICORE_FEATURE_HASV130,
+	TRICORE_FEATURE_HASV131,
+	TRICORE_FEATURE_HASV160,
+	TRICORE_FEATURE_HASV161,
+	TRICORE_FEATURE_HASV162,
+	TRICORE_FEATURE_HASV120_UP,
+	TRICORE_FEATURE_HASV130_UP,
+	TRICORE_FEATURE_HASV131_UP,
+	TRICORE_FEATURE_HASV160_UP,
+	TRICORE_FEATURE_HASV161_UP,
+	TRICORE_FEATURE_HASV162_UP,
+	TRICORE_FEATURE_HASV120_DN,
+	TRICORE_FEATURE_HASV130_DN,
+	TRICORE_FEATURE_HASV131_DN,
+	TRICORE_FEATURE_HASV160_DN,
+	TRICORE_FEATURE_HASV161_DN,
+	TRICORE_FEATURE_HASV162_DN,
 
 	// clang-format on
-	// generate content <TriCoreGenCSFeatureEnum.inc> end
+	// generated content <TriCoreGenCSFeatureEnum.inc> end
 	TRICORE_FEATURE_ENDING, ///< mark the end of the list of features
 } tricore_feature;